227 lines
13 KiB
C
227 lines
13 KiB
C
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/*
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* Copyright (C) 2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef _ANC_CMDS_H_
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#define _ANC_CMDS_H_
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#define LINK_CMDQ_SIZE 128
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#define DMA_CMDQ_SIZE 64 // 64b words, not 32b
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#define LINK_PIO_READ_FIFO_SIZE 64
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////////////////////////////////////////////////////////////////////////////////
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// DMA Command Definitions
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#define DMA_COMMAND__OPCODE(n) (((n) & 0x7FULL) << 60)
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#define DMA_COMMAND__OPCODE__CONFIG (0)
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#define DMA_COMMAND__OPCODE__BUFDESC (1)
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#define DMA_COMMAND__OPCODE__AES_KEY_IV (2)
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#define DMA_COMMAND__OPCODE__AES_UID1_IV (3)
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#define DMA_COMMAND__OPCODE__AES_IV (4)
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#define DMA_COMMAND__OPCODE__FLAG (5)
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#define DMA_COMMAND_CONFIG__DMA_DIRECTION(n) (((n) & 0x1ULL) << 53)
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#define DMA_DIRECTION_M2N (0)
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#define DMA_DIRECTION_N2M (1)
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#define DMA_COMMAND_CONFIG__PROC_ENABLE_AES(n) (((n) & 0x1ULL) << 54)
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#define DMA_COMMAND_BUFDESC__LENGTH(n) (((n) & 0x1FFFULL) << 40)
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#define DMA_COMMAND_BUFDESC__ADDRESS(n) (((n) & 0xFFFFFFFFFFULL) << 0)
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#define DMA_COMMAND_AESKEY__UNWRAP(n) (((n) & 0x1ULL) << 2)
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#define DMA_COMMAND_AESKEY__KEY_LEN(n) (((n) & 0x3ULL) << 0)
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#define DMA_COMMAND_AESKEY_128_BITS (0)
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#define DMA_COMMAND_AESKEY_192_BITS (1)
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#define DMA_COMMAND_AESKEY_256_BITS (2)
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#define DMA_COMMAND_FLAG__PAUSE(n) (((n) & 0x1ULL) << 16)
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#define DMA_COMMAND_FLAG__CODE(n) (((n) & 0xFFFFULL) << 0)
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#define DMA_COMMAND_CONFIG(dir,aes) \
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(DMA_COMMAND__OPCODE(DMA_COMMAND__OPCODE__CONFIG) | \
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DMA_COMMAND_CONFIG__DMA_DIRECTION(dir) | \
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DMA_COMMAND_CONFIG__PROC_ENABLE_AES(aes))
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#define DMA_COMMAND_BUFDESC(data_bytes,address) \
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(DMA_COMMAND__OPCODE(DMA_COMMAND__OPCODE__BUFDESC) | \
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DMA_COMMAND_BUFDESC__LENGTH(data_bytes) | \
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DMA_COMMAND_BUFDESC__ADDRESS(address))
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#define DMA_COMMAND_AES_KEY_IV(key_len, unwrap_en) \
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(DMA_COMMAND__OPCODE(DMA_COMMAND__OPCODE__AES_KEY_IV) | \
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DMA_COMMAND_AESKEY__KEY_LEN(key_len) | \
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DMA_COMMAND_AESKEY__UNWRAP(unwrap_en))
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#define DMA_COMMAND_FLAG(code,pause) \
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(DMA_COMMAND__OPCODE(DMA_COMMAND__OPCODE__FLAG) | \
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DMA_COMMAND_FLAG__PAUSE(pause) | \
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DMA_COMMAND_FLAG__CODE(code))
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////////////////////////////////////////////////////////////////////////////////
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// Link Command Definitions
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#define LINK_COMMAND__YIELD (1UL << 31)
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#define LINK_COMMAND__OPCODE(n) (((n) & 0x3FUL) << 24)
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#define LINK_CMD_OP_DEBUG_DLL 0x00
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#define LINK_CMD_OP_CMD0 0x01
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#define LINK_CMD_OP_CMD1 0x02
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#define LINK_CMD_OP_CMD1_OP 0x03
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#define LINK_CMD_OP_CMD2 0x04
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#define LINK_CMD_OP_CMD2_OP 0x05
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#define LINK_CMD_OP_CMD3 0x06
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#define LINK_CMD_OP_CMD3_OP 0x07
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#define LINK_CMD_OP_CMD4 0x08
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#define LINK_CMD_OP_CMD4_OP 0x09
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#define LINK_CMD_OP_CMD5 0x0A
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#define LINK_CMD_OP_CMD5_OP 0x0B
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#define LINK_CMD_OP_CMD6 0x0C
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#define LINK_CMD_OP_CMD6_OP 0x0D
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#define LINK_CMD_OP_CMD7 0x0E
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#define LINK_CMD_OP_CMD7_OP 0x0F
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#define LINK_CMD_OP_CMD8_OP 0x10
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#define LINK_CMD_OP_ADDR1 0x12
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#define LINK_CMD_OP_ADDR1_OP 0x13
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#define LINK_CMD_OP_ADDR2 0x14
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#define LINK_CMD_OP_ADDR2_OP 0x15
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#define LINK_CMD_OP_ADDR3 0x16
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#define LINK_CMD_OP_ADDR3_OP 0x17
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#define LINK_CMD_OP_ADDR4 0x18
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#define LINK_CMD_OP_ADDR4_OP 0x19
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#define LINK_CMD_OP_ADDR5 0x1A
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#define LINK_CMD_OP_ADDR5_OP 0x1B
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#define LINK_CMD_OP_ADDR6 0x1C
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#define LINK_CMD_OP_ADDR6_OP 0x1D
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#define LINK_CMD_OP_ADDR7 0x1E
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#define LINK_CMD_OP_ADDR7_OP 0x1F
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#define LINK_CMD_OP_ADDR8_OP 0x20
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#define LINK_CMD_OP_READ_RELEASE 0x21
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#define LINK_CMD_OP_CE 0x22
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#define LINK_CMD_OP_CE_OP 0x23
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#define LINK_CMD_OP_READ_DMA 0x24
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#define LINK_CMD_OP_READ_DMA_OP 0x25
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#define LINK_CMD_OP_READ_PIO 0x26
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#define LINK_CMD_OP_READ_PIO_OP 0x27
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#define LINK_CMD_OP_READ_NUL 0x28
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#define LINK_CMD_OP_READ_NUL_OP 0x29
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#define LINK_CMD_OP_READ_STATUS 0x2A
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#define LINK_CMD_OP_READ_STATUS_ABORT_ENABLED 0x2B
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#define LINK_CMD_OP_WRITE_DMA 0x2C
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#define LINK_CMD_OP_WRITE_DMA_OP 0x2D
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#define LINK_CMD_OP_WRITE_PIO 0x2E
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#define LINK_CMD_OP_WRITE_PIO_OP 0x2F
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#define LINK_CMD_OP_WRITE_PIO_IMM 0x30
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#define LINK_CMD_OP_WRITE_PAD 0x32
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#define LINK_CMD_OP_WRITE_PAD_OP 0x33
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#define LINK_CMD_OP_READ_REGISTER 0x34
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#define LINK_CMD_OP_WRITE_REGISTER 0x35
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#define LINK_CMD_OP_POLL_REGISTER 0x36
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#define LINK_CMD_OP_POLL_REGISTER_ABORT_ENABLED 0x37
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#define LINK_CMD_OP_WAIT_TIME 0x38
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#define LINK_CMD_OP_WAIT_TIME_ABORT_ENABLED 0x39
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#define LINK_CMD_OP_WAIT_FOR_INTERRUPT 0x3A
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#define LINK_CMD_OP_WAIT_FOR_INTERRUPT_ABORT_ENABLED 0x3B
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#define LINK_CMD_OP_SEND_INTERRUPT 0x3C
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#define LINK_CMD_OP_MACRO 0x3D
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#define LINK_CMD_OP_DPI_OUT 0x3E
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#define LINK_CMD_OP_DPI_IN 0x3F
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#define LINK_COMMAND__CE__CE(ce) (((ce) & 0xFFUL) << 0)
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#define LINK_COMMAND__CE(ce) (LINK_COMMAND__OPCODE(LINK_CMD_OP_CE) | LINK_COMMAND__CE__CE(ce))
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#define LINK_COMMAND__CMD__CMD2(n) (((n) & 0xFFUL) << 16)
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#define LINK_COMMAND__CMD__CMD1(n) (((n) & 0xFFUL) << 8)
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#define LINK_COMMAND__CMD__CMD0(n) (((n) & 0xFFUL) << 0)
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#define LINK_COMMAND__CMD1(cmd1) (LINK_COMMAND__OPCODE(LINK_CMD_OP_CMD1) | LINK_COMMAND__CMD__CMD0(cmd1))
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#define LINK_COMMAND__CMD2(cmd1,cmd2) (LINK_COMMAND__OPCODE(LINK_CMD_OP_CMD2) | \
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LINK_COMMAND__CMD__CMD0(cmd1) | \
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LINK_COMMAND__CMD__CMD1(cmd2))
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#define LINK_COMMAND__CMD3(cmd1,cmd2,cmd3) (LINK_COMMAND__OPCODE(LINK_CMD_OP_CMD3) | \
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LINK_COMMAND__CMD__CMD0(cmd1) | \
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LINK_COMMAND__CMD__CMD1(cmd2) | \
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LINK_COMMAND__CMD__CMD2(cmd3))
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#define LINK_COMMAND__ADDR__ADDR2(n) (((n) & 0xFFUL) << 16)
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#define LINK_COMMAND__ADDR__ADDR1(n) (((n) & 0xFFUL) << 8)
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#define LINK_COMMAND__ADDR__ADDR0(n) (((n) & 0xFFUL) << 0)
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#define LINK_COMMAND__ADDR1(addr0) (LINK_COMMAND__OPCODE(LINK_CMD_OP_ADDR1) | \
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LINK_COMMAND__ADDR__ADDR0(addr0))
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#define LINK_COMMAND__ADDR2(addr0,addr1) (LINK_COMMAND__OPCODE(LINK_CMD_OP_ADDR2) | \
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LINK_COMMAND__ADDR__ADDR0(addr0) | \
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LINK_COMMAND__ADDR__ADDR1(addr1))
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#define LINK_COMMAND__ADDR3(addr0,addr1,addr2) (LINK_COMMAND__OPCODE(LINK_CMD_OP_ADDR3) | \
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LINK_COMMAND__ADDR__ADDR0(addr0) | \
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LINK_COMMAND__ADDR__ADDR1(addr1) | \
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LINK_COMMAND__ADDR__ADDR2(addr2))
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#define LINK_COMMAND__WRITE_DMA__LEN(n) (((n) & 0x7FFFUL) << 0)
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#define LINK_COMMAND__WRITE_DMA__CRC_START(n) (((n) & 0x1UL) << 22)
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#define LINK_COMMAND__WRITE_DMA__CRC_STOP(n) (((n) & 0x1UL) << 23)
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#define LINK_COMMAND__WRITE_DMA(len, crc_start, crc_stop) (LINK_COMMAND__OPCODE(LINK_CMD_OP_WRITE_DMA) | \
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LINK_COMMAND__WRITE_DMA__LEN(len) | \
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LINK_COMMAND__WRITE_DMA__CRC_START(crc_start) | \
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LINK_COMMAND__WRITE_DMA__CRC_STOP(crc_stop))
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#define LINK_COMMAND__WRITE_PIO__LEN(n) (((n) & 0x7FFFUL) << 0)
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#define LINK_COMMAND__WRITE_PIO__CRC_START(n) (((n) & 0x1UL) << 22)
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#define LINK_COMMAND__WRITE_PIO__CRC_STOP(n) (((n) & 0x1UL) << 23)
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#define LINK_COMMAND__WRITE_PIO(len, crc_start, crc_stop) (LINK_COMMAND__OPCODE(LINK_CMD_OP_WRITE_PIO) | \
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LINK_COMMAND__WRITE_PIO__LEN(len) | \
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LINK_COMMAND__WRITE_PIO__CRC_START(crc_start) | \
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LINK_COMMAND__WRITE_PIO__CRC_STOP(crc_stop))
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#define LINK_COMMAND__READ_DMA__LEN(n) (((n) & 0x7FFFUL) << 0)
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#define LINK_COMMAND__READ_DMA__CRC_START(n) (((n) & 0x1UL) << 22)
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#define LINK_COMMAND__READ_DMA__CRC_STOP(n) (((n) & 0x1UL) << 23)
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#define LINK_COMMAND__READ_DMA(len, crc_start, crc_stop) (LINK_COMMAND__OPCODE(LINK_CMD_OP_READ_DMA) | \
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LINK_COMMAND__READ_DMA__LEN(len) | \
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LINK_COMMAND__READ_DMA__CRC_START(crc_start) | \
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LINK_COMMAND__READ_DMA__CRC_STOP(crc_stop))
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#define LINK_COMMAND__READ_PIO__LEN(n) (((n) & 0x7FFFUL) << 0)
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#define LINK_COMMAND__READ_PIO__CRC_START(n) (((n) & 0x1UL) << 22)
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#define LINK_COMMAND__READ_PIO__CRC_STOP(n) (((n) & 0x1UL) << 23)
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#define LINK_COMMAND__READ_PIO(len, crc_start, crc_stop) (LINK_COMMAND__OPCODE(LINK_CMD_OP_READ_PIO) | \
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LINK_COMMAND__READ_PIO__LEN(len) | \
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LINK_COMMAND__READ_PIO__CRC_START(crc_start) | \
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LINK_COMMAND__READ_PIO__CRC_STOP(crc_stop))
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#define LINK_COMMAND__READ_STATUS__CODE(n) (((n) & 0xFFUL) << 16)
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#define LINK_COMMAND__READ_STATUS__MASK(n) (((n) & 0xFFUL) << 8)
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#define LINK_COMMAND__READ_STATUS__COND(n) (((n) & 0xFFUL) << 0)
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#define LINK_COMMAND__READ_STATUS(code,mask,cond) (LINK_COMMAND__OPCODE(LINK_CMD_OP_READ_STATUS) | \
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LINK_COMMAND__READ_STATUS__CODE(code) | \
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LINK_COMMAND__READ_STATUS__MASK(mask) | \
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LINK_COMMAND__READ_STATUS__COND(cond))
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#define LINK_COMMAND__SEND_INTERRUPT__PAUSE(n) (((n) & 0x1UL) << 23)
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#define LINK_COMMAND__SEND_INTERRUPT__CODE(n) (((n) & 0xFFFFUL) << 0)
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#define LINK_COMMAND__SEND_INTERRUPT(pause,code) (LINK_COMMAND__OPCODE(LINK_CMD_OP_SEND_INTERRUPT) | \
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LINK_COMMAND__SEND_INTERRUPT__PAUSE(pause) | \
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LINK_COMMAND__SEND_INTERRUPT__CODE(code))
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#define LINK_COMMAND__READ_REGISTER__ADDR(n) (((n) & 0xFFFFFFUL) << 0)
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#define LINK_COMMAND__READ_REGISTER(addr) (LINK_COMMAND__OPCODE(LINK_CMD_OP_READ_REGISTER) | \
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LINK_COMMAND__READ_REGISTER__ADDR(addr))
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#define LINK_COMMAND__WRITE_REGISTER__ADDR(n) (((n) & 0xFFFFFFUL) << 0)
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#define LINK_COMMAND__WRITE_REGISTER(addr) (LINK_COMMAND__OPCODE(LINK_CMD_OP_WRITE_REGISTER) | \
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LINK_COMMAND__WRITE_REGISTER__ADDR(addr))
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#define LINK_COMMAND__WAIT_TIME__CYCLES(n) (((n) & 0xFFFFUL) << 0)
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#define LINK_COMMAND__WAIT_TIME(link_cycles) (LINK_COMMAND__OPCODE(LINK_CMD_OP_WAIT_TIME) | \
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LINK_COMMAND__WAIT_TIME__CYCLES((link_cycles)))
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#define LINK_COMMAND__MACRO__LENGTH(n) (((n) & 0xFFUL) << 0)
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#define LINK_COMMAND__MACRO__ADDR(n) (((n) & 0xFFUL) << 8)
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#define LINK_COMMAND__MACRO__REPEAT(n) (((n) & 0xFFUL) << 16)
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#define LINK_COMMAND__MACRO(addr,length,repeat) (LINK_COMMAND__OPCODE(LINK_CMD_OP_MACRO) | \
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LINK_COMMAND__MACRO__LENGTH(length-1) | \
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LINK_COMMAND__MACRO__ADDR(addr) | \
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LINK_COMMAND__MACRO__REPEAT(repeat))
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#endif // _ANC_CMDS_H_
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