148 lines
8.1 KiB
C
148 lines
8.1 KiB
C
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/*
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* Copyright (C) 2009-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __APPLE_DISPLAYPIPE_H
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#define __APPLE_DISPLAYPIPE_H
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#include <platform/soc/hwregbase.h>
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#define rDPCVERSION (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1018))
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#define rDPCSTATE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x101C))
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#define rDPCGO (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1020))
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#define rDPCRESTART (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1024))
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#define rDPCIRQENAB (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1028))
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#define DPCIRQ_MSTRERR (1<<11)
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#define rDPCIRQ (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x102C))
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#define rDPCSIZE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1030))
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#define rDPCFRMCNT (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1034))
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#define rDPCENAB (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1038))
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#if DISP_VERSION < 5
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#define rDPCPFTOP (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x103C))
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#endif
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#define rDPCPFSIZE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1040))
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#define rDPCPFSTAT (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1044))
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#define rDPCPFHEAD (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1048))
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#if DISP_VERSION < 5
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#define rDPCPFDMA (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104C))
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#define DPCPFDMA_AUTOMODE (1 << 4)
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#define DPCPFDMA_BURSTSIZE_1WORD (0 << 8)
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#define DPCPFDMA_BURSTSIZE_2WORDS (1 << 8)
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#define DPCPFDMA_BURSTSIZE_4WORDS (2 << 8)
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#define DPCPFDMA_BURSTSIZE_8WORDS (3 << 8)
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#define DPCPFDMA_BURSTSIZE_16WORDS (4 << 8)
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#define DPCPFDMA_BURSTSIZE_MASK (7 << 8)
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#define DPCPFDMA_WATERMARK(n) ((n) << 16)
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#define DPCPFDMA_WATERMARK_MASK (0x7FF << 16)
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#else
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#define rDPCPFMODE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104C))
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#define DPCPFMODE_WBEN (1 << 1)
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#define DPCPFMODE_AUTOEN (1 << 0)
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#endif
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#define rDPCPFFLUSH (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1050))
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#define rDPCCLKCNTL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1054))
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#define DPCCLKCNTL_FLOOR(n) ((n && 0xFFFF) << 16)
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#define DPCCLKCNTL_PIPE_ENABLE (1 << 12)
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#define DPCCLKCNTL_LB_ENABLE (1 << 8)
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#define DPCCLKCNTL_V_ENABLE (1 << 4)
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#define DPCCLKCNTL_GATEENAB (1 << 0)
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#define rDPCMEMACC (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1058))
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#if (DISP_VERSION < 3)
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#define rDPCPANCNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x105C))
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#define DPCPANCNFG_PANENAB (1 << 0)
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#define DPCPANCNFG_PANU0ENAB (1 << 8)
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#define DPCPANCNFG_PANU1ENAB (1 << 9)
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#define DPCPANCNFG_PANVENAB (1 << 10)
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#define DPCPANCNFG_PANBENAB (1 << 11)
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#define DPCPANCNFG_PANTIMER(n) ((n) << 16)
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#define DPCPANCNFG_PANTIMER_MASK (0xFFFF << 16)
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#else
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#define rDPCQOSCNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x105C))
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#define DPCQOSCNFG_QOS_ENABLE (1 << 0)
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#define DPCQOSCNFG_UIFIFO_ENABLE (1 << 1)
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#define DPCQOSCNFG_VIDFIFO_ENABLE (1 << 2)
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#if (DISP_VERSION < 4)
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#define DPCQOSCNFG_QOS_OPTIMISTIC (1 << 3)
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#else
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#define DPCQOSCNFG_QOS_OPTIMISTIC (1 << 4)
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#endif
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#define DPCQOSCNFG_PIPE_ENABLE (1 << 8)
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#define DPCQOSCNFG_QOS_TIMER(n) ((n) << 16)
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#endif
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#define rDPBBACKCOLOR (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x203C))
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#define rDPBLAY1CNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2040))
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#define rDPBLAY2CNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2044))
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#define rDPBLAY3CNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2048))
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#define rDPBCRCENAB (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x204C))
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#define rDPBCRCDATA (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2050))
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#define rDPBCRCSNAP (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2054))
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#define rDPBOUTSIZE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2058))
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#define rDPBCLKLVL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x205C))
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#define DPBCLKLVL_OFFLVL(n) ((n) << 0)
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#define DPBCLKLVL_ONLVL(n) ((n) << 16)
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#define rDPBUNDRCNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2064))
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#if (DISP_VERSION < 3)
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#define rDPBPANLVL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2060))
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#else
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#define rDPBQOSLVL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2060))
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#define DPBQOSLVL_MED_WATERMARK(n) ((n) << 0)
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#define DPBQOSLVL_HIGH_WATERMARK(n) ((n) << 16)
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#define rDPBCSCCOEFR(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x4 * (n)) + 0x2068))
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#define rDPBCSCCOEFG(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x4 * (n)) + 0x2074))
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#define rDPBCSCCOEFB(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x4 * (n)) + 0x2080))
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#define rDPBCSCCOFFR (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x208C))
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#define rDPBCSCCOFFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2090))
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#define rDPBCSCCOFFB (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2094))
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#endif
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#if (DISP_VERSION > 4)
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#define rDPUREQCFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x403C))
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#define DPUREQCFG_REQ_CNT(_n) ((_n) & 0xFF)
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#endif
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#define rDPUSRCFMT(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4040))
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#define rDPUSRCBASE(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4044))
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#define rDPUSRCSTRD(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4048))
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#define DPUSRCSTRD_SRCBURST_1BLOCK (0 << 0)
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#define DPUSRCSTRD_SRCBURST_2BLOCKS (1 << 0)
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#define DPUSRCSTRD_SRCBURST_4BLOCKS (2 << 0)
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#define DPUSRCSTRD_SRCBURST_8BLOCKS (3 << 0)
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#define DPUSRCSTRD_SRCBURST_MASK (3 << 0)
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#define DPUSRCSTRD_SRCSTRIDE_MASK (~0x3F)
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#if (DISP_VERSION < 3)
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#define rDPUSRCRGNENAB(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x404C))
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#define rDPUOUTSIZE(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4070))
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#define rDPUCLKLVL(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4074))
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#define rDPUPANLVL(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4078))
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#define rDPUSRCSTRXY(n, r) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4050 + (4 * (r))))
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#define rDPUSRCENDXY(n, r) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4060 + (4 * (r))))
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#else
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#define rDPUSRCXY(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x404C))
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#define rDPUSRCWH(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4050))
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#define rDPUDSTXY(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4054))
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#define rDPUDSTWH(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4058))
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#define rDPUSRCRGN(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x405C))
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#define rDPUSRCSTRXY(n, r) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4060 + (4 * (r))))
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#define rDPUSRCENDXY(n, r) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4070 + (4 * (r))))
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#define rDPUDDAINITX(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4080))
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#define rDPUDDAINITY(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4084))
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#define rDPUDDASTEPX(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4088))
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#define rDPUDDASTEPY(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x408C))
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#define rDPUMMUCNTL(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4090))
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#endif
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#define rDPCPERFCNTL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x6008))
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#define rDPCPERFSTAT (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x600C))
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#define rDPCPERFCNFG(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x6010 + (4 * (n))))
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#define rDPCPERFDATA(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x6020 + (4 * (n))))
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#define rDPCPERFSNAP(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x6030 + (4 * (n))))
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#endif /* ! __APPLE_DISPLAYPIPE_H */
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