iBoot/docs/dcs-specs/Maui_Init_B0_May_20_2015.html

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<h1>AMC Initialization Sequence</h1>
This file was created using the following files on: Wed May 20 11:51:00 2015<br />AMC Version: Major Release: Minor Release: <br />AMP Version: 3 Major Release: 1 Minor Release: 3<br />AMC UM Init sourced from: //depot/ip_lib/apple/amcc/b0.maui/amcc/tb/cfg/static/maqstb_cfg.pl#23<br />AMP UM Init sourced from: //depot/ip_lib/apple/amp/b0.maui/amp/tb/cfg/phy_helper_fxns.pl#11<br />
<h4> Change Log</h4>
* ------------------------------------------------------------------<br /> * Version:1 - Files Edited: all<br /> * Initial fiji checkin<br /> * ------------------------------------------------------------------<br /> * Version:6 - thuang - Files Edited: mcu_helper_fxns.c#5 - mcu_helper_fxns.c#7 - mcu_helper_fxns.h#6 - <br /> * Added Rama's change in pmgr_amc_clk_cfg<br /> * ------------------------------------------------------------------<br /> * Version:7 - thuang - Files Edited: mcu_helper_fxns.c#8 - mcu_helper_fxns.h#6 - <br /> * Release init, specifically to deal with 1202MHz at bucket 0<br /> * ------------------------------------------------------------------<br /> * Version:8 - jayp - Files Edited: mcu_helper_fxns.c#8 - mcu_helper_fxns.h#6 - <br /> * release latest init to match AMCX release<br /> * ------------------------------------------------------------------<br /> * Version:9 - jayp - Files Edited: mcu_helper_fxns.c#9 - mcu_helper_fxns.h#7 - <br /> * update to new dcsh/v.hspds that now points to the real amph.spds<br /> * ------------------------------------------------------------------<br /> * Version:10 - jayp - Files Edited: mcu_helper_fxns.c#10 - mcu_helper_fxns.h#8 - <br /> * updating to preFinal releases of amp, amph, and amcx<br /> * ------------------------------------------------------------------<br /> * Version:11 - thuang - Files Edited: mcu_helper_fxns.c#11 - mcu_helper_fxns.h#9 - <br /> * Init update<br /> * ------------------------------------------------------------------<br /> * Version:12 - jayp - Files Edited: mcu_helper_fxns.c#11 - mcu_helper_fxns.h#9 - <br /> * moving to new amp pointer<br /> * ------------------------------------------------------------------<br /> * Version:13 - cpolapra - Files Edited: maqstb_cfg.pl#72 - calibration_fxns.pl#8 - mcu_helper_fxns.c#12 - mcu_helper_fxns.h#10 - <br /> * Updated chip level config files for calibration at both Bucket 0 & Bucket 1<br /> * ------------------------------------------------------------------<br /> * Version:14 - jayp - Files Edited: mcu_helper_fxns.c#13 - mcu_helper_fxns.h#12 - <br /> * update to init code for latest amcx and amp releases<br /> * ------------------------------------------------------------------<br /> * Version:15 - jayp - Files Edited: gen_mcu_init.pl#6 - mcu_helper_fxns.c#15 - mcu_helper_fxns.h#14 - <br /> * moving to latest amph, amcx, and amp pointers<br /> * ------------------------------------------------------------------<br /> * Version:16 - allin - Files Edited: maqs_gen_cfg_c.pl#12 - maqstb_cfg.pl#123 - mem_tparams.pl#27 - phy_helper_fxns.pl#53 - move_generated_files.pl#4 - mcu_helper_fxns.c#18 - mcu_helper_fxns.h#16 - <br /> * Fixes to MRR/MRW inclusion in resume boot<br /> * ------------------------------------------------------------------<br /> * Version:17 - jayp - Files Edited: maqstb_cfg.pl#125 - mcu_helper_fxns.c#20 - mcu_helper_fxns.h#18 - <br /> * moving to latest amp and amcx releases<br /> * ------------------------------------------------------------------<br /> * Version:18 - jayp - Files Edited: maqs_gen_cfg_c.pl#14 - maqstb_cfg.pl#135 - <br /> * releasing new amp to change global timer register naming so that chip and ams both work<br /> * ------------------------------------------------------------------<br /> * Version:19 - cpolapra - Files Edited: maqstb_cfg.pl#141 - <br /> * Fixed tDIPW denali error<br /> * ------------------------------------------------------------------<br /> * Version:20 - cpolapra - Files Edited: maqstb_cfg.pl#148 - <br /> * PMGR random fixes<br /> * ------------------------------------------------------------------<br /> * Version:21 - cpolapra - Files Edited: maqstb_cfg.pl#152 - <br /> * Waiting 5us after frequency change in Step 3 of init sequence<br /> * ------------------------------------------------------------------<br /> * Version:22 - allin - Files Edited: maqs_gen_cfg.pl#12 - maqs_gen_cfg_h
<h4>0. AMC Prolog</h4>
<p>Program SPLL registers<br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == ONE_CH_ONE_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_mccchnldec = 0x00050200<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelHiBits = 0x5 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelTyp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChnlStartBit = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NumMcuChnl = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == ONE_CH_TWO_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_mccchnldec = 0x00050200<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelHiBits = 0x5 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelTyp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChnlStartBit = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NumMcuChnl = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == TWO_CH_TWO_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_mccchnldec = 0x00050210<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelHiBits = 0x5 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelTyp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChnlStartBit = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NumMcuChnl = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == TWO_CH_ONE_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_mccchnldec = 0x00050210<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelHiBits = 0x5 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelTyp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChnlStartBit = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NumMcuChnl = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcc_MccLockRegion_mccchnldec = 0x00050220<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelHiBits = 0x5 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelTyp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChnlStartBit = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NumMcuChnl = 0x2 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; spllctrl_SpllCtrl_ChargePump(n) = 0x00000068<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_cp_boost = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_cp_i_set = 0x3 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_cp_lp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_cp_md = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_cp_pd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_cp_r_set = 0x8 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; spllctrl_SpllCtrl_VCO(n) = 0x00000076<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_vco_buf_pd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_vco_cap = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_vco_kvco = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_vco_pd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_vco_rv2i = 0x6 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; spllctrl_SpllCtrl_VCO(n) = 0x00000078<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_vco_buf_pd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_vco_cap = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_vco_kvco = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_vco_pd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_vco_rv2i = 0x8 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; spllctrl_SpllCtrl_LDO(n) = 0x00000004<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_bg_start_sel = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_reg_pd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; slvpll_vreg_adj = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; spllctrl_SpllCtrl_SPLLPwrDnCfg(n) = 0x00000011<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; bypass_en_stby_pd = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; spll_fast_pd_exit = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; spll_mode_dcs_pwrdn = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; use_idle_for_pd = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Call custom API provided in mcu_helper_fxns.c for setting PLL3 frequency to 99Mhz. This call is only applicable to Cold boot. <br /><br /><b>FPGA:</b> Skip this step<br /><br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Call custom API provided in mcu_helper_fxns.c for setting PLL3 frequency to 99Mhz. This call is only applicable to Cold boot. <br /><br /><b>FPGA:</b> Skip this step<br /><br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>1. AMC Initial Configuration</h4>
<p>Perform the proper configurations of the AMC. Note that all the timing parameters should be programmed with respect to the normal clock, not the slow boot clock.<br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</table>
<h4> Setting up MCU registers and FSP for Freq change</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl0_freq0(n) = 0x18cd104d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_addr_freq0 = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_ctrl_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_data_freq0 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_addr_freq0 = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_ctrl_freq0 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_data_freq0 = 0x18 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl1_freq0(n) = 0x110c110e<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_addr_freq0 = 0xe <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_ctrl_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_data_freq0 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_addr_freq0 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_ctrl_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_data_freq0 = 0x11 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl2_freq0(n) = 0xb303000b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_addr_freq0 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_ctrl_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_data_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_addr_freq0 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_ctrl_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_data_freq0 = 0xb3 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl2_freq0(n) = 0xb303440b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_addr_freq0 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_ctrl_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_data_freq0 = 0x44 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_addr_freq0 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_ctrl_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_data_freq0 = 0xb3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl3_freq0(n) = 0xce012402<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_addr_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_ctrl_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_data_freq0 = 0x24 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_addr_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_ctrl_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_data_freq0 = 0xce <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl4_freq0(n) = 0x00000416<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_addr_freq0 = 0x16 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_ctrl_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_data_freq0 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_addr_freq0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_ctrl_freq0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_data_freq0 = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngtim_freq0(n) = 0x000c1108<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngclkofflat_freq0 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngclkonlat_freq0 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngsocupdlat_freq0 = 0xc <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl0_freq1(n) = 0x18cd104d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_addr_freq1 = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_ctrl_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_data_freq1 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_addr_freq1 = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_ctrl_freq1 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_data_freq1 = 0x18 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl1_freq1(n) = 0x110c110e<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_addr_freq1 = 0xe <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_ctrl_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_data_freq1 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_addr_freq1 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_ctrl_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_data_freq1 = 0x11 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl2_freq1(n) = 0xf303000b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_addr_freq1 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_ctrl_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_data_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_addr_freq1 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_ctrl_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_data_freq1 = 0xf3 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl2_freq1(n) = 0xf303020b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_addr_freq1 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_ctrl_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_data_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_addr_freq1 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_ctrl_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_data_freq1 = 0xf3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl3_freq1(n) = 0xae015202<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_addr_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_ctrl_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_data_freq1 = 0x52 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_addr_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_ctrl_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_data_freq1 = 0xae <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl4_freq1(n) = 0x00000416<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_addr_freq1 = 0x16 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_ctrl_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_data_freq1 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_addr_freq1 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_ctrl_freq1 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_data_freq1 = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngtim_freq1(n) = 0x000c1108<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngclkofflat_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngclkonlat_freq1 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngsocupdlat_freq1 = 0xc <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl0_freq2(n) = 0x18cd104d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_addr_freq2 = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_ctrl_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_data_freq2 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_addr_freq2 = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_ctrl_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_data_freq2 = 0x18 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl1_freq2(n) = 0x590c590e<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_addr_freq2 = 0xe <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_ctrl_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_data_freq2 = 0x59 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_addr_freq2 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_ctrl_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_data_freq2 = 0x59 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl2_freq2(n) = 0xf303000b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_addr_freq2 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_ctrl_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_data_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_addr_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_ctrl_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_data_freq2 = 0xf3 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl2_freq2(n) = 0xf303000b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_addr_freq2 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_ctrl_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_data_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_addr_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_ctrl_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_data_freq2 = 0xf3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl3_freq2(n) = 0x8e010002<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_addr_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_ctrl_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_data_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_addr_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_ctrl_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_data_freq2 = 0x8e <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl4_freq2(n) = 0x00000016<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_addr_freq2 = 0x16 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_ctrl_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_data_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_addr_freq2 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_ctrl_freq2 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_data_freq2 = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngtim_freq2(n) = 0x000c1108<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngclkofflat_freq2 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngclkonlat_freq2 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngsocupdlat_freq2 = 0xc <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl0_freq3(n) = 0x18cd104d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_addr_freq3 = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_ctrl_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw0_data_freq3 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_addr_freq3 = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_ctrl_freq3 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw1_data_freq3 = 0x18 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl1_freq3(n) = 0x590c590e<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_addr_freq3 = 0xe <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_ctrl_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_data_freq3 = 0x59 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_addr_freq3 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_ctrl_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_data_freq3 = 0x59 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl2_freq3(n) = 0xf303000b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_addr_freq3 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_ctrl_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_data_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_addr_freq3 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_ctrl_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_data_freq3 = 0xf3 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl2_freq3(n) = 0xf303000b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_addr_freq3 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_ctrl_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw4_data_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_addr_freq3 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_ctrl_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw5_data_freq3 = 0xf3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl3_freq3(n) = 0x8e010002<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_addr_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_ctrl_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw6_data_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_addr_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_ctrl_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw7_data_freq3 = 0x8e <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl4_freq3(n) = 0x00000016<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_addr_freq3 = 0x16 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_ctrl_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw8_data_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_addr_freq3 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_ctrl_freq3 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw9_data_freq3 = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngtim_freq3(n) = 0x000c1108<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngclkofflat_freq3 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngclkonlat_freq3 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngsocupdlat_freq3 = 0xc <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_rwcfg(n) = 0x000210ef<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CasAPEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIRDEn_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIRDEn_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIRDEn_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIRDEn_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIWREn_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIWREn_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIWREn_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIWREn_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIWRType = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCCDMWCyc = 0x2 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_rwcfg(n) = 0x000210ef<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CasAPEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIRDEn_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIRDEn_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIRDEn_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIRDEn_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIWREn_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIWREn_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIWREn_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIWREn_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DBIWRType = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCCDMWCyc = 0x2 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dllupdtctrl(n) = 0x50017350<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllInitUpdtDur = 0x7 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtDur = 0x3 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtMode = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtPhyUpdtTyp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqChangeSDLLUpdDur = 0x50 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SDLLUpdDur = 0x50 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscadllctl_dllupdtctrl(n) = 0x50017350<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllInitUpdtDur = 0x7 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtDur = 0x3 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtMode = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtPhyUpdtTyp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqChangeSDLLUpdDur = 0x50 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SDLLUpdDur = 0x50 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM timing parameters for default frequencyset. Example here shows LPDDR4-2667 8Gb DRAM die. See Section 3.2.2.4 for other value. <br /> Configure the PHY timing. These are determined by the design of the PHY and the interface between the PHY and AMC. </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq0(n) = 0x001030c2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq0 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq0 = 0x3 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq0 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq0(n) = 0x00103306<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq0 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq0 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq0 = 0x3 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq0 = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq1(n) = 0x001020c2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq1 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq1 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq1 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq1 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq1(n) = 0x00102206<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq1 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq1 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq1 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq1 = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_phytim_phyrdwrtim_freq0(n) = 0x00010c01<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYRdLat_freq0 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtPhyWrlat_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtRddataEn_freq0 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_phytim_phyrdwrtim_freq0(n) = 0x00050c0a<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYRdLat_freq0 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtPhyWrlat_freq0 = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtRddataEn_freq0 = 0xa <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_phytim_phyrdwrtim_freq1(n) = 0x00010b01<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYRdLat_freq1 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtPhyWrlat_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtRddataEn_freq1 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_phytim_phyrdwrtim_freq1(n) = 0x00050b06<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYRdLat_freq1 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtPhyWrlat_freq1 = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtRddataEn_freq1 = 0x6 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_phytim_phyrdwrtim_freq2(n) = 0x00010b01<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYRdLat_freq2 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtPhyWrlat_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtRddataEn_freq2 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_phytim_phyrdwrtim_freq2(n) = 0x00010b01<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYRdLat_freq2 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtPhyWrlat_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtRddataEn_freq2 = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_phytim_phyrdwrtim_freq3(n) = 0x00010901<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYRdLat_freq3 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtPhyWrlat_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtRddataEn_freq3 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_phytim_phyrdwrtim_freq3(n) = 0x00010901<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYRdLat_freq3 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtPhyWrlat_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PHYtRddataEn_freq3 = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq0(n) = 0x42110408<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq0 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq0 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq0 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq0 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq0 = 0x4 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq0(n) = 0x40c20402<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq0 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq0 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq0 = 0x4 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq0(n) = 0x531a060b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq0 = 0x1a <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq0 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq0 = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq0 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq0 = 0x6 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_act_freq0(n) = 0x10040908<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFAWCyc_freq0 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPCyc_freq0 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabCyc_freq0 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDCyc_freq0 = 0x4 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_act_freq0(n) = 0x01020202<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFAWCyc_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPCyc_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabCyc_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDCyc_freq0 = 0x2 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_act_freq0(n) = 0x18060d0b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFAWCyc_freq0 = 0x18 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPCyc_freq0 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabCyc_freq0 = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDCyc_freq0 = 0x6 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq0(n) = 0x24480078<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq0 = 0x78 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq0 = 0x48 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq0 = 0x24 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq0(n) = 0x01010078<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq0 = 0x78 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq0 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq0(n) = 0x366c0078<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq0 = 0x78 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq0 = 0x6c <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq0 = 0x36 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq0(n) = 0x50057012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq0 = 0x50 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq0 = 0x57 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq0 = 0x12 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq0(n) = 0x28002012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq0 = 0x28 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq0 = 0x12 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq0(n) = 0x78071012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq0 = 0x78 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq0 = 0x71 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq0 = 0x12 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_modereg(n) = 0x0e0a9084<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tMRRCyc = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tMRRICyc = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tMRWCyc = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tVRCGOFFCyc = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQLatCyc = 0xe <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_modereg(n) = 0x060a9024<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tMRRCyc = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tMRRICyc = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tMRWCyc = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tVRCGOFFCyc = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQLatCyc = 0x6 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_modereg(n) = 0x140a90b4<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tMRRCyc = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tMRRICyc = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tMRWCyc = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tVRCGOFFCyc = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQLatCyc = 0x14 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM timing parameters for alternative frequency points. For the dynamic frequency change support, all frequency sets should be programmed. See Section 3.2.2.3 for details. The actual values should correspond to the desired frequency points and the actual device specifications. <br />(N=1/2/3)<br />*since mcu_clk freq1 = 200MHz and per-bank refresh is not enabled,<br />mcusch.mifcassch_freq1. HiTempRefRnkAgeOut_freq1 =0x0 </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq1(n) = 0x42110408<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq1 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq1 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq1 = 0x4 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq1(n) = 0x40c20402<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq1 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq1 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq1 = 0x4 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq1(n) = 0x42110408<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq1 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq1 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq1 = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_act_freq1(n) = 0x01020202<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFAWCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDCyc_freq1 = 0x2 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_act_freq1(n) = 0x10040908<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFAWCyc_freq1 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPCyc_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabCyc_freq1 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDCyc_freq1 = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > **IMPORTANT** : For power saving on SOC's using Samsung and Hynix DRAM's, it's mandatory to set autoref_freq1 to 0x1C480050. For SOC's using Micron DRAM, autoref_freq1 should be set to 0x20480050. </td>
</tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq1(n) = 0x01010050<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq1 = 0x50 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq1 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq1(n) = 0x24480050<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq1 = 0x50 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq1 = 0x48 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq1 = 0x24 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq1(n) = 0x50057012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq1 = 0x50 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq1 = 0x57 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq1 = 0x12 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq1(n) = 0x28002012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq1 = 0x28 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq1 = 0x12 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq1(n) = 0x5004b012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq1 = 0x50 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq1 = 0x4b <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq1 = 0x12 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq2(n) = 0x42110408<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq2 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq2 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq2 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq2 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq2 = 0x4 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq2(n) = 0x40c20402<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq2 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq2 = 0x4 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq2(n) = 0x40c50402<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq2 = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq2 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq2 = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_act_freq2(n) = 0x10040908<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFAWCyc_freq2 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPCyc_freq2 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabCyc_freq2 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDCyc_freq2 = 0x4 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_act_freq2(n) = 0x01020202<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFAWCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDCyc_freq2 = 0x2 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_act_freq2(n) = 0x04020302<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFAWCyc_freq2 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabCyc_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDCyc_freq2 = 0x2 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq2(n) = 0x24480014<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq2 = 0x14 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq2 = 0x48 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq2 = 0x24 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq2(n) = 0x01010014<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq2 = 0x14 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq2 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq2(n) = 0x09120014<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq2 = 0x14 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq2 = 0x12 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq2 = 0x9 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq2(n) = 0x50057012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq2 = 0x50 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq2 = 0x57 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq2 = 0x12 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq2(n) = 0x28002012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq2 = 0x28 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq2 = 0x12 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq2(n) = 0x28013012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq2 = 0x28 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq2 = 0x13 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq2 = 0x12 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq3(n) = 0x42110408<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq3 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq3 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq3 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq3 = 0x4 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq3(n) = 0x40c20402<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq3 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq3 = 0x4 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_caspch_freq3(n) = 0x40c20402<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRTPCyc_freq3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWRCyc_freq3 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWTRCyc_freq3 = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Process act_freq3 for all platforms </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_act_freq3(n) = 0x10040b0a<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFAWCyc_freq3 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPCyc_freq3 = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabCyc_freq3 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDCyc_freq3 = 0x4 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_act_freq3(n) = 0x01020404<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFAWCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPCyc_freq3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabCyc_freq3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDCyc_freq3 = 0x2 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_act_freq3(n) = 0x02020404<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFAWCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPCyc_freq3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabCyc_freq3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDCyc_freq3 = 0x2 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq3(n) = 0x24480005<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq3 = 0x5 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq3 = 0x48 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq3 = 0x24 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq3(n) = 0x01010005<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq3 = 0x5 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq3 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq3(n) = 0x03050005<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq3 = 0x5 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq3 = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq3 = 0x3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq3(n) = 0x50057012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq3 = 0x50 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq3 = 0x57 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq3 = 0x12 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq3(n) = 0x28002012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq3 = 0x28 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq3 = 0x12 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_selfref_freq3(n) = 0x28006012<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tFCCyc_freq3 = 0x28 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXSRCyc_freq3 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tZQCalCyc_freq3 = 0x12 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_params(n) = 0x00150013<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFBWtRFCcnt = 0x15 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFICyc = 0x13 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_params(n) = 0x0015005d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFBWtRFCcnt = 0x15 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFICyc = 0x5d <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_pdn(n) = 0x31263263<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKECyc = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEPDECyc = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKESRCyc = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEafSRCyc = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEb4SRCyc = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKafCKECyc = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKb4CKECyc = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXPCyc = 0x3 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_pdn(n) = 0x21262222<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKECyc = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEPDECyc = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKESRCyc = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEafSRCyc = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEb4SRCyc = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKafCKECyc = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKb4CKECyc = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXPCyc = 0x2 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_pdn(n) = 0x62265295<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKECyc = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEPDECyc = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKESRCyc = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEafSRCyc = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEb4SRCyc = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKafCKECyc = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKb4CKECyc = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tXPCyc = 0x5 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq0(n) = 0x28835488<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq0 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq0 = 0x12 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq0 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq0 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq0 = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq0 = 0x5 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq0(n) = 0x08212082<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq0 = 0x2 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq0(n) = 0x38c486cc<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq0 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq0 = 0x1b <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq0 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq0 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq0 = 0xe <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq0 = 0x8 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq1(n) = 0x28835488<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq1 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq1 = 0x12 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq1 = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq1 = 0x5 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq1(n) = 0x08212082<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq1 = 0x2 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq1(n) = 0x28835488<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq1 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq1 = 0x12 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq1 = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq1 = 0x5 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq2(n) = 0x28835488<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq2 = 0x12 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq2 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq2 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq2 = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq2 = 0x5 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq2(n) = 0x08212082<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq2 = 0x2 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq2(n) = 0x0c212142<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq2 = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq2 = 0x2 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq3(n) = 0x30a35488<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq3 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq3 = 0x12 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq3 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq3 = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq3 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq3 = 0x5 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq3(n) = 0x10412082<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq3 = 0x2 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_derate_freq3(n) = 0x10412082<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxDrtCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRASDrtCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRCDDrtCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPDrtCyc_freq3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRPabDrtCyc_freq3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRRDDrtCyc_freq3 = 0x2 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq0(n) = 0x00112306<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq0 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq0 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq0 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq0(n) = 0x001110c2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq0 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq0 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq0(n) = 0x00113306<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq0 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq0 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq0 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq0 = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq1(n) = 0x00112206<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq1 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq1 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq1(n) = 0x001110c2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq1 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq1 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq1(n) = 0x00112206<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq1 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq1 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq1 = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq2(n) = 0x001120c2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq2 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq2(n) = 0x001110c2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq2 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq2(n) = 0x001110c2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq2 = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq3(n) = 0x001120c2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq3 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq3 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq3(n) = 0x001110c2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq3 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq3 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_lat_freq3(n) = 0x001110c2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMRL_freq3 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DRAMWL_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMaxCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSCKMinCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tDQSSMaxCyc_freq3 = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_tat_freq0(n) = 0x01212222<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rRnkMissTatDeadCyc_freq0 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rTatDeadCyc_freq0 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wRnkMissTatDeadCyc_freq0 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wTatDeadCyc_freq0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2rRnkMissTatDeadCyc_freq0 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wRnkMissTatDeadCyc_freq0 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wTatDeadCyc_freq0 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_tat_freq0(n) = 0x01312222<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rRnkMissTatDeadCyc_freq0 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rTatDeadCyc_freq0 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wRnkMissTatDeadCyc_freq0 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wTatDeadCyc_freq0 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2rRnkMissTatDeadCyc_freq0 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wRnkMissTatDeadCyc_freq0 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wTatDeadCyc_freq0 = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_tat_freq1(n) = 0x01212222<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rRnkMissTatDeadCyc_freq1 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rTatDeadCyc_freq1 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wRnkMissTatDeadCyc_freq1 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wTatDeadCyc_freq1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2rRnkMissTatDeadCyc_freq1 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wRnkMissTatDeadCyc_freq1 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wTatDeadCyc_freq1 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_tat_freq1(n) = 0x01312222<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rRnkMissTatDeadCyc_freq1 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rTatDeadCyc_freq1 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wRnkMissTatDeadCyc_freq1 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wTatDeadCyc_freq1 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2rRnkMissTatDeadCyc_freq1 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wRnkMissTatDeadCyc_freq1 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wTatDeadCyc_freq1 = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_tat_freq2(n) = 0x01312222<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rRnkMissTatDeadCyc_freq2 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rTatDeadCyc_freq2 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wRnkMissTatDeadCyc_freq2 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wTatDeadCyc_freq2 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2rRnkMissTatDeadCyc_freq2 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wRnkMissTatDeadCyc_freq2 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wTatDeadCyc_freq2 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_tat_freq2(n) = 0x01212222<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rRnkMissTatDeadCyc_freq2 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rTatDeadCyc_freq2 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wRnkMissTatDeadCyc_freq2 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wTatDeadCyc_freq2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2rRnkMissTatDeadCyc_freq2 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wRnkMissTatDeadCyc_freq2 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wTatDeadCyc_freq2 = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_tat_freq3(n) = 0x01312222<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rRnkMissTatDeadCyc_freq3 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rTatDeadCyc_freq3 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wRnkMissTatDeadCyc_freq3 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wTatDeadCyc_freq3 = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2rRnkMissTatDeadCyc_freq3 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wRnkMissTatDeadCyc_freq3 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wTatDeadCyc_freq3 = 0x1 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_tat_freq3(n) = 0x01212222<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rRnkMissTatDeadCyc_freq3 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2rTatDeadCyc_freq3 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wRnkMissTatDeadCyc_freq3 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R2wTatDeadCyc_freq3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2rRnkMissTatDeadCyc_freq3 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wRnkMissTatDeadCyc_freq3 = 0x2 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; W2wTatDeadCyc_freq3 = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_rnkcfg(n) = 0x00006061<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rnk0Odts = 0x6 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rnk0Valid = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rnk1Odts = 0x6 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rnk1Valid = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_mifqctrl_mifqmaxctrl_freq0(n) = 0x00000100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiTempMifQMax_freq0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MifQMaxAlways = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_mifqctrl_mifqmaxctrl_freq3(n) = 0x00000003<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiTempMifQMax_freq3 = 0x3 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_mifqctrl_mifqmaxctrl_freq3(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiTempMifQMax_freq3 = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn off optional power- savingfeatures. This includes dynamic power down, auto self-refresh entry, and clock stopping. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_pwrmngten(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AutoSR = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DynPwrDnEn = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; McPhyUpdDramClkOff = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PwrDnClkOff = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRClkOff = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitOpt = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn off optional power- savingfeatures. This includes dynamic power down, auto self-refresh entry, and clock stopping. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_odtszqc(n) = 0x00002000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DerateParamSRExit = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OdtsRdIntrvl = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitZQCChnlQuiet = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ShareZQRes = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TempDrtEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCChnlQuiet = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCStack = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZqCalIntrvl = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn off transaction scheduling for non- initialization commands </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_amcgen_amcctrl(n) = 0x00000002<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; McuEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SchEn = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_mcphyupdtparam(n) = 0x15030000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqCSettleCyc = 0x5 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; McPhyTimeParamCyc = 0x3 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyInitStartCyc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyUpdMDLL = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; UpdPhyLatCyc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tPhyUpdGap = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program AMC to <br /> - wait tXP+2tCK after actual clock changes before valid command<br /> - wait 2 cycles after all timing parameter are satisfied before actual clock change<br /> - wait indefinitely for AMP to complete handshake. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_mcphyupdtparam(n) = 0x15030000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqCSettleCyc = 0x5 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; McPhyTimeParamCyc = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyInitStartCyc = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyUpdMDLL = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; UpdPhyLatCyc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tPhyUpdGap = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>2. AMP Initial Configurations</h4>
<p>Perform the proper configurations of the AMP. There are two separate AMP register blocks; the code below must be repeated on both AMP0 and AMP1. (N=0..1)<br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert AMP enable </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscagen_ampen(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AmpEn = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert AMP enable </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqgen_ampen(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AmpEn = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_nondqdspd_f0(n) = 0x000b316b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaDsPd_f0 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck0DsPd_f0 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck1DsPd_f0 = 0xc *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsDsPd_f0 = 0xb <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_nondqdspd_f1(n) = 0x000b216b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaDsPd_f1 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck0DsPd_f1 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck1DsPd_f1 = 0x8 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsDsPd_f1 = 0xb <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_nondqdspd_f2(n) = 0x000b3d6b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaDsPd_f2 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck0DsPd_f2 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck1DsPd_f2 = 0xf *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsDsPd_f2 = 0xb <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_nondqdspd_f3(n) = 0x000b3d6b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaDsPd_f3 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck0DsPd_f3 = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck1DsPd_f3 = 0xf *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsDsPd_f3 = 0xb <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_nondqds_f1(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaDs_f1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck0Ds_f1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck1Ds_f1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsDs_f1 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_nondqds_f2(n) = 0x00083d08<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaDs_f2 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck0Ds_f2 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck1Ds_f2 = 0xf *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsDs_f2 = 0x8 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_nondqds_f3(n) = 0x00083d08<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaDs_f3 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck0Ds_f3 = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ck1Ds_f3 = 0xf *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsDs_f3 = 0x8 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_CaCkCsWkDs(n) = 0x000000db<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaWkDs = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CkWkDs = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsWkDs = 0x3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaodt_VRef_f0(n) = 0x00000003<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VRefSel = 0x3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaodt_VRef_f1(n) = 0x00000003<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VRefSel = 0x3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaodt_VRef_f2(n) = 0x00000003<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VRefSel = 0x3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaodt_VRef_f3(n) = 0x00000003<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VRefSel = 0x3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > ODTEnable_f0 </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ODTEnable = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ODTEnable = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ODTEnable = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > ODTEnable_f1 </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ODTEnable = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ODTEnable = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ODTEnable = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > ODTEnable_f3 </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaodt_ODTEnable_f3(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ODTEnable = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_dqds_f0(n) = 0x000c0b08<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDqODTDs = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqPdDs = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqPuDs = 0x8 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_dqds_f1(n) = 0x00080b00<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDqODTDs = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqPdDs = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqPuDs = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_dqds_f2(n) = 0x00080b00<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDqODTDs = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqPdDs = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqPuDs = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_dqds_f3(n) = 0x00080b00<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDqODTDs = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqPdDs = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqPuDs = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_dqdqsds_f0(n) = 0x00030b08<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDqDqsODTDs = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsPdDs = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsPuDs = 0x8 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_dqdqsds_f1(n) = 0x00010b00<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDqDqsODTDs = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsPdDs = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsPuDs = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_dqdqsds_f2(n) = 0x00080b00<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDqDqsODTDs = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsPdDs = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsPuDs = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_dqdqsds_f3(n) = 0x00080b00<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDqDqsODTDs = 0x8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsPdDs = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsPuDs = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqodt_VRef_f0(n) = 0x00c000c0<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsVRefSel = 0xc0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VRefSel = 0xc0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > **IMPORTANT** : For power saving on SOC's these setings are mandatory. With Samsung DRAM, VRef_f1 should be set to 0x00EC00EC. With Micron DRAM, VRef_f1 should be set to 0x00EA00EA. With Hynix DRAM, VRef_f1 should be set to 0x00DF00DF. </td>
</tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqodt_VRef_f1(n) = 0x00df00df<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsVRefSel = 0xdf <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VRefSel = 0xdf <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_dqspdres(n) = 0x00000031<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdVal = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsWkPuPdVal = 0x3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscasdllctrl_SDLLUpdateCtrl(n) = 0x0303030b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ClkEn2Valid = 0x3 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ReqWaitDelay = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Valid2ClkEn = 0x3 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ValidLen = 0x3 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqsdllctrl_SDLLUpdateCtrl(n) = 0x0003000b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ClkEn2Valid = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ReqWaitDelay = 0xb <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Valid2ClkEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ValidLen = 0x3 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_diffmode_freq3(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqInVrefMode_f3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsInDiffMode_f3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsOutDiffMode_f3 = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqsdllctrl_rd0sdllctrl(n) = 0x00ff0004<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rd0RunSDLLUpd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rd0RunSDLLUpdOverride = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rd0RunSDLLUpdWrResult = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rd0SDLLOvrVal = 0xff <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampsdqsdllctrl rd0sdllctrl </td>
<td><table class="platform">
<tr><td class="programming"> Poll: ampsdqsdllctrl_rd0sdllctrl<br />
&nbsp;&nbsp;&nbsp; Rd0RunSDLLUpdWrResult<br />
&nbsp;&nbsp;&nbsp;while((CSR(ampsdq_ampsdqsdllctrl_rd0sdllctrl(n)) & 0x4) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000004<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsRunSDLLUpd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsRunSDLLUpdOverride = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsRunSDLLUpdWrResult = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsWrLvlReBalanceEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f1 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f2 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f3 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLHalfClkEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLOvrVal = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqsSDLLOvrVal = 0xff <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampsdqsdllctrl WrDqDqsSDLLCtrl </td>
<td><table class="platform">
<tr><td class="programming"> Poll: ampsdqsdllctrl_WrDqDqsSDLLCtrl<br />
&nbsp;&nbsp;&nbsp; WrDqDqsRunSDLLUpdWrResult<br />
&nbsp;&nbsp;&nbsp;while((CSR(ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n)) & 0x4) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscawrlvl_ampcawrlvlsdllcode(n) = 0x00ff02ff<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrLvlMaxWrDqsSDLLCode = 0xff *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrLvlRunUpdOverride = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrLvlRunUpdWrResult = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrLvlSDLLCode = 0xff <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampscawrlvl ampcawrlvlsdllcode </td>
<td><table class="platform">
<tr><td class="programming"> Poll: ampscawrlvl_ampcawrlvlsdllcode<br />
&nbsp;&nbsp;&nbsp; WrLvlRunUpdWrResult<br />
&nbsp;&nbsp;&nbsp;while((CSR(ampsca_ampscawrlvl_ampcawrlvlsdllcode(n)) & 0x200) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscadllctl_dlllocktim(n) = 0x012c012c<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllIncLockTim = 0x12c <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllInitLockTim = 0x12c <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dlllocktim(n) = 0x012c012c<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllIncLockTim = 0x12c <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllInitLockTim = 0x12c <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_dqsPdEnAlwaysOn(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEnAlwaysOn = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_DFICalTiming(n) = 0x04000410<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAEntry = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAExit = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHEntry = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHExit = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_DFICalTiming2_DFICalTiming_f1(n) = 0x04000410<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAEntry_f1 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAExit_f1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHEntry_f1 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHExit_f1 = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_DFICalTiming2_DFICalTiming_f2(n) = 0x04000410<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAEntry_f2 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAExit_f2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHEntry_f2 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHExit_f2 = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_DFICalTiming2_DFICalTiming_f3(n) = 0x04000410<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAEntry_f3 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAExit_f3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHEntry_f3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHExit_f3 = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_DFICalTiming_DFICalTiming_f0(n) = 0x04020402<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAEntry_f0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAExit_f0 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHEntry_f0 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHExit_f0 = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_DFICalTiming_DFICalTiming_f1(n) = 0x04020402<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAEntry_f1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAExit_f1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHEntry_f1 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHExit_f1 = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_DFICalTiming_DFICalTiming_f2(n) = 0x04020402<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAEntry_f2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAExit_f2 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHEntry_f2 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHExit_f2 = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_DFICalTiming_DFICalTiming_f3(n) = 0x04020402<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAEntry_f3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCA2CAExit_f3 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHEntry_f3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tCKEHExit_f3 = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_MDLLCodeCaptureControl(n) = 0x00000002<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MDLLLoopCnt = 0x2 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_RdWrDqCalTiming_f0(n) = 0x00001426<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CoarseStepSize = 0x4 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FineStepSize = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRL = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWL = 0x2 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f0(n) = 0x00010002<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRdDqCalSegLen = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWrDqCalSegLen = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_RdWrDqCalTiming_f1(n) = 0x00001422<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CoarseStepSize = 0x4 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FineStepSize = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRL = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWL = 0x2 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f1(n) = 0x00010002<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRdDqCalSegLen = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWrDqCalSegLen = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_HWRdWrDqCalTimingCtrl1(n) = 0x0000301e<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRd2SDLL = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tSDLL2Rd = 0x1e <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tSDLL2Wr = 0x30 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWr2SDLL = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_HWRdWrDqCalTimingCtrl2(n) = 0x03111004<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRd2Rd = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRd2Wr = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWr2Rd = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWr2Wr = 0x3 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_HWRdDqCalPatPRBS4I(n) = 0x55555e26<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PatInvertMask = 0x5555 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PatPRBS4 = 0x5e26 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS4I(n) = 0x55555e26<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PatInvertMask = 0x5555 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PatPRBS4 = 0x5e26 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_RdDqCalWindow_f0(n) = 0x00aa01d1<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; EndPoint = 0xaa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; StartPoint = 0x1d1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_WrDqCalWindow_f0(n) = 0x00ca0160<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; EndPoint = 0xca <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; StartPoint = 0x160 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_RdDqCalWindow_f1(n) = 0x00aa01d1<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; EndPoint = 0xaa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; StartPoint = 0x1d1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_WrDqCalWindow_f1(n) = 0x00ca0160<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; EndPoint = 0xca <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; StartPoint = 0x160 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_MaxWrDqsSDLLMulFactor(n) = 0xa0a0080c<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MaxWrDqsSDLLCodeStatusF0 = 0xa0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MaxWrDqsSDLLCodeStatusF1 = 0xa0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqsSDLLMulFactorF0 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqsSDLLMulFactorF1 = 0x8 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqMulFactor_RdDqsMulFactor(n) = 0x20181000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Factor0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Factor1 = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Factor2 = 0x18 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Factor3 = 0x20 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscadllctl_caoutdllscl_freq0(n) = 0x00000008<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaOutDllScl_f0 = 0x8 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dqsindll0scl_freq0(n) = 0x00000008<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsInDll0Scl_f0 = 0x8 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program capture latency and recapture latency </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_rdcapcfg_freq0(n) = 0x0100070a<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIeDeAssertPullIn_f0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEn_f0 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCapLat_f0 = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDatLat_f0 = 0x7 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrPhaseDelay_f0 = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_rdcapcfg_freq0(n) = 0x01000606<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIeDeAssertPullIn_f0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEn_f0 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCapLat_f0 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDatLat_f0 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrPhaseDelay_f0 = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_rdcapcfg_freq0(n) = 0x0100070d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIeDeAssertPullIn_f0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEn_f0 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCapLat_f0 = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDatLat_f0 = 0x7 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrPhaseDelay_f0 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscadllctl_caoutdllscl_freq1(n) = 0x0000000d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaOutDllScl_f1 = 0xd <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dqsindll0scl_freq1(n) = 0x0000000d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsInDll0Scl_f1 = 0xd <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program capture latency and recapture latency </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_rdcapcfg_freq1(n) = 0x21000606<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIeDeAssertPullIn_f1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEn_f1 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCapLat_f1 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDatLat_f1 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrPhaseDelay_f1 = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_rdcapcfg_freq1(n) = 0x2100060a<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIeDeAssertPullIn_f1 = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEn_f1 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCapLat_f1 = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDatLat_f1 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrPhaseDelay_f1 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscadllctl_caoutdllscl_freq2(n) = 0x00000030<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaOutDllScl_f2 = 0x30 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dqsindll0scl_freq2(n) = 0x00000030<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsInDll0Scl_f2 = 0x30 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program capture latency and recapture latency </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_rdcapcfg_freq2(n) = 0x4100040a<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIeDeAssertPullIn_f2 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEn_f2 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCapLat_f2 = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDatLat_f2 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrPhaseDelay_f2 = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_rdcapcfg_freq2(n) = 0x41000606<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIeDeAssertPullIn_f2 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEn_f2 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCapLat_f2 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDatLat_f2 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrPhaseDelay_f2 = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_rdcapcfg_freq2(n) = 0x41000406<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIeDeAssertPullIn_f2 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEn_f2 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCapLat_f2 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDatLat_f2 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrPhaseDelay_f2 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscadllctl_caoutdllscl_freq3(n) = 0x0000003f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CaOutDllScl_f3 = 0x3f <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL scaling factors (assuming freq0/1/2/3 = 522/400/200/50MHz, FMCLK=522 MHz) </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dqsindll0scl_freq3(n) = 0x0000003f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsInDll0Scl_f3 = 0x3f <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program capture latency and recapture latency </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_rdcapcfg_freq3(n) = 0x6100040a<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIeDeAssertPullIn_f3 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEn_f3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCapLat_f3 = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDatLat_f3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrPhaseDelay_f3 = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_rdcapcfg_freq3(n) = 0x61000606<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIeDeAssertPullIn_f3 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEn_f3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCapLat_f3 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDatLat_f3 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrPhaseDelay_f3 = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqrdtim_rdcapcfg_freq3(n) = 0x61000406<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIeDeAssertPullIn_f3 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsPdEn_f3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCapLat_f3 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdDatLat_f3 = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrPhaseDelay_f3 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Updating the programming of DLL*UpdtDur Fields<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscadllctl_dllupdtctrl(n) = 0x50017550<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllInitUpdtDur = 0x7 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtDur = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtMode = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtPhyUpdtTyp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqChangeSDLLUpdDur = 0x50 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SDLLUpdDur = 0x50 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Updating the programming of DLL*UpdtDur Fields<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dllupdtctrl(n) = 0x50017550<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllInitUpdtDur = 0x7 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtDur = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtMode = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtPhyUpdtTyp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqChangeSDLLUpdDur = 0x50 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SDLLUpdDur = 0x50 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_impautocal(n) = 0x00010000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; impautocalen = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; impcalintvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; impcaltype = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscadllctl_dllupdtintvl(n) = 0x10200020<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllFastUpdtAlwaysON = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllFastUpdtIntvl = 0x20 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtAlwaysON = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtIntvl = 0x20 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dllupdtintvl(n) = 0x10200020<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllFastUpdtAlwaysON = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllFastUpdtIntvl = 0x20 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtAlwaysON = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllUpdtIntvl = 0x20 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable DLL </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscadllctl_dllen(n) = 0x00000100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DLLEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MDllReset = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable DLL </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dllen(n) = 0x00000100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DLLEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MDllReset = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Run impedance calibration and optionally enable periodic auto impedance calibration<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_impcalcmd(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunImpCal = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunImpCalType = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_BISTRxMode(n) = 0x0000001c<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BISTRxMode = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BISTRxODT = 0x7 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BISTRxODTEn = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amph_SLC_SLC_REG0(n) = 0x0000003f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; pad_ca0_slc = 0xf <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; pad_ca1_slc = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; pad_ca2_slc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; pad_ca3_slc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; pad_ca4_slc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; pad_ca5_slc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; pad_ck_slc = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert init_done </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscagen_ampinit(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; InitDone = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert init_done </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqgen_ampinit(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; InitDone = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>3. Self-Refresh Exit</h4>
<p>Prior to this step, the DRAM is assumed to be in the self-refresh state, and CKE has been kept low, either by retention circuitry in the PHY/IO, or, after SOC power is up and the reset is done, by the controller. This step will take DRAM out of the self-refresh mode. Software must guarantee that at least 50 us have passed since the de- assertion of AMC reset before self-refresh exit, in the resume-boot case.
The frequency change to 50MHz here is initiated by PMGR.
For ResumeBoot, the auto-refresh must be enabled before exiting self-refresh state.<br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 5us after Impedance Calibration in Step2. This is to avoid McPhyPending preventing the SRFSM from exiting SR. </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > radar #8707478 has been fixed. SetSRExitRefCnt to 2. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_arefparam(n) = 0x0d010019<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqChngWaitThr = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyUpdWaitRefresh = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyUpdWaitThr = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyUpdWaittXSR = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefAssertCnt = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitRefCnt = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq3(n) = 0x24480050<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq3 = 0x50 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq3 = 0x48 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq3 = 0x24 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq3(n) = 0x01010001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq3 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq3(n) = 0x03050005<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq3 = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq3 = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq3 = 0x3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq2(n) = 0x24480050<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq2 = 0x50 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq2 = 0x48 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq2 = 0x24 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq2(n) = 0x01010001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq2 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq2(n) = 0x09120013<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq2 = 0x13 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq2 = 0x12 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq2 = 0x9 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > **IMPORTANT** : For power saving on SOC's using Samsung and Hynix DRAM's, it's mandatory to set autoref_freq1 to 0x1C480049. For SOC's using Micron DRAM, autoref_freq1 should be set to 0x20480049. </td>
</tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq1(n) = 0x01010001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq1 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq1(n) = 0x24480049<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq1 = 0x49 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq1 = 0x48 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq1 = 0x24 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq0(n) = 0x24480050<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq0 = 0x50 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq0 = 0x48 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq0 = 0x24 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq0(n) = 0x01010001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq0 = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_freq0(n) = 0x366c006e<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCBaseCyc_freq0 = 0x6e <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCCyc_freq0 = 0x6c <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRFCpbCyc_freq0 = 0x36 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_params(n) = 0x0017005d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFBWtRFCcnt = 0x17 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFICyc = 0x5d <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_params(n) = 0x00170013<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFBWtRFCcnt = 0x17 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFICyc = 0x13 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramtim_autoref_params(n) = 0x0017005d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFBWtRFCcnt = 0x17 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFICyc = 0x5d <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable auto refresh derating by setting TempDrtEn to 1. However, we do not enable ODTS interval until the end of the init. Setting TempDrtEn to 1 allows the chip to be in the hi-temp state and become more conservative. </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_odtszqc(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DerateParamSRExit = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OdtsRdIntrvl = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitZQCChnlQuiet = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ShareZQRes = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TempDrtEn = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCChnlQuiet = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCStack = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZqCalIntrvl = 0x0 *read-only<br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_odtszqc(n) = 0x00001000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DerateParamSRExit = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OdtsRdIntrvl = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitZQCChnlQuiet = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ShareZQRes = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TempDrtEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCChnlQuiet = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCStack = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZqCalIntrvl = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > set SRExtraRefCnt to correct value (which is 1) and set LongSRCnt to be tREFW/4 (32ms/4=8ms) <br /> If RefCntrHiWaterMark is changed from its default value, then LongSRExitRefCnt needs to be programmed to the same value.<br /> Palladium: LongSRCnt=0x1004 because Palladium uses 1Gb device. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_longsr(n) = 0x01022008<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LongSRCnt = 0x2008 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LongSRExitRefCnt = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExtraRefCnt = 0x2 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_mcphyupdtparam(n) = 0x15030007<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqCSettleCyc = 0x5 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; McPhyTimeParamCyc = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyInitStartCyc = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyUpdMDLL = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; UpdPhyLatCyc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tPhyUpdGap = 0x7 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Call custom API provided by PMGR for changing mcu_clk to 55Mhz and mcu_fixed_clk to Mhz<br /> // TO BE COMPLETED<br /><br /><b>FPGA:</b> Skip this step<br /><br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 5us to avoid a race condition between frequency change to bucket 3 & MCU being enabled </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on enables for various AMC blocks MCU. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_amcgen_amcctrl(n) = 0x00000003<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; McuEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SchEn = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Run impedance calibration and optionally enable periodic auto impedance calibration<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_impcalcmd(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunImpCal = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunImpCalType = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampscaiocfg impcalcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: ampscaiocfg_impcalcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunImpCal<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(ampsca_ampscaiocfg_impcalcmd(n)) & 0x1) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_arefen_freq3(n) = 0x10100000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ARpbEn_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiTempRefRnkAgeOut_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrHiWaterMark_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrLoWaterMark_freq3 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_arefen_freq2(n) = 0x10000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ARpbEn_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiTempRefRnkAgeOut_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrHiWaterMark_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrLoWaterMark_freq2 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_arefen_freq1(n) = 0x10110000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ARpbEn_freq1 = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiTempRefRnkAgeOut_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrHiWaterMark_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrLoWaterMark_freq1 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on auto refresh. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_arefen_freq0(n) = 0x1011013f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ARpbEn_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AutoRefEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AutoRefSchEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DisableHiTempREFab = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; EarlyCasAgeOut = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiPriREFpbPch = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiTempRefRnkAgeOut_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; REFpb2bank = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; REFpbEarlyPch = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrHiWaterMark_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrLoWaterMark_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefOpptEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFBWREFpb = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 200us for tINIT1 in real init, which we have cooked down to 200ns for simulation. </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 2 ms for tINIT3 in real init, which we have cooked down to 200ns for simulation. </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl(n) = 0x00010000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngfspop = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq1 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq2 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq3 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngrunsocupd = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcfg freqchngctl </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcfg_freqchngctl<br />
&nbsp;&nbsp;&nbsp; freqchngrunsocupd<br />
&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcfg_freqchngctl(n)) & 0x10000) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngfspop = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq1 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq2 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq3 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngrunsocupd = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 2us for the soc update to finish </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert MPC to Sending SR Exit during Resume Boot </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x00004000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Issue self-refresh exit command. One for each channel.<br /> SW needs to guarantee that at least 50usec has passed since removal of reset to AMC before issuing the self-refresh exit command, in case of resume boot. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x00004001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x1) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Assert MPC to Sending SR Exit during Resume Boot </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Issue self-refresh exit command. One for each channel.<br /> SW needs to guarantee that at least 50usec has passed since removal of reset to AMC before issuing the self-refresh exit command, in case of resume boot. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x1) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 2 us for tINIT5 in real init, which we have cooked down to 200ns for simulation. </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_ChEn = 0x0000000f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChEn = 0xf <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4> 4. DRAM Reset, ZQ Calibration & Configuration (Cold Boot Only).</h4>
<p> This step is only required for ColdBoot.
This step is to be repeated for each of the number of ranks per channel. The dramcmd.mrcmdch{N}.MRCmdCsCh{N} bit (Noted by letter R in the section) should be incremented in each loop.<br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Issue DRAM ZQ calibration START MPC command MRINIT CMD registers.<br /> Note that the MPC command can be issued to different channels independently, as long as the system has separate ZQ reference resistor for eachchannel. TheZQcalibration MPC to each rank within the same channel must be issued in series. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x4f004100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 1us for tZQCAL. </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Issue DRAM ZQ calibration LATCH MPC command MRINIT CMD registers </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x51004100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 20ns for tZQLAT. </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM MR2 register (latency) through MRR/MRW command registers. The example shows the nominal programming for LPDDR2-1066 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x00020100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM MR1 register through MRR/MRW command registers.<br /> This includes the following: WC=Wrap BT=Sequential BL=BL16.<br /> nWR, the example shows the nominal programming for LPDDR3- 1600 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x8e010100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0xf3030100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x00160100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x000b0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program MR11 for FPGA<br /><br /> <b>FPGA</b>: Perform this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x000b0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Perform this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program VRCG and Modified Refresh to 1 </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x180d0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x590c0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x590e0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x80170100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program MR15/20 to match PatInvertMask of HW RdDQ calibration </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x550f4100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program MR15/20 to match PatInvertMask of HW RdDQ calibration </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x55144100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program MR32/40 to match the PatPRBS4 pattern for HW RdDQ calibration </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x26204100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program MR32/40 to match the PatPRBS4 pattern for HW RdDQ calibration </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x5e284100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></table>
<h4>5. Topology-specific configuration.</h4>
<p>Here we perform MRR's to the memory to find out device density and program addrcfg, DramAccCtrl and mccchnldec registers<br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == ONE_CH_TWO_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_addrcfg = 0x01030201<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BnkAddrWid = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ColAddrWid = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsWid = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RowAddrWid = 0x3 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == TWO_CH_TWO_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_addrcfg = 0x01030201<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BnkAddrWid = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ColAddrWid = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsWid = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RowAddrWid = 0x3 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FOUR_CH_TWO_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_addrcfg = 0x01030201<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BnkAddrWid = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ColAddrWid = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsWid = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RowAddrWid = 0x3 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcc_MccLockRegion_addrcfg = 0x00030201<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BnkAddrWid = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ColAddrWid = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CsWid = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RowAddrWid = 0x3 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA_LPDDR3)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_DramAccCtrl = 0x00000007<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramSize = 0x7 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == ONE_CH_ONE_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_DramAccCtrl = 0x00000003<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramSize = 0x3 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == ONE_CH_TWO_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_DramAccCtrl = 0x00000007<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramSize = 0x7 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FOUR_CH_ONE_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_DramAccCtrl = 0x0000000f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramSize = 0xf <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == TWO_CH_TWO_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_DramAccCtrl = 0x0000000f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramSize = 0xf <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_DramAccCtrl = 0x0000000f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramSize = 0xf <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FOUR_CH_TWO_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_DramAccCtrl = 0x0000001f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramSize = 0x1f <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == TWO_CH_ONE_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_DramAccCtrl = 0x00000007<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramSize = 0x7 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcc_MccLockRegion_DramAccCtrl = 0x0000000f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramSize = 0xf <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > dram_Density_config(); </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == ONE_CH_ONE_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_mccchnldec = 0x00050201<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelHiBits = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelTyp = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChnlStartBit = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NumMcuChnl = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == ONE_CH_TWO_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_mccchnldec = 0x00060201<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelHiBits = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelTyp = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChnlStartBit = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NumMcuChnl = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == TWO_CH_TWO_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_mccchnldec = 0x00060210<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelHiBits = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelTyp = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChnlStartBit = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NumMcuChnl = 0x1 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FOUR_CH_TWO_RANK)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_MccLockRegion_mccchnldec = 0x00060220<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelHiBits = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelTyp = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChnlStartBit = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NumMcuChnl = 0x2 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcc_MccLockRegion_mccchnldec = 0x00050220<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelHiBits = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChSelTyp = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ChnlStartBit = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NumMcuChnl = 0x2 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>6. Prepare for switch from boot-clock speed to normal operation speed</h4>
<p>The frequency change is initiated by PMGR.<br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 5us before issuing a freq change to make sure all refreshes have been flushed. </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable AMC scheduler to allow normal transactions to be processed. <br /> Scheduler has to be enabled to let AMC issue self-refresh entry and allow frequency change. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_amcgen_amcctrl(n) = 0x00000003<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; McuEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SchEn = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>7. Setup registers for CA calibration for bucket 1</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FSP-WR to 1, and set VRCG and modified refresh </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x580d0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM MR2 register (latency) through MRR/MRW command registers. The example shows the nominal programming for LPDDR2-1066 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices.<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x52020100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM MR1 register through MRR/MRW command registers.<br /> This includes the following: WC=Wrap BT=Sequential BL=BL16.<br /> nWR, the example shows the nominal programming for LPDDR3- 1600 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices.<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0xae010100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0xf3030100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x04160100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x020b0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Perform this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x000b0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Perform this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x110c0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x110e0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscawrlvl_ampcawrlvlsdllcode(n) = 0x00000200<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrLvlMaxWrDqsSDLLCode = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrLvlRunUpdOverride = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrLvlRunUpdWrResult = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrLvlSDLLCode = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampscawrlvl ampcawrlvlsdllcode </td>
<td><table class="platform">
<tr><td class="programming"> Poll: ampscawrlvl_ampcawrlvlsdllcode<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrLvlRunUpdWrResult<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(ampsca_ampscawrlvl_ampcawrlvlsdllcode(n)) & 0x200) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></table>
<h4>8. AMP Dynamic Address Timing Calibration</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step8Calibration(0, LPDDR3, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, CA_CALIB, 0, 0, 0, 0, 0, 0, 1, 16, 12);<br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscadllctl_dlllocktim(n) = 0x00130013<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllIncLockTim = 0x13 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllInitLockTim = 0x13 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dlllocktim(n) = 0x00130013<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllIncLockTim = 0x13 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllInitLockTim = 0x13 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Disable AMP Clock Gating for RunDllUpdt to go through<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscagen_ampclk(n) = 0x00100001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FMClkIdleDetectEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceDRAMClkEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceDiv2MClkTopGaterOn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceFMClkWakeUp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceMClkWakeUp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TopClkGateDis = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Defer SDLL update until frequency change </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscasdllctrl_SDLLUpdateDeferEn(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DeferEn = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Defer SDLL update until frequency change </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqsdllctrl_SDLLUpdateDeferEn(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DeferEn = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Set MDLL override to 0 </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_MDLLOverride(n) = 0x00010000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MDLLOvrCode = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MDLLOvrSel = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Run MDLL update </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dllupdtcmd(n) = 0x00000001<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunDllUpdt = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampsdqdllctl dllupdtcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: ampsdqdllctl_dllupdtcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunDllUpdt<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(ampsdq_ampsdqdllctl_dllupdtcmd(n)) & 0x1) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable back AMP Clock Gating for RunDllUpdt to go through<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscagen_ampclk(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FMClkIdleDetectEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceDRAMClkEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceDiv2MClkTopGaterOn = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceFMClkWakeUp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceMClkWakeUp = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TopClkGateDis = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscadllctl_dlllocktim(n) = 0x012c012c<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllIncLockTim = 0x12c <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllInitLockTim = 0x12c <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program DLL Init and Incr lock timers based on 24 MHz value<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_dlllocktim(n) = 0x012c012c<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllIncLockTim = 0x12c <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DllInitLockTim = 0x12c <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > RdWrDqCalSegLen_f0<br /><br /> <b>PALLADIUM</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f0(n) = 0x00010002<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRdDqCalSegLen = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWrDqCalSegLen = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > RdWrDqCalSegLen_f1<br /><br /> <b>PALLADIUM</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f1(n) = 0x00010002<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tRdDqCalSegLen = 0x2 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tWrDqCalSegLen = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl1_freq1(n) = 0x110c110e<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_addr_freq1 = 0xe <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_ctrl_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw2_data_freq1 = 0x11 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_addr_freq1 = 0xc <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_ctrl_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrw3_data_freq1 = 0x11 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > HWRdWrDqCalFullScanEnable<br /><br /> <b>PALLADIUM</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000003<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HWRdDqCalFullScanEnable = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HWWrDqCalFullScanEnable = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></table>
<h4>9. Setup registers for DQ calibration for bucket 1</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FSP-WR and FSP-OP to 1 and set VRCG and modified refresh </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0xd80d0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 1us for FSP setting to take affect. </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program AutoSR </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_pwrmngten(n) = 0x00000002<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AutoSR = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DynPwrDnEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; McPhyUpdDramClkOff = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PwrDnClkOff = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRClkOff = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitOpt = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FreqChngMRW Cnt </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl(n) = 0x00009999<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngfspop = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq0 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq1 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq2 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq3 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngrunsocupd = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > WrDqDqsSDLLCtrl </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff00000c<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsRunSDLLUpd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsRunSDLLUpdOverride = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsRunSDLLUpdWrResult = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsWrLvlReBalanceEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f1 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f2 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f3 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLHalfClkEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLOvrVal = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqsSDLLOvrVal = 0xff <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Re-enable SDLL updates </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscasdllctrl_SDLLUpdateDeferEn(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DeferEn = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Re-enable SDLL updates </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqsdllctrl_SDLLUpdateDeferEn(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DeferEn = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Disable MDLL override </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqdllctl_MDLLOverride(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MDLLOvrCode = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MDLLOvrSel = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">Yes</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Call custom API provided by PMGR for changing mcu_clk to 800Mhz and mcu_fixed_clk to Mhz<br /> // TO BE COMPLETED<br /><br /><b>FPGA:</b> Skip this step<br /><br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl(n) = 0x00010000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngfspop = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngrunsocupd = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcfg freqchngctl </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcfg_freqchngctl<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngrunsocupd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcfg_freqchngctl(n)) & 0x10000) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngfspop = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngrunsocupd = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 2us for the soc update to finish </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>10. AMP Dynamic DQ Calibration</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step10Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WRLVL, 0, 0, 0, 0, 1, 16, 12);<br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_dqfltctrl(n) = 0x00000010<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIdleActive = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsIdleActive = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step10Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, RD_DQ_CAL, 0, 0, 0, 0, 1, 16, 12);<br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step10Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WR_DQ_CAL, 0, 0, 0, 0, 1, 16, 12);<br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > The scale factors for Bin0 and Bin1 WR DQS/DQ skew have to to programmed to the correct values based on board charaterization. Fields are being set to 0 here, since exact board skews are not available now (04/01/14). </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqsdllctrl_WrtDQSDQSkewControl(n) = 0x06000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsIDTVTScaleEn = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsMDLLVTScaleEn = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrtDQSDQScaleFactorF0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrtDQSDQScaleFactorF1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrtDQSDQScaleFactorPlusSel = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>11. Setup registers for CA calibration for bucket 0</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_dqfltctrl(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIdleActive = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsIdleActive = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FSP-WR to 0 and FSP-OP to 1 and set VRCG and modified refresh </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x980d0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM MR2 register (latency) through MRR/MRW command registers. The example shows the nominal programming for LPDDR2-1066 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices.<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x24020100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure DRAM MR1 register through MRR/MRW command registers.<br /> This includes the following: WC=Wrap BT=Sequential BL=BL16.<br /> nWR, the example shows the nominal programming for LPDDR3- 1600 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices.<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0xce010100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0xb3030100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x04160100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x440b0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>FPGA</b>: Perform this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x000b0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd<br /><br /> <b>FPGA</b>: Perform this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x110c0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x110e0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></table>
<h4>12. AMP Dynamic Address Timing Calibration</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step12Calibration(0, LPDDR3, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, CA_CALIB, 0, 0, 0, 0, 0, 0, 0, 24, 12);<br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>13. Setup registers for DQ calibration for bucket 0</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FSP-WR and FSP-OP to 0 and set VRCG and modified refresh </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x180d0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 1us for FSP setting to take affect. </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Call custom API provided by PMGR for changing mcu_clk to 1200Mhz and mcu_fixed_clk to Mhz<br /> // TO BE COMPLETED<br /><br /><b>FPGA:</b> Skip this step<br /><br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl(n) = 0x00010000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngfspop = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngrunsocupd = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcfg freqchngctl </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcfg_freqchngctl<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngrunsocupd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcfg_freqchngctl(n)) & 0x10000) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngfspop = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq1 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngrunsocupd = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 2us for the soc update to finish </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>14. AMP Dynamic DQ Calibration</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WRLVL, 0, 0, 0, 0, 0, 24, 12);<br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqiocfg_dqfltctrl(n) = 0x00000010<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqIdleActive = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DqsIdleActive = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, RD_DQ_CAL, 0, 0, 0, 0, 0, 24, 12);<br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WR_DQ_CAL, 0, 0, 0, 0, 0, 24, 12);<br /> </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>15. Setup registers for boot.</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscaiocfg_BISTRxMode(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BISTRxMode = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BISTRxODT = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BISTRxODTEn = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FSP-WR to 1 and FSP-OP to 0 and reset VRCG, since all calibrations are done <rdar://problem/16695199> </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x500d0100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Wait 1us for FSP setting to take affect. </td>
<td><table class="platform">
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program FreqChngMRW Cnt </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_freqchngctl(n) = 0x00009999<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngfspop = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq0 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq1 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq2 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngmrwcnt_freq3 = 0x9 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; freqchngrunsocupd = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000008<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsRunSDLLUpd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsRunSDLLUpdOverride = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsRunSDLLUpdWrResult = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqDqsWrLvlReBalanceEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f1 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f2 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLAddHalfClk_f3 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLHalfClkEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqSDLLOvrVal = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrDqsSDLLOvrVal = 0xff <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>DO_CALIBRATION</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsdq_ampsdqsdllctrl_rd0sdllctrl(n) = 0x00150004<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rd0RunSDLLUpd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rd0RunSDLLUpdOverride = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rd0RunSDLLUpdWrResult = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rd0SDLLOvrVal = 0x15 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll ampsdqsdllctrl rd0sdllctrl<br /><br /> <b>DO_CALIBRATION</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> Poll: ampsdqsdllctrl_rd0sdllctrl<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Rd0RunSDLLUpdWrResult<br />
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;while((CSR(ampsdq_ampsdqsdllctrl_rd0sdllctrl(n)) & 0x4) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HWRdDqCalFullScanEnable = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HWWrDqCalFullScanEnable = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > <br /><br /> <b>PALLADIUM</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000003<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HWRdDqCalFullScanEnable = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HWWrDqCalFullScanEnable = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>16. Enable other features</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on the freq change waiting for refresh and self-refresh exit feature </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_arefparam(n) = 0x0d010019<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqChngWaitThr = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyUpdWaitRefresh = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyUpdWaitThr = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PhyUpdWaittXSR = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefAssertCnt = 0xd <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitRefCnt = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable periodic ZQC. (Optional) <br /> Note the ZqCalIntrvl setting shown here is based on tREFI=3.9us and the target interval is ~128ms (max supported value). The actual setting may vary depending on the DRAM and the system. </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_odtszqc(n) = 0xc0000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DerateParamSRExit = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OdtsRdIntrvl = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitZQCChnlQuiet = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ShareZQRes = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TempDrtEn = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCChnlQuiet = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCStack = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZqCalIntrvl = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_odtszqc(n) = 0xc0001000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DerateParamSRExit = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OdtsRdIntrvl = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitZQCChnlQuiet = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ShareZQRes = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TempDrtEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCChnlQuiet = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCStack = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZqCalIntrvl = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on the QBR enables. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_mcusch_qbren(n) = 0x0000000d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ErlyQbrEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LateQbrEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MifQbrEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PredictiveM2AReq = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_arefen_freq3(n) = 0x10100000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ARpbEn_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiTempRefRnkAgeOut_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrHiWaterMark_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrLoWaterMark_freq3 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_arefen_freq2(n) = 0x10000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ARpbEn_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiTempRefRnkAgeOut_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrHiWaterMark_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrLoWaterMark_freq2 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_arefen_freq1(n) = 0x10110000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ARpbEn_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiTempRefRnkAgeOut_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrHiWaterMark_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrLoWaterMark_freq1 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on auto refresh. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_arefen_freq0(n) = 0x1011013f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ARpbEn_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AutoRefEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AutoRefSchEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DisableHiTempREFab = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; EarlyCasAgeOut = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiPriREFpbPch = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HiTempRefRnkAgeOut_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; REFpb2bank = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; REFpbEarlyPch = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrHiWaterMark_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefCntrLoWaterMark_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RefOpptEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tREFBWREFpb = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></table>
<h4>17. Enable the Fast Critical Word Forwarding feature (optional)</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Configure the MIF FCWF pull- in cycles. <br /> (Here we just use 0x8 as an example, please refer to register description for the valid programming range and refer to performance simulation results) </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_mcusch_qbrparam(n) = 0x61616161<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq0 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq2 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq3 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq0 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq1 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq2 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq3 = 0x6 <br /> </td></tr>
<tr><td style="font-weight: bold">else if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_mcusch_qbrparam(n) = 0x00006100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq0 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq1 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq3 = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_mcusch_qbrparam(n) = 0x000061a5<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq0 = 0x5 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq1 = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCwfEarlyCyc_freq3 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq0 = 0xa <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq1 = 0x6 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq2 = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdRemEarlyCyc_freq3 = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on the PredictiveM2AReq feature in MIF. (The other Qbr enables are turned on here, but not related to CWF feature) </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == PALLADIUM)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_mcusch_qbren(n) = 0x0000000d<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ErlyQbrEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LateQbrEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MifQbrEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PredictiveM2AReq = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_mcusch_qbren(n) = 0x0000000f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ErlyQbrEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LateQbrEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MifQbrEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PredictiveM2AReq = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_mcccfg_MccGen = 0x00000126<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramAccessEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; EccEn = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HitBypassEcc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccRamEn = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccRamEnLock = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccStop = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SpecRdEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SpecRdNum = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_amccperfcntr_Mcc0QPropCtrl = 0x300011a2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0AfCacheRdPropQCmd = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0AfCacheRdPropQTrakEnbl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0AfDramRdPropQCmd = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0AfDramRdPropQTrakEnbl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0DpPropQCfg = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0DpPropQCmd = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0DpPropQTrakEnbl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0MsqQPropCfg = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0MsqQPropQCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0MsqQPropTrakEnbl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0QpropOutSel = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0TpPropQCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0TpPropQTrakEnbl = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0TpQPropSel = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc0TpQpropMask = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_amccperfcntr_Mcc1QPropCtrl = 0x300011a2<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1AfCacheRdPropQCmd = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1AfCacheRdPropQTrakEnbl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1AfDramRdPropQCmd = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1AfDramRdPropQTrakEnbl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1DpPropQCfg = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1DpPropQCmd = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1DpPropQTrakEnbl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1MsqQPropCfg = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1MsqQPropQCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1MsqQPropTrakEnbl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1QpropOutSel = 0x3 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1TpPropQCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1TpPropQTrakEnbl = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1TpQPropSel = 0x4 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mcc1TpQpropMask = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>18. Enable Power & ClockGating features and Configure the MCC and Global Timer</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable AMPCA Fixed MCLK Clock Gating </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsca_ampscagen_ampclk(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FMClkIdleDetectEn = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceDRAMClkEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceDiv2MClkTopGaterOn = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceFMClkWakeUp = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceMClkWakeUp = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TopClkGateDis = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable AMPDQ Fixed MCLK Clock Gating </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; ampsdq_ampsdqgen_ampclk(n) = 0x00000000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FMClkIdleDetectEn = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceDRAMClkEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceDiv2MClkTopGaterOn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceFMClkWakeUp = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ForceMClkWakeUp = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TopClkGateDis = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > disable dynamic power-down. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcfg_pwrmngten(n) = 0x00000132<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AutoSR = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DynPwrDnEn = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; McPhyUpdDramClkOff = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PwrDnClkOff = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRClkOff = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitOpt = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > disable dynamic power-down. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_pwrmngten(n) = 0x00000133<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AutoSR = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DynPwrDnEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; McPhyUpdDramClkOff = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PwrDnClkOff = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRClkOff = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitOpt = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">No</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Revert auto self-refresh wait timer to guided value.<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_pwrmngtparam_freq0(n) = 0x01800000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BypsPwrDnDlyCyc_freq0 = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SelfRefTmrVal_freq0 = 0x180 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Setting WqAgeOutVal to be 3/4 of SelfRefTmrVal, to flush writes in a reasonable time.<br /><br /> <b>FPGA</b>: Skip this step </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_mcusch_psqwqctl1(n) = 0x01640120<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WqAgeOutVal_freq0 = 0x120 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WqAgeOutVal_freq1 = 0x164 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable wakeups from glbl timer to pmgr </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_PmgrWakeUpCfg = 0x000000ff<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqChngEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IdtEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ImpCalEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MdllEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCalEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VoltRampEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrCalEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCalEn = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_PreFreq2AllBankDly0 = 0x01500150<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PreFreqChng2AllBankDly_f0 = 0x150 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PreFreqChng2AllBankDly_f1 = 0x150 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_PreFreq2AllBankDly1 = 0x01500150<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PreFreqChng2AllBankDly_f2 = 0x150 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PreFreqChng2AllBankDly_f3 = 0x150 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_PreFreqChng2FreqChngDly0 = 0x02a002a0<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PreFreqChng2FreqChngDly_f0 = 0x2a0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PreFreqChng2FreqChngDly_f1 = 0x2a0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_PreFreqChng2FreqChngDly1 = 0x02a002a0<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PreFreqChng2FreqChngDly_f2 = 0x2a0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PreFreqChng2FreqChngDly_f3 = 0x2a0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_Cal2PreFreqChngDly0 = 0x00900090<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Cal2PreFreqChngDly_f0 = 0x90 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Cal2PreFreqChngDly_f1 = 0x90 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_Cal2PreFreqChngDly1 = 0x00900090<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Cal2PreFreqChngDly_f2 = 0x90 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Cal2PreFreqChngDly_f3 = 0x90 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_FreqChng2PstCalDly0 = 0x01200120<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqChng2PstCalDly_f0 = 0x120 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqChng2PstCalDly_f1 = 0x120 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_FreqChng2PstCalDly1 = 0x01200120<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqChng2PstCalDly_f2 = 0x120 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FreqChng2PstCalDly_f3 = 0x120 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_MdllTimer = 0x00000bb8<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MdllTimerCnt = 0xbb8 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_MdllVoltRampTimer = 0x0000004b<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MdllVoltRampTimerCnt = 0x4b <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_CtrlUpdMaskTimer = 0x0000000f<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CtrlUpdMaskTimerCnt = 0xf <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_RdCalTimer = 0x002dc6c0<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RdCalTimerCnt = 0x2dc6c0 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_WrCalTimer = 0x002dc6c0<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WrCalTimerCnt = 0x2dc6c0 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_ZQCTimer = 0x003d0900<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCTimerCnt = 0x3d0900 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_PerCal_FreqChngTimer = 0x000493e0<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PerCal_FreqChngTimerCnt = 0x493e0 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_VoltRampTimer = 0x000493e0<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VoltRampTimerCnt = 0x493e0 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_ImpCalTimer = 0x00002ee0<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ImpCalTimerCnt = 0x2ee0 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_VoltRamp2AllBankDly0 = 0x00d800d8<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VoltRamp2AllBankDly_f0 = 0xd8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VoltRamp2AllBankDly_f1 = 0xd8 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_VoltRamp2AllBankDly1 = 0x00d800d8<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VoltRamp2AllBankDly_f2 = 0xd8 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; VoltRamp2AllBankDly_f3 = 0xd8 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_AllBank2PmgrAckDly0 = 0x00900090<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AllBank2PmgrAckDly_f0 = 0x90 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AllBank2PmgrAckDly_f1 = 0x90 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; glbtimer_GlbTimer_AllBank2PmgrAckDly1 = 0x00900090<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AllBank2PmgrAckDly_f2 = 0x90 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AllBank2PmgrAckDly_f3 = 0x90 <br /> </td></tr>
</table></td>
<td class="run_option">Yes</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Dynamic clk pwr gating reg </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_amcgen_amcclkpwrgate(n) = 0x050a0000<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ClkPwrWaitCyc = 0xa *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MCUBCGClkGateEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MCUBCGPwrGateEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PwrRstCyc = 0x5 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>19. Do a ODTS read and set ODTS interval so MR4 on-die temperature sensor read occurs periodically.</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Perform an MRR to DRAM mode register MR4 to establish a base value for ODTS reading.<br /> Another intention is to bring DRAM out of self-refresh. Done in both cold boot and resume boot. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcx_dramcmd_mrinitcmd(n) = 0x50041100<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdAddr = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdCs = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdData = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsMPC = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MRCmdIsRd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunMRCmd = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunRdLvl = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RunSRExit = 0x0 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll dramcmd mrinitcmd </td>
<td><table class="platform">
<tr><td class="programming"> Poll: dramcmd_mrinitcmd<br />
&nbsp;&nbsp;&nbsp; RunMRCmd<br />
&nbsp;&nbsp;&nbsp;while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Enable periodic ODTS and temperature based refresh rate modulation. (Optional) <br /> Note the OdtsRdIntrvl setting shown here is based on tREFI=3.9us and the target interval is ~100. The actual setting may vary depending on the DRAM and the system. <br /> Palladium: this step is skipped, ODTS is not supported<br /><br /> <b>PALLADIUM</b>: Skip this step </td>
<td><table class="platform">
<tr><td style="font-weight: bold">if (platform == FPGA)</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_odtszqc(n) = 0xc0002320<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DerateParamSRExit = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OdtsRdIntrvl = 0x320 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitZQCChnlQuiet = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ShareZQRes = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TempDrtEn = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCChnlQuiet = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCStack = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZqCalIntrvl = 0x0 <br /> </td></tr>
<tr><td style="font-weight: bold">else</td></tr>
<tr><td class="programming"> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; amcx_dramcfg_odtszqc(n) = 0xc0003320<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DerateParamSRExit = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OdtsRdIntrvl = 0x320 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SRExitZQCChnlQuiet = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ShareZQRes = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TempDrtEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCChnlQuiet = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZQCStack = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ZqCalIntrvl = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></table>
<h4>Mcc Cache Initialization. This section is not part of the essential init sequence. This should be run when the system is done using the CacheAsRam</h4>
<p><br /> </p>
<table class="section">
<tr><th class="description" align="left">Description</th><th class="programming" align="left">Register Programming</th><th class="run_option" align="left">AOP AWAKE</th><th class="run_option" align="left">Resume Boot</th><th class="run_option" align="left">AOP DDR</th></tr>
</tr>
<tr>
<td class="description" valign="top" > </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_mcccfg_MccGen = 0x00000124<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramAccessEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; EccEn = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HitBypassEcc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccRamEn = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccRamEnLock = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccStop = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SpecRdEn = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SpecRdNum = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Program AF Allocation Hints, allocation does not happen unless there is a hint as the generic allocation policy </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_mcccfg_MccAlcHint = 0x00001110<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccAlcHintEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccGenericAlc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccSclDtyEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccStickyEn = 0x1 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Poll mcccfg MccPwrOnWayCntStatus </td>
<td><table class="platform">
<tr><td class="programming"> Poll: mcccfg_MccPwrOnWayCntStatus<br />
&nbsp;&nbsp;&nbsp; Mcc0CurDatWayOnCnt<br />
&nbsp;&nbsp;&nbsp; Mcc0CurWayCnt<br />
&nbsp;&nbsp;&nbsp; Mcc0TgtWayCnt<br />
&nbsp;&nbsp;&nbsp; Mcc1CurDatWayOnCnt<br />
&nbsp;&nbsp;&nbsp; Mcc1CurWayCnt<br />
&nbsp;&nbsp;&nbsp; Mcc1TgtWayCnt<br />
&nbsp;&nbsp;&nbsp;while((CSR(amcc_mcccfg_MccPwrOnWayCntStatus) & 0x7fff7fff) != 0x42104210) <br />
</td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Maximum Number of Powered Ways. </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_mcccfg_MccPwrOnWayCntCtrl = 0x00000110<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccMaxWayOnCnt = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccMaxWayOnExact = 0x1 *read-only<br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Turn on the MCC </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_mcccfg_MccGen = 0x00000195<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; DramAccessEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; EccEn = 0x1 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HitBypassEcc = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccRamEn = 0x0 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccRamEnLock = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccStop = 0x0 *read-only<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SpecRdEn = 0x1 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SpecRdNum = 0x4 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td></tr>
<tr>
<tr ><td class='wide' colspan='3'></td></tr><td class="description" valign="top" > Set Dynamic Way PowerGating </td>
<td><table class="platform">
<tr><td class="programming"> &nbsp;&nbsp;&nbsp; amcc_mcccfg_MccPwrOnWayCntCtrl = 0x00000010<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccMaxWayOnCnt = 0x10 <br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MccMaxWayOnExact = 0x0 <br /> </td></tr>
</table></td>
<td class="run_option">-</td><td class="run_option">-</td><td class="run_option">-</td>