98 lines
5.2 KiB
C
98 lines
5.2 KiB
C
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/*
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* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __ADBE_REGS_H
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#define __ADBE_REGS_H
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#include <platform/soc/hwregbase.h>
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#define rDBEMODECNTL (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x4))
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#define DBEMODECNTL_ENABLE (1 << 31)
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#define DBEMODECNTL_PRE_CSC_LUT_ENABLE (1 << 30)
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#define DBEMODECNTL_CSC_ENABLE (1 << 29)
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#define DBEMODECNTL_POST_CSC_LUT_ENABLE (1 << 28)
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#define DBEMODECNTL_AAP_ENABLE (1 << 27)
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#define DBEMODECNTL_DPB_ENABLE (1 << 26)
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#define DBEMODECNTL_BN_DITHER_ENABLE (1 << 25)
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#define DBEMODECNTL_ST_DITHER_ENABLE (1 << 24)
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#define DBEMODECNTL_DYN_CLK_GATE_ENABLE (1 << 23)
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#define DBEMODECNTL_AFC_TEARDOWN_ENABLE (1 << 22)
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#define DBEMODECNTL_PMGR_CLK_GATE_ENABL (1 << 21)
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#define DBEMODECNTL_BLK_CLK_GATE_ENABLE (1 << 20)
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#define DBEMODECNTL_VSYNC_POLARITY (1 << 19)
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#define DBEMODECNTL_HSYNC_POLARITY (1 << 18)
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#define DBEMODECNTL_I_P_SELECT(x) (x << 16)
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#define DBEMODECNTL_UPDATE_ENABLE_TIMING (1 << 15)
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#define DBEMODECNTL_UPDATE_REQ_TIMING (1 << 14)
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#define DBEMODECNTL_CH2_SEL(x) (x << 12)
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#define DBEMODECNTL_CH1_SEL(x) (x << 10)
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#define DBEMODECNTL_CH0_SEL(x) (x << 8)
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#define DBEMODECNTL_CRC_ENABLE (1 << 7)
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#define DBEMODECNTL_CRC_MULTIFRAME_ENABLE (1 << 6)
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#define DBEMODECNTL_CRC_WINDOW_ENABLE (1 << 5)
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#define DBEMODECNTL_CRC_VALID (1 << 4)
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#define DBEMODECNTL_VFTG_STATUS (1 << 0)
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#define rDBECONSTCOLOR (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x8))
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#define rDBESCRNSZ (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0xC))
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#define rDBEFRONTPORCH (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x10))
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#define rDBESYNCPULSE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x14))
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#define rDBEBACKPORCH (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x18))
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#define rDBEVBLANKPOS (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x1C))
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#define rDBEVBLANKCLKGATE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x20))
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#define rDBEVBLANKIDLE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x24))
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#define rDBECRCWINDOW (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x28))
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#define rDBECRCRESULT (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x2C))
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//Only Alcatraz has the color manager on the back end. No need to generated a new driver just for it.
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#define rCM_DEGAMMA_RED(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x0400 + ((n) * 4)))
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#define rCM_DEGAMMA_GREEN(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x0800 + ((n) * 4)))
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#define rCM_DEGAMMA_BLUE(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x0c00 + ((n) * 4)))
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#define rCM_CSC_00 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1000)
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#define rCM_MATRIX_BASE(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1000 + ((n) * 4)))
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#define rCM_CSC_01 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1004))
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#define rCM_CSC_02 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1008))
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#define rCM_CSC_C0 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x100c))
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#define rCM_CSC_CI0 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1010))
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#define rCM_CSC_10 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1014))
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#define rCM_CSC_11 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1018))
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#define rCM_CSC_12 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x101c))
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#define rCM_CSC_C1 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1020))
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#define rCM_CSC_CI1 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1024))
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#define rCM_CSC_20 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1028))
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#define rCM_CSC_21 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1020))
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#define rCM_CSC_22 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1030))
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#define rCM_CSC_C2 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1034))
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#define rCM_CSC_CI2 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1038))
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#define rCM_LUT_CTL (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x103c))
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#define CM_LUT_CTL (DISP_CM_BASE_ADDR + 0x103c)
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#define CM_LUT_CTL_UPDATE_ENABLE_ENG_BLUE (1 << 23)
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#define CM_LUT_CTL_UPDATE_REQ_ENG_BLUE (1 << 22)
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#define CM_LUT_CTL_BYPASS_ENG_BLUE (1 << 21)
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#define CM_LUT_CTL_UPDATE_ENABLE_DEG_BLUE (1 << 19)
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#define CM_LUT_CTL_UPDATE_REQ_DEG_BLUE (1 << 18)
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#define CM_LUT_CTL_BYPASS_DEG_BLUE (1 << 17)
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#define CM_LUT_CTL_UPDATE_ENABLE_ENG_GREEN (1 << 15)
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#define CM_LUT_CTL_UPDATE_REQ_ENG_GREEN (1 << 14)
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#define CM_LUT_CTL_BYPASS_ENG_GREEN (1 << 13)
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#define CM_LUT_CTL_UPDATE_ENABLE_DEG_GREEN (1 << 11)
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#define CM_LUT_CTL_UPDATE_REQ_DEG_GREEN (1 << 10)
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#define CM_LUT_CTL_BYPASS_DEG_GREEN (1 << 9)
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#define CM_LUT_CTL_UPDATE_ENABLE_ENG_RED (1 << 7)
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#define CM_LUT_CTL_UPDATE_REQ_ENG_RED (1 << 6)
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#define CM_LUT_CTL_BYPASS_ENG_RED (1 << 5)
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#define CM_LUT_CTL_UPDATE_ENABLE_DEG_RED (1 << 3)
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#define CM_LUT_CTL_UPDATE_REQ_DEG_RED (1 << 2)
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#define CM_LUT_CTL_BYPASS_DEG_RED (1 << 1)
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#define rCM_ENGAMMA_RED(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1200 + ((n) * 4)))
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#define rCM_ENGAMMA_GREEN(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x2200 + ((n) * 4)))
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#define rCM_ENGAMMA_BLUE(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x3200 + ((n) * 4)))
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#endif /* __ADBE_REGS_H */
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