330 lines
9.3 KiB
C
330 lines
9.3 KiB
C
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/dma.h>
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#include <platform.h>
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#include <platform/int.h>
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#include <platform/pl080dmac_config.h>
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#include <platform/soc/hwdmachannels.h>
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#include <sys/task.h>
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#include <sys/menu.h>
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#include <sys.h>
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#include "pl080dmac_regs.h"
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#define CHANNEL_STATUS_UNINIT 0
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#define CHANNEL_STATUS_IDLE 1
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#define CHANNEL_STATUS_BUSY 2
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#define CHANNEL_STATUS_BUSY_UNINIT 3
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struct pl080dmac_channel {
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uint8_t status;
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uint32_t actual_xfer_size;
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uint32_t current_xfer_size;
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uint32_t total_xferred;
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/* callback for async operations */
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dma_completion_function callback;
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void *callback_arg;
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};
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static bool pl080dmac_inited[PL080DMAC_COUNT];
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static struct pl080dmac_channel pl080dmac_channels[PL080DMAC_COUNT][PL080DMAC_SUPPORTED_CHANNEL_COUNT];
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static void pl080dmac_dump_channel(int dma_channel);
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static void pl080dmac_tc_int_handler(void *arg);
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static void pl080dmac_err_int_handler(void *arg);
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void dma_init()
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{
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uint8_t pl080dmac_idx;
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for (pl080dmac_idx = 0; pl080dmac_idx < PL080DMAC_COUNT; pl080dmac_idx++) {
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clock_gate(pl080dmac_configs[pl080dmac_idx].dmac_clk, true);
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if (pl080dmac_configs[pl080dmac_idx].dmac_tc_irq) {
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set_int_type(pl080dmac_configs[pl080dmac_idx].dmac_tc_irq, INT_TYPE_IRQ | INT_TYPE_LEVEL);
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install_int_handler(pl080dmac_configs[pl080dmac_idx].dmac_tc_irq, pl080dmac_tc_int_handler, (void *)pl080dmac_idx);
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unmask_int(pl080dmac_configs[pl080dmac_idx].dmac_tc_irq);
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}
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if (pl080dmac_configs[pl080dmac_idx].dmac_err_irq) {
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set_int_type(pl080dmac_configs[pl080dmac_idx].dmac_err_irq, INT_TYPE_IRQ | INT_TYPE_LEVEL);
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install_int_handler(pl080dmac_configs[pl080dmac_idx].dmac_err_irq, pl080dmac_err_int_handler, (void *)pl080dmac_idx);
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unmask_int(pl080dmac_configs[pl080dmac_idx].dmac_err_irq);
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}
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// Enable DMAC
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rPL080DMAC_CFG(pl080dmac_idx) = (1 << 0);
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pl080dmac_inited[pl080dmac_idx] = true;
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}
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}
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int dma_execute_cmd(uint32_t cmd, int dma_channel, void *src,
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void *dst, uint32_t length, uint32_t word_size,
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uint32_t burst_size)
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{
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struct task_event event;
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struct dma_segment seg;
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void *fifo;
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int32_t ret;
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// build an SGL for the one segment
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switch (cmd & DMA_CMD_DIR_MASK) {
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case DMA_CMD_DIR_TX:
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seg.paddr = (uintptr_t)src;
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fifo = dst;
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break;
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case DMA_CMD_DIR_RX:
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seg.paddr = (uintptr_t)dst;
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fifo = src;
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break;
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default:
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return -1;
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}
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seg.length = length;
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// run the operation
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event_init(&event, EVENT_FLAG_AUTO_UNSIGNAL, false);
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ret = dma_execute_async(cmd, dma_channel, &seg, fifo, length, word_size, burst_size,
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(dma_completion_function)event_signal, (void *)&event);
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if (!ret)
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// and block waiting for it to complete
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event_wait(&event);
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return ret;
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}
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int dma_execute_async(uint32_t cmd, int dma_channel,
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struct dma_segment *sgl, void *fifo, uint32_t length,
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uint32_t word_size, uint32_t burst_size,
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dma_completion_function completion, void *completion_arg)
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{
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uint8_t dmac_idx;
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struct pl080dmac_channel *ch;
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const struct pl080dmac_channel_config *ch_config;
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uint8_t expected_direction;
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uint16_t xfer_size, xfer_width;
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dmac_idx = (dma_channel >> DMA_SELECTOR_SHIFT) & DMA_CHANNEL_MASK;
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dma_channel = dma_channel & DMA_CHANNEL_MASK;
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ch = &pl080dmac_channels[dmac_idx][dma_channel];
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ch_config = &pl080dmac_configs[dmac_idx].dmac_channel_config[dma_channel];
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expected_direction = (ch_config->type == PL080DMAC_PERPH_SRC) ? DMA_CMD_DIR_RX : DMA_CMD_DIR_TX;
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// sanity check
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ASSERT(dmac_idx <= PL080DMAC_COUNT);
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ASSERT(dma_channel <= PL080DMAC_CHANNEL_COUNT);
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ASSERT(sgl);
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ASSERT(length > 0);
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ASSERT((uintptr_t)fifo == ch_config->fifo_address);
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// make sure controller is inited
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ASSERT(pl080dmac_inited[dmac_idx] != false);
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// word_size and burst_size default are in pl080dmac_config table, overrides not allowed
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ASSERT(word_size == 0);
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ASSERT(burst_size == 0);
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// validate command
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ASSERT((cmd & DMA_CMD_DIR_MASK) == expected_direction);
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// update channel status to busy but not initialized
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enter_critical_section();
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ch->status = CHANNEL_STATUS_BUSY_UNINIT;
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exit_critical_section();
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// save the completion
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ch->callback = completion;
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ch->callback_arg = completion_arg;
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// calcuate transfer size, and cap it to max_trasnfer_size
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xfer_width = (expected_direction == DMA_CMD_DIR_RX) ?
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(ch_config->control >> 21) & 7 : (ch_config->control >> 18) & 7;
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// make sure length is multiple of transfer width
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ASSERT((length % (1 << xfer_width)) == 0);
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xfer_size = length >> xfer_width;
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ch->actual_xfer_size = xfer_size;
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xfer_size = (xfer_size < PL080DMAC_MAX_TRANSFER_SIZE) ? xfer_size : PL080DMAC_MAX_TRANSFER_SIZE;
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ch->current_xfer_size = xfer_size;
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ch->total_xferred = 0;
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// initialize and configure channel
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// PL080DMAC TRM, section 3.2.7
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// step 2
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rPL080DMAC_INTTCCLR(dmac_idx) = (1 << dma_channel);
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rPL080DMAC_INTERRCLR(dmac_idx) = (1 << dma_channel);
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// step 3,4,6,7
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if (ch_config->type == PL080DMAC_PERPH_SRC) {
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rPL080DMAC_CHCTRL(dmac_idx, dma_channel) = (1 << 31) | (ch_config->control) | xfer_size;
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rPL080DMAC_CHCFG(dmac_idx, dma_channel) = (1 << 15) | (1 << 14) | (ch_config->config);
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rPL080DMAC_CHSRCADDR(dmac_idx, dma_channel) = ch_config->fifo_address;
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rPL080DMAC_CHDESTADDR(dmac_idx, dma_channel) = sgl->paddr;
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} else {
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rPL080DMAC_CHCTRL(dmac_idx, dma_channel) = (1 << 31) | (ch_config->control) | xfer_size;
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rPL080DMAC_CHCFG(dmac_idx, dma_channel) = (1 << 15) | (1 << 14) | (ch_config->config);
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rPL080DMAC_CHDESTADDR(dmac_idx, dma_channel) = ch_config->fifo_address;
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rPL080DMAC_CHSRCADDR(dmac_idx, dma_channel) = sgl->paddr;
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}
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// we only support 1 segment (linear dma)
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rPL080DMAC_CHLLI(dmac_idx, dma_channel) = 0;
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// update channel status to busy
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enter_critical_section();
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ch->status = CHANNEL_STATUS_BUSY;
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exit_critical_section();
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// start channel
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rPL080DMAC_CHCFG(dmac_idx, dma_channel) |= (1 << 0);
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return 0;
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}
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void dma_cancel(int dma_channel)
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{
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uint8_t dmac_idx;
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struct pl080dmac_channel *ch;
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utime_t start_time;
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dmac_idx = (dma_channel >> DMA_SELECTOR_SHIFT) & DMA_CHANNEL_MASK;
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dma_channel = dma_channel & DMA_CHANNEL_MASK;
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ch = &pl080dmac_channels[dmac_idx][dma_channel];
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// make sure controller is inited
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ASSERT(pl080dmac_inited[dmac_idx] != false);
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// sanity check
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ASSERT(dmac_idx <= PL080DMAC_COUNT);
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ASSERT(dma_channel <= PL080DMAC_CHANNEL_COUNT);
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// it's legal but not interesting to cancel a channel that hasn't been initialized
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if (CHANNEL_STATUS_UNINIT == ch->status)
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return;
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start_time = system_time();
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rPL080DMAC_CHCFG(dmac_idx, dma_channel) = 0;
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while ((rPL080DMAC_ENBLDCHNLS(dmac_idx) >> dma_channel) != 0) {
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if (time_has_elapsed(start_time, 10000))
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panic("PL080DMAC%d: channel %d timeout during abort", dmac_idx, dma_channel);
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}
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// mark the channel idle
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ch->status = CHANNEL_STATUS_IDLE;
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}
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void dma_use_int(int dma_channel, bool use)
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{
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uint8_t dmac_idx;
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dmac_idx = (dma_channel >> DMA_SELECTOR_SHIFT) & DMA_CHANNEL_MASK;
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dma_channel = dma_channel & DMA_CHANNEL_MASK;
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if (use)
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rPL080DMAC_CHCFG(dmac_idx, dma_channel) |= ((1 << 14) | (1 << 15));
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else
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rPL080DMAC_CHCFG(dmac_idx, dma_channel) &= ~((1 << 14) | (1 << 15));
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}
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bool dma_poll(int dma_channel)
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{
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bool ret = false;
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struct pl080dmac_channel *ch;
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uint8_t dmac_idx;
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dmac_idx = (dma_channel >> DMA_SELECTOR_SHIFT) & DMA_CHANNEL_MASK;
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dma_channel = dma_channel & DMA_CHANNEL_MASK;
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ch = &pl080dmac_channels[dmac_idx][dma_channel];
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if (CHANNEL_STATUS_IDLE == ch->status) {
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ret = true;
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goto exit;
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}
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enter_critical_section();
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if (rPL080DMAC_INTTCSTATUS(dmac_idx) >> dma_channel)
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pl080dmac_tc_int_handler((void *)dmac_idx);
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else if (rPL080DMAC_INTERRSTATUS(dmac_idx) >> dma_channel)
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pl080dmac_err_int_handler((void *)dmac_idx);
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exit_critical_section();
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if (CHANNEL_STATUS_IDLE == ch->status) {
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ret = true;
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goto exit;
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}
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exit:
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return ret;
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}
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int dma_set_aes(int dma_channel, struct dma_aes_config *config)
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{
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// Not supported (PL080DMAC doesn't support AES)
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return -1;
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}
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static void pl080dmac_tc_int_handler(void *args)
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{
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uint8_t pl080dmac_idx;
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uint32_t tc_intsts;
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uint8_t ch;
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struct pl080dmac_channel *ch_info;
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pl080dmac_idx = (uint8_t)args;
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RELEASE_ASSERT(pl080dmac_idx < PL080DMAC_COUNT);
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tc_intsts = rPL080DMAC_INTTCSTATUS(pl080dmac_idx);
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rPL080DMAC_INTTCCLR(pl080dmac_idx) = tc_intsts;
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while(tc_intsts != 0) {
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ch = 31 - clz(tc_intsts);
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ch_info = &pl080dmac_channels[pl080dmac_idx][ch];
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ch_info->total_xferred += ch_info->current_xfer_size;
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if (ch_info->total_xferred < ch_info->actual_xfer_size) {
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// start again
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}
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else {
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ch_info->status = CHANNEL_STATUS_IDLE;
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// call the user-supplied callback
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if (ch_info->callback != NULL)
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ch_info->callback(ch_info->callback_arg);
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}
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tc_intsts &= ~(1 << ch);
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}
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}
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static void pl080dmac_err_int_handler(void *args)
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{
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uint8_t pl080dmac_idx;
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uint32_t err_intsts;
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pl080dmac_idx = (uint8_t)args;
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RELEASE_ASSERT(pl080dmac_idx < PL080DMAC_COUNT);
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err_intsts = rPL080DMAC_INTERRSTATUS(pl080dmac_idx);
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rPL080DMAC_INTERRCLR(pl080dmac_idx) = err_intsts;
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panic("PL080DMAC reported error on channels:0x%08x\n", err_intsts);
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}
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