86 lines
3.1 KiB
C
86 lines
3.1 KiB
C
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/*
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* Copyright (C) 2007 Apple Inc. All rights reserved.
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* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __SAMSUNG_GPIO_H
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#define __SAMSUNG_GPIO_H
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#include <platform/soc/hwregbase.h>
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/* Register Offsets for Samsung GPIOs */
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#define rPCONn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x000 + (n) * 0x20))
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#define rPDATn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x004 + (n) * 0x20))
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#define rPCTLn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x008 + (n) * 0x20))
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#define rPPURn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x00C + (n) * 0x20))
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#define rPPDRn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x010 + (n) * 0x20))
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#define rPPIEn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x014 + (n) * 0x20))
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#define rFSEL (*(volatile u_int32_t *)(GPIO_BASE_ADDR + GPIO_FSEL_OFFSET))
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#define rDSTR0 (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x380))
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#define rOSC_DSTR (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x388))
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#define rODEN (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x3C0))
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#define rEMAC0 (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x3C4))
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#define rEMAC1 (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x3C8))
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#define rEMAC2 (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x3CC))
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/* Base Pin Defines for Samsung GPIOs */
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#define PORT(port, pin) ((u_int32_t)((port) << 8) | pin)
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#define GPIO2PIN(gpio) ((gpio) & 0x7)
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#define GPIO2PAD(gpio) (((gpio) >> 8) & 0x1f)
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/* Precomputes the PCON register's value */
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#define PCON(pinfunc0, pinfunc1, pinfunc2, pinfunc3, pinfunc4, pinfunc5, pinfunc6, pinfunc7) \
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((u_int32_t)(((pinfunc0) << 0) | ((pinfunc1) << 4) | ((pinfunc2) << 8) | ((pinfunc3) << 12) | \
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((pinfunc4) << 16) | ((pinfunc5) << 20) | ((pinfunc6) << 24) | ((pinfunc7) << 28)))
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/* some PCON constants */
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enum {
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PCON_IN = 0,
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PCON_OUT = 1,
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PCON_FUNC2 = 2,
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PCON_FUNC3 = 3,
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PCON_FUNC4 = 4,
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PCON_FUNC5 = 5,
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PCON_FUNC6 = 6,
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PCON_DISABLE = 0xd, /* not actually supported by the hardware, implies PCON_IN
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and input enable disabled */
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PCON_OUT_0 = 0xe, /* same as PCON_OUT, but also sets PDAT to zero */
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PCON_OUT_1 = 0xf /* same as PCON_OUT, but also sets PDAT to one */
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};
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/* pull up/down configuration */
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enum {
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NO_PUPDN = 0,
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PUP = (1 << 0),
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PDN = (1 << 8)
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};
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#define PUPDN(pinupdn0, pinupdn1, pinupdn2, pinupdn3, pinupdn4, pinupdn5, pinupdn6, pinupdn7) \
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((uint16_t)(((pinupdn0) << 0) | ((pinupdn1) << 1) | ((pinupdn2) << 2) | ((pinupdn3) << 3) | \
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((pinupdn4) << 4) | ((pinupdn5) << 5) | ((pinupdn6) << 6) | ((pinupdn7) << 7)))
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struct gpio_default_config {
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uint32_t pcon;
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uint16_t pupdn;
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};
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#define PINCONFIG(pcon0, pupdn0, pcon1, pupdn1, pcon2, pupdn2, pcon3, pupdn3, \
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pcon4, pupdn4, pcon5, pupdn5, pcon6, pupdn6, pcon7, pupdn7) \
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{ .pcon = PCON(pcon0, pcon1, pcon2, pcon3, pcon4, pcon5, pcon6, pcon7), \
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.pupdn = PUPDN(pupdn0, pupdn1, pupdn2, pupdn3, pupdn4, pupdn5, pupdn6, pupdn7) \
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}
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#endif /* __SAMSUNG_GPIO_H */
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