308 lines
9.4 KiB
C
308 lines
9.4 KiB
C
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/*
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* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <arch.h>
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#include <debug.h>
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#include <drivers/miu.h>
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#include <platform.h>
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#include <platform/memmap.h>
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#include <platform/miu.h>
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#include <platform/soc/miu.h>
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#include <platform/soc/pmgr.h>
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#include <platform/clocks.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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static void miu_configure_bridge(const u_int32_t *bridge_settings);
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#define STATIC_BRIDGE_SHIFT (28)
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#define STATIC_BRIDGE_MASK ((1 << STATIC_BRIDGE_SHIFT) - 1)
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#define SB_WIDGETS (0 << STATIC_BRIDGE_SHIFT)
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#define SOCBUSMUX_WIDGETS (1 << STATIC_BRIDGE_SHIFT)
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#define IOBUSMUX_WIDGETS (2 << STATIC_BRIDGE_SHIFT)
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#define SWITCH_FAB_WIDGETS (3 << STATIC_BRIDGE_SHIFT)
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#define CP_WIDGETS (4 << STATIC_BRIDGE_SHIFT)
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#define ANS_WIDGETS (5 << STATIC_BRIDGE_SHIFT)
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#define LIO_WIDGETS (6 << STATIC_BRIDGE_SHIFT)
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static const u_int64_t bridge_registers[] = {
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SB_BASE_ADDR,
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SOC_BUSMUX_BASE_ADDR,
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IOBUSMUX_BASE_ADDR,
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SWTCH_FAB_BASE_ADDR,
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CP_COM_BASE_ADDR,
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ANS_AFC_AIU_BASE_ADDR,
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LIO_AFC_AIU_BASE_ADDR
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};
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#if (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
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#if SUB_PLATFORM_T7000
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static const u_int32_t bridge_settings_static[] = {
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SB_WIDGETS | ASIO_CLK_CTRL, 0x03000102,
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SB_WIDGETS | DYN_CLK_GATING, (0x30 << 16) | (0x1 << 5) | (0x1 << 4) | (0x1 << 3) | (0x1 << 0),
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SB_WIDGETS | SIO_ASYNC_FIFO_SB_RD_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_ASYNC_FIFO_SB_WR_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_ASYNC_FIFO_SB_WGATHER, (0x1 << 8),
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SB_WIDGETS | SIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_DAPASYNC_FIFO_SB_WGATHER, (0x1 << 8),
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SB_WIDGETS | AIU_SB_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x1 << 12) | 0x4,
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0,0,
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SOCBUSMUX_WIDGETS | DWRRCFG_DISPMUX_BULK, (0x51 << 8) | (0x41 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL0_CAMERAMUX, (0x40 << 8) | (0xff << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL1_CAMERAMUX, (0x20 << 8) | (0x80 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL1_MEDIAMUX, (0x60 << 8) | (0x20 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL2_MEDIAMUX, (0x40 << 8) | (0x10 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL0_IOMUX, 0xa2,
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SOCBUSMUX_WIDGETS | TLIMIT_LVL1_IOMUX, 0xa2,
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SOCBUSMUX_WIDGETS | TLIMIT_LVL2_IOMUX, 0xa2,
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SOCBUSMUX_WIDGETS | TLIMIT_LVL3_IOMUX, 0xa2,
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SOCBUSMUX_WIDGETS | SOCBUSMUX_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x1 << 12) | (0x1 << 11) | (0x1 << 10) | (0x4 << 0),
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0,0,
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IOBUSMUX_WIDGETS | IOBUSMUX_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x1 << 13) | (0x1 << 12) | (0x1 << 10) | (0x4 << 0),
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0,0,
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SWITCH_FAB_WIDGETS | SWITCH_FAB_AMAP_LOCK, (0x1 << 0),
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SWITCH_FAB_WIDGETS | SWITCH_FAB_ARBCFG, (0x1 << 10) | (0x1 << 8) | (0x1 << 5) | (0x1 << 4) | (0x4 << 0),
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SWITCH_FAB_WIDGETS | SWITCH_FAB_CPG_CNTL, (0x1 << 31) | (0x1 << 30) | (0x1 << 16) | (0x1 << 12) | (0x1 << 11) | (0x1 << 10) | (0x4 << 0),
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0,0,
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CP_WIDGETS | CP_DYN_CLK_GATING_CTRL, (0x1 << 4) | (0x1 << 3) | (0x1 << 2) | (0x1 << 1) | (0x1 << 0),
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0,0,
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LIO_WIDGETS | LIO_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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0,0,
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0,0
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};
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#elif SUB_PLATFORM_T7001
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static const u_int32_t bridge_settings_static[] = {
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SB_WIDGETS | ASIO_CLK_CTRL, 0x03000102,
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SB_WIDGETS | DYN_CLK_GATING, (0x30 << 16) | (0x1 << 5) | (0x1 << 4) | (0x1 << 3) | (0x1 << 0),
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SB_WIDGETS | SIO_ASYNC_FIFO_SB_RD_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_ASYNC_FIFO_SB_WR_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_ASYNC_FIFO_SB_WGATHER, (0x1 << 8),
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SB_WIDGETS | SIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT, 0x0,
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SB_WIDGETS | SIO_DAPASYNC_FIFO_SB_WGATHER, (0x1 << 8),
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SB_WIDGETS | AIU_SB_CPG_CNTL, (0x1 << 31) | (0x1 << 30) | (0x1 << 16) | (0x1 << 12) | 0x4,
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0,0,
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SOCBUSMUX_WIDGETS | DWRRCFG_DISP0_RT, (0x28 << 8) | (0x20 << 0),
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SOCBUSMUX_WIDGETS | DWRRCFG_IOMUX_BULK, (0x51 << 8) | (0x41 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL0_DISP0, (0x60 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL0_CAMERAMUX, (0x40 << 8) | (0xff << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL1_CAMERAMUX, (0x20 << 8) | (0x80 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL1_MEDIAMUX, (0x60 << 8) | (0x20 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL2_MEDIAMUX, (0x40 << 8) | (0x10 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL0_IOMUX, (0x40 << 8) | (0xa4 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL1_IOMUX, (0x40 << 8) | (0x40 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL2_IOMUX, (0x30 << 8) | (0x30 << 0),
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SOCBUSMUX_WIDGETS | TLIMIT_LVL3_IOMUX, (0x20 << 8) | (0x20 << 0),
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SOCBUSMUX_WIDGETS | SOCBUSMUX_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x1 << 12) | (0x1 << 11) | (0x1 << 10) | (0x4 << 0),
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0,0,
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IOBUSMUX_WIDGETS | IOBUSMUX_REGS_DWRRCFG_DISP1_BULK, (0x1e << 8) | (0x18 << 0),
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IOBUSMUX_WIDGETS | IOBUSMUX_CPG_CNTL, (0x1 << 31) | (0x1 << 16) | (0x1 << 14) | (0x1 << 13) | (0x1 << 12) | (0x1 << 10) | (0x4 << 0),
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0,0,
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SWITCH_FAB_WIDGETS | SWITCH_FAB_AMAP_LOCK, (0x1 << 0),
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SWITCH_FAB_WIDGETS | SWITCH_FAB_CPG_CNTL, (0x1 << 31) | (0x1 << 30) | (0x1 << 16) | (0x1 << 13) | (0x1 << 12) | (0x1 << 11) | (0x1 << 10) | (0x4 << 0),
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0,0,
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CP_WIDGETS | CP_DYN_CLK_GATING_CTRL, (0x1 << 4) | (0x1 << 3) | (0x1 << 2) | (0x1 << 1) | (0x1 << 0),
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0,0,
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LIO_WIDGETS | LIO_MEMCACHE_DATASETID_OVERRIDE, (0xC00F000F),
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0,0,
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0,0,
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};
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#endif
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#endif // (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
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#if WITH_DEVICETREE
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#if SUPPORT_FPGA
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struct bridge_list_t {
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char *bridge_settings;
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uint32_t fpga_enable_mask;
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};
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#define BRIDGE(b, m) { "bridge-settings-" #b, (m) }
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// ALERT: The ordering effects the device tree entries under pmgr node's reg dictionary.
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// It also affects the bridge id used in the pmgr device-clock nodes. The
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// bridge id must match the id on the device tree bridge-settings-<n> properties.
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// NOTE: The second parameter on the BRIDGE macro is used to dynamically determine
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// which bridge settings properties should exist based upon the hardware
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// blocks actually present on the device.
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static const struct bridge_list_t bridge_list[] = {
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BRIDGE(0, FPGA_HAS_ALWAYS),
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BRIDGE(1, FPGA_HAS_MEDIA),
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BRIDGE(2, FPGA_HAS_MSR),
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BRIDGE(3, FPGA_HAS_JPEG),
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BRIDGE(4, FPGA_HAS_AVE),
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BRIDGE(5, FPGA_HAS_VXD),
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BRIDGE(6, FPGA_HAS_ISP),
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#if SUB_PLATFORM_T7000
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BRIDGE(7, (FPGA_HAS_DISP0 | FPGA_HAS_DISP1)),
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BRIDGE(8, FPGA_HAS_DISP0),
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BRIDGE(9, FPGA_HAS_DISP1),
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BRIDGE(10, FPGA_HAS_GFX),
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BRIDGE(11, FPGA_HAS_GFX),
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BRIDGE(12, FPGA_HAS_ALWAYS),
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BRIDGE(13, FPGA_HAS_PCIE),
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#elif SUB_PLATFORM_T7001
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BRIDGE(7, FPGA_HAS_DISP0),
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BRIDGE(8, FPGA_HAS_DISP1),
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BRIDGE(9, FPGA_HAS_GFX),
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BRIDGE(10, FPGA_HAS_GFX),
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BRIDGE(11, FPGA_HAS_ALWAYS),
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BRIDGE(12, FPGA_HAS_PCIE),
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#endif
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};
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#endif // SUPPORT_FPGA
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#endif // WITH_DEVICETREE
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extern void ausb_setup_widgets();
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int miu_initialize_internal_ram(void)
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{
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#if APPLICATION_SECUREROM
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// Ensure that rPMGR_SCRATCH0-3 get cleared
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rPMGR_SCRATCH0 = 0;
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rPMGR_SCRATCH1 = 0;
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rPMGR_SCRATCH2 = 0;
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rPMGR_SCRATCH3 = 0;
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#endif /* APPLICATION_SECUREROM */
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// Save the Security Epoch in the top byte of PMGR_SCRATCH0
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rPMGR_SCRATCH0 &= ~0xFF000000;
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rPMGR_SCRATCH0 |= (platform_get_security_epoch()) << 24;
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return 0;
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}
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int miu_init(void)
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{
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#if APPLICATION_IBOOT && !PRODUCT_IBEC
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// Verify that the Security Epoch in PMGR_SCRATCH0 matches
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if ((rPMGR_SCRATCH0 >> 24) != platform_get_security_epoch()) {
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panic("miu_init: Epoch Mismatch\n");
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}
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#endif
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#if (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
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miu_configure_bridge(bridge_settings_static);
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#endif
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ausb_setup_widgets();
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return 0;
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}
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void miu_suspend(void)
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{
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/* nothing required for suspend */
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}
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int miu_initialize_dram(bool resume)
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{
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#if APPLICATION_IBOOT && WITH_HW_AMC
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mcu_initialize_dram(resume);
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#endif
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return 0;
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}
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void miu_select_remap(enum remap_select sel)
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{
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switch (sel) {
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case REMAP_SRAM:
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rSECUREROMCTRL_ROMADDRREMAP = (rSECUREROMCTRL_ROMADDRREMAP & ~3) | (1 << 0);
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break;
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case REMAP_SDRAM:
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rSECUREROMCTRL_ROMADDRREMAP = (rSECUREROMCTRL_ROMADDRREMAP & ~3) | (2 << 0);
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break;
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}
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}
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void miu_bypass_prep(void)
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{
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}
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static void miu_configure_bridge(const u_int32_t *bridge_settings)
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{
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volatile u_int32_t *reg;
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u_int32_t cnt = 0, bridge, offset, data;
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while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
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while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
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bridge = bridge_settings[cnt] >> STATIC_BRIDGE_SHIFT;
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offset = bridge_settings[cnt] & STATIC_BRIDGE_MASK;
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data = bridge_settings[cnt + 1];
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reg = (volatile u_int32_t *)(bridge_registers[bridge] + offset);
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*reg = data;
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cnt += 2;
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}
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cnt += 2;
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}
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}
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#if WITH_DEVICETREE
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void miu_update_device_tree(DTNode *pmgr_node)
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{
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#if SUPPORT_FPGA
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DTNode *node;
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char *propName;
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void *propData;
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uint32_t propSize;
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uint32_t fpga_blocks = chipid_get_fpga_block_instantiation();
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uint32_t i;
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dprintf(DEBUG_INFO, "chipid_get_fpga_block_instantiation() = 0x%08X\n",
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fpga_blocks);
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if (FindNode(0, "arm-io/pmgr", &node)) {
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// For each bridge...
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for (i = 0; i < ARRAY_SIZE(bridge_list); i++) {
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// Filter out if not supported by FPGA
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if (!(fpga_blocks & bridge_list[i].fpga_enable_mask)) {
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propName = bridge_list[i].bridge_settings;
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if (FindProperty(node, &propName, &propData, &propSize)) {
|
||
|
|
dprintf(DEBUG_CRITICAL, "Eliding %s\n", propName);
|
||
|
|
propName[0] = '~';
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif // SUPPORT_FPGA
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif // WITH_DEVICETREE
|
||
|
|
|