177 lines
5.6 KiB
C
177 lines
5.6 KiB
C
/*
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* Copyright (C) 2006-2011 Apple Computer, Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Computer, Inc.
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*/
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#include <debug.h>
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#include <compiler.h>
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#include <sys.h>
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#include <arch.h>
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#include <arch/arm/arm.h>
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#include <platform.h>
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#include <platform/memmap.h>
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#define SECTION_SIZE MB
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#define LARGE_PAGE_SIZE 65536
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#define PAGE_SIZE 4096
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#define TTBCR_PD1 (1 << 5)
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typedef u_int32_t tt_ent;
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/* needs to be in non-static, initialized data for successful patching
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* during IOP firmware loading */
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u_int32_t tt_size __attribute__((used)) = MMU_TT_SIZE;
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tt_ent *tt = (void *)0xffffffff;
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/* ARM MMU first-level section descriptor definitions */
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#define ARM_DESC_SECT ((0 << 18) | (1 << 1))
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#define ARM_SECT_B (1 << 2)
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#define ARM_SECT_C (1 << 3)
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#define ARM_SECT_XN (1 << 4)
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#define ARM_SECT_DOMAIN(_d) ((_d) << 5)
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#define ARM_SECT_TEX(_t) ((_t) << 12)
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#define ARM_SECT_SHARED (1 << 16)
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#define ARM_SECT_FULLACC ((0 << 15) | (3 << 10))
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#define ARM_SECT_EXEC (ARM_SECT_DOMAIN(0))
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#define ARM_SECT_NOEXEC (ARM_SECT_DOMAIN(1) | ARM_SECT_XN)
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#define ARM_SECT_READ_ONLY (1 << 15)
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/* Non-normal memory needs XN set (and consequently a client domain assignment) to avoid
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* instruction prefetch to those regions */
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static u_int32_t sect_flags[] = {
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[kARMMMUStronglyOrdered] = ARM_SECT_NOEXEC | ARM_SECT_FULLACC,
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[kARMMMUDevice] = ARM_SECT_NOEXEC | ARM_SECT_B | ARM_SECT_FULLACC,
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[kARMMMUNormal] = ARM_SECT_EXEC | ARM_SECT_C | ARM_SECT_B | ARM_SECT_FULLACC,
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[kARMMMUInnerNormalOuterNoncached] = ARM_SECT_EXEC | ARM_SECT_TEX(4) | ARM_SECT_C | ARM_SECT_B | ARM_SECT_FULLACC,
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[kARMMMUWriteCombined] = ARM_SECT_NOEXEC | ARM_SECT_TEX(1) | ARM_SECT_FULLACC,
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[kARMMMUNormalRX] = ARM_SECT_DOMAIN(1) | ARM_SECT_C | ARM_SECT_B | ARM_SECT_READ_ONLY | ARM_SECT_FULLACC,
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};
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static tt_ent attr_to_sect_flags(arm_mmu_attr_t attr)
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{
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if (attr >= kARMMMUNumAttr)
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attr = kARMMMUStronglyOrdered;
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return sect_flags[attr];
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}
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void arm_mmu_map_section(addr_t vaddr, addr_t paddr, arm_mmu_attr_t attr, bool shared)
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{
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if ((vaddr & (SECTION_SIZE - 1)) != 0)
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panic("section virtual address base is nonzero");
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if ((paddr & (SECTION_SIZE - 1)) != 0)
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panic("section physical address base is nonzero");
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tt[vaddr / MB] = paddr | ARM_DESC_SECT | attr_to_sect_flags(attr) | (shared ? ARM_SECT_SHARED : 0);
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arm_clean_dcache_line((unsigned long)&tt[vaddr / MB]);
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arm_flush_tlbs();
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}
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void arm_mmu_map_section_range(addr_t vaddr, addr_t paddr, size_t sections, arm_mmu_attr_t attr, bool shared, bool flush)
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{
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tt_ent entry, *tt_ptr;
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addr_t flush_start, flush_stop;
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u_int32_t cnt;
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if ((vaddr & (SECTION_SIZE - 1)) != 0)
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panic("section range virtual address base is nonzero");
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if ((paddr & (SECTION_SIZE - 1)) != 0)
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panic("section range physical address base is nonzero");
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entry = paddr | ARM_DESC_SECT | attr_to_sect_flags(attr) | (shared ? ARM_SECT_SHARED : 0);
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tt_ptr = &tt[vaddr / MB];
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while (sections > 0) {
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cnt = (sections < 16) ? sections : 16;
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switch (cnt) {
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case 16 : tt_ptr[15] = entry + MB * 15;
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case 15 : tt_ptr[14] = entry + MB * 14;
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case 14 : tt_ptr[13] = entry + MB * 13;
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case 13 : tt_ptr[12] = entry + MB * 12;
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case 12 : tt_ptr[11] = entry + MB * 11;
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case 11 : tt_ptr[10] = entry + MB * 10;
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case 10 : tt_ptr[ 9] = entry + MB * 9;
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case 9 : tt_ptr[ 8] = entry + MB * 8;
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case 8 : tt_ptr[ 7] = entry + MB * 7;
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case 7 : tt_ptr[ 6] = entry + MB * 6;
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case 6 : tt_ptr[ 5] = entry + MB * 5;
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case 5 : tt_ptr[ 4] = entry + MB * 4;
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case 4 : tt_ptr[ 3] = entry + MB * 3;
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case 3 : tt_ptr[ 2] = entry + MB * 2;
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case 2 : tt_ptr[ 1] = entry + MB * 1;
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case 1 : tt_ptr[ 0] = entry + MB * 0;
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}
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entry += MB * cnt;
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tt_ptr += cnt;
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sections -= cnt;
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}
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if (flush) {
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flush_start = ((addr_t)&tt[vaddr / MB]) & ~CPU_CACHELINE_SIZE;
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flush_stop = ((addr_t)tt_ptr + (CPU_CACHELINE_SIZE - 1)) & ~CPU_CACHELINE_SIZE;
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while (flush_start < flush_stop) {
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arm_clean_dcache_line(flush_start);
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flush_start += CPU_CACHELINE_SIZE;
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}
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arm_flush_tlbs();
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}
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}
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void arm_mmu_init(bool resume)
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{
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#ifdef MMU_TT_BASE
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/* TT usually at the end of memory */
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tt = (tt_ent *)MMU_TT_BASE;
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#endif
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if (false == resume) {
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/* identity map everything using the translation table as noncached */
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arm_mmu_map_section_range(0, 0, MMU_TT_SIZE / sizeof(tt_ent), kARMMMUStronglyOrdered, false, false);
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}
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/* let the platform code get a shot at mapping some ranges */
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platform_mmu_setup(resume);
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/* set up the domain register */
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arm_write_dar(0x7); /* domain 0 manager, domain 1 client */
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/* write the new translation table */
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#if MMU_TT_SIZE == 0x4000
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arm_write_ttbcr(0);
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#elif (MMU_TT_SIZE == 0x1000) && (WITH_MMU_SECURITY_EXTENSIONS)
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arm_write_ttbcr(2 | TTBCR_PD1);
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#else
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#error "Must set up TTBCR appropriately for translation table smaller than 16 kB"
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#endif
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arm_write_ttb(tt);
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arm_flush_tlbs();
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}
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u_int32_t arm_get_noncached_address(u_int32_t address)
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{
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#ifdef MMU_NONCACHE0_SIZE
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if (((int32_t)(address - MMU_NONCACHE0_PBASE) >= 0) && ((address - MMU_NONCACHE0_PBASE) < MMU_NONCACHE0_SIZE)) {
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return address - MMU_NONCACHE0_PBASE + MMU_NONCACHE0_VBASE;
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}
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#endif
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#ifdef MMU_NONCACHE1_SIZE
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if (((int32_t)(address - MMU_NONCACHE1_PBASE) >= 0) && ((address - MMU_NONCACHE1_PBASE) < MMU_NONCACHE1_SIZE)) {
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return address - MMU_NONCACHE1_PBASE + MMU_NONCACHE1_VBASE;
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}
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#endif
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return 0xFFFFFFFF;
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}
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