997 lines
28 KiB
C
997 lines
28 KiB
C
/*
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* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <assert.h>
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#include <arch.h>
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#include <platform.h>
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#include <platform/int.h>
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#include <platform/clocks.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/hwisr.h>
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#include <platform/soc/hwregbase.h>
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#include <platform/soc/pmgr.h>
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#include <sys.h>
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#include <sys/task.h>
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#include <sys/callout.h>
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#include <drivers/displayport/displayport.h>
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#include <drivers/displayport.h>
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#include <drivers/lpdp_phy/lpdp_phy.h>
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#include "regs_v2.h"
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#if WITH_DEVICETREE
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#include <lib/devicetree.h>
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#endif
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/////////////////////////////////////////
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////////// debug support
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#define LPDP_DEBUG_MASK ( \
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LPDP_DEBUG_INIT | \
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LPDP_DEBUG_ERROR | \
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LPDP_DEBUG_INFO | \
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LPDP_DEBUG_PLL | \
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LPDP_DEBUG_PHY | \
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0)
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#undef LPDP_DEBUG_MASK
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#define LPDP_DEBUG_MASK (LPDP_DEBUG_INIT | LPDP_DEBUG_ERROR)
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#define LPDP_DEBUG_INIT (1<<16) // initialisation
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#define LPDP_DEBUG_ERROR (1<<17) // errors
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#define LPDP_DEBUG_INFO (1<<18) // info
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#define LPDP_DEBUG_PLL (1<<24) // PLL
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#define LPDP_DEBUG_PHY (1<<25) // PLL
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#define LPDP_DEBUG_ALWAYS (1<<31) // unconditional output
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#define debug(_fac, _fmt, _args...) \
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do { \
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if ((LPDP_DEBUG_ ## _fac) & (LPDP_DEBUG_MASK | LPDP_DEBUG_ALWAYS)) \
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dprintf(DEBUG_CRITICAL, "DP: %s, %d: " _fmt, __FUNCTION__, __LINE__, ##_args); \
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} while(0)
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#define kMaxLaneCount 4
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#define kLinkRatePhysical_162gbpsi 1620000000ULL
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#define kLinkRatePhysical_270gps 2700000000ULL
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//ERRORS
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#define RET_SUCCESS 0
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#define RET_ERROR -1
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#ifndef LPDP_PHY_VERSION
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#error LPDP_PHY_VERSION undefined
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#endif
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#ifndef LPDP_LINK_CAL_TABLE_VERSION
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#error LPDP_LINK_CAL_TABLE_VERSION undefined
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#endif
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/////////////////////////////////////////
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////////// typedefs, enums, structs
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enum {
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kDPAuxTranscationStatus_None = -1,
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kDPAuxTranscationStatus_Success,
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kDPAuxTranscationStatus_IODefer,
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kDPAuxTranscationStatus_IOError,
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kDPAuxTranscationStatus_OtherError
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};
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enum {
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kBaseVoltageType_Neg_120mV,
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kBaseVoltageType_Neg_80mV,
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kBaseVoltageType_Neg_40mV,
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kBaseVoltageType_Pos_0mV,
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kBaseVoltageType_Pos_40mV,
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kBaseVoltageType_Pos_80mV,
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kBaseVoltageType_Pos_120mV,
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kBaseVoltageType_Pos_160mV
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};
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/*
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Device tree calibration data formats:
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link-calibration-type: t700x-fixed
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link-calibration-data: ${ VS DE }
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link-calibration-type: t700x-training-table
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link-calibration-data: ${ VS DE VS DE VS DE VS DE } // voltage swing level 0, pre-emphasis levels 0~3
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link-calibration-data: ${ VS DE VS DE VS DE 00 00 } // voltage swing level 1, pre-emphasis levels 0~3
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link-calibration-data: ${ VS DE VS DE 00 00 00 00 } // voltage swing level 2, pre-emphasis levels 0~3
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link-calibration-data: ${ VS DE 00 00 00 00 00 00 } // voltage swing level 3, pre-emphasis level 0~3
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link-calibration-type: s800x-fixed
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link-calibration-data: $VS $R
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link-calibration-type: s800x-training-table
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link-calibration-data: $VS $R $VS $R $VS $R $VS $R // voltage swing level 0, pre-emphasis levels 0~3
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link-calibration-data: $VS $R $VS $R $VS $R $00 $00 // voltage swing level 1, pre-emphasis levels 0~3
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link-calibration-data: $VS $R $VS $R $00 $00 $00 $00 // voltage swing level 2, pre-emphasis levels 0~3
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link-calibration-data: $VS $R $00 $00 $00 $00 $00 $00 // voltage swing level 3, pre-emphasis level 0~3
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*/
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#if LPDP_LINK_CAL_TABLE_VERSION < 2
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struct lpdp_port_calibration {
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uint8_t swing;
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uint8_t deemphasis;
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} __attribute__((packed));
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static const char *training_table_text = "t700x-training-table";
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static const char *fixed_text = "t700x-fixed";
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#else
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struct lpdp_port_calibration {
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uint32_t swing;
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uint32_t r;
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} __attribute__((packed));
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static const char *training_table_text = "s800x-training-table";
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static const char *fixed_text = "s800x-fixed";
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#endif
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#if WITH_HW_DISPLAY_EDP
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#include <target/lpdp_settings.h>
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#ifndef LPDP_PORT_CALIBRATION_TABLE_FIXED
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#error LPDP_PORT_CALIBRATION_TABLE_FIXED not defined
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#endif
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#else
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static struct lpdp_port_calibration lpdp_port_calibration_table[kDPVoltageLevelMax+1][kDPEQLevelMax+1];
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#endif
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struct pll_timing {
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// reference clock frequency in MHz
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unsigned int ref_mhz;
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// sequencer configuration
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unsigned int ref_div : 5; // sequencer divisor
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unsigned int setup_count : 8; // sequencer ticks
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unsigned int start_count : 8; // sequencer ticks
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unsigned int pwrdn_count : 14; // sequencer ticks
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unsigned int reset_count : 8; // sequencer ticks
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unsigned int update_count : 8; // sequencer ticks
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unsigned int finish_count : 8; // sequencer ticks
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unsigned int wakeup_count : 8; // sequencer ticks
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unsigned int hold_count : 8; // sequencer ticks
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};
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typedef enum {
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lpdp_pll_state_off = 0,
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lpdp_pll_state_on = 1,
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lpdp_pll_state_unknown = 2,
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} lpdp_pll_state_t;
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/////////////////////////////////////////
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////////// PHY local variables
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static addr_t __base_address = LPDP_PHY_BASE_ADDR;
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static uint32_t _linkRate;
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static bool lpdp_pll_state = true;
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static uint32_t lpdp_voltage_levels[kMaxLaneCount];
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static uint32_t lpdp_voltage_base[kMaxLaneCount];
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static uint32_t lpdp_eq_levels[kMaxLaneCount];
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static uint32_t lpdp_voltage_levels[kMaxLaneCount];
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static bool lpdp_port_calibration_table_fixed;
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static uint32_t pll_vco_rctrl;
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static struct pll_timing lpdp_pll_timing;
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static uint32_t t_cal_duration_microseconds;
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/////////////////////////////////////////
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////////// PHY local functions
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static void set_bias_power_enable(bool enable);
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static void set_aux_power_enable(bool enable);
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static void set_lane_power_controls(unsigned int first, unsigned int limit, uint32_t mask, uint32_t bits);
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static void set_lane_power_enable(bool enable);
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static bool lpdp_get_pll_is_locked();
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static void set_aux_voltage_swing(uint32_t vreg_adj);
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#if LPDP_PHY_VERSION < 2
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static void set_phy_configure_ldos(uint32_t ldopre_vreg_adj, uint32_t ldoclk_vreg_adj, uint32_t auxvreg_adj);
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#endif
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static void enable_phy_ldos();
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#if LPDP_LINK_CAL_TABLE_VERSION < 2
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static void set_lane_adjustment_levels(unsigned int lane, uint8_t vreg_adj, uint8_t eq);
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#else
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static void set_lane_adjustment_levels(unsigned int lane, uint32_t vreg_adj, uint32_t r);
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#endif
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static int update_pll_dividers(uint32_t lr);
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static int lpdp_power_pll(bool poweron);
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static int lpdp_power_down_pll();
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static int lpdp_power_up_pll();
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static int lpdp_phy_impedance_calibration(void);
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static unsigned int micro_seconds_for_count(struct pll_timing *tm, unsigned int count);
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static unsigned int get_sleep_to_power_down_duration(struct pll_timing *tm);
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static unsigned int get_power_down_duration(struct pll_timing *tm);
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static unsigned int get_reset_duration(struct pll_timing *tm);
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static unsigned int get_reset_to_update_duration(struct pll_timing *tm);
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static unsigned int get_lock_duration(struct pll_timing *tm);
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static uint32_t read_reg(uint32_t offset);
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static void write_reg(uint32_t offset, uint32_t val);
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static void and_reg(uint32_t offset, uint32_t val);
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static void or_reg(uint32_t offset, uint32_t val);
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static void set_bits_in_reg(uint32_t offset, uint32_t pos, uint32_t mask, uint32_t value);
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/////////////////////////////////////////
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////////// PHY global functions
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int lpdp_init(const char *dt_path)
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{
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int i;
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for (i = 0; i < kMaxLaneCount; i++)
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lpdp_voltage_base[i] = kBaseVoltageType_Pos_0mV;
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t_cal_duration_microseconds = 1000; // 1ms
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lpdp_pll_state = lpdp_pll_state_unknown;
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// Note: 200uS is the worst-case from pll_pwrdn to PLL locked under all
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// conditions and settings per <rdar://problem/15238851>.
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// The period from pll_pwrdn to PLL locked is:
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// reset_count + update_count + finish_count
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lpdp_pll_timing.ref_mhz = 24;
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lpdp_pll_timing.ref_div = 24; // ref clock ticks per (1µs) sequencer tick
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lpdp_pll_timing.setup_count = 4; // µs
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lpdp_pll_timing.start_count = 1; // µs
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lpdp_pll_timing.pwrdn_count = 10; // µs
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lpdp_pll_timing.reset_count = 100; // µs
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lpdp_pll_timing.update_count = 5; // µs
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lpdp_pll_timing.finish_count = 50; // µs
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#if WITH_HW_DISPLAY_EDP
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lpdp_port_calibration_table_fixed = LPDP_PORT_CALIBRATION_TABLE_FIXED;
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#else
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#if WITH_DEVICETREE
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DTNodePtr node;
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char * prop_name;
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void * prop_data;
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uint32_t prop_size;
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// Copy DT settings in to local copy
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if ( FindNode(0, dt_path, &node) ) {
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prop_name = "link-calibration-type";
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if ( FindProperty(node, &prop_name, &prop_data, &prop_size) ) {
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if (strcmp(training_table_text, prop_data) == 0) {
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lpdp_port_calibration_table_fixed = false;
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} else if (strcmp(fixed_text, prop_data) == 0) {
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lpdp_port_calibration_table_fixed = true;
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} else {
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panic("Unknown DT LPDP Calibration Table Type.");
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}
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} else {
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panic("Missing DT LPDP Calibration Table Type.");
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}
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// gather calibration data from DeviceTree
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prop_name = "link-calibration-data";
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if ( FindProperty(node, &prop_name, &prop_data, &prop_size) ) {
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uint32_t table_size = (lpdp_port_calibration_table_fixed) ?
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sizeof(struct lpdp_port_calibration) : sizeof(struct lpdp_port_calibration) * 16;
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if ( prop_size != table_size ) {
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debug(ERROR, "calibration-data size mismatch, expected:%d, read:%d \n",
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table_size, prop_size);
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return -1;
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}
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bcopy(prop_data, (void *)lpdp_port_calibration_table, prop_size);
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} else {
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panic("Missing DT LPDP Calibration Table Data.");
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}
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} else
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#endif
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{
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debug(ERROR, "Missing DT LPDP Calibration Table. Using Defaults\n");
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lpdp_port_calibration_table_fixed = true;
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#if LPDP_LINK_CAL_TABLE_VERSION < 2
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lpdp_port_calibration_table[0][0].swing = LPDP_PHY_LANE_x_VREG_ADJ_MAX;
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lpdp_port_calibration_table[0][0].deemphasis = 0;
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#else
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lpdp_port_calibration_table[0][0].swing = LPDP_PHY_LANE_x_VREG_ADJ_MAX;
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lpdp_port_calibration_table[0][0].r = 0;
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#endif
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}
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#endif
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//the block should had been properly reset. validating such assumption
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assert(read_reg(rLPDP_PHY_GEN_CTRL) & (LPDP_PHY_GEN_CTRL_SEQ_OW | LPDP_PHY_GEN_CTRL_LANE_PD_OW));
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assert(read_reg(rLPDP_PLL_GEN) & LPDP_PLL_GEN_RST);
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//extract Configuration of PLL
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//PMGR should have programmed correctly
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//we save the value to pass to the OS.
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pll_vco_rctrl = read_reg(rLPDP_PLL_CLK);
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if (pll_vco_rctrl & LPDP_PLL_CLK_VCO_RCTRL_SEL_ENABLE)
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pll_vco_rctrl = ((pll_vco_rctrl >> LPDP_PLL_CLK_VCO_RCTRL_OW_SHIFT) & LPDP_PLL_CLK_VCO_RCTRL_OW_MASK);
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else
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pll_vco_rctrl = 0;
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return RET_SUCCESS;
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}
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int lpdp_initialize_phy_and_pll(void)
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{
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int ret = RET_SUCCESS;
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int i;
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// ensure lane_pd_ow=1 (default) to allow software control of lane power
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or_reg(rLPDP_PHY_GEN_CTRL, (LPDP_PHY_GEN_CTRL_SEQ_OW | LPDP_PHY_GEN_CTRL_SLEEP_SW ));
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#if LPDP_PHY_VERSION < 2
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for (i = 0 ; i < kMaxLaneCount; i++) {
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set_lane_adjustment_levels(i, LPDP_PHY_LANE_VREG_ADJ_420_mV, 0);
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}
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//TODO!!
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set_aux_voltage_swing(0xA);
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set_phy_configure_ldos(0x4, 0x4, 0x3);
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#elif LPDP_PHY_VERSION == 2
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for (i = 0 ; i < kMaxLaneCount; i++) {
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set_lane_adjustment_levels(i, LPDP_PHY_LANE_VREG_ADJ_450_mV, 0);
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}
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//TODO!!
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set_aux_voltage_swing(0x6);
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#endif
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//reset calibration
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write_reg(rLPDP_PHY_CAL, 0);
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#if LPDP_PHY_VERSION < 2
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write_reg(rLPDP_PHY_RESERVED, (1 << 4));
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#endif
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write_reg(rLPDP_PHY_CLK_CTRL, LPDP_PHY_CLK_CTRL_CLK_ENABLE | LPDP_PHY_CLK_CTRL_CLKDIV5_RESET);
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or_reg(rLPDP_PHY_GEN_CTRL, LPDP_PHY_GEN_CTRL_LANE_PD_OW);
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set_bias_power_enable(true);
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// power up all lanes
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set_lane_power_enable(true);
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enable_phy_ldos();
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set_aux_power_enable(true);
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#if LPDP_PHY_VERSION < 2
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and_reg(rLPDP_PHY_BIST, ~LPDP_PHY_BIST_LOOPBACK_SRC_SEL(LPDP_PHY_BIST_LOOPBACK_SRC_SEL_MASK));
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#endif
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spin(1000); //1 ms
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spin(10); //10 us
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write_reg(rLPDP_PHY_CAL, LPDP_PHY_CAL_RESET_N);
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#if LPDP_PHY_VERSION < 2
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and_reg(rLPDP_PHY_RESERVED, ~(1 << 4));
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#endif
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and_reg(rLPDP_PHY_CLK_CTRL, ~LPDP_PHY_CLK_CTRL_CLKDIV5_RESET);
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spin(10); //10 us
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// perform PHY impedance calibration
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ret = lpdp_phy_impedance_calibration();
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// panic if impedance calibration procedure failed
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if ( ret != 0 ) {
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panic("lpdp impedance calibration failed\n");
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}
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set_lane_power_controls(0, kMaxLaneCount, LPDP_PHY_LANE_HI_Z, 0);
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//configure PLL to an initial value
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lpdp_set_link_rate(kLinkRate162Gbps);
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#if LPDP_PHY_VERSION < 2
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write_reg(rLPDP_GEN_DISPLAY_SPLIT, 0);
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#endif
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return ret;
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}
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void lpdp_init_finalize(void)
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{
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//remove the overrides
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and_reg(rLPDP_PHY_GEN_CTRL, ~(LPDP_PHY_GEN_CTRL_SEQ_OW | LPDP_PHY_GEN_CTRL_LANE_PD_OW));
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}
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void lpdp_quiesce()
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{
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// power down all lanes [LANE_x.hi_z=1, LANE_x.ldo_pwrdn=1, LANE_x.pwrdn=1]
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set_lane_power_enable(false);
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// power down AUX channel [AUX_CTRL.pwrdn=1]
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set_aux_power_enable(false);
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// power down PHY's central bias [GEN_CTRL.bias_pwrdn=1]
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set_bias_power_enable(false);
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// assert lpdp_sleep, pll_pwrdn, and pll_reset
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lpdp_power_pll(false);
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}
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int lpdp_set_link_rate(uint32_t lr)
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{
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int ret = 0;
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debug(PHY, "Setting link rate to 0x%02x\n", (uint8_t)lr);
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#if LPDP_PHY_VERSION == 2
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//<rdar://problem/20158240> Bug Fix for Default Register Value of asg_adppll Calibration Reset
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or_reg(rLPDP_PLL_FCAL, LPDP_PLL_FCAL_RESET);
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#endif
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// Block clock output during PLL setup
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or_reg(rLPDP_PLL_CLK, LPDP_PLL_CLK_VCO_BLK_VCLK);
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// assert lpdp_sleep, pll_pwrdn, and pll_reset
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lpdp_power_pll(false);
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// initialize link rate to 0
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_linkRate = kLinkRate000Gbps;
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// if the target link rate is nonzero, reconfigure and power up the PLL
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if ( lr > kLinkRate000Gbps ) {
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// update PLL dividers for new link rate
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if (update_pll_dividers(lr)) {
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ret = -1;
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goto exit;
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}
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// power up PLL and wait for lock,
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// if this fails, power it back down and leave link rate at 0
|
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if (lpdp_power_pll(true)) {
|
|
ret = -1;
|
|
lpdp_power_pll(false);
|
|
goto exit;
|
|
}
|
|
|
|
// finally, update the current link rate
|
|
_linkRate = lr;
|
|
}
|
|
|
|
exit:
|
|
return ret;
|
|
}
|
|
|
|
int lpdp_get_link_rate(uint32_t *link_rate)
|
|
{
|
|
*link_rate = _linkRate;
|
|
return RET_SUCCESS;
|
|
}
|
|
|
|
int lpdp_phy_set_adjustment_levels(uint32_t lane, uint32_t voltage_swing, uint32_t eq,
|
|
bool *voltage_max_reached, bool *eq_max_reached)
|
|
{
|
|
int ret = 0;
|
|
|
|
if ( lane > kMaxLaneCount )
|
|
return -1;
|
|
|
|
debug(PHY, "lane=%d voltage=%d eq=%d\n", lane, voltage_swing, eq);
|
|
|
|
if (voltage_swing > kDPVoltageLevelMax) {
|
|
voltage_swing = kDPVoltageLevelMax;
|
|
}
|
|
|
|
if (eq > kDPEQLevelMax) {
|
|
eq = kDPEQLevelMax;
|
|
}
|
|
|
|
if (lpdp_port_calibration_table_fixed) {
|
|
#if LPDP_LINK_CAL_TABLE_VERSION < 2
|
|
set_lane_adjustment_levels(lane,
|
|
lpdp_port_calibration_table[0][0].swing,
|
|
lpdp_port_calibration_table[0][0].deemphasis);
|
|
#else
|
|
set_lane_adjustment_levels(lane,
|
|
lpdp_port_calibration_table[0][0].swing,
|
|
lpdp_port_calibration_table[0][0].r);
|
|
#endif
|
|
} else {
|
|
#if LPDP_LINK_CAL_TABLE_VERSION < 2
|
|
set_lane_adjustment_levels(lane,
|
|
lpdp_port_calibration_table[voltage_swing][eq].swing,
|
|
lpdp_port_calibration_table[voltage_swing][eq].deemphasis);
|
|
#else
|
|
set_lane_adjustment_levels(lane,
|
|
lpdp_port_calibration_table[voltage_swing][eq].swing,
|
|
lpdp_port_calibration_table[voltage_swing][eq].r);
|
|
#endif
|
|
}
|
|
|
|
if (voltage_max_reached) {
|
|
*voltage_max_reached = (voltage_swing == kDPVoltageLevelMax);
|
|
}
|
|
|
|
if (eq_max_reached) {
|
|
*eq_max_reached = (eq == kDPEQLevelMax);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
void lpdp_phy_reset()
|
|
{
|
|
lpdp_phy_impedance_calibration();
|
|
}
|
|
|
|
bool lpdp_get_supports_downspread()
|
|
{
|
|
return false;
|
|
}
|
|
|
|
int lpdp_set_downspread(bool value)
|
|
{
|
|
//not supported but needs to succeed.. hence noop
|
|
return RET_SUCCESS;
|
|
}
|
|
|
|
int lpdp_get_downspread(void)
|
|
{
|
|
//not supported but needs to succeed.. hence noop
|
|
return RET_SUCCESS;
|
|
}
|
|
|
|
int lpdp_phy_get_adjustment_levels(uint32_t lane, uint32_t *voltage_swing, uint32_t *eq)
|
|
{
|
|
if (eq)
|
|
*eq = lpdp_eq_levels[lane];
|
|
|
|
if (voltage_swing)
|
|
*voltage_swing = lpdp_voltage_levels[lane];
|
|
|
|
return RET_SUCCESS;
|
|
}
|
|
|
|
void lpdp_phy_set_lane_count(const uint32_t lane_count)
|
|
{
|
|
// enable active lanes
|
|
set_lane_power_controls(0, lane_count, LPDP_PHY_LANE_HI_Z, 0);
|
|
|
|
// disable inactive lanes
|
|
set_lane_power_controls(lane_count, kMaxLaneCount, LPDP_PHY_LANE_HI_Z, LPDP_PHY_LANE_HI_Z);
|
|
}
|
|
|
|
#if WITH_DEVICETREE
|
|
|
|
#include <lib/devicetree.h>
|
|
|
|
int lpdp_phy_update_device_tree(DTNode *lpdp_node)
|
|
{
|
|
u_int32_t propSize;
|
|
char *propName;
|
|
void *propData;
|
|
|
|
if (lpdp_node == NULL) {
|
|
return RET_ERROR;
|
|
}
|
|
propName = "pll_vco_rctrl";
|
|
if (FindProperty(lpdp_node, &propName, &propData, &propSize)) {
|
|
if (pll_vco_rctrl == 0) {
|
|
((char **)propData)[0] = "~";
|
|
} else {
|
|
((u_int32_t *)propData)[0] = pll_vco_rctrl;
|
|
}
|
|
}
|
|
|
|
#if WITH_HW_DISPLAY_EDP
|
|
// Copy local settings to the DT
|
|
propName = "link-calibration-type";
|
|
if ( FindProperty(lpdp_node, &propName, &propData, &propSize) ) {
|
|
memset(propData, 0, propSize);
|
|
if (lpdp_port_calibration_table_fixed) {
|
|
if (propSize < strlen(fixed_text) + 1) {
|
|
panic("link-calibration-type DT entry too small.");
|
|
}
|
|
snprintf(propData, propSize, "%s", fixed_text);
|
|
} else {
|
|
if (propSize < strlen(training_table_text) + 1) {
|
|
panic("link-calibration-type DT entry too small.");
|
|
}
|
|
snprintf(propData, propSize, "%s", training_table_text);
|
|
}
|
|
} else {
|
|
panic("Missing DT LPDP Calibration Table Type.");
|
|
}
|
|
|
|
propName = "link-calibration-data";
|
|
if ( FindProperty(lpdp_node, &propName, &propData, &propSize) ) {
|
|
memset(propData, 0, propSize);
|
|
uint32_t table_size = (lpdp_port_calibration_table_fixed) ?
|
|
sizeof(struct lpdp_port_calibration) : sizeof(struct lpdp_port_calibration) * 16;
|
|
if (propSize < table_size) {
|
|
panic("link-calibration-data table too small.");
|
|
}
|
|
bcopy((void *)lpdp_port_calibration_table, propData, table_size);
|
|
} else {
|
|
panic("Missing DT LPDP Calibration Table Data.");
|
|
}
|
|
#endif
|
|
|
|
return RET_SUCCESS;
|
|
}
|
|
#endif //WITH_DEVICETREE
|
|
|
|
/////////////////////////////////////////
|
|
////////// PHY local functions
|
|
|
|
static int lpdp_phy_impedance_calibration( void )
|
|
{
|
|
int result = RET_SUCCESS;
|
|
uint32_t reg;
|
|
|
|
// Let the pull down calibration start
|
|
or_reg(rLPDP_PHY_CAL, LPDP_PHY_CAL_START);
|
|
|
|
// Wait for calibration to complete
|
|
spin(t_cal_duration_microseconds);
|
|
|
|
reg = read_reg(rLPDP_PHY_CAL);
|
|
if (!(reg & LPDP_PHY_CAL_DONE) || (reg & LPDP_PHY_CAL_FAIL)) {
|
|
printf("impedance Calibration failed rLPDP_PHY_CAL 0x%x\n", reg);
|
|
result = RET_ERROR;
|
|
}
|
|
|
|
spin(1);
|
|
|
|
and_reg(rLPDP_PHY_CAL, ~LPDP_PHY_CAL_START);
|
|
|
|
return result;
|
|
}
|
|
|
|
static void set_bias_power_enable(bool enable)
|
|
{
|
|
uint32_t rmw = read_reg(rLPDP_PHY_GEN_CTRL);
|
|
rmw &= ~( LPDP_PHY_GEN_CTRL_BIAS_PWRDN);
|
|
rmw |= ( enable ? 0 : LPDP_PHY_GEN_CTRL_BIAS_PWRDN);
|
|
write_reg(rLPDP_PHY_GEN_CTRL, rmw);
|
|
}
|
|
|
|
static void set_aux_power_enable(bool enable)
|
|
{
|
|
uint32_t rmw = read_reg(rLPDP_PHY_AUX_CTRL);
|
|
rmw &= ~(LPDP_PHY_AUX_CTRL_PWRDN);
|
|
rmw |= ( enable ? 0 : LPDP_PHY_AUX_CTRL_PWRDN);
|
|
write_reg(rLPDP_PHY_AUX_CTRL, rmw);
|
|
}
|
|
|
|
static void set_lane_power_enable(bool enable)
|
|
{
|
|
uint32_t bits = enable ? 0 : LPDP_PHY_LANE_x_FULL_DISABLE;
|
|
|
|
set_lane_power_controls(0, kMaxLaneCount, LPDP_PHY_LANE_x_FULL_DISABLE, bits);
|
|
}
|
|
|
|
static void set_lane_power_controls(unsigned int first, unsigned int limit, uint32_t mask, uint32_t bits)
|
|
{
|
|
for (unsigned int i = first; i < limit; i++) {
|
|
// allow at least 5ns between lane power/enable state changes
|
|
spin(1);
|
|
|
|
// set power state of lane 'i'
|
|
uint32_t rmw = read_reg(rLPDP_PHY_LANE(i));
|
|
rmw &= ~mask;
|
|
rmw |= bits;
|
|
write_reg(rLPDP_PHY_LANE(i), rmw);
|
|
}
|
|
}
|
|
|
|
static bool lpdp_get_pll_is_locked()
|
|
{
|
|
return (read_reg(rLPDP_PLL_LOCK) & LPDP_PLL_LOCK_OUT_ON);
|
|
}
|
|
|
|
#if LPDP_PHY_VERSION < 2
|
|
static void set_phy_configure_ldos(uint32_t ldopre_vreg_adj, uint32_t ldoclk_vreg_adj, uint32_t auxvreg_adj)
|
|
{
|
|
uint32_t reg;
|
|
|
|
reg = read_reg(rLPDP_PHY_PRE_LDO_CTRL);
|
|
reg &= ~(LPDP_PHY_PRE_LDO_CTR_LDOPRE_VREG_ADJ(0xf));
|
|
reg |= LPDP_PHY_PRE_LDO_CTR_LDOPRE_VREG_ADJ(ldopre_vreg_adj);
|
|
write_reg(rLPDP_PHY_PRE_LDO_CTRL, reg);
|
|
|
|
reg = read_reg(rLPDP_PHY_CLK_LDO_CTRL);
|
|
reg &= ~LPDP_PHY_CLK_LDO_CTRL_LDOCLK_VREG_ADJ(0xf);
|
|
reg |= LPDP_PHY_CLK_LDO_CTRL_LDOCLK_VREG_ADJ(ldoclk_vreg_adj);
|
|
write_reg(rLPDP_PHY_CLK_LDO_CTRL, reg);
|
|
|
|
reg = read_reg(rLPDP_PHY_AUX_LDO_CTRL);
|
|
reg &= ~LPDP_PHY_AUX_LDO_CTRL_AUXVREG_ADJ(0xf);
|
|
reg |= LPDP_PHY_AUX_LDO_CTRL_AUXVREG_ADJ(auxvreg_adj);
|
|
write_reg(rLPDP_PHY_AUX_LDO_CTRL, reg);
|
|
}
|
|
#endif
|
|
|
|
static void enable_phy_ldos()
|
|
{
|
|
#if LPDP_PHY_VERSION < 2
|
|
and_reg(rLPDP_PHY_CLK_LDO_CTRL, ~LPDP_PHY_CLK_LDO_CTRL_LDOCLK_PWRDN(LPDP_PHY_CLK_LDO_CTRL_LDOCLK_PWRDN_MAX));
|
|
and_reg(rLPDP_PHY_PRE_LDO_CTRL, ~LPDP_PHY_PRE_LDO_CTR_LDOPRE_PWRDN(LPDP_PHY_PRE_LDO_CTR_LDOPRE_PWRDN_MAX));
|
|
and_reg(rLPDP_PHY_AUX_LDO_CTRL, ~LPDP_PHY_AUX_LDO_CTRL_AUXLDO_PWRDN);
|
|
#elif LPDP_PHY_VERSION == 2
|
|
and_reg(rLPDP_PHY_CLK_LDO_CTRL, ~(LPDP_PHY_CLK_LDO_CTRL_LDOCLK_PWRDN_SML(LPDP_PHY_CLK_LDO_CTRL_LDOCLK_PWRDN_SML_MAX)|
|
|
LPDP_PHY_CLK_LDO_CTRL_LDOCLK_PWRDN(LPDP_PHY_CLK_LDO_CTRL_LDOCLK_PWRDN_MAX)));
|
|
and_reg(rLPDP_PHY_AUX_LDO_CTRL, ~(LPDP_PHY_AUX_LDO_CTRL_LDOPOST_PWRDN_SML|LPDP_PHY_AUX_LDO_CTRL_LDOCLK_PWRDN_SML|
|
|
LPDP_PHY_AUX_LDO_CTRL_LDOPOST_PWRDN_BIG|LPDP_PHY_AUX_LDO_CTRL_LDOCLK_PWRDN_BIG));
|
|
#endif
|
|
}
|
|
|
|
static void set_aux_voltage_swing(uint32_t vreg_adj)
|
|
{
|
|
uint32_t rmw = read_reg(rLPDP_PHY_AUX_CTRL);
|
|
rmw &= ~LPDP_PHY_AUX_CTRL_VREG_ADJ_MASK;
|
|
rmw |= vreg_adj << LPDP_PHY_AUX_CTRL_VREG_ADJ_SHIFT;
|
|
write_reg(rLPDP_PHY_AUX_CTRL, rmw);
|
|
}
|
|
|
|
|
|
#if LPDP_LINK_CAL_TABLE_VERSION < 2
|
|
static void set_lane_adjustment_levels(unsigned int lane, uint8_t voltage_swing, uint8_t eq)
|
|
#else
|
|
static void set_lane_adjustment_levels(unsigned int lane, uint32_t voltage_swing, uint32_t r)
|
|
#endif
|
|
{
|
|
uint32_t rmw = read_reg(rLPDP_PHY_LANE(lane));
|
|
rmw &= ~(LPDP_PHY_LANE_x_VREG_ADJ_MASK);
|
|
rmw |= LPDP_PHY_LANE_VREG_ADJ(voltage_swing);
|
|
write_reg(rLPDP_PHY_LANE(lane), rmw);
|
|
|
|
lpdp_voltage_levels[lane] = voltage_swing;
|
|
#if LPDP_LINK_CAL_TABLE_VERSION < 2
|
|
lpdp_eq_levels[lane] = eq;
|
|
#else
|
|
#if LPDP_LINK_CAL_TABLE_VERSION < 3
|
|
// Maui
|
|
lpdp_eq_levels[lane] = (((((rLPDP_PHY_CAL_TX & LPDP_PHY_CAL_TX_CODE_FSM_MASK) >> LPDP_PHY_CAL_TX_CODE_FSM_SHIFT) * r) / 2) + (1 << 15)) >> 16;
|
|
#else
|
|
// Elba/Malta +
|
|
lpdp_eq_levels[lane] = ((((((rLPDP_PHY_CAL_TX & LPDP_PHY_CAL_TX_CODE_FSM_MASK) >> LPDP_PHY_CAL_TX_CODE_FSM_SHIFT) + 24) * r) / 2) + (1 << 15)) >> 16;
|
|
#endif
|
|
#endif
|
|
}
|
|
|
|
//TODO: Get the correct values for gclk_div
|
|
static int update_pll_dividers(uint32_t lr)
|
|
{
|
|
int ret = 0;
|
|
uint32_t fb;
|
|
uint32_t pre;
|
|
|
|
// determine feedback and pre-divider ratios
|
|
switch ( lr ) {
|
|
case kLinkRate000Gbps:
|
|
fb = pre = 0;
|
|
break;
|
|
|
|
case kLinkRate162Gbps:
|
|
fb = 135;
|
|
pre = 4;
|
|
break;
|
|
|
|
case kLinkRate270Gbps:
|
|
fb = 225;
|
|
pre = 4;
|
|
break;
|
|
|
|
case kLinkRate324Gbps:
|
|
fb = 135;
|
|
pre = 2;
|
|
break;
|
|
|
|
case kLinkRate540Gbps: // Not supported on Fiji/Capri
|
|
fb = 225;
|
|
pre = 2;
|
|
break;
|
|
|
|
default:
|
|
debug(ERROR, "unsupported link rate: %u", lr);
|
|
ret = -1;
|
|
goto exit;
|
|
}
|
|
|
|
// Set new PLL divider ratios
|
|
uint32_t rmw = read_reg(rLPDP_PLL_IDIV);
|
|
rmw &= ~LPDP_PLL_IDIV_FB_MASK;
|
|
rmw |= (fb << LPDP_PLL_IDIV_FB_SHIFT);
|
|
rmw &= ~LPDP_PLL_IDIV_PRE_MASK;
|
|
rmw |= (pre << LPDP_PLL_IDIV_PRE_SHIFT);
|
|
write_reg(rLPDP_PLL_IDIV, rmw);
|
|
and_reg(rLPDP_PLL_GEN, ~(LPDP_PLL_GEN_GCLK_DIV(LPDP_PLL_GEN_GCLK_DIV_MASK)));
|
|
|
|
exit:
|
|
return ret;
|
|
}
|
|
|
|
static int lpdp_power_pll(bool poweron)
|
|
{
|
|
int result = RET_ERROR;
|
|
|
|
if ((lpdp_pll_state != lpdp_pll_state_unknown) && (lpdp_pll_state == poweron))
|
|
return RET_SUCCESS;
|
|
|
|
lpdp_pll_state = poweron;
|
|
if (poweron)
|
|
result = lpdp_power_up_pll();
|
|
else
|
|
result = lpdp_power_down_pll();
|
|
return result;
|
|
}
|
|
|
|
static int lpdp_power_down_pll()
|
|
{
|
|
or_reg(rLPDP_PHY_GEN_CTRL, (LPDP_PHY_GEN_CTRL_SEQ_OW | LPDP_PHY_GEN_CTRL_SLEEP_SW));
|
|
|
|
spin(31); //> 30 ns
|
|
|
|
// de-assert pll_pwrdn after at least 10µS
|
|
and_reg(rLPDP_PLL_GEN, ~LPDP_PLL_GEN_PWRDN);
|
|
|
|
//spin(get_reset_duration(&lpdp_pll_timing));
|
|
spin(100);
|
|
|
|
or_reg(rLPDP_PLL_CLK, LPDP_PLL_CLK_VCO_BLK_VCLK);
|
|
// de-assert pll_reset after at least 100µS
|
|
and_reg(rLPDP_PLL_GEN, ~LPDP_PLL_GEN_RST);
|
|
or_reg(rLPDP_PLL_GEN, (LPDP_PLL_GEN_PWRDN | LPDP_PLL_GEN_RST));
|
|
|
|
return RET_SUCCESS;
|
|
}
|
|
|
|
static int lpdp_power_up_pll()
|
|
{
|
|
// Note: powerDownPll() must be called first
|
|
assert(read_reg(rLPDP_PHY_GEN_CTRL & LPDP_PHY_GEN_CTRL_SEQ_OW));
|
|
assert(read_reg(rLPDP_PHY_GEN_CTRL & LPDP_PHY_GEN_CTRL_SLEEP_SW));
|
|
assert(read_reg(rLPDP_PLL_GEN & LPDP_PLL_GEN_PWRDN));
|
|
assert(read_reg(rLPDP_PLL_GEN & LPDP_PLL_GEN_RST));
|
|
|
|
//spin(get_power_down_duration(&lpdp_pll_timing));
|
|
spin(10);
|
|
|
|
// de-assert pll_pwrdn after at least 10µS
|
|
and_reg(rLPDP_PLL_GEN, ~LPDP_PLL_GEN_PWRDN);
|
|
|
|
//spin(get_reset_duration(&lpdp_pll_timing));
|
|
spin(100);
|
|
|
|
// de-assert pll_reset after at least 100µS
|
|
and_reg(rLPDP_PLL_GEN, ~LPDP_PLL_GEN_RST);
|
|
|
|
//spin(get_reset_to_update_duration(&lpdp_pll_timing));
|
|
spin(5);
|
|
|
|
// assert pll_update_divn for at least 1µS
|
|
or_reg(rLPDP_PLL_IDIV, LPDP_PLL_IDIV_UPDT);
|
|
spin(1);
|
|
and_reg(rLPDP_PLL_IDIV, ~LPDP_PLL_IDIV_UPDT);
|
|
|
|
// wait for PLL lock
|
|
//spin(get_lock_duration(&lpdp_pll_timing));
|
|
spin(50);
|
|
|
|
// check for PLL lock, bail if not locked
|
|
if (!lpdp_get_pll_is_locked()) {
|
|
printf("failed to lock lpdp pll\n");
|
|
return RET_ERROR;
|
|
}
|
|
|
|
// Enable clock output after PLL is locked
|
|
and_reg(rLPDP_PLL_CLK, ~LPDP_PLL_CLK_VCO_BLK_VCLK);
|
|
|
|
// de-assert lpdp_sleep
|
|
|
|
// Note: The sleep signal is used by the LPDP PHY to gate-off PLL clock;
|
|
// see <rdar://problem/15238851>.
|
|
and_reg(rLPDP_PHY_GEN_CTRL, ~LPDP_PHY_GEN_CTRL_SLEEP_SW);
|
|
|
|
// wait at least 1µS for output driver ready
|
|
spin(2);
|
|
|
|
or_reg(rLPDP_PLL_GEN, LPDP_PLL_GEN_CLKDIV2_RESET_N);
|
|
|
|
return RET_SUCCESS;
|
|
}
|
|
|
|
void lpdp_phy_configure_alpm(bool enable)
|
|
{
|
|
|
|
if (enable) {
|
|
// Clear Sequencer overwrite and Lane power-down overwrite
|
|
and_reg(rLPDP_PHY_GEN_CTRL, ~(LPDP_PHY_GEN_CTRL_SLEEP_SW | LPDP_PHY_GEN_CTRL_LANE_PD_OW));
|
|
|
|
// Program ALPM PHY Sequence Timers
|
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write_reg(rLPDP_GEN_SEQ_1, LPDP_GEN_SEQ_1_START_COUNT(lpdp_pll_timing.start_count));
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or_reg(rLPDP_GEN_SEQ_1, LPDP_GEN_SEQ_1_SETUP_COUNT(lpdp_pll_timing.setup_count));
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//Hardcodede value to be fixed in <rdar://problem/16786136> Make display_config a void * for future flexibility
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write_reg(rLPDP_GEN_SEQ_2, 1873);
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write_reg(rLPDP_GEN_SEQ_3, lpdp_pll_timing.reset_count);
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write_reg(rLPDP_GEN_SEQ_4, LPDP_GEN_SEQ_4_HOLD_COUNT(lpdp_pll_timing.hold_count));
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write_reg(rLPDP_GEN_SEQ_5, LPDP_GEN_SEQ_5_FINISH_COUNT(lpdp_pll_timing.finish_count));
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or_reg(rLPDP_GEN_SEQ_4, LPDP_GEN_SEQ_4_UPDATE_COUNT(lpdp_pll_timing.update_count));
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write_reg(rLPDP_GEN_SEQ_5, LPDP_GEN_SEQ_5_WAKEUP_COUNT(lpdp_pll_timing.wakeup_count));
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}
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}
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// convenience methods for conversion to µs (for software use)
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static unsigned int micro_seconds_for_count(struct pll_timing *tm, unsigned int count) {
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// Note: Normally, ref_mhz == ref_div, but it is not assumed.
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// Values are rounded up.
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return ((count * tm->ref_div) + tm->ref_mhz - 1) / tm->ref_mhz;
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}
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static unsigned int get_sleep_to_power_down_duration(struct pll_timing *tm) {
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return micro_seconds_for_count(tm, tm->start_count);
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}
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static unsigned int get_power_down_duration(struct pll_timing *tm) {
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return micro_seconds_for_count(tm, tm->pwrdn_count);
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}
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static unsigned int get_reset_duration(struct pll_timing *tm) {
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return micro_seconds_for_count(tm, tm->reset_count);
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}
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static unsigned int get_reset_to_update_duration(struct pll_timing *tm) {
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return micro_seconds_for_count(tm, tm->update_count);
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}
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|
|
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static unsigned int get_lock_duration(struct pll_timing *tm) {
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return micro_seconds_for_count(tm, tm->finish_count);
|
|
}
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|
|
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static uint32_t read_reg(uint32_t offset)
|
|
{
|
|
volatile uint32_t reg;
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|
|
|
reg = (*(volatile uint32_t *)(__base_address + offset));
|
|
return reg;
|
|
}
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|
|
|
static void write_reg(uint32_t offset, uint32_t value)
|
|
{
|
|
*(volatile uint32_t *)(__base_address + offset) = value;
|
|
}
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|
|
|
static void and_reg(uint32_t offset, uint32_t value)
|
|
{
|
|
uint32_t reg;
|
|
reg = read_reg(offset);
|
|
reg &= value;
|
|
write_reg(offset, reg);
|
|
}
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|
|
|
static void or_reg(uint32_t offset, uint32_t value)
|
|
{
|
|
uint32_t reg;
|
|
reg = read_reg(offset);
|
|
reg |= value;
|
|
write_reg(offset, reg);
|
|
}
|
|
|
|
static void set_bits_in_reg(uint32_t offset, uint32_t pos, uint32_t mask, uint32_t value)
|
|
{
|
|
uint32_t set = read_reg(offset);
|
|
|
|
set &= ~mask;
|
|
set |= (value << pos);
|
|
|
|
write_reg(offset, set);
|
|
}
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