262 lines
10 KiB
C
262 lines
10 KiB
C
/*
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* Copyright (C) 2010-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#define DPCD_ADDR_DPCD_REV 0x00000
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#define DPCD_ADDR_DPCD_REV_MAJOR_SHIFT 4
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#define DPCD_ADDR_DPCD_REV_MAJOR_MASK (0xf << DPCD_ADDR_DPCD_REV_MAJOR_SHIFT)
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#define DPCD_ADDR_DPCD_REV_MINOR_SHIFT 0
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#define DPCD_ADDR_DPCD_REV_MINOR_MASK (0xf << DPCD_ADDR_DPCD_REV_MINOR_SHIFT)
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#define DPCD_ADDR_MAX_LINK_RATE 0x00001
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#define DPCD_ADDR_MAX_LANE_COUNT 0x00002
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#define DPCD_ADDR_MAX_DOWNSPREAD 0x00003
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#define DPCD_ADDR_NORP 0x00004
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#define DPCD_ADDR_DOWNSTREAMPORT_PRESENT 0x00005
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#define DPCD_ADDR_RECEIVE_PORT0_CAP_0 0x00008
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#define DPCD_ADDR_RECEIVE_PORT0_CAP_0_EDID (1 << 1)
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#define DPCD_ADDR_DOWNSTREAMPORT_COUNT 0x00007
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#define DPCD_ADDR_RECEIVE_PORT0_CAP_1 0x00009
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#define DPCD_ADDR_RECEIVE_PORT0_CAP_2 0x0000a
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#define DPCD_ADDR_RECEIVE_PORT0_CAP_3 0x0000b
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#define DPCD_ADDR_ALTERNATE_SCRAMBLE 0x0000d
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#define DPCD_ADDR_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
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#define DPCD_ADDR_FRAMING_CHANGE_CAP (1 << 1)
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#define DPCD_ADDR_INVERTED_TRAINING_BIT_CAP (1 << 2)
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#define DPCD_ADDR_DOWNSTREAMPORT_0_CAPS 0x00080
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#define DPCD_ADDR_ALPM_CAP 0x0002e
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#define DPCD_ADDR_LINK_BW_SET 0x00100
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#define DPCD_ADDR_LANE_COUNT_SET 0x00101
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#define DPCD_ADDR_LANE_COUNT_SET_ENHANCED (1 << 7)
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#define DPCD_ADDR_LANE_COUNT_SET_COUNT_MASK (0x1f)
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#define DPCD_ADDR_LANE_COUNT_TPS3_SUPPORTED (1 << 6)
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#define DPCD_ADDR_TRAINING_PATTERN_SET 0x00102
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#define DPCD_ADDR_PATTERN_SET_MASK 0x3
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#define DPCD_ADDR_QUALITY_PATTERN_SHIFT 2
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#define DPCD_ADDR_TRAINING_PATTERN_SET_SCRMB_DISABLE (1 << 5)
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#define DPCD_ADDR_TRAINNIG_LANE0_SET 0x00103
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#define DPCD_ADDR_TRAINNIG_LANE1_SET 0x00104
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#define DPCD_ADDR_TRAINNIG_LANE2_SET 0x00105
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#define DPCD_ADDR_TRAINNIG_LANE3_SET 0x00106
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#define DPCD_ADDR_TRAINNIG_SET_VOL_SWING_SHIFT 0
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#define DPCD_ADDR_TRAINNIG_SET_VOL_SWING_MASK (0x3 << DPCD_ADDR_TRAINNIG_SET_VOL_SWING_SHIFT)
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#define DPCD_ADDR_TRAINNIG_SET_VOL_SWING_MAX (0x1 << 2)
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#define DPCD_ADDR_TRAINNIG_SET_PRE_EMPH_SHIFT 3
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#define DPCD_ADDR_TRAINNIG_SET_PRE_EMPH_MASK (0x3 << DPCD_ADDR_TRAINNIG_SET_PRE_EMPH_SHIFT)
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#define DPCD_ADDR_TRAINNIG_SET_PRE_EMPH_MAX (0x1 << 5)
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#define DPCD_ADDR_DOWNSPREAD_CTRL 0x00107
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#define DPCD_ADDR_DOWNSPREAD_ENABLE (1 << 4)
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// eDP (DPCD 1.2)
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#define DPCD_ADDR_RECEIVER_EDP_CONFIG 0x0010a
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#define DPCD_ADDR_RECEIVER_EDP_CONFIG_ASSR_ENABLE (1<<0)
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#define DPCD_ADDR_ALPM_CTRL 0x00116
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#define DPCD_ADDR_ALPM_ENABLE (1 << 0)
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#define DPCD_ADDR_ALPM_ALPM_LOCK_ERROR_IRQ_HPD (1 << 1)
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#define DPCD_ADDR_SINK_COUNT 0x00200
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#define DPCD_ADDR_DEVICE_SERVICE_IRQ_VECTOR 0x00201
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#define DPCD_IRQ_VECTOR_REMOTE_COMMAND (1 << 0)
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#define DPCD_IRQ_VECTOR_AUTOMATED_TEST (1 << 1)
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#define DPCD_IRQ_VECTOR_CP_IRQ (1 << 2)
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#define DPCD_IRQ_VECTOR_SINK_SPECIFIC (1 << 6)
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#define DPCD_ADDR_LANE0_1_STATUS 0x00202
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#define DPCD_ADDR_LANE2_3_STATUS 0x00203
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#define DPCD_ADDR_LANEX_Y_STATUS_X_SHIFT (0)
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#define DPCD_ADDR_LANEX_Y_STATUS_Y_SHIFT (4)
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#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x00204
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#define DPCD_ADDR_SINK_STATUS 0x00205
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#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x00206
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#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x00207
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#define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_X_SHIFT 0
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#define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_X_MASK (0x3 << DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_X_SHIFT)
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#define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_X_SHIFT 2
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#define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_X_MASK (0x3 << DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_X_SHIFT)
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#define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_Y_SHIFT 4
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#define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_Y_MASK (0x3 << DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_VOL_SWG_Y_SHIFT)
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#define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_Y_SHIFT 6
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#define DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_Y_MASK (0x3 << DPCD_ADDR_ADJUST_REQUEST_LANEX_Y_PRE_EMP_Y_SHIFT)
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#define DPCD_ADDR_TRAINING_SCORE_LANE0 0x00208
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#define DPCD_ADDR_TRAINING_SCORE_LANE1 0x00209
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#define DPCD_ADDR_TRAINING_SCORE_LANE2 0x0020a
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#define DPCD_ADDR_TRAINING_SCORE_LANE3 0x0020b
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#define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE0_BYTE0 0x00210
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#define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE0_BYTE1 0x00211
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#define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE1_BYTE0 0x00212
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#define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE1_BYTE1 0x00213
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#define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE2_BYTE0 0x00214
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#define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE2_BYTE1 0x00215
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#define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE3_BYTE0 0x00216
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#define DPCD_ADDR_SYMBOL_ERROR_COUNT_LANE3_BYTE1 0x00217
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#define DPCD_ADDR_TEST_REQUEST 0x00218
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#define DPCD_ADDR_TEST_REQUEST_LINK (1 << 0)
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#define DPCD_ADDR_TEST_REQUEST_PATTERN (1 << 1)
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#define DPCD_ADDR_TEST_REQUEST_EDID (1 << 2)
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#define DPCD_ADDR_TEST_REQUEST_PHY (1 << 3)
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#define DPCD_ADDR_TEST_LINK_RATE 0x00219
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#define DPCD_ADDR_TEST_LANE_COUNT 0x00220
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#define DPCD_ADDR_TEST_PATTERN 0x00221
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#define DPCD_ADDR_TEST_H_TOTAL_H 0x00222
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#define DPCD_ADDR_TEST_H_TOTAL_L 0x00223
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#define DPCD_ADDR_TEST_V_TOTAL_H 0x00224
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#define DPCD_ADDR_TEST_V_TOTAL_L 0x00225
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#define DPCD_ADDR_TEST_H_START_H 0x00226
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#define DPCD_ADDR_TEST_H_START_L 0x00227
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#define DPCD_ADDR_TEST_V_START_H 0x00228
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#define DPCD_ADDR_TEST_V_START_L 0x00229
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#define DPCD_ADDR_TEST_HSYNC_H 0x0022a
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#define DPCD_ADDR_TEST_HSYNC_L 0x0022b
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#define DPCD_ADDR_TEST_VSYNC_H 0x0022c
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#define DPCD_ADDR_TEST_VSYNC_L 0x0022d
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#define DPCD_ADDR_TEST_H_WIDTH_H 0x0022e
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#define DPCD_ADDR_TEST_H_WIDTH_L 0x0022f
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#define DPCD_ADDR_TEST_V_HEGHT_H 0x00230
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#define DPCD_ADDR_TEST_V_HEGHT_L 0x00231
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#define DPCD_ADDR_TEST_PHY 0x00248
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#define DPCD_ADDR_TEST_PHY_SEL_MASK 3
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#define DPCD_ADDR_TEST_RESPONSE 0x00260
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#define DPCD_ADDR_TEST_RESPONSE_ACK (1 << 0)
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#define DPCD_ADDR_TEST_RESPONSE_NACK (1 << 1)
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#define DPCD_ADDR_TEST_RESPONSE_EDID (1 << 2)
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#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x00261
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#define DPCD_ADDR_SOURCE_IEEE_OUI_7_0 0x00300
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#define DPCD_ADDR_SOURCE_IEEE_OUI_15_8 0x00301
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#define DPCD_ADDR_SOURCE_IEEE_OUI_23_16 0x00302
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#define DPCD_ADDR_SOURCE_DEVICE_ID_BYTE_0 0x00303
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#define DPCD_ADDR_SINK_IEEE_OUI_7_0 0x00400
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#define DPCD_ADDR_SINK_IEEE_OUI_15_8 0x00401
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#define DPCD_ADDR_SINK_IEEE_OUI_23_16 0x00402
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#define DPCD_ADDR_SINK_DEVICE_ID_BYTE_0 0x00403
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#define DPCP_ADDR_VENDOR_BYTES 0x00430
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#define DPCD_ADDR_BRANCH_IEEE_OUI_7_0 0x00500
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#define DPCD_ADDR_BRANCH_IEEE_OUI_15_8 0x00501
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#define DPCD_ADDR_BRANCH_IEEE_OUI_23_16 0x00502
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#define DPCD_ADDR_BRANCH_DEVICE_ID_BYTE_0 0x00503
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#define DPCD_ADDR_HDMI_DVI_MODE_SELECT 0x00519
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#define DPCD_HDMI_DVI_SELECT_DEFAULT 0x00
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#define DPCD_ADDR_HDMI_DVI_MODE_SELECT_DVI 0x01
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#define DPCD_HDCP_ENABLE 0x00
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#define DPCD_HDCP_DISABLE 0x02
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#define DPCD_ADDR_SINK_POWER_STATE 0x00600
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#define DPCD_ADDR_SINK_POWER_STATE_ON 0x1
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#define DPCD_ADDR_SINK_POWER_STATE_OFF 0x2
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#define DPCD_ADDR_HDCP_BKSV_0 0x68000
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#define DPCD_ADDR_HDCP_BKSV_1 0x68001
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#define DPCD_ADDR_HDCP_BKSV_2 0x68002
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#define DPCD_ADDR_HDCP_BKSV_3 0x68003
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#define DPCD_ADDR_HDCP_BKSV_4 0x68004
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#define DPCD_ADDR_HDCP_R0_0 0x68005
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#define DPCD_ADDR_HDCP_R0_1 0x68006
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#define DPCD_ADDR_HDCP_AKSV_0 0x68007
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#define DPCD_ADDR_HDCP_AKSV_1 0x68008
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#define DPCD_ADDR_HDCP_AKSV_2 0x68009
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#define DPCD_ADDR_HDCP_AKSV_3 0x6800a
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#define DPCD_ADDR_HDCP_AKSV_4 0x6800b
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#define DPCD_ADDR_HDCP_AN_0 0x6800c
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#define DPCD_ADDR_HDCP_AN_1 0x6800d
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#define DPCD_ADDR_HDCP_AN_2 0x6800e
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#define DPCD_ADDR_HDCP_AN_3 0x6800f
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#define DPCD_ADDR_HDCP_AN_4 0x68010
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#define DPCD_ADDR_HDCP_AN_5 0x68011
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#define DPCD_ADDR_HDCP_AN_6 0x68012
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#define DPCD_ADDR_HDCP_AN_7 0x68013
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#define DPCD_ADDR_HDCP_H0_0 0x68014
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#define DPCD_ADDR_HDCP_H0_1 0x68015
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#define DPCD_ADDR_HDCP_H0_2 0x68016
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#define DPCD_ADDR_HDCP_H0_3 0x68017
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#define DPCD_ADDR_HDCP_H1_0 0x68018
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#define DPCD_ADDR_HDCP_H1_1 0x68019
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#define DPCD_ADDR_HDCP_H1_2 0x6801a
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#define DPCD_ADDR_HDCP_H1_3 0x6801b
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#define DPCD_ADDR_HDCP_H2_0 0x6801c
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#define DPCD_ADDR_HDCP_H2_1 0x6801d
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#define DPCD_ADDR_HDCP_H2_2 0x6801e
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#define DPCD_ADDR_HDCP_H2_3 0x6801f
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#define DPCD_ADDR_HDCP_H3_0 0x68020
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#define DPCD_ADDR_HDCP_H3_1 0x68021
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#define DPCD_ADDR_HDCP_H3_2 0x68022
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#define DPCD_ADDR_HDCP_H3_3 0x68023
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#define DPCD_ADDR_HDCP_H4_0 0x68024
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#define DPCD_ADDR_HDCP_H4_1 0x68025
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#define DPCD_ADDR_HDCP_H4_2 0x68026
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#define DPCD_ADDR_HDCP_H4_3 0x68027
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#define DPCD_ADDR_HDCP_BCAPS 0x68028
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#define DPCD_ADDR_HDCP_BCAPS_HDCP_CAPABLE (1 << 0)
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#define DPCD_ADDR_HDCP_BCAPS_IS_REPEATER (1 << 1)
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#define DPCD_ADDR_HDCP_STATUS 0x68029
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#define DPCD_ADDR_HDCP_STATUS_LINK_INTEGRITY_FAILURE (1 << 2)
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#define DPCD_ADDR_HDCP_STATUS_R0PRIME_AVAILABLE (1 << 1)
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#define DPCD_ADDR_HDCP_STATUS_READY (1 << 0)
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#define DPCD_ADDR_HDCP_BINFO_0 0x6802a
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#define DPCD_ADDR_HDCP_BINFO_1 0x6802b
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#define DPCD_ADDR_HDCP_INFO_MAX_CASCADE_EXCEEDED (1 << 11)
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#define DPCD_ADDR_HDCP_INFO_MAX_DEVS_EXCEEDED (1 << 7)
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#define DPCD_ADDR_HDCP_KSV_FIFO_0 0x6802c
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#define DPCD_ADDR_HDCP_KSV_FIFO_1 0x6802d
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#define DPCD_ADDR_HDCP_KSV_FIFO_2 0x6802e
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#define DPCD_ADDR_HDCP_KSV_FIFO_3 0x6802f
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#define DPCD_ADDR_HDCP_KSV_FIFO_4 0x68030
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#define DPCD_ADDR_HDCP_KSV_FIFO_5 0x68031
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#define DPCD_ADDR_HDCP_KSV_FIFO_6 0x68032
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#define DPCD_ADDR_HDCP_KSV_FIFO_7 0x68033
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#define DPCD_ADDR_HDCP_KSV_FIFO_8 0x68034
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#define DPCD_ADDR_HDCP_KSV_FIFO_9 0x68035
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#define DPCD_ADDR_HDCP_KSV_FIFO_10 0x68036
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#define DPCD_ADDR_HDCP_KSV_FIFO_11 0x68037
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#define DPCD_ADDR_HDCP_KSV_FIFO_12 0x68038
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#define DPCD_ADDR_HDCP_KSV_FIFO_13 0x68039
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#define DPCD_ADDR_HDCP_KSV_FIFO_14 0x6803a
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#define DPCD_ADDR_HDCP_RSVD 0x6803b
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