455 lines
14 KiB
C
455 lines
14 KiB
C
/*
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* Copyright (C) 2012 Apple Computer, Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/iic.h>
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#include <drivers/tristar.h>
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#include <drivers/power.h>
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#include <platform.h>
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#include <platform/gpiodef.h>
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#include <sys.h>
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#include <sys/boot.h>
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#include <sys/menu.h>
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#include <target/powerconfig.h>
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#define CBTL1610_ADDR_R 0x35
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#define CBTL1610_ADDR_W 0x34
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enum {
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DXCTRL = 0x01,
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DXCTRL_DX2OVRD = (1 << 7),
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DXCTRL_DPDN2SW_mask = (7 << 4),
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DXCTRL_DPDN2SW_open = (0 << 4),
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DXCTRL_DPDN2SW_usb0 = (1 << 4),
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DXCTRL_DPDN2SW_uart0 = (2 << 4),
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DXCTRL_DPDN2SW_dig = (3 << 4),
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DXCTRL_DPDN2SW_brick_id_p = (4 << 4),
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DXCTRL_DPDN2SW_brick_id_n = (5 << 4),
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DXCTRL_DPDN2SW_uart2 = (6 << 4),
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DXCTRL_DPDN2SW_uart1 = (7 << 4),
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DXCTRL_DX1OVRD = (1 << 3),
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DXCTRL_DPDN1SW_mask = (7 << 0),
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DXCTRL_DPDN1SW_open = (0 << 0),
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DXCTRL_DPDN1SW_usb0 = (1 << 0),
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DXCTRL_DPDN1SW_uart0 = (2 << 0),
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DXCTRL_DPDN1SW_dig = (3 << 0),
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DXCTRL_DPDN1SW_brick_id_p = (4 << 0),
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DXCTRL_DPDN1SW_brick_id_n = (5 << 0),
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DXCTRL_DPDN1SW_usb1 = (6 << 0),
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DXCTRL_DPDN1SW_jtag = (7 << 0),
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ACC_CTRL = 0x02,
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ACC_CTRL_ACC2OVRD = (1 << 7),
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ACC_CTRL_ACC2SW_mask = (7 << 4),
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ACC_CTRL_ACC2SW_open = (0 << 4),
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ACC_CTRL_ACC2SW_uart1_tx = (1 << 4),
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ACC_CTRL_ACC2SW_jtag_clk = (2 << 4),
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ACC_CTRL_ACC2SW_acc_pwr = (3 << 4),
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ACC_CTRL_ACC2SW_brick_id = (4 << 4),
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ACC_CTRL_ACC1OVRD = (1 << 3),
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ACC_CTRL_ACC1SW_mask = (7 << 0),
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ACC_CTRL_ACC1SW_open = (0 << 0),
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ACC_CTRL_ACC1SW_uart1_rx = (1 << 0),
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ACC_CTRL_ACC1SW_jtag_dio = (2 << 0),
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ACC_CTRL_ACC1SW_acc_pwr = (3 << 0),
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ACC_CTRL_ACC1SW_brick_id = (4 << 0),
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DCP_CTRL = 0x03,
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DCP_CTRL_IDXSINKEN = (1 << 3),
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DCP_CTRL_VDXSRCSW_mask = (7 << 0),
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DCP_CTRL_VDXSRCSW_off = (0 << 0),
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DCP_CTRL_VDXSRCSW_dp1 = (1 << 0),
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DCP_CTRL_VDXSRCSW_dn1 = (2 << 0),
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DCP_CTRL_VDXSRCSW_dp2 = (3 << 0),
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DCP_CTRL_VDXSRCSW_dn2 = (4 << 0),
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MISC_CTRL = 0x05,
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MISC_CTRL_DPDN2_TERM = (1 << 5),
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MISC_CTRL_DPDN1_TERM = (1 << 4),
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MISC_CTRL_IDBUS_RESET = (1 << 3),
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MISC_CTRL_IDBUS_BREAK = (1 << 2),
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MISC_CTRL_IDBUS_REORIENT = (1 << 1),
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MISC_CTRL_IDBUS_P_INSINK_EN = (1 << 0),
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DIG_ID = 0x06,
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DIG_ID_Dx1 = (1 << 3),
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DIG_ID_Dx0 = (1 << 2),
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DIG_ID_ACCx1 = (1 << 1),
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DIG_ID_ACCx0 = (1 << 0),
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FAULT_ENABLE = 0x09,
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DYNAMIC_CHRG_PUMP = (1 << 7),
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CHECK_VICT = (1 << 6),
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CHECK_AGGR = (1 << 5),
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PROTECT_UNDER = (1 << 4),
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PROTECT_DIG = (1 << 3),
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PROTECT_UART = (1 << 2),
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PROTECT_USB = (1 << 1),
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PROTECT_ACC = (1 << 0),
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EVENT1 = 0x0A,
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EVENT1_Dx2_FAULT = (1 << 2),
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EVENT1_Dx1_FAULT = (1 << 1),
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EVENT1_ACCx_FAULT = (1 << 0),
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STATUS1 = 0x0B,
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STATUS1_CMD_PEND = (1 << 0),
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STATUS0 = 0x0C,
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STATUS0_IDBUS_CONNECTED = (1 << 7),
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STATUS0_IDBUS_ORIENT = (1 << 6),
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STATUS0_SWITCH_EN = (1 << 5),
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STATUS0_HOST_RESET = (1 << 4),
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STATUS0_POWER_GATE_EN = (1 << 3),
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STATUS0_CON_DET_L = (1 << 2),
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STATUS0_P_IN_STAT_mask = (3 << 0),
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STATUS0_P_IN_STAT_brownout = (0 << 0),
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STATUS0_P_IN_STAT_maintain = (1 << 0),
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STATUS0_P_IN_STAT_ovp = (2 << 0),
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STATUS0_P_IN_STAT_insdet = (3 << 0),
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EVENT0 = 0x0D,
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EVENT_IO_FAULT = (1 << 7),
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EVENT_IDBUS_TIMEOUT = (1 << 6),
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EVENT_FIFO_ERR = (1 << 5),
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EVENT_FIFO_RDY = (1 << 4),
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EVENT_CRC_ERR = (1 << 5),
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EVENT_RESP_VALID = (1 << 4),
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EVENT_DIGITAL_ID = (1 << 3),
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EVENT_CON_DET_L = (1 << 2),
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EVENT_IDBUS_WAKE = (1 << 1),
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EVENT_P_IN = (1 << 0),
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MASK = 0x0E,
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MASK_IO_FAULT = (1 << 7),
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MASK_IDBUS_TIMEOUT = (1 << 6),
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MASK_CRC_ERR = (1 << 5),
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MASK_RESP_VALID = (1 << 4),
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MASK_DIGITAL_ID = (1 << 3),
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MASK_CON_DET_L = (1 << 2),
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MASK_IDBUS_WAKE = (1 << 1),
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MASK_P_IN = (1 << 0),
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REV = 0x0F,
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REV_VENDOR_ID_shift = (6),
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REV_VENDOR_ID_mask = (3 << REV_VENDOR_ID_shift),
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REV_VENDOR_ID_nxp = (2 << REV_VENDOR_ID_shift),
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REV_BASE_VER_shift = (3),
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REV_BASE_VER_mask = (7 << REV_BASE_VER_shift),
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REV_METAL_VER_shift = (0),
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REV_METAL_VER_mask = (7 << REV_METAL_VER_shift),
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DP1_DP2_UART_CTL = 0x10,
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DP1_DP2_UART_CTL_DP2_SLEW_mask = (3 << 2),
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DP1_DP2_UART_CTL_DP2_SLEW_10ns = (0 << 2),
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DP1_DP2_UART_CTL_DP2_SLEW_20ns = (1 << 2),
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DP1_DP2_UART_CTL_DP2_SLEW_40ns = (2 << 2),
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DP1_DP2_UART_CTL_DP2_SLEW_80ns = (3 << 2),
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DP1_DP2_UART_CTL_DP1_SLEW_mask = (3 << 0),
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DP1_DP2_UART_CTL_DP1_SLEW_10ns = (0 << 0),
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DP1_DP2_UART_CTL_DP1_SLEW_20ns = (1 << 0),
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DP1_DP2_UART_CTL_DP1_SLEW_40ns = (2 << 0),
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DP1_DP2_UART_CTL_DP1_SLEW_80ns = (3 << 0),
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AUTH_CTRL0 = 0x11,
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AUTH_CTRL0_LOCK_STAT_VALID = (1 << 7),
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AUTH_CTRL0_ESN_LOCK_STAT = (1 << 6),
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AUTH_CTRL0_KEYSET2_LOCK_STAT = (1 << 5),
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AUTH_CTRL0_KEYSET1_LOCK_STAT = (1 << 4),
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AUTH_CTRL0_SELECT_AUTH_DOMAIN_mask = (1 << 3),
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AUTH_CTRL0_SELECT_AUTH_DOMAIN_0 = (0 << 3),
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AUTH_CTRL0_SELECT_AUTH_DOMAIN_1 = (1 << 3),
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AUTH_CTRL0_I2C_AUTH_DONE = (1 << 1),
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AUTH_CTRL0_I2C_AUTH_START = (1 << 0),
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ACC_FAULT_STATUS = 0x12,
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ACC_FAULT_STATUS_RVR_COMP_OUT = (1 << 6),
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ACC_FAULT_STATUS_ACC_FINGERS_5 = (1 << 5),
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ACC_FAULT_STATUS_ACC_FINGERS_4 = (1 << 4),
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ACC_FAULT_STATUS_ACC_FINGERS_3 = (1 << 3),
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ACC_FAULT_STATUS_ACC_FINGERS_2 = (1 << 2),
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ACC_FAULT_STATUS_ACC_FINGERS_1 = (1 << 1),
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ACC_FAULT_STATUS_ACC_FINGERS_0 = (1 << 0),
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ACC_FAULT_CTRL0 = 0x13,
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ACC_FAULT_CTRL0_EN_2X_OFFSET = (1 << 7),
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ACC_FAULT_CTRL0_BP_DISABLE_ACC_DISCONNECT = (1 << 6),
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ACC_FAULT_CTRL0_BP_DEGLITCH_mask = (15 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_no = (0 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_12us = (1 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_36us = (2 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_60us = (3 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_100us = (4 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_200us = (5 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_500us = (6 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_1000us = (7 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_2ms = (8 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_5ms = (9 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_10ms = (10 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_20ms = (11 << 0),
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ACC_FAULT_CTRL0_BP_DEGLITCH_50ms = (12 << 0),
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ACC_FAULT_CTRL1 = 0x14,
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ACC_FAULT_CTRL1_BP_MODE_mask = (3 << 6),
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ACC_FAULT_CTRL1_BP_MODE_no = (0 << 6),
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ACC_FAULT_CTRL1_BP_SW_CTRL_mask = (63 << 0),
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ACC_FAULT_CTRL1_BP_SW_CTRL_800mohm = (0 << 0),
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ACC_FAULT_CTRL1_BP_SW_CTRL_270mohm = (32 << 0),
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ACC_FAULT_CTRL1_BP_SW_CTRL_170mohm = (48 << 0),
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ACC_FAULT_CTRL1_BP_SW_CTRL_130mohm = (56 << 0),
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ACC_FAULT_CTRL1_BP_SW_CTRL_100mohm = (52 << 0),
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ACC_FAULT_CTRL1_BP_SW_CTRL_90mohm = (60 << 0),
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ACC_FAULT_CTRL1_BP_SW_CTRL_600mohm = (62 << 0),
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ACC_FAULT_CTRL1_BP_SW_CTRL_40mohm = (63 << 0),
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MISC_IO = 0x1D,
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MISC_IO_IDBUS_TIMEOUT_mask = (3 << 3),
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MISC_IO_IDBUS_TIMEOUT_disabled = (0 << 3),
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MISC_IO_IDBUS_TIMEOUT_5s = (1 << 3),
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MISC_IO_IDBUS_TIMEOUT_10s = (2 << 3),
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MISC_IO_IDBUS_TIMEOUT_30s = (3 << 3),
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MISC_IO_UART2_LOOP_BK = (1 << 2),
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MISC_IO_UART1_LOOP_BK = (1 << 1),
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MISC_IO_UART0_LOOP_BK = (1 << 0),
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CON_DET_SMPL = 0x1E,
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CON_DET_SMPL_CON_DET_PULLUP_mask = (3 << 5),
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CON_DET_SMPL_CON_DET_PULLUP_20kohm = (0 << 5),
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CON_DET_SMPL_CON_DET_PULLUP_40kohm = (1 << 5),
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CON_DET_SMPL_CON_DET_PULLUP_60kohm = (2 << 5),
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CON_DET_SMPL_CON_DET_PULLUP_80kohm = (3 << 5),
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CON_DET_SMPL_SMPL_DUR_mask = (3 << 3),
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CON_DET_SMPL_SMPL_DUR_15us = (0 << 3),
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CON_DET_SMPL_SMPL_DUR_70us = (1 << 3),
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CON_DET_SMPL_SMPL_DUR_130us = (2 << 3),
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CON_DET_SMPL_SMPL_DUR_260us = (3 << 3),
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CON_DET_SMPL_SMPL_RATE_mask = (3 << 1),
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CON_DET_SMPL_SMPL_RATE_660Hz = (0 << 1),
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CON_DET_SMPL_SMPL_RATE_265Hz = (1 << 1),
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CON_DET_SMPL_SMPL_RATE_130Hz = (2 << 1),
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CON_DET_SMPL_SMPL_RATE_70Hz = (3 << 1),
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CON_DET_SMPL_SMPL_MODE_mask = (1 << 0),
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CON_DET_SMPL_SMPL_MODE_TriStar2 = (0 << 0),
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CON_DET_SMPL_SMPL_MODE_TriStar1 = (1 << 0),
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RD_FIFO = 0x1F,
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FIFO0 = 0x20,
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FIFO63 = 0x5F,
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FIFO_LEN = (FIFO63 - FIFO0 + 1),
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FIFO_MTP2_TIMING = 0x20,
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FIFO_KEY_CTRL = 0x21,
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FIFO_KEY_CTRL_LOCK_REQ = (1 << 5),
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FIFO_KEY_CTRL_ESN = (1 << 4),
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FIFO_KEY_CTRL_KEY2_2 = (1 << 3),
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FIFO_KEY_CTRL_KEY2_1 = (1 << 2),
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FIFO_KEY_CTRL_KEY1_2 = (1 << 1),
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FIFO_KEY_CTRL_KEY1_1 = (1 << 0),
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FIFO_KEY_ESN_BYTE0 = 0x22,
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FIFO_KEY_ESN_BYTE1 = 0x23,
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FIFO_KEY_ESN_BYTE2 = 0x24,
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FIFO_KEY_ESN_BYTE3 = 0x25,
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FIFO_KEY_ESN_BYTE4 = 0x26,
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FIFO_KEY_ESN_BYTE5 = 0x27,
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FIFO_KEY_ESN_BYTE6 = 0x28,
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FIFO_KEY_ESN_BYTE7 = 0x29,
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FIFO_MTP2_PRG_CTRL = 0x2E,
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FIFO_ENONCE_M_BYTE0 = 0x49,
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FIFO_ENONCE_M_BYTE1 = 0x50,
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FIFO_ENONCE_M_BYTE2 = 0x51,
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FIFO_ENONCE_M_BYTE3 = 0x52,
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FIFO_ENONCE_M_BYTE4 = 0x53,
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FIFO_ENONCE_M_BYTE5 = 0x54,
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FIFO_ENONCE_M_BYTE6 = 0x55,
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FIFO_ENONCE_M_BYTE7 = 0x56,
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FIFO_ESN_BYTE0 = 0x57,
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FIFO_ESN_BYTE1 = 0x58,
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FIFO_ESN_BYTE2 = 0x59,
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FIFO_ESN_BYTE3 = 0x5A,
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FIFO_ESN_BYTE4 = 0x5B,
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FIFO_ESN_BYTE5 = 0x5C,
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FIFO_ESN_BYTE6 = 0x5D,
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FIFO_ESN_BYTE7 = 0x5E,
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FIFO_CTRL1 = 0x60,
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FIFO_CTRL1_ULIMITED_RX = (1 << 7),
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FIFO_CTRL1_RESP_LENGTH_shift = (1),
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FIFO_CTRL1_RESP_LENGTH_mask = (63 << FIFO_CTRL1_RESP_LENGTH_shift),
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FIFO_CTRL1_RD_TRIG_LVL_shift = (1),
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FIFO_CTRL1_RD_TRIG_LVL_mask = (63 << FIFO_CTRL1_RD_TRIG_LVL_shift),
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FIFO_CTRL1_CMD_KILL = (1 << 0),
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FIFO_CTRL0 = 0x61,
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FIFO_CTRL0_CMD_LENGTH_shift = (1),
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FIFO_CTRL0_CMD_LENGTH_mask = (63 << FIFO_CTRL0_CMD_LENGTH_shift),
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FIFO_CTRL0_AID_CMD_SEND = (1 << 0),
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FIFO_FILL_STATUS = 0x62,
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FIFO_FILL_STATUS_FIFO_RD_LVL_shift = (0),
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FIFO_FILL_STATUS_FIFO_RD_LVL_mask = (127 << FIFO_FILL_STATUS_FIFO_RD_LVL_shift),
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};
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static int tristar_write(uint8_t reg, uint8_t value)
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{
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uint8_t data[2] = { reg, value };
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return iic_write(TRISTAR_IIC_BUS, CBTL1610_ADDR_W, data, sizeof(data));
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}
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static int tristar_read(uint8_t reg, uint8_t *data)
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{
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return iic_read(TRISTAR_IIC_BUS, CBTL1610_ADDR_R, ®, sizeof(reg), data, sizeof(uint8_t), IIC_NORMAL);
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}
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bool cbtl1610_set_usb_brick_detect(int select)
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{
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// check status to make sure cable is connected and determine orientation
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uint8_t status;
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if (tristar_read(STATUS0, &status) != 0) {
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return false;
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}
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if ((status & STATUS0_CON_DET_L) || !(status & STATUS0_IDBUS_CONNECTED)) {
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return false;
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}
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bool orient = (status & STATUS0_IDBUS_ORIENT) == STATUS0_IDBUS_ORIENT;
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// check ID to find out if USB is supported
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uint8_t dig_id;
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if (tristar_read(DIG_ID, &dig_id) != 0) {
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return false;
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}
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// only Dx=1 or Dx=2 have USB device mode
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if (((dig_id & DIG_ID_Dx0) != 0) == ((dig_id & DIG_ID_Dx1) != 0)) {
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return false;
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}
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uint8_t dxctrl;
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uint8_t dcp_ctrl;
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switch (select) {
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case kUSB_DP:
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case kUSB_CP2:
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dxctrl = orient ? (DXCTRL_DX2OVRD | DXCTRL_DPDN2SW_brick_id_p) : (DXCTRL_DX1OVRD | DXCTRL_DPDN1SW_brick_id_p);
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break;
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case kUSB_DM:
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case kUSB_CP1:
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dxctrl = orient ? (DXCTRL_DX2OVRD | DXCTRL_DPDN2SW_brick_id_n) : (DXCTRL_DX1OVRD | DXCTRL_DPDN1SW_brick_id_n);
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break;
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case kUSB_NONE:
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dxctrl = 0;
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break;
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default:
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return false;
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}
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if (select == kUSB_CP1) {
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dcp_ctrl = DCP_CTRL_IDXSINKEN | (orient ? DCP_CTRL_VDXSRCSW_dp2 : DCP_CTRL_VDXSRCSW_dp1);
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} else if (select == kUSB_CP2) {
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dcp_ctrl = DCP_CTRL_IDXSINKEN | (orient ? DCP_CTRL_VDXSRCSW_dn2 : DCP_CTRL_VDXSRCSW_dn1);
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} else {
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dcp_ctrl = 0;
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}
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tristar_write(DCP_CTRL, dcp_ctrl);
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tristar_write(DXCTRL, dxctrl);
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return true;
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}
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bool cbtl1610_read_id(uint8_t digital_id[6])
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{
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// check status to make sure cable is connected and ID bus is connected
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uint8_t status;
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if (tristar_read(STATUS0, &status) != 0) {
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return false;
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}
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if ((status & STATUS0_CON_DET_L) || !(status & STATUS0_IDBUS_CONNECTED)) {
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return false;
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}
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// FIFO should contain the ID response
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uint8_t resp;
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if (tristar_read(FIFO0, &resp) != 0) {
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return false;
|
|
}
|
|
|
|
if (resp != 0x75) {
|
|
return false;
|
|
}
|
|
|
|
// read ID
|
|
for (int i = 0; i < 6; i++) {
|
|
if (tristar_read(FIFO0 + i + 1, &digital_id[i])) {
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool cbtl1610_enable_acc_pwr(bool enabled)
|
|
{
|
|
if (enabled) {
|
|
tristar_write(ACC_CTRL, ACC_CTRL_ACC2SW_acc_pwr | ACC_CTRL_ACC1SW_acc_pwr);
|
|
}
|
|
|
|
power_enable_ldo(ACC_PWR_LDO, enabled);
|
|
|
|
if (!enabled) {
|
|
tristar_write(ACC_CTRL, 0);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
#if WITH_HW_TRISTAR_THS7383
|
|
|
|
extern bool target_has_tristar2(void);
|
|
extern bool ths7383_set_usb_brick_detect(int select);
|
|
extern bool ths7383_read_id(uint8_t digital_id[6]);
|
|
extern bool ths7383_enable_acc_pwr(bool enabled);
|
|
|
|
bool tristar_set_usb_brick_detect(int select)
|
|
{
|
|
return target_has_tristar2() ? cbtl1610_set_usb_brick_detect(select) : ths7383_set_usb_brick_detect(select);
|
|
}
|
|
|
|
bool tristar_read_id(uint8_t digital_id[6])
|
|
{
|
|
return target_has_tristar2() ? cbtl1610_read_id(digital_id) : ths7383_read_id(digital_id);
|
|
}
|
|
|
|
bool tristar_enable_acc_pwr(bool enabled)
|
|
{
|
|
return target_has_tristar2() ? cbtl1610_enable_acc_pwr(enabled) : ths7383_enable_acc_pwr(enabled);
|
|
}
|
|
|
|
#else // !WITH_HW_TRISTAR_THS7383
|
|
|
|
bool tristar_set_usb_brick_detect(int select)
|
|
{
|
|
return cbtl1610_set_usb_brick_detect(select);
|
|
}
|
|
|
|
bool tristar_read_id(uint8_t digital_id[6])
|
|
{
|
|
return cbtl1610_read_id(digital_id);
|
|
}
|
|
|
|
bool tristar_enable_acc_pwr(bool enabled)
|
|
{
|
|
return cbtl1610_enable_acc_pwr(enabled);
|
|
}
|
|
|
|
#endif // WITH_HW_TRISTAR_THS7383
|