147 lines
3.0 KiB
C
147 lines
3.0 KiB
C
/*
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* Copyright (C) 2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <platform.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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bool chipid_get_production_mode(void)
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{
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while (!chipid_get_read_done());
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return ((rCHIPIDL >> 0) & 1) != 0;
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}
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bool chipid_get_secure_mode(void)
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{
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while (!chipid_get_read_done());
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return ((rCHIPIDH >> 1) & 1) != 0;
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}
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u_int32_t chipid_get_security_domain(void)
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{
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while (!chipid_get_read_done());
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#if SUPPORT_FPGA
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return kPlatformSecurityDomainDarwin;
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#else
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return (rCHIPIDH >> 1) & 3;
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#endif
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}
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u_int32_t chipid_get_minimum_epoch(void)
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{
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while (!chipid_get_read_done());
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return (rCHIPIDH >> 3) & 0x7F;
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}
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bool chipid_get_ecid_image_personalization_required(void)
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{
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return ((rCHIPIDH >> 14) & 1) != 0;
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}
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u_int32_t chipid_get_board_id(void)
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{
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while (!chipid_get_read_done());
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return (rCHIPIDH >> 10) & 3;
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}
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u_int32_t chipid_get_chip_id(void)
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{
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while (!chipid_get_read_done());
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return (rCHIPIDH >> 16) & 0xFFFF;
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}
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u_int32_t chipid_get_chip_revision(void)
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{
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while (!chipid_get_read_done());
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return (((rCHIPIDL >> 24) & 0xF) << 4) | (((rCHIPIDL >> 28) & 0xF) << 0);
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}
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u_int32_t chipid_get_osc_frequency(void)
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{
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return OSC_FREQ;
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}
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u_int64_t chipid_get_ecid_id(void)
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{
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u_int64_t ecid = 0;
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while (!chipid_get_read_done());
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#if SUPPORT_FPGA
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ecid = 0x000012345678ABCDULL;
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#else
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/*
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* For the sake of the next poor bastard that comes along and has
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* to decode the ECID produced by this silliness, the code here
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* produces output formatted thus:
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*
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* 6 4 3 1
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* 3 8 2 6 0
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* ......................lllllllllllllllllllllwwwwwyyyyyyyyxxxxxxxx
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*
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* l - lot number
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* w - wafer number
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* y - wafer y position
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* x - wafer x position
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*/
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ecid |= ((rDIEIDL >> 0)) & ((1ULL << (21 - 0)) - 1); // LOT_ID
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ecid <<= (26 - 21);
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ecid |= ((rDIEIDL >> 21)) & ((1ULL << (26 - 21)) - 1); // WAFER_NUM
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ecid <<= (10 - 2);
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ecid |= ((rDIEIDH >> 2)) & ((1ULL << (10 - 2)) - 1); // Y_POS
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ecid <<= (32 - 26);
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ecid |= ((rDIEIDL >> 26)) & ((1ULL << (32 - 26)) - 1); // X_POS_H
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ecid <<= ( 2 - 0);
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ecid |= ((rDIEIDH >> 0)) & ((1ULL << ( 2 - 0)) - 1); // X_POS_L
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#endif
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return ecid;
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}
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u_int64_t chipid_get_die_id(void)
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{
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while (!chipid_get_read_done());
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return ((u_int64_t)rDIEIDH << 32) | rDIEIDL;
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}
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// chipid_get_tv_dac_cals
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// Saves the three tv dac calibration values in the given array.
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//
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void chipid_get_tv_dac_cals(u_int32_t *dac_cals)
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{
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while (!chipid_get_read_done());
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dac_cals[0] = (rCHIPIDL >> 9) & 0x1F;
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dac_cals[1] = (rCHIPIDL >> 14) & 0x1F;
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dac_cals[2] = (rCHIPIDL >> 19) & 0x1F;
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}
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bool chipid_get_read_done(void)
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{
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#if !SUPPORT_FPGA
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return ((rEFUSE_READ_DONE >> 0) & 1) != 0;
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#else
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return true;
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#endif
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}
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