131 lines
2.6 KiB
C
131 lines
2.6 KiB
C
/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <platform.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/pmgr.h>
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bool chipid_get_current_production_mode(void)
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{
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return ((rCFG_FUSE0 >> 0) & 1) != 0;
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}
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bool chipid_get_raw_production_mode(void)
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{
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return ((rCFG_FUSE0_RAW >> 0) & 1) != 0;
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}
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void chipid_clear_production_mode(void)
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{
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rCFG_FUSE0 &= ~1;
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}
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bool chipid_get_secure_mode(void)
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{
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// we never demote secure mode on platforms that don't have an SEP
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return ((rCFG_FUSE0_RAW >> 1) & 1) != 0;
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}
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uint32_t chipid_get_security_domain(void)
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{
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return (rCFG_FUSE0 >> 2) & 3;
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}
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uint32_t chipid_get_board_id(void)
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{
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return (rCFG_FUSE0 >> 4) & 3;
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}
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uint32_t chipid_get_minimum_epoch(void)
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{
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return (rCFG_FUSE0 >> 9) & 0x7F;
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}
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uint32_t chipid_get_chip_id(void)
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{
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return 0x7002;
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}
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uint32_t chipid_get_chip_revision(void)
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{
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return (((rCFG_FUSE0 >> 25) & 0x7) << 4) | (((rCFG_FUSE0 >> 22) & 0x7) << 0);
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}
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uint32_t chipid_get_osc_frequency(void)
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{
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return OSC_FREQ;
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}
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uint64_t chipid_get_ecid_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint64_t chipid_get_die_id(void)
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{
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return ((uint64_t)rECIDHI << 32) | rECIDLO;
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}
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uint32_t chipid_get_soc_voltage(uint32_t index)
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{
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uint32_t soc_voltage = 0;
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return soc_voltage;
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}
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uint32_t chipid_get_cpu_voltage(uint32_t index)
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{
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uint32_t cpu_voltage = 0;
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return cpu_voltage;
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}
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uint32_t chipid_get_ram_voltage(uint32_t index)
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{
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uint32_t sram_voltage = 0;
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return sram_voltage;
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}
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bool chipid_get_fuse_lock(void)
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{
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return (rCFG_FUSE1 & (1 << 31)) != 0;
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}
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void chipid_set_fuse_lock(bool locked)
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{
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if (locked) rCFG_FUSE1 |= (1 << 31);
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}
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uint32_t chipid_get_fuse_revision(void)
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{
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return (rCFG_FUSE0 >> 18) & 0xf;
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}
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uint32_t chipid_get_total_rails_leakage()
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{
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uint32_t total_leakage;
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uint32_t leakage_data0;
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uint8_t leakage_data1;
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leakage_data0 = rCFG_FUSE5;
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leakage_data1 = (rCFG_FUSE4 >> 31) & 1;
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total_leakage = ((leakage_data0 >> 28) & 0xf) + 1; // soc_sram: cfg_fuse4[31:28]
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total_leakage += ((leakage_data0 >> 24) & 0xf) + 1; // cpu_sram: cfg_fuse4[27:24]
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total_leakage += ((leakage_data0 >> 16) & 0xff) + 1; // gpu: cfg_fuse4[23:16]
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total_leakage += ((leakage_data0 >> 8) & 0xff) + 1; // soc: cfg_fuse4[15:8]
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total_leakage += ((((leakage_data0 >> 0) & 0xff) << 1) | leakage_data1) + 1; // cpu: cfg_fuse4[7:0], cfg_fuse4[31]
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return total_leakage;
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}
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