277 lines
9.5 KiB
C
277 lines
9.5 KiB
C
/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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/*
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* This file is only a database of the performance sate for CPU and GPU, regarding the kind of chip
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* or board, it has no access to the chip.
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*/
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#include <platform.h>
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#include <platform/soc/dvfmperf.h>
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// These array are the first iteration, the next part will include reference to board id, board rev, fuse rev.
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static const enum chipid_voltage_index s8000_cpu[] = {
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CHIPID_CPU_VOLTAGE_BYPASS,
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CHIPID_CPU_VOLTAGE_SECUREROM,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_600,
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CHIPID_CPU_VOLTAGE_912,
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CHIPID_CPU_VOLTAGE_1200,
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CHIPID_CPU_VOLTAGE_1512,
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CHIPID_CPU_VOLTAGE_1800,
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CHIPID_CPU_VOLTAGE_1848,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_1512_WA,
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CHIPID_CPU_VOLTAGE_1200_WA,
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CHIPID_CPU_VOLTAGE_396_WA,
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};
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static const enum chipid_voltage_index s8003_cpu[] = {
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CHIPID_CPU_VOLTAGE_BYPASS,
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CHIPID_CPU_VOLTAGE_SECUREROM,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_600,
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CHIPID_CPU_VOLTAGE_912,
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CHIPID_CPU_VOLTAGE_1200,
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CHIPID_CPU_VOLTAGE_1512,
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CHIPID_CPU_VOLTAGE_1800,
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CHIPID_CPU_VOLTAGE_1848,
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};
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static const enum chipid_voltage_index s8000a1_cpu[] = {
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CHIPID_CPU_VOLTAGE_BYPASS,
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CHIPID_CPU_VOLTAGE_SECUREROM,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_600,
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CHIPID_CPU_VOLTAGE_912,
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CHIPID_CPU_VOLTAGE_1200,
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CHIPID_CPU_VOLTAGE_1512,
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CHIPID_CPU_VOLTAGE_1800,
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CHIPID_CPU_VOLTAGE_1896,
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};
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static const enum chipid_voltage_index s8000_gpu[] = {
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CHIPID_GPU_VOLTAGE_OFF,
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CHIPID_GPU_VOLTAGE_340,
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CHIPID_GPU_VOLTAGE_474,
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CHIPID_GPU_VOLTAGE_550,
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CHIPID_GPU_VOLTAGE_723,
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};
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static const enum chipid_voltage_index s8003_gpu[] = {
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CHIPID_GPU_VOLTAGE_OFF,
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CHIPID_GPU_VOLTAGE_340,
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CHIPID_GPU_VOLTAGE_474,
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CHIPID_GPU_VOLTAGE_550,
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CHIPID_GPU_VOLTAGE_723,
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};
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static const enum chipid_voltage_index s8000a1_gpu[] = {
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CHIPID_GPU_VOLTAGE_OFF,
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CHIPID_GPU_VOLTAGE_340,
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CHIPID_GPU_VOLTAGE_474,
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CHIPID_GPU_VOLTAGE_550,
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CHIPID_GPU_VOLTAGE_616,
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};
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static const enum chipid_voltage_index s8001_cpu[] = {
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CHIPID_CPU_VOLTAGE_BYPASS,
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CHIPID_CPU_VOLTAGE_SECUREROM,
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CHIPID_CPU_VOLTAGE_396,
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CHIPID_CPU_VOLTAGE_720,
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CHIPID_CPU_VOLTAGE_1080,
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CHIPID_CPU_VOLTAGE_1440,
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CHIPID_CPU_VOLTAGE_1800,
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CHIPID_CPU_VOLTAGE_2160,
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CHIPID_CPU_VOLTAGE_2256_1core,
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};
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static const enum chipid_voltage_index s8001_gpu[] = {
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CHIPID_GPU_VOLTAGE_OFF,
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CHIPID_GPU_VOLTAGE_360,
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CHIPID_GPU_VOLTAGE_520,
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CHIPID_GPU_VOLTAGE_650,
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CHIPID_GPU_VOLTAGE_723,
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};
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static const enum chipid_voltage_index s8000_soc[] = {
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CHIPID_SOC_VOLTAGE_BYPASS,
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CHIPID_SOC_VOLTAGE_SECUREROM,
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CHIPID_SOC_VOLTAGE_VMIN,
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CHIPID_SOC_VOLTAGE_VNOM,
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};
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static const enum chipid_voltage_index s8003_soc[] = {
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CHIPID_SOC_VOLTAGE_BYPASS,
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CHIPID_SOC_VOLTAGE_SECUREROM,
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CHIPID_SOC_VOLTAGE_VMIN,
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CHIPID_SOC_VOLTAGE_VNOM,
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};
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static const enum chipid_voltage_index s8001_soc[] = {
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CHIPID_SOC_VOLTAGE_BYPASS,
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CHIPID_SOC_VOLTAGE_SECUREROM,
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CHIPID_SOC_VOLTAGE_VMIN,
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CHIPID_SOC_VOLTAGE_VMIN,
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};
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static const enum chipid_voltage_index s8001_j127_gpu[] = {
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CHIPID_GPU_VOLTAGE_OFF,
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CHIPID_GPU_VOLTAGE_360,
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CHIPID_GPU_VOLTAGE_520,
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CHIPID_GPU_VOLTAGE_650,
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CHIPID_GPU_VOLTAGE_723,
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CHIPID_GPU_VOLTAGE_804,
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};
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static const enum chipid_voltage_index s8001_j105_cpu[] = {
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CHIPID_CPU_VOLTAGE_BYPASS,
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CHIPID_CPU_VOLTAGE_SECUREROM,
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CHIPID_CPU_VOLTAGE_2256,
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};
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static const enum chipid_voltage_index s8001_j105_soc[] = {
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CHIPID_SOC_VOLTAGE_BYPASS,
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CHIPID_SOC_VOLTAGE_SECUREROM,
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CHIPID_SOC_VOLTAGE_VMIN,
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CHIPID_SOC_VOLTAGE_VMIN,
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};
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static const enum chipid_voltage_index s8001_j105_gpu[] = {
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CHIPID_GPU_VOLTAGE_OFF,
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CHIPID_GPU_VOLTAGE_723,
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};
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static const enum chipid_voltage_index s8001_j127_soc[] = {
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CHIPID_SOC_VOLTAGE_BYPASS,
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CHIPID_SOC_VOLTAGE_SECUREROM,
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CHIPID_SOC_VOLTAGE_VNOM,
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CHIPID_SOC_VOLTAGE_VNOM,
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};
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static const enum chipid_voltage_index s8001_j99a_soc[] = {
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CHIPID_SOC_VOLTAGE_BYPASS,
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CHIPID_SOC_VOLTAGE_SECUREROM,
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CHIPID_SOC_VOLTAGE_VMIN,
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CHIPID_SOC_VOLTAGE_VMIN,
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};
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struct dvfmperf {
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uint32_t chip_id;
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uint32_t chip_rev;
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uint32_t board_id;
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const enum chipid_voltage_index *voltage_indexes;
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uint32_t size;
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};
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// The dvfmperfs arays must be sorted to have :
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// - BOARD_ID_NONE always coming last for chip/chip revision
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// - Highest chip revision coming first
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static const struct dvfmperf dvfmperfs_cpu[] = { // Entry with highest chip revision must come first
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{0x8000, CHIP_REVISION_B0, BOARD_ID_NONE, s8000_cpu, sizeof(s8000_cpu)/sizeof(s8000_cpu[0])},
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{0x8000, CHIP_REVISION_A1, BOARD_ID_NONE, s8000a1_cpu, sizeof(s8000a1_cpu)/sizeof(s8000a1_cpu[0])},
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{0x8003, CHIP_REVISION_A0, BOARD_ID_NONE, s8003_cpu, sizeof(s8003_cpu)/sizeof(s8003_cpu[0])},
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{0x8001, CHIP_REVISION_A0, J105_AP_BOARD_ID, s8001_j105_cpu, sizeof(s8001_j105_cpu)/sizeof(s8001_j105_cpu[0])},
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{0x8001, CHIP_REVISION_A0, J105_DEV_BOARD_ID, s8001_j105_cpu, sizeof(s8001_j105_cpu)/sizeof(s8001_j105_cpu[0])},
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{0x8001, CHIP_REVISION_A0, BOARD_ID_NONE, s8001_cpu, sizeof(s8001_cpu)/sizeof(s8000_cpu[0])},
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};
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static const struct dvfmperf dvfmperfs_gpu[] = { // Entry with highest chip revision must come first
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{0x8000, CHIP_REVISION_B0, BOARD_ID_NONE, s8000_gpu, sizeof(s8000_gpu)/sizeof(s8000_gpu[0])},
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{0x8000, CHIP_REVISION_A1, BOARD_ID_NONE, s8000a1_gpu, sizeof(s8000a1_gpu)/sizeof(s8000a1_gpu[0])},
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{0x8003, CHIP_REVISION_A0, BOARD_ID_NONE, s8003_gpu, sizeof(s8003_gpu)/sizeof(s8003_gpu[0])},
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{0x8001, CHIP_REVISION_A0, J128_AP_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
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{0x8001, CHIP_REVISION_A0, J128_DEV_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
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{0x8001, CHIP_REVISION_A0, J127_AP_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
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{0x8001, CHIP_REVISION_A0, J127_DEV_BOARD_ID, s8001_j127_gpu, sizeof(s8001_j127_gpu)/sizeof(s8001_j127_gpu[0])},
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{0x8001, CHIP_REVISION_A0, J105_AP_BOARD_ID, s8001_j105_gpu, sizeof(s8001_j105_gpu)/sizeof(s8001_j105_gpu[0])},
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{0x8001, CHIP_REVISION_A0, J105_DEV_BOARD_ID, s8001_j105_gpu, sizeof(s8001_j105_gpu)/sizeof(s8001_j105_gpu[0])},
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{0x8001, CHIP_REVISION_A0, BOARD_ID_NONE, s8001_gpu, sizeof(s8001_gpu)/sizeof(s8001_gpu[0])},
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};
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static const struct dvfmperf dvfmperfs_soc[] = { // Entry with highest chip revision must come first
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{0x8000, CHIP_REVISION_B0, BOARD_ID_NONE, s8000_soc, sizeof(s8000_soc)/sizeof(s8000_soc[0])},
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{0x8003, CHIP_REVISION_A0, BOARD_ID_NONE, s8003_soc, sizeof(s8003_soc)/sizeof(s8003_soc[0])},
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{0x8001, CHIP_REVISION_A0, J105_AP_BOARD_ID, s8001_j105_soc, sizeof(s8001_j105_soc)/sizeof(s8001_j105_soc[0])},
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{0x8001, CHIP_REVISION_A0, J105_DEV_BOARD_ID, s8001_j105_soc, sizeof(s8001_j105_soc)/sizeof(s8001_j105_soc[0])},
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{0x8001, CHIP_REVISION_A0, J128_AP_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
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{0x8001, CHIP_REVISION_A0, J128_DEV_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
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{0x8001, CHIP_REVISION_A0, J127_AP_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
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{0x8001, CHIP_REVISION_A0, J127_DEV_BOARD_ID, s8001_j127_soc, sizeof(s8001_j127_soc)/sizeof(s8001_j127_soc[0])},
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{0x8001, CHIP_REVISION_A0, J99A_AP_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
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{0x8001, CHIP_REVISION_A0, J99A_DEV_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
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{0x8001, CHIP_REVISION_A0, J98A_AP_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
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{0x8001, CHIP_REVISION_A0, J98A_DEV_BOARD_ID, s8001_j99a_soc, sizeof(s8001_j99a_soc)/sizeof(s8001_j99a_soc[0])},
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{0x8001, CHIP_REVISION_A0, BOARD_ID_NONE, s8001_soc, sizeof(s8001_soc)/sizeof(s8001_soc[0])},
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};
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enum chipid_voltage_index dvfmperf_get_voltage_index(uint32_t index, enum chipid_voltage_type voltage_type)
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{
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const struct dvfmperf *dvfmperfs;
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enum chipid_voltage_index voltage_index_for_filling;
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uint32_t chip_id = chipid_get_chip_id();
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uint32_t chip_rev = chipid_get_chip_revision();
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uint32_t board_id = platform_get_board_id();
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uint32_t i;
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uint32_t size = 0;
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switch (voltage_type) {
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case CHIPID_CPU_VOLTAGE:
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dvfmperfs = dvfmperfs_cpu;
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voltage_index_for_filling = CHIPID_CPU_VOLTAGE_396;
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size = sizeof(dvfmperfs_cpu)/sizeof(dvfmperfs_cpu[0]);
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break;
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case CHIPID_GPU_VOLTAGE:
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dvfmperfs = dvfmperfs_gpu;
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size = sizeof(dvfmperfs_gpu)/sizeof(dvfmperfs_gpu[0]);
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voltage_index_for_filling = CHIPID_GPU_VOLTAGE_OFF;
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break;
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case CHIPID_SOC_VOLTAGE:
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dvfmperfs = dvfmperfs_soc;
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size = sizeof(dvfmperfs_soc)/sizeof(dvfmperfs_soc[0]);
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break;
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default:
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panic("Invalid voltage type\n");
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voltage_index_for_filling = CHIPID_GPU_VOLTAGE_OFF; // prevent compiler warning
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dvfmperfs = NULL; // Prevent compiler warning
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break;
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}
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for (i = 0; i < size; i++) {
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if (chip_id != dvfmperfs[i].chip_id) {
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continue;
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}
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if (chip_rev < dvfmperfs[i].chip_rev) {
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continue;
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}
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if ((board_id != dvfmperfs[i].board_id) && (dvfmperfs[i].board_id != BOARD_ID_NONE)) {
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continue;
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}
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if (index >= dvfmperfs[i].size) {
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if (voltage_type == CHIPID_SOC_VOLTAGE) {
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if (dvfmperfs[i].size < 4) {
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panic("Invalid number of SOC perf states");
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}
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voltage_index_for_filling = dvfmperfs[i].voltage_indexes[2];
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}
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return voltage_index_for_filling;
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}
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return dvfmperfs[i].voltage_indexes[index];
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}
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panic("Unknown voltage for current chip\n");
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return CHIPID_GPU_VOLTAGE_OFF; // Never reach this code
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}
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