121 lines
2.8 KiB
C
121 lines
2.8 KiB
C
/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/amc/amc.h>
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#include <drivers/amc/amc_phy.h>
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#include <drivers/amc/amc_regs.h>
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#include <drivers/dram.h>
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#include <drivers/miu.h>
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#include <sys.h>
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#include <platform/soc/hwclocks.h>
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int mcu_initialize_dram (bool resume)
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{
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// Don't perform DRAM initializion if the memory controller is already
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// initialized (e.g., for SecureROM validation testing).
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if (resume || rAMC_AMCEN == 0) {
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clock_gate(CLK_MCU, true);
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clock_gate(CLK_MCC, true);
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clock_gate(CLK_AMP, true);
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amc_init(resume);
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}
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return 0;
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}
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void mcu_bypass_prep (int step)
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{
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amc_phy_bypass_prep(step);
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}
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uint64_t mcu_get_memory_size (void)
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{
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return amc_get_memory_size();
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}
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void amc_configure_address_decoding_and_mapping(void)
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{
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rAMC_MCSADDRBNKHASH(2) = 0x000036db;
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rAMC_MCSADDRBNKHASH(1) = 0x00005b6d;
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rAMC_MCSADDRBNKHASH(0) = 0x00006db6;
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rAMC_ADDRMAP_MODE = amc_get_params()->addrmapmode;
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}
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void amc_enable_slow_boot (bool enable)
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{
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if (enable) {
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// switch to slow clock
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clocks_set_performance(kPerformanceMemoryLow);
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spin(1);
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}
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else {
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#if !SUPPORT_FPGA
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// switch back to full-speed
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clocks_set_performance(kPerformanceMemoryFull);
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spin(1);
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#endif
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}
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}
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void amc_finalize (bool resume)
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{
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// Enabling clock gating and AutoSR only after wrdqcal is done
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rAMC_CLKPWRGATE = 0x050a0000;
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rAMC_CLKPWRGATE2 = 0x00660300;
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// <rdar://problem/16239984> Alcatraz, Fiji, Capri: L2_TB: MCU PIO accesses to the same address and device stream getting reordered in CP
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platform_memory_barrier();
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rAMC_PWRMNGTEN &= ~0x00100000;
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#if !SUPPORT_FPGA
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rAMC_PWRMNGTEN |= 0x00011011;
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// These 2 values are replaced later in the sequence when tunables are programmed
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rAMC_PWRMNGTPARAM = 0x01803000;
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rAMC_PSQWQCTL1 = 0x00000120;
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#else
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rAMC_PWRMNGTEN |= 0x00000010;
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#endif
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}
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void amc_dram_workarounds (bool resume)
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{
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const struct amc_memory_device_info *dev_info;
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dev_info = amc_get_memory_device_info();
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switch (dev_info->vendor_id) {
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case JEDEC_MANUF_ID_HYNIX:
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// No work-arounds for Hynix ... yet!
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break;
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case JEDEC_MANUF_ID_ELPIDA:
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/* Filter only for Elpida 25nm to apply test MRS */
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if ((dev_info->rev_id == 0x2) && (dev_info->rev_id2 <= 0x2)) { // MR6 = 2(25nm) and MR7 = 2(Rev2)
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if (!resume) {
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// Elpida has no TestMRS entry/exit cmd
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// <rdar://problem/15465954> Fiji: Need Duty Cycle Adjust work-around to improve Fiji+Elpida 25nm DDR eye margin
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0xbb);
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amc_mrcmd(MR_WRITE, AMC_NUM_CHANNELS, AMC_NUM_RANKS, 0x9, 0x27);
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}
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}
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break;
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default:
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break;
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}
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return;
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}
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