55 lines
1.5 KiB
ArmAsm
55 lines
1.5 KiB
ArmAsm
/*
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* Copyright (c) 2013-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <platform/memmap.h>
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.text
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.balign 4
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.globl _platform_start
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_platform_start:
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////////////////////////////////////////////////
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// Must preserve X0 and X1
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////////////////////////////////////////////////
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#if !APPLICATION_SECUREROM
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// Enable the L2 cache load/store prefetcher.
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mrs x2, s3_0_c15_c5_0 // HID5
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and x2, x2, #~(3<<44) // Enable L2C load (bit 44)/store (bit 45) prefetch
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msr s3_0_c15_c5_0, x2 // HID5
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isb
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#endif
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#if WITH_L2_AS_RAM
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#if APPLICATION_SECUREROM
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// Enable L2 as RAM
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mrs x2, s3_3_c15_c7_0 // L2_CRAMCONFIG
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orr x2, x2, #2 // L2_CRAMCONFIG.EnableSize (2 MiB SRAM)
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msr s3_3_c15_c7_0, x2 // L2_CRAMCONFIG
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1:
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// Poll for RAM ready
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mrs x2, s3_3_c15_c7_0 // L2_CRAMCONFIG
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and x2, x2, #(1<<63) // L2_CRAMCONFIG.Ready
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cbz x2, 1b // Not ready
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#endif
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#if PRODUCT_IBOOT || PRODUCT_IBEC
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// Disable L2 as RAM
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mrs x2, s3_3_c15_c7_0 // L2_CRAMCONFIG
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and x2, x2, #~0x3F // L2_CRAMCONFIG.EnableSize (disable SRAM)
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msr s3_3_c15_c7_0, x2 // L2_CRAMCONFIG
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1:
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// Poll for RAM not ready
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mrs x2, s3_3_c15_c7_0 // L2_CRAMCONFIG
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and x2, x2, #(1<<63) // L2_CRAMCONFIG.Ready
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cbnz x2, 1b // Still ready
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#endif
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#endif
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ret
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