317 lines
12 KiB
C
317 lines
12 KiB
C
/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
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I/O Spreadsheet version: rev 1v0
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I/O Spreadsheet tracker: <rdar://problem/16391334> E86: IO Spreadsheet Tracker
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Conversion command: csvtopinconfig.py --soc fiji --copyright 2014 --radar '<rdar://problem/16391334> E86: IO Spreadsheet Tracker' <filename>
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*/
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#include <debug.h>
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#include <drivers/apple/gpio.h>
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#include <platform.h>
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#include <platform/soc/hwregbase.h>
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#include <stdint.h>
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static const uint32_t pinconfig_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {
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/* Port 0 */
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CFG_DISABLED, // 0 : ULPI_DIR ->
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CFG_DISABLED, // 1 : ULPI_STP ->
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CFG_DISABLED, // 2 : ULPI_NXT ->
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CFG_DISABLED, // 3 : ULPI_DATA[7] ->
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CFG_DISABLED, // 4 : ULPI_DATA[6] ->
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CFG_DISABLED, // 5 : ULPI_DATA[5] ->
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CFG_DISABLED, // 6 : ULPI_DATA[4] ->
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CFG_DISABLED, // 7 : ULPI_CLK ->
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/* Port 1 */
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CFG_DISABLED, // 8 : ULPI_DATA[3] ->
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CFG_DISABLED, // 9 : ULPI_DATA[2] ->
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CFG_DISABLED, // 10 : ULPI_DATA[1] ->
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CFG_DISABLED, // 11 : ULPI_DATA[0] ->
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CFG_DISABLED, // 12 : SPI1_SCLK ->
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CFG_DISABLED, // 13 : SPI1_MOSI ->
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CFG_DISABLED, // 14 : SPI1_MISO ->
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CFG_DISABLED, // 15 : SPI1_SSIN ->
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/* Port 2 */
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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/* Port 3 */
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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/* Port 4 */
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CFG_IN | PULL_UP, // 32 : GPIO[11] -> SYS_BTN_MENU_L
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CFG_IN | PULL_UP, // 33 : GPIO[12] -> SYS_BTN_HOLD_L
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CFG_DISABLED, // 34 : I2S3_MCK ->
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CFG_DISABLED, // 35 : I2S3_LRCK ->
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CFG_DISABLED, // 36 : I2S3_BCLK ->
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CFG_DISABLED, // 37 : I2S3_DOUT ->
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CFG_DISABLED, // 38 : I2S3_DIN ->
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CFG_DISABLED, // 39 : CLK32K_OUT ->
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/* Port 5 */
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CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 40 : PCIE_CLKREQ0_N -> GMAC_CLKREQ_L
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CFG_FUNC0 | PULL_UP | INPUT_SCHMITT, // 41 : PCIE_CLKREQ1_N -> WLAN_PCIE_CLKREQ_L
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CFG_DISABLED, // 42 : NAND_SYS_CLK ->
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CFG_DISABLED, // 43 : GPIO[0] ->
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CFG_DISABLED, // 44 : GPIO[1] ->
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CFG_IN | PULL_UP, // 45 : GPIO[2] -> SYS_BTN_VOL_UP_L
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CFG_IN | PULL_UP, // 46 : GPIO[3] -> SYS_BTN_VOL_DN_L
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CFG_DISABLED, // 47 : GPIO[4] ->
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/* Port 6 */
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CFG_DISABLED, // 48 : GPIO[5] ->
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CFG_DISABLED, // 49 : GPIO[6] ->
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CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 50 : GPIO[7] -> WLAN_BT_DEV_WAKE
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CFG_DISABLED, // 51 : GPIO[14] ->
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CFG_DISABLED, // 52 : GPIO[16] -> DUT_BOARD_ID3
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CFG_DISABLED, // 53 : GPIO[17] ->
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CFG_DISABLED, // 54 : GPIO[18] -> DUT_BOOT_CFG0
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CFG_DISABLED, // 55 : GPIO[20] ->
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/* Port 7 */
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CFG_IN | PULL_DOWN, // 56 : GPIO[21] -> HOOVER_IRQ
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CFG_DISABLED, // 57 : UART5_RTXD ->
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CFG_DISABLED, // 58 : UART8_TXD ->
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CFG_DISABLED, // 59 : UART8_RXD ->
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CFG_DISABLED, // 60 : SPI0_SCLK -> DUT_BOARD_ID0
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CFG_DISABLED, // 61 : SPI0_MOSI -> DUT_BOARD_ID1
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CFG_DISABLED, // 62 : SPI0_MISO -> DUT_BOARD_ID2
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CFG_DISABLED, // 63 : SPI0_SSIN ->
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/* Port 8 */
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 64 : I2C2_SDA -> GMAC_SMB_DATA
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 65 : I2C2_SCL -> GMAC_SMB_CLK
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CFG_DISABLED, // 66 : GPIO[22] ->
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CFG_DISABLED, // 67 : GPIO[23] ->
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CFG_DISABLED, // 68 : GPIO[25] -> DUT_BOOT_CFG1
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CFG_DISABLED, // 69 : GPIO[28] -> DUT_BOOT_CFG2
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CFG_DISABLED, // 70 : GPIO[29] -> DUT_BOARD_ID4
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CFG_DISABLED, // 71 : GPIO[34] -> DUT_BOARD_REV3
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/* Port 9 */
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CFG_DISABLED, // 72 : GPIO[35] -> DUT_BOARD_REV2
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CFG_DISABLED, // 73 : GPIO[36] -> DUT_BOARD_REV1
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CFG_DISABLED, // 74 : GPIO[37] -> DUT_BOARD_REV0
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CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 75 : GPIO[39]/ PCIE_PERST0_N -> GMAC_PERST_L
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CFG_DISABLED, // 76 : GPIO[42] ->
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CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 77 : GPIO[43]/PCIE_PERST1_N -> WLAN_PCIE_RST_L
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CFG_DISABLED, // 78 : DISP_VSYNC ->
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CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 79 : UART0_TXD -> TRISTAR_UART1_TX
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/* Port 10 */
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CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 80 : UART0_RXD -> TRISTAR_UART1_RX
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CFG_DISABLED, // 81 : TMR32_PWM0 ->
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CFG_DISABLED, // 82 : TMR32_PWM1 ->
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CFG_DISABLED, // 83 : TMR32_PWM2 ->
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CFG_FUNC0 | PULL_UP | SLOW_SLEW, // 84 : UART6_TXD -> TRISTAR_UART0_TX
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CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT, // 85 : UART6_RXD -> TRISTAR_UART0_RX
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CFG_DISABLED, // 86 : I2C3_SDA -> HUB0_NON_REM1_SDA
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CFG_DISABLED, // 87 : I2C3_SCL -> HUB0_CFG_SEL0_SCL
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/* Port 11 */
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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/* Port 12 */
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 96 : I2C0_SDA -> PMU_SDA
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 97 : I2C0_SCL -> PMU_SCL
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CFG_DISABLED, // 98 : GPIO[38] ->
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CFG_DISABLED, // 99 : UART2_TXD -> << CPLD MUX >>
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CFG_DISABLED, // 100 : UART2_RXD -> << CPLD MUX >>
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CFG_DISABLED, // 101 : UART2_RTSN -> << CPLD MUX >>
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CFG_DISABLED, // 102 : UART2_CTSN -> << CPLD MUX >>
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CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 103 : DWI_DO -> PMU_DWI_DI
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/* Port 13 */
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CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 104 : DWI_CLK -> PMU_DWI_CLK
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CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 105 : WDOG -> PMU_RESET_IN1
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CFG_IN | PULL_UP, // 106 : GPIO[13] -> PMU_IRQ_L
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CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 107 : GPIO[19] -> PMU_KEEPACT
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CFG_DISABLED, // 108 : GPIO[26] -> DUT_FORCE_DFU
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CFG_DISABLED, // 109 : GPIO[27] -> DUT_DFU_STATUS
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CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 110 : SOCHOT0 -> PMU_PRE_UVLO
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CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 111 : SOCHOT1 -> PMU_RESET_IN3
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/* Port 14 */
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CFG_DISABLED, // 112 : UNSPECIFIED -> UNSPECIFIED
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CFG_DISABLED, // 113 : TST_CLKOUT -> << SMA CONN >>
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CFG_DISABLED, // 114 : GPIO[8] ->
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CFG_DISABLED, // 115 : GPIO[9] -> WLAN_JTAG_SWCLK
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CFG_DISABLED, // 116 : GPIO[10] -> WLAN_JTAG_SWDIO
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CFG_DISABLED, // 117 : GPIO[15] ->
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CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 118 : UART4_TXD -> WLAN_UART_RXD
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CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 119 : UART4_RXD -> WLAN_UART_TXD
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/* Port 15 */
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CFG_OUT_1 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 120 : UART4_RTSN -> WLAN_UART_CTS_L
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CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 121 : UART4_CTSN -> WLAN_UART_RTS_L
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CFG_DISABLED, // 122 : SPI3_MOSI ->
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CFG_DISABLED, // 123 : SPI3_MISO ->
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CFG_DISABLED, // 124 : SPI3_SCLK ->
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CFG_DISABLED, // 125 : SPI3_SSIN ->
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CFG_DISABLED, // 126 : GPIO[24] ->
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CFG_DISABLED, // 127 : GPIO[30] -> << CPLD SPARE >>
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/* Port 16 */
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CFG_DISABLED, // 128 : GPIO[31] -> << CPLD SPARE >>
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CFG_DISABLED, // 129 : GPIO[32] -> << CPLD SPARE >>
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CFG_DISABLED, // 130 : GPIO[33] -> << CPLD SPARE >>
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CFG_IN, // 131 : GPIO[40] -> SYS_BTN_RING_L
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CFG_DISABLED, // 132 : GPIO[41] ->
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CFG_IN | PULL_DOWN, // 133 : I2S4_MCK -> TRISTAR_INT
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CFG_DISABLED, // 134 : I2S4_LRCK ->
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CFG_DISABLED, // 135 : I2S4_BCLK ->
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/* Port 17 */
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CFG_DISABLED, // 136 : I2S4_DOUT ->
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CFG_DISABLED, // 137 : I2S4_DIN ->
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 138 : I2C1_SDA -> HOOVER_I2C_SDA
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 139 : I2C1_SCL -> HOOVER_I2C_SCL
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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/* Port 18 */
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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/* Port 19 */
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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/* Port 20 */
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 160 : I2S0_LRCK -> HOOVER_MCA_LRCK
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 161 : I2S0_BCLK -> HOOVER_MCA_BCLK
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 162 : I2S0_DOUT -> HOOVER_MCA_D0
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CFG_DISABLED, // 163 : I2S0_DIN ->
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CFG_DISABLED, // 164 : I2S1_MCK ->
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 165 : I2S1_LRCK -> WLAN_BT_I2S_LRCK
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 166 : I2S1_BCLK -> WLAN_BT_I2S_BCLK
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 167 : I2S1_DOUT -> WLAN_BT_I2S_DIN
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/* Port 21 */
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 168 : I2S1_DIN -> WLAN_B2_I2S_DOUT
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CFG_DISABLED, // 169 : I2S2_LRCK ->
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CFG_DISABLED, // 170 : I2S2_BCLK ->
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CFG_DISABLED, // 171 : I2S2_DOUT ->
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CFG_DISABLED, // 172 : I2S2_DIN ->
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CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 173 : UART1_TXD -> WLAN_BT_UART_RXD
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CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT, // 174 : UART1_RXD -> WLAN_BT_UART_TXD
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CFG_OUT_1 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 175 : UART1_RTSN -> WLAN_BT_UART_CTS_L
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/* Port 22 */
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CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW, // 176 : UART1_CTSN -> WLAN_BT_UART_RTS_L
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CFG_FUNC0 | PULL_DOWN, // 177 : EDP_HPD -> HOOVER_HPD_OUT
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CFG_DISABLED, // 178 : UART3_TXD ->
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CFG_DISABLED, // 179 : UART3_RXD ->
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CFG_DISABLED, // 180 : UART3_RTSN ->
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CFG_DISABLED, // 181 : UART3_CTSN ->
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CFG_DISABLED, // 182 : SPI2_SCLK ->
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CFG_DISABLED, // 183 : SPI2_MOSI ->
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/* Port 23 */
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CFG_DISABLED, // 184 : SPI2_MISO ->
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CFG_DISABLED, // 185 : SPI2_SSIN ->
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CFG_DISABLED, // 186 : ISP0_SDA ->
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CFG_DISABLED, // 187 : ISP0_SCL ->
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CFG_DISABLED, // 188 : ISP1_SDA ->
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CFG_DISABLED, // 189 : ISP1_SCL ->
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CFG_DISABLED, // 190 : SENSOR0_RST ->
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CFG_DISABLED, // 191 : SENSOR0_CLK ->
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/* Port 24 */
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CFG_DISABLED, // 192 : SENSOR0_XSHUTDOWN ->
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CFG_DISABLED, // 193 : SENSOR0_ISTRB ->
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CFG_DISABLED, // 194 : ISP_UART0_TXD ->
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CFG_DISABLED, // 195 : ISP_UART0_RXD ->
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CFG_DISABLED, // 196 : SENSOR1_RST ->
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CFG_DISABLED, // 197 : SENSOR1_CLK ->
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CFG_DISABLED, // 198 : SENSOR1_XSHUTDOWN ->
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CFG_DISABLED, // 199 : SENSOR1_ISTRB ->
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/* Port 25 */
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CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW, // 200 : UART7_TXD -> WLAN_GPIO_1_WLAN_DEV_WAKE
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CFG_DISABLED, // 201 : UART7_RXD ->
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CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW, // 202 : I2S0_MCK -> HOOVER_MCA_MCK
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CFG_DISABLED, // 203 : I2S2_MCK ->
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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CFG_DISABLED,
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};
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struct pinconfig_map {
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uint32_t board_id;
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uint32_t board_id_mask;
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const uint32_t *pinconfigs[GPIOC_COUNT];
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};
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static const struct pinconfig_map cfg_map[] = {
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{ 0, 0, { pinconfig_0 } },
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};
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const uint32_t * target_get_default_gpio_cfg(int gpioc)
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{
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static const struct pinconfig_map *selected_map = NULL;
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if (selected_map == NULL) {
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uint32_t board_id = platform_get_board_id();
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for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
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if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
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selected_map = &cfg_map[i];
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break;
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}
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}
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if (selected_map == NULL)
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panic("no default pinconfig for board id %u", board_id);
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}
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ASSERT(gpioc < GPIOC_COUNT);
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return selected_map->pinconfigs[gpioc];
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}
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