271 lines
7.1 KiB
C
271 lines
7.1 KiB
C
/*
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* Copyright (C) 2010-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/amc/amc.h>
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#include <drivers/amc/amc_phy.h>
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#include <drivers/amp/amp_v1.h>
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#include <drivers/dram.h>
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#include <drivers/miu.h>
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#include <platform.h>
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#include <platform/chipid.h>
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#include <sys.h>
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#define CA_PIVOTS_LIST_SIZE (9)
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#define DQ_PIVOTS_LIST_SIZE (5)
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static const int ca_pivot_ps[CA_PIVOTS_LIST_SIZE] = {-400, -300, -200, -100, 0, 100, 200, 300, 400};
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static const int dq_pivot_ps[DQ_PIVOTS_LIST_SIZE] = {-300, -150, 0, 150, 300};
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static const struct amc_phy_calibration_data amp_calibration_data = {
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.bit_time_ps = 1875,
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.min_ca_window_width_ps = 150,
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.min_dq_window_width_ps = 150,
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.ca_pivot_step_size_ps = 100,
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.dq_pivot_step_size_ps = 150,
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.max_offset_setting = 63,
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.min_offset_factor = 0,
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.dll_f2_delay_fs = 10,
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.ca_pivots_list_size = CA_PIVOTS_LIST_SIZE,
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.ca_pivot_ps = (int *)ca_pivot_ps,
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.dq_pivots_list_size = DQ_PIVOTS_LIST_SIZE,
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.dq_pivot_ps = (int *)dq_pivot_ps,
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.use_resume_boot_flow = true, // to use static CA but dynamic DQ calibration
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};
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static uint32_t amp_dllupdtctrl[AMC_NUM_CHANNELS];
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void amc_phy_init(bool resume)
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{
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int i, d, f;
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for (i = 0; i < AMC_NUM_CHANNELS; i++) {
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int ch = AMP_INDEX_FOR_CHANNEL(i); // cope with hole in AMP address space
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rAMP_AMPEN(ch) = 1;
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#if !SUPPORT_FPGA
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rAMP_DQDQSDS(ch) = 0x0a0a0a0a;
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rAMP_NONDQDS(ch) = 0x0a0a0a0a;
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#endif
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if (amc_phy_params.flags & FLAG_AMP_PARAM_FULLDIFFMODE) {
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for (f = 0; f < AMP_FREQUENCY_SLOTS; f++)
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rAMP_DIFFMODE_FREQ(ch, f) = 0x00000121;
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}
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for (f = 0; f < AMP_FREQUENCY_SLOTS; f++) {
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for (d = 0; d < AMP_NUM_DLL; d++) {
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rAMP_DQSINDLLSCL_FREQ(ch,d,f) = amc_phy_params.freq[f].scl;
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rAMP_DQOUTDLLSCL_FREQ(ch,d,f) = amc_phy_params.freq[f].scl;
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}
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rAMP_CAOUTDLLSCL_FREQ(ch,f) = amc_phy_params.freq[f].scl;
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rAMP_CTLOUTDLLSCL_FREQ(ch,f) = amc_phy_params.freq[f].scl;
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}
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#if !SUPPORT_FPGA
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for (f = 0; f < AMP_FREQUENCY_SLOTS; f++) {
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rAMP_RDCAPCFG_FREQ(ch,f) = amc_phy_params.freq[f].rdcapcfg;
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}
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rAMP_DLLEN(ch) = 0x100;
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// Reset the master DLL to make sure that master DLL locking happens from scratch
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rAMP_DLLEN(ch) |= 0x1;
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rAMP_DLLEN(ch) &= ~0x1;
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amc_phy_run_dll_update(ch);
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#endif
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rAMP_AMPINIT(ch) = 0x1;
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#if !SUPPORT_FPGA
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rAMP_IMPCALCMD(ch) = 0x101;
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while (rAMP_IMPCALCMD(ch) & 0x1) ;
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#endif
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}
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}
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void amc_phy_enable_dqs_pulldown(bool enable)
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{
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}
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void amc_phy_scale_dll(int freqsel, int factor)
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{
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int i;
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for (i=0; i<AMC_NUM_CHANNELS; i++) {
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int ch = AMP_INDEX_FOR_CHANNEL(i); // cope with hole in AMP address space
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rAMP_AMPCLK(ch) = freqsel << 16;
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amc_phy_run_dll_update(ch);
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}
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}
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bool amc_phy_rddq_cal()
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{
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// use static CA offset and calibrated & shifted DQ offsets
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return false;
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}
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void amc_phy_bypass_prep(int step)
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{
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int i;
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// Make sure AMP was inited.
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// Assumptions: all supported channels are inited together,
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// and channel 0 is always used.
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if ((rAMP_AMPINIT(0) & 1) == 0)
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return;
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switch (step) {
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case 0:
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for (i = 0; i < AMC_NUM_CHANNELS; i++) {
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int ch = AMP_INDEX_FOR_CHANNEL(i); // cope with hole in AMP address space
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// change the DllUpdtIntvl and DllFastUpdtIntvl to 0.
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// DllUpdtAlwaysOn and DllFastUpdtAlwaysOn should be enabled
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rAMP_DLLUPDTINTVL(ch) = (1 << 28) | (1 << 12);
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// disable DLLEn
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rAMP_DLLEN(ch) = 0;
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};
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break;
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case 1:
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for (i = 0; i < AMC_NUM_CHANNELS; i++) {
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int ch = AMP_INDEX_FOR_CHANNEL(i); // cope with hole in AMP address space
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// Turn off periodic DLL update
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// Taken care of in step(0)
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// Turn off periodic impedance auto-calibration
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rAMP_IMPAUTOCAL(ch) = 0;
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};
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break;
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}
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}
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void amc_phy_finalize()
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{
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uint8_t i;
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// Change Master DLL from Always-on mode to periodic-on mode
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for(i = 0; i < AMC_NUM_CHANNELS; i++) {
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int ch = AMP_INDEX_FOR_CHANNEL(i); // cope with hole in AMP address space
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rAMP_DLLUPDTINTVL(ch) = ((1 << 28) | (0 << 12) | (0x80 << 0));
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if (amc_phy_params.flags & FLAG_AMP_PARAM_SUPPORT_FMCLK_OFF)
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rAMP_AMPCLK(ch) |= (1 << 8);
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// Make sure the pmgr_ENABLE_CLK_GATE.MCU_CLK_FIXED_GATE_ENABLE is enabled in the PMGR
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// AMC should be enabled so that it can respond to phyupd_req from AMP
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rAMP_IMPAUTOCAL(ch) = 0x00010514;
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}
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}
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void amc_phy_reset_fifos()
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{
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}
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const struct amc_phy_calibration_data * amc_phy_get_calibration_data()
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{
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return &_calibration_data;
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}
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void amc_phy_calibration_init(uint32_t *fine_lock_ps)
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{
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uint8_t i;
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const struct amc_memory_device_info *dev_info;
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dev_info = amc_get_memory_device_info();
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ASSERT(fine_lock_ps != NULL);
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*fine_lock_ps = 0;
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for (i = 0; i < AMC_NUM_CHANNELS; i++) {
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int ch = AMP_INDEX_FOR_CHANNEL(i); // cope with hole in AMP address space
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amp_dllupdtctrl[ch] = rAMP_DLLUPDTCTRL(ch);
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rAMP_DLLUPDTCTRL(ch) &= ~((3 << 20) | (1 << 16)); // DLLUptMode = 0, DllUpdtPhyUpdtTyp = 0
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*fine_lock_ps += amp_calibration_data.bit_time_ps / (((rAMP_MDLLCODE(ch) & 0x7f) + amp_calibration_data.dll_f2_delay_fs) * 4);
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rAMP_CALPATCFG(ch) = (0x3 << 8);
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rAMP_DQTRNCFG(ch) = 0x3f;
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if ( ((dev_info->vendor_id == JEDEC_MANUF_ID_SAMSUNG) && (dev_info->rev_id == 0)) ||
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((dev_info->vendor_id == JEDEC_MANUF_ID_HYNIX) && (dev_info->density == JEDEC_DENSITY_1Gb)) )
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rAMP_CALDQMSK(ch) = 0xfefefefe;
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else
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rAMP_CALDQMSK(ch) = 0x00000000;
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}
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*fine_lock_ps = *fine_lock_ps / AMC_NUM_CHANNELS;
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}
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void amc_phy_run_dll_update(uint8_t ch)
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{
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ch = AMP_INDEX_FOR_CHANNEL(ch); // cope with hole in AMP address space
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rAMP_DLLUPDTCMD(ch) = 0x1;
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while ((rAMP_DLLUPDTCMD(ch) & 0x1) != 0) ;
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}
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void amc_phy_set_addr_offset(uint8_t ch, uint8_t value)
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{
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rAMP_CAOUTDLLOVRRD(AMP_INDEX_FOR_CHANNEL(ch)) = value;
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}
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void amc_phy_set_rd_offset(uint8_t ch, uint8_t byte, uint8_t value)
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{
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rAMP_DQSINDLLOVRRD(AMP_INDEX_FOR_CHANNEL(ch), byte) = value;
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}
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void amc_phy_set_wr_offset(uint8_t ch, uint8_t byte, uint8_t value)
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{
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rAMP_DQOUTDLLOVRRD(AMP_INDEX_FOR_CHANNEL(ch), byte) = value;
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}
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void amc_phy_run_dq_training(uint8_t ch)
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{
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ch = AMP_INDEX_FOR_CHANNEL(ch); // cope with hole in AMP address space
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amc_phy_run_dll_update(ch);
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rAMP_DQTRNCMD(ch) = 0x1; // execute DQ training sequence
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while ((rAMP_DQTRNCMD(ch) & 0x1) != 0) ; // wait for training to be finished
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}
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uint32_t amc_phy_get_dq_training_status(uint8_t ch, uint8_t byte, uint8_t num_bytes)
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{
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uint8_t byte_result;
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uint32_t status;
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status = rAMP_DQTRNSTS(AMP_INDEX_FOR_CHANNEL(ch));
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byte_result = (status & (1 << (byte + 16)));
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return byte_result;
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}
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void amc_phy_configure_dll_pulse_mode(uint8_t ch, bool enable)
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{
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ch = AMP_INDEX_FOR_CHANNEL(ch); // cope with hole in AMP address space
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if (!enable) {
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rAMP_DLLUPDTCTRL(ch) &= ~((3 << 20) | (1 << 16)); // DLLUptMode = 0, DllUpdtPhyUpdtTyp = 0
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}
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else {
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rAMP_DLLUPDTCTRL(ch) = amp_dllupdtctrl[ch];
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amc_phy_run_dll_update(ch);
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}
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}
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void amc_phy_shift_dq_offset(int8_t *dq_offset, uint8_t num_bytes) {
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amc_dram_shift_dq_offset(dq_offset, num_bytes);
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}
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