/*
 * Copyright (C) 2015 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */

/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
   I/O Spreadsheet version: rev 1v1
   I/O Spreadsheet tracker: <rdar://problem/19579177>
   Conversion command: ./tools/csvtopinconfig.py --soc fiji --copyright 2015 --config-column Dir --radar '<rdar://problem/19579177>' <filename>
*/

#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>

static const uint32_t pinconfig_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	CFG_OUT_0 | SLOW_SLEW,						//   0 : ULPI_DIR		-> LAN_PME_MODE_1V8
	CFG_DISABLED | SLOW_SLEW,					//   1 : ULPI_STP		->
	CFG_OUT_0 | SLOW_SLEW,						//   2 : ULPI_NXT		-> LAN_RESET_1V8_L
	CFG_DISABLED | SLOW_SLEW,					//   3 : ULPI_DATA[7]		->
	CFG_IN | SLOW_SLEW,						//   4 : ULPI_DATA[6]		-> LAN_PHY_IRQ_1V8
	CFG_IN | SLOW_SLEW,						//   5 : ULPI_DATA[5]		-> LAN_PME_1V8
	CFG_IN | SLOW_SLEW,						//   6 : ULPI_DATA[4]		-> LAN_HSIC_DEV_RDY
	CFG_DISABLED | SLOW_SLEW,					//   7 : ULPI_CLK		->

/* Port  1 */
	CFG_OUT_0 | SLOW_SLEW,						//   8 : ULPI_DATA[3]		-> SOC2WLB_DEVICE_WAKE_R
	CFG_OUT_0 | SLOW_SLEW,						//   9 : ULPI_DATA[2]		-> SOC2WLB_THROTTLE_R
	CFG_IN | SLOW_SLEW,						//  10 : ULPI_DATA[1]		-> WLB2PMU_HOST_WAKE_R
	CFG_OUT_0 | SLOW_SLEW,						//  11 : ULPI_DATA[0]		-> SOC2BTB_BTWAKE_R
	CFG_DISABLED | SLOW_SLEW,					//  12 : SPI1_SCLK		->
	CFG_DISABLED | SLOW_SLEW,					//  13 : SPI1_MOSI		->
	CFG_DISABLED | SLOW_SLEW,					//  14 : SPI1_MISO		->
	CFG_DISABLED | SLOW_SLEW,					//  15 : SPI1_SSIN		->

/* Port  2 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  3 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  4 */
	CFG_IN | SLOW_SLEW,						//  32 : GPIO[11]		-> AP_BUTTON1_L
	CFG_IN | SLOW_SLEW,						//  33 : GPIO[12]		-> AP_BUTTON2_L
	CFG_FUNC0 | SLOW_SLEW,						//  34 : I2S3_MCK		-> AP_TDM3_MCLK
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				//  35 : I2S3_LRCK		-> AP_TDM3_FSYNC
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				//  36 : I2S3_BCLK		-> AP_TDM3_BCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  37 : I2S3_DOUT		-> AP_TDM3_DOUT
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  38 : I2S3_DIN		-> AP_TDM3_DIN
	CFG_DISABLED | SLOW_SLEW,					//  39 : CLK32K_OUT		->

/* Port  5 */
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		//  40 : PCIE_CLKREQ0_N		-> PCIE0_WLA2SOC_CLKREQ_R_L
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		//  41 : PCIE_CLKREQ1_N		-> PCIE1_WLB2SOC_CLKREQ_R_L
	CFG_DISABLED | SLOW_SLEW,					//  42 : NAND_SYS_CLK		->
	CFG_OUT_0 | SLOW_SLEW,						//  43 : GPIO[0]		-> SOC2WLA_DEVICE_WAKE_R
	CFG_OUT_0 | SLOW_SLEW | INPUT_SCHMITT,				//  44 : GPIO[1]		-> SOC2WLA_THROTTLE_R
	CFG_DISABLED | SLOW_SLEW,					//  45 : GPIO[2]		->
	CFG_DISABLED | SLOW_SLEW,					//  46 : GPIO[3]		->
	CFG_OUT_1 | SLOW_SLEW,						//  47 : GPIO[4]		-> CODEC_RESET_L

/* Port  6 */
	CFG_OUT_1 | SLOW_SLEW,						//  48 : GPIO[5]		-> DEV_TUX_AUX_EN
	CFG_OUT_1 | SLOW_SLEW,						//  49 : GPIO[6]		-> DEV_TUX_SYNC_L
	CFG_OUT_0 | SLOW_SLEW,						//  50 : GPIO[7]		-> DEV_TUX_EN
	CFG_DISABLED | SLOW_SLEW,					//  51 : GPIO[14]		->
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  52 : GPIO[16]		-> AP_BOARD_ID_3
	CFG_DISABLED | SLOW_SLEW,					//  53 : GPIO[17]		->
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  54 : GPIO[18]		-> AP_BOARD_CFG_0
	CFG_DISABLED | SLOW_SLEW | INPUT_SCHMITT,			//  55 : GPIO[20]		->

/* Port  7 */
	CFG_OUT_1 | SLOW_SLEW,						//  56 : GPIO[21]		-> AP_TS_RST_L
	CFG_DISABLED | SLOW_SLEW | INPUT_SCHMITT,			//  57 : UART5_RTXD		->
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				//  58 : UART8_TXD		-> AP_UART8_SOC2MCU
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		//  59 : UART8_RXD		-> AP_UART8_MCU2SOC
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  60 : SPI0_SCLK		-> AP_BOARD_ID_0
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  61 : SPI0_MOSI		-> AP_BOARD_ID_1
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  62 : SPI0_MISO		-> AP_BOARD_ID_2
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  63 : SPI0_SSIN		->

/* Port  8 */
	CFG_FUNC0 | FAST_SLEW | INPUT_SCHMITT,				//  64 : I2C2_SDA		-> I2C2_SDA
	CFG_FUNC0 | FAST_SLEW | INPUT_SCHMITT,				//  65 : I2C2_SCL		-> I2C2_SCL
	CFG_IN | SLOW_SLEW | INPUT_SCHMITT,				//  66 : GPIO[22]		-> AP_TRIG_MYSELF
	CFG_OUT_1 | SLOW_SLEW | INPUT_SCHMITT,				//  67 : GPIO[23]		-> NITRO_MCA_BUF_EN_L
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  68 : GPIO[25]		-> AP_BOARD_CFG_1
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  69 : GPIO[28]		-> AP_BOARD_CFG_2
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  70 : GPIO[29]		-> AP_BOARD_ID_4
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  71 : GPIO[34]		-> AP_BOARD_REV_3

/* Port  9 */
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  72 : GPIO[35]		-> AP_BOARD_REV_2
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  73 : GPIO[36]		-> AP_BOARD_REV_1
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  74 : GPIO[37]		-> AP_BOARD_REV_0
	CFG_IN | SLOW_SLEW | INPUT_SCHMITT,				//  75 : GPIO[39]		-> PCIE0_SOC2WLA_RESET_R_L
	CFG_OUT_0 | SLOW_SLEW,						//  76 : GPIO[42]		-> AP_LED_SEL
	CFG_IN | SLOW_SLEW | INPUT_SCHMITT,				//  77 : GPIO[43]		-> PCIE1_SOC2WLB_RESET_R_L
	CFG_DISABLED | SLOW_SLEW,					//  78 : DISP_VSYNC		->
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				//  79 : UART0_TXD		-> AP_UART0_SOC2USR

/* Port 10 */
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		//  80 : UART0_RXD		-> AP_UART0_USR2SOC
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  81 : TMR32_PWM0		-> WLA2SOC_TIME_SYNC_R
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  82 : TMR32_PWM1		-> WLB2SOC_TIME_SYNC_R
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  83 : TMR32_PWM2		-> AP_LED_PWM
	CFG_OUT_0 | SLOW_SLEW,						//  84 : UART6_TXD		-> PLL_S0
	CFG_OUT_0 | SLOW_SLEW,						//  85 : UART6_RXD		-> PLL_S1
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		//  86 : I2C3_SDA		-> I2C3_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		//  87 : I2C3_SCL		-> I2C3_SCL

/* Port 11 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 12 */
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				//  96 : I2C0_SDA		-> I2C0_SDA
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				//  97 : I2C0_SCL		-> I2C0_SCL
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  98 : GPIO[38]		->
	CFG_FUNC0 | PULL_UP | FAST_SLEW,				//  99 : UART2_TXD		-> AP_UART2_SOC2BTB
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 100 : UART2_RXD		-> AP_UART2_BTB2SOC
	CFG_FUNC0 | SLOW_SLEW,						// 101 : UART2_RTSN		-> AP_UART2_SOC2BTB_RTS_L
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 102 : UART2_CTSN		-> AP_UART2_BTB2SOC_CTS_L
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | FAST_SLEW,			// 103 : DWI_DO			-> AP_DWI_DAT

/* Port 13 */
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | FAST_SLEW,			// 104 : DWI_CLK		-> AP_DWI_CLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				// 105 : WDOG			-> AP_WDOG
	CFG_IN | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,			// 106 : GPIO[13]		-> PMU_IRQ_L
	CFG_OUT_0 | FAST_SLEW,						// 107 : GPIO[19]		-> SOC2PMU_KEEPACT
	CFG_IN | SLOW_SLEW | INPUT_SCHMITT,				// 108 : GPIO[26]		-> FORCE_DFU
	CFG_OUT_0 | SLOW_SLEW,						// 109 : GPIO[27]		-> DFU_STATUS
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		// 110 : SOCHOT0		-> AP_SOCHOT0_L
	CFG_FUNC0 | PULL_UP | FAST_SLEW | INPUT_SCHMITT,		// 111 : SOCHOT1		-> SOC2PMU_SOCHOT1_L

/* Port 14 */
	CFG_DISABLED,							// 112 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 113 : TST_CLKOUT		->
	CFG_DISABLED | SLOW_SLEW,					// 114 : GPIO[8]		->
	CFG_DISABLED | SLOW_SLEW,					// 115 : GPIO[9]		->
	CFG_DISABLED | SLOW_SLEW,					// 116 : GPIO[10]		->
	CFG_DISABLED | SLOW_SLEW,					// 117 : GPIO[15]		->
	CFG_FUNC0 | PULL_UP | FAST_SLEW,				// 118 : UART4_TXD		-> AP_UART4_SOC2WLB
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 119 : UART4_RXD		-> AP_UART4_WLB2SOC

/* Port 15 */
	CFG_FUNC0 | SLOW_SLEW,						// 120 : UART4_RTSN		-> AP_UART4_SOC2WLB_RTS_L
	CFG_FUNC0 | SLOW_SLEW,						// 121 : UART4_CTSN		-> AP_UART4_WLB2SOC_CTS_L
	CFG_DISABLED | SLOW_SLEW,					// 122 : SPI3_MOSI		->
	CFG_DISABLED | SLOW_SLEW,					// 123 : SPI3_MISO		->
	CFG_DISABLED | SLOW_SLEW,					// 124 : SPI3_SCLK		->
	CFG_DISABLED | SLOW_SLEW,					// 125 : SPI3_SSIN		->
	CFG_DISABLED | SLOW_SLEW,					// 126 : GPIO[24]		->
	CFG_DISABLED | SLOW_SLEW,					// 127 : GPIO[30]		->

/* Port 16 */
	CFG_DISABLED | SLOW_SLEW,					// 128 : GPIO[31]		->
	CFG_DISABLED | SLOW_SLEW,					// 129 : GPIO[32]		->
	CFG_DISABLED | SLOW_SLEW,					// 130 : GPIO[33]		->
	CFG_DISABLED | SLOW_SLEW,					// 131 : GPIO[40]		->
	CFG_DISABLED | SLOW_SLEW,					// 132 : GPIO[41]		->
	CFG_FUNC0 | SLOW_SLEW,						// 133 : I2S4_MCK		-> AP_I2S4_MCLK
	CFG_FUNC0 | SLOW_SLEW,						// 134 : I2S4_LRCK		-> AP_I2S4_LRCLK
	CFG_FUNC0 | SLOW_SLEW,						// 135 : I2S4_BCLK		-> AP_I2S4_BCLK

/* Port 17 */
	CFG_FUNC0 | SLOW_SLEW,						// 136 : I2S4_DOUT		-> AP_I2S4_DOUT
	CFG_FUNC0 | SLOW_SLEW,						// 137 : I2S4_DIN		-> AP_I2S4_DIN
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,				// 138 : I2C1_SDA		-> I2C1_SDA
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,				// 139 : I2C1_SCL		-> I2C1_SCL
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 18 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 19 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 20 */
	CFG_FUNC0 | SLOW_SLEW,						// 160 : I2S0_LRCK		-> AP_TDM0_FSYNC
	CFG_FUNC0 | SLOW_SLEW,						// 161 : I2S0_BCLK		-> AP_TDM0_BCLK
	CFG_FUNC0 | SLOW_SLEW,						// 162 : I2S0_DOUT		-> AP_TDM0_DOUT
	CFG_FUNC0 | SLOW_SLEW,						// 163 : I2S0_DIN		-> AP_TDM0_DIN
	CFG_FUNC0 | SLOW_SLEW,						// 164 : I2S1_MCK		-> AP_TDM1_MCLK
	CFG_FUNC0 | SLOW_SLEW,						// 165 : I2S1_LRCK		-> AP_TDM1_FSYNC
	CFG_FUNC0 | SLOW_SLEW,						// 166 : I2S1_BCLK		-> AP_TDM1_BCLK
	CFG_FUNC0 | SLOW_SLEW,						// 167 : I2S1_DOUT		-> AP_TDM1_DOUT

/* Port 21 */
	CFG_FUNC0 | SLOW_SLEW,						// 168 : I2S1_DIN		-> AP_TDM1_DIN
	CFG_FUNC0 | SLOW_SLEW,						// 169 : I2S2_LRCK		-> AP_TDM2_FSYNC
	CFG_FUNC0 | SLOW_SLEW,						// 170 : I2S2_BCLK		-> AP_TDM2_BCLK
	CFG_FUNC0 | SLOW_SLEW,						// 171 : I2S2_DOUT		-> AP_TDM2_DOUT
	CFG_FUNC0 | SLOW_SLEW,						// 172 : I2S2_DIN		-> AP_TDM2_DIN
	CFG_FUNC0 | PULL_UP | FAST_SLEW,				// 173 : UART1_TXD		-> AP_UART1_SOC2BTA
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 174 : UART1_RXD		-> AP_UART1_BTA2SOC
	CFG_FUNC0 | SLOW_SLEW,						// 175 : UART1_RTSN		-> AP_UART1_SOC2BTA_RTS_L

/* Port 22 */
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 176 : UART1_CTSN		-> AP_UART1_BTA2SOC_CTS_L
	CFG_DISABLED | SLOW_SLEW,					// 177 : EDP_HPD		->
	CFG_FUNC0 | PULL_UP | FAST_SLEW,				// 178 : UART3_TXD		-> AP_UART3_SOC2WLA
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 179 : UART3_RXD		-> AP_UART3_WLA2SOC
	CFG_FUNC0 | SLOW_SLEW,						// 180 : UART3_RTSN		-> AP_UART3_SOC2WLA_RTS_L
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 181 : UART3_CTSN		-> AP_UART3_WLA2SOC_CTS_L
	CFG_FUNC0 | SLOW_SLEW,						// 182 : SPI2_SCLK		-> MCU_SPI2_SCLK
	CFG_FUNC0 | SLOW_SLEW,						// 183 : SPI2_MOSI		-> MCU_SPI2_MOSI

/* Port 23 */
	CFG_FUNC0 | SLOW_SLEW,						// 184 : SPI2_MISO		-> MCU_SPI2_MISO
	CFG_FUNC0 | SLOW_SLEW,						// 185 : SPI2_SSIN		-> MCU_SPI2_CS_L
	CFG_DISABLED | SLOW_SLEW,					// 186 : ISP0_SDA		->
	CFG_DISABLED | SLOW_SLEW,					// 187 : ISP0_SCL		->
	CFG_DISABLED | SLOW_SLEW,					// 188 : ISP1_SDA		->
	CFG_DISABLED | SLOW_SLEW,					// 189 : ISP1_SCL		->
	CFG_DISABLED | SLOW_SLEW,					// 190 : SENSOR0_RST		->
	CFG_DISABLED | SLOW_SLEW,					// 191 : SENSOR0_CLK		->

/* Port 24 */
	CFG_DISABLED | SLOW_SLEW,					// 192 : SENSOR0_XSHUTDOWN	->
	CFG_DISABLED | SLOW_SLEW,					// 193 : SENSOR0_ISTRB		->
	CFG_DISABLED | SLOW_SLEW,					// 194 : ISP_UART0_TXD		->
	CFG_DISABLED | SLOW_SLEW,					// 195 : ISP_UART0_RXD		->
	CFG_DISABLED | SLOW_SLEW,					// 196 : SENSOR1_RST		->
	CFG_DISABLED | SLOW_SLEW,					// 197 : SENSOR1_CLK		->
	CFG_DISABLED | SLOW_SLEW,					// 198 : SENSOR1_XSHUTDOWN	->
	CFG_DISABLED | SLOW_SLEW,					// 199 : SENSOR1_ISTRB		->

/* Port 25 */
	CFG_OUT_0 | FAST_SLEW,						// 200 : UART7_TXD		-> SOC2BTA_BTWAKE_R
	CFG_IN | PULL_DOWN | SLOW_SLEW,					// 201 : UART7_RXD		-> WLA2PMU_HOST_WAKE_R
	CFG_FUNC0 | FAST_SLEW,						// 202 : I2S0_MCK		-> AP_TDM0_MCLK
	CFG_FUNC0 | FAST_SLEW,						// 203 : I2S2_MCK		-> AP_TDM2_MCLK
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
};

static const uint32_t pinconfig_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	CFG_OUT_0 | SLOW_SLEW,						//   0 : ULPI_DIR		-> LAN_PME_MODE_1V8
	CFG_DISABLED | SLOW_SLEW,					//   1 : ULPI_STP		->
	CFG_OUT_0 | SLOW_SLEW,						//   2 : ULPI_NXT		-> LAN_RESET_1V8_L
	CFG_DISABLED | SLOW_SLEW,					//   3 : ULPI_DATA[7]		->
	CFG_IN | SLOW_SLEW,						//   4 : ULPI_DATA[6]		-> LAN_PHY_IRQ_1V8
	CFG_IN | SLOW_SLEW,						//   5 : ULPI_DATA[5]		-> LAN_PME_1V8
	CFG_IN | SLOW_SLEW,						//   6 : ULPI_DATA[4]		-> LAN_HSIC_DEV_RDY
	CFG_DISABLED | SLOW_SLEW,					//   7 : ULPI_CLK		->

/* Port  1 */
	CFG_OUT_0 | SLOW_SLEW,						//   8 : ULPI_DATA[3]		-> SOC2WLB_DEVICE_WAKE_R
	CFG_OUT_0 | SLOW_SLEW,						//   9 : ULPI_DATA[2]		-> SOC2WLB_THROTTLE_R
	CFG_IN | SLOW_SLEW,						//  10 : ULPI_DATA[1]		-> WLB2PMU_HOST_WAKE_R
	CFG_OUT_0 | SLOW_SLEW,						//  11 : ULPI_DATA[0]		-> SOC2BTB_BTWAKE_R
	CFG_DISABLED | SLOW_SLEW,					//  12 : SPI1_SCLK		->
	CFG_DISABLED | SLOW_SLEW,					//  13 : SPI1_MOSI		->
	CFG_DISABLED | SLOW_SLEW,					//  14 : SPI1_MISO		->
	CFG_DISABLED | SLOW_SLEW,					//  15 : SPI1_SSIN		->

/* Port  2 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  3 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  4 */
	CFG_IN | SLOW_SLEW,						//  32 : GPIO[11]		-> AP_BUTTON1_L
	CFG_IN | SLOW_SLEW,						//  33 : GPIO[12]		-> AP_BUTTON2_L
	CFG_FUNC0 | SLOW_SLEW,						//  34 : I2S3_MCK		-> AP_TDM3_MCLK
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				//  35 : I2S3_LRCK		-> AP_TDM3_FSYNC
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				//  36 : I2S3_BCLK		-> AP_TDM3_BCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  37 : I2S3_DOUT		-> AP_TDM3_DOUT
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  38 : I2S3_DIN		-> AP_TDM3_DIN
	CFG_DISABLED | SLOW_SLEW,					//  39 : CLK32K_OUT		->

/* Port  5 */
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,	//  40 : PCIE_CLKREQ0_N		-> PCIE0_WLA2SOC_CLKREQ_R_L
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,	//  41 : PCIE_CLKREQ1_N		-> PCIE1_WLB2SOC_CLKREQ_R_L
	CFG_DISABLED | SLOW_SLEW,					//  42 : NAND_SYS_CLK		->
	CFG_OUT_0 | SLOW_SLEW,						//  43 : GPIO[0]		-> SOC2WLA_DEVICE_WAKE_R
	CFG_OUT_0 | SLOW_SLEW | INPUT_SCHMITT,				//  44 : GPIO[1]		-> SOC2WLA_THROTTLE_R
	CFG_DISABLED | SLOW_SLEW,					//  45 : GPIO[2]		->
	CFG_DISABLED | SLOW_SLEW,					//  46 : GPIO[3]		->
	CFG_OUT_1 | SLOW_SLEW,						//  47 : GPIO[4]		-> CODEC_RESET_L

/* Port  6 */
	CFG_OUT_1 | SLOW_SLEW,						//  48 : GPIO[5]		-> DEV_TUX_AUX_EN
	CFG_OUT_1 | SLOW_SLEW,						//  49 : GPIO[6]		-> DEV_TUX_SYNC_L
	CFG_OUT_0 | SLOW_SLEW,						//  50 : GPIO[7]		-> DEV_TUX_EN
	CFG_DISABLED | SLOW_SLEW,					//  51 : GPIO[14]		->
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  52 : GPIO[16]		-> AP_BOARD_ID_3
	CFG_DISABLED | SLOW_SLEW,					//  53 : GPIO[17]		->
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  54 : GPIO[18]		-> AP_BOARD_CFG_0
	CFG_DISABLED | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//  55 : GPIO[20]		->

/* Port  7 */
	CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW,				//  56 : GPIO[21]		-> AP_TS_RST_L
	CFG_DISABLED | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//  57 : UART5_RTXD		->
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,			//  58 : UART8_TXD		-> AP_UART8_SOC2MCU
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		//  59 : UART8_RXD		-> AP_UART8_MCU2SOC
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  60 : SPI0_SCLK		-> AP_BOARD_ID_0
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  61 : SPI0_MOSI		-> AP_BOARD_ID_1
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  62 : SPI0_MISO		-> AP_BOARD_ID_2
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  63 : SPI0_SSIN		->

/* Port  8 */
	CFG_FUNC0 | DRIVE_X4 | FAST_SLEW | INPUT_SCHMITT,		//  64 : I2C2_SDA		-> I2C2_SDA
	CFG_FUNC0 | DRIVE_X4 | FAST_SLEW | INPUT_SCHMITT,		//  65 : I2C2_SCL		-> I2C2_SCL
	CFG_IN | SLOW_SLEW | INPUT_SCHMITT,				//  66 : GPIO[22]		-> AP_TRIG_MYSELF
	CFG_OUT_1 | SLOW_SLEW | INPUT_SCHMITT,				//  67 : GPIO[23]		-> NITRO_MCA_BUF_EN_L
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  68 : GPIO[25]		-> AP_BOARD_CFG_1
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  69 : GPIO[28]		-> AP_BOARD_CFG_2
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  70 : GPIO[29]		-> AP_BOARD_ID_4
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  71 : GPIO[34]		-> AP_BOARD_REV_3

/* Port  9 */
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  72 : GPIO[35]		-> AP_BOARD_REV_2
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  73 : GPIO[36]		-> AP_BOARD_REV_1
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  74 : GPIO[37]		-> AP_BOARD_REV_0
	CFG_IN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,			//  75 : GPIO[39]		-> PCIE0_SOC2WLA_RESET_R_L
	CFG_OUT_0 | SLOW_SLEW,						//  76 : GPIO[42]		-> AP_LED_SEL
	CFG_IN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,			//  77 : GPIO[43]		-> PCIE1_SOC2WLB_RESET_R_L
	CFG_DISABLED | SLOW_SLEW,					//  78 : DISP_VSYNC		->
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,			//  79 : UART0_TXD		-> AP_UART0_SOC2USR

/* Port 10 */
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		//  80 : UART0_RXD		-> AP_UART0_USR2SOC
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  81 : TMR32_PWM0		-> WLA2SOC_TIME_SYNC_R
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  82 : TMR32_PWM1		-> WLB2SOC_TIME_SYNC_R
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  83 : TMR32_PWM2		-> AP_LED_PWM
	CFG_OUT_0 | SLOW_SLEW,						//  84 : UART6_TXD		-> PLL_S0
	CFG_OUT_0 | SLOW_SLEW,						//  85 : UART6_RXD		-> PLL_S1
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//  86 : I2C3_SDA		-> I2C3_SDA
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//  87 : I2C3_SCL		-> I2C3_SCL

/* Port 11 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 12 */
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//  96 : I2C0_SDA		-> I2C0_SDA
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//  97 : I2C0_SCL		-> I2C0_SCL
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  98 : GPIO[38]		->
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW,			//  99 : UART2_TXD		-> AP_UART2_SOC2BTB
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 100 : UART2_RXD		-> AP_UART2_BTB2SOC
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW,				// 101 : UART2_RTSN		-> AP_UART2_SOC2BTB_RTS_L
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 102 : UART2_CTSN		-> AP_UART2_BTB2SOC_CTS_L
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | FAST_SLEW,			// 103 : DWI_DO			-> AP_DWI_DAT

/* Port 13 */
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | FAST_SLEW,			// 104 : DWI_CLK		-> AP_DWI_CLK
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			// 105 : WDOG			-> AP_WDOG
	CFG_IN | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,			// 106 : GPIO[13]		-> PMU_IRQ_L
	CFG_OUT_0 | FAST_SLEW,						// 107 : GPIO[19]		-> SOC2PMU_KEEPACT
	CFG_IN | SLOW_SLEW | INPUT_SCHMITT,				// 108 : GPIO[26]		-> FORCE_DFU
	CFG_OUT_0 | SLOW_SLEW,						// 109 : GPIO[27]		-> DFU_STATUS
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		// 110 : SOCHOT0		-> AP_SOCHOT0_L
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW | INPUT_SCHMITT,	// 111 : SOCHOT1		-> SOC2PMU_SOCHOT1_L

/* Port 14 */
	CFG_DISABLED,							// 112 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 113 : TST_CLKOUT		->
	CFG_DISABLED | SLOW_SLEW,					// 114 : GPIO[8]		->
	CFG_DISABLED | SLOW_SLEW,					// 115 : GPIO[9]		->
	CFG_DISABLED | SLOW_SLEW,					// 116 : GPIO[10]		->
	CFG_DISABLED | SLOW_SLEW,					// 117 : GPIO[15]		->
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW,			// 118 : UART4_TXD		-> AP_UART4_SOC2WLB
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 119 : UART4_RXD		-> AP_UART4_WLB2SOC

/* Port 15 */
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW,				// 120 : UART4_RTSN		-> AP_UART4_SOC2WLB_RTS_L
	CFG_FUNC0 | SLOW_SLEW,						// 121 : UART4_CTSN		-> AP_UART4_WLB2SOC_CTS_L
	CFG_DISABLED | SLOW_SLEW,					// 122 : SPI3_MOSI		->
	CFG_DISABLED | SLOW_SLEW,					// 123 : SPI3_MISO		->
	CFG_DISABLED | SLOW_SLEW,					// 124 : SPI3_SCLK		->
	CFG_DISABLED | SLOW_SLEW,					// 125 : SPI3_SSIN		->
	CFG_DISABLED | SLOW_SLEW,					// 126 : GPIO[24]		->
	CFG_DISABLED | SLOW_SLEW,					// 127 : GPIO[30]		->

/* Port 16 */
	CFG_DISABLED | SLOW_SLEW,					// 128 : GPIO[31]		->
	CFG_DISABLED | SLOW_SLEW,					// 129 : GPIO[32]		->
	CFG_DISABLED | SLOW_SLEW,					// 130 : GPIO[33]		->
	CFG_DISABLED | SLOW_SLEW,					// 131 : GPIO[40]		->
	CFG_DISABLED | SLOW_SLEW,					// 132 : GPIO[41]		->
	CFG_FUNC0 | SLOW_SLEW,						// 133 : I2S4_MCK		-> AP_I2S4_MCLK
	CFG_FUNC0 | SLOW_SLEW,						// 134 : I2S4_LRCK		-> AP_I2S4_LRCLK
	CFG_FUNC0 | SLOW_SLEW,						// 135 : I2S4_BCLK		-> AP_I2S4_BCLK

/* Port 17 */
	CFG_FUNC0 | SLOW_SLEW,						// 136 : I2S4_DOUT		-> AP_I2S4_DOUT
	CFG_FUNC0 | SLOW_SLEW,						// 137 : I2S4_DIN		-> AP_I2S4_DIN
	CFG_FUNC0 | DRIVE_X4 | FAST_SLEW,				// 138 : I2C1_SDA		-> I2C1_SDA
	CFG_FUNC0 | DRIVE_X4 | FAST_SLEW,				// 139 : I2C1_SCL		-> I2C1_SCL
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 18 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 19 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 20 */
	CFG_FUNC0 | SLOW_SLEW,						// 160 : I2S0_LRCK		-> AP_TDM0_FSYNC
	CFG_FUNC0 | SLOW_SLEW,						// 161 : I2S0_BCLK		-> AP_TDM0_BCLK
	CFG_FUNC0 | SLOW_SLEW,						// 162 : I2S0_DOUT		-> AP_TDM0_DOUT
	CFG_FUNC0 | SLOW_SLEW,						// 163 : I2S0_DIN		-> AP_TDM0_DIN
	CFG_FUNC0 | SLOW_SLEW,						// 164 : I2S1_MCK		-> AP_TDM1_MCLK
	CFG_FUNC0 | SLOW_SLEW,						// 165 : I2S1_LRCK		-> AP_TDM1_FSYNC
	CFG_FUNC0 | SLOW_SLEW,						// 166 : I2S1_BCLK		-> AP_TDM1_BCLK
	CFG_FUNC0 | SLOW_SLEW,						// 167 : I2S1_DOUT		-> AP_TDM1_DOUT

/* Port 21 */
	CFG_FUNC0 | SLOW_SLEW,						// 168 : I2S1_DIN		-> AP_TDM1_DIN
	CFG_FUNC0 | SLOW_SLEW,						// 169 : I2S2_LRCK		-> AP_TDM2_FSYNC
	CFG_FUNC0 | SLOW_SLEW,						// 170 : I2S2_BCLK		-> AP_TDM2_BCLK
	CFG_FUNC0 | SLOW_SLEW,						// 171 : I2S2_DOUT		-> AP_TDM2_DOUT
	CFG_FUNC0 | SLOW_SLEW,						// 172 : I2S2_DIN		-> AP_TDM2_DIN
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW,			// 173 : UART1_TXD		-> AP_UART1_SOC2BTA
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 174 : UART1_RXD		-> AP_UART1_BTA2SOC
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW,				// 175 : UART1_RTSN		-> AP_UART1_SOC2BTA_RTS_L

/* Port 22 */
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 176 : UART1_CTSN		-> AP_UART1_BTA2SOC_CTS_L
	CFG_DISABLED | SLOW_SLEW,					// 177 : EDP_HPD		->
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW,			// 178 : UART3_TXD		-> AP_UART3_SOC2WLA
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 179 : UART3_RXD		-> AP_UART3_WLA2SOC
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW,				// 180 : UART3_RTSN		-> AP_UART3_SOC2WLA_RTS_L
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 181 : UART3_CTSN		-> AP_UART3_WLA2SOC_CTS_L
	CFG_FUNC0 | SLOW_SLEW,						// 182 : SPI2_SCLK		-> MCU_SPI2_SCLK
	CFG_FUNC0 | SLOW_SLEW,						// 183 : SPI2_MOSI		-> MCU_SPI2_MOSI

/* Port 23 */
	CFG_FUNC0 | SLOW_SLEW,						// 184 : SPI2_MISO		-> MCU_SPI2_MISO
	CFG_FUNC0 | SLOW_SLEW,						// 185 : SPI2_SSIN		-> MCU_SPI2_CS_L
	CFG_DISABLED | SLOW_SLEW,					// 186 : ISP0_SDA		->
	CFG_DISABLED | SLOW_SLEW,					// 187 : ISP0_SCL		->
	CFG_DISABLED | SLOW_SLEW,					// 188 : ISP1_SDA		->
	CFG_DISABLED | SLOW_SLEW,					// 189 : ISP1_SCL		->
	CFG_DISABLED | SLOW_SLEW,					// 190 : SENSOR0_RST		->
	CFG_DISABLED | SLOW_SLEW,					// 191 : SENSOR0_CLK		->

/* Port 24 */
	CFG_DISABLED | SLOW_SLEW,					// 192 : SENSOR0_XSHUTDOWN	->
	CFG_DISABLED | SLOW_SLEW,					// 193 : SENSOR0_ISTRB		->
	CFG_DISABLED | SLOW_SLEW,					// 194 : ISP_UART0_TXD		->
	CFG_DISABLED | SLOW_SLEW,					// 195 : ISP_UART0_RXD		->
	CFG_DISABLED | SLOW_SLEW,					// 196 : SENSOR1_RST		->
	CFG_DISABLED | SLOW_SLEW,					// 197 : SENSOR1_CLK		->
	CFG_DISABLED | SLOW_SLEW,					// 198 : SENSOR1_XSHUTDOWN	->
	CFG_DISABLED | SLOW_SLEW,					// 199 : SENSOR1_ISTRB		->

/* Port 25 */
	CFG_OUT_0 | DRIVE_X4 | FAST_SLEW,				// 200 : UART7_TXD		-> SOC2BTA_BTWAKE_R
	CFG_IN | PULL_DOWN | SLOW_SLEW,					// 201 : UART7_RXD		-> WLA2PMU_HOST_WAKE_R
	CFG_FUNC0 | FAST_SLEW,						// 202 : I2S0_MCK		-> AP_TDM0_MCLK
	CFG_FUNC0 | FAST_SLEW,						// 203 : I2S2_MCK		-> AP_TDM2_MCLK
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
};

struct pinconfig_map {
	uint32_t board_id;
	uint32_t board_id_mask;
	const uint32_t *pinconfigs[GPIOC_COUNT];
};

static const struct pinconfig_map cfg_map[] = {
	{ 0, 1, { pinconfig_ap_0 } },
	{ 1, 1, { pinconfig_dev_0 } },
};

const uint32_t * target_get_default_gpio_cfg(uint32_t gpioc)
{
	static const struct pinconfig_map *selected_map = NULL;

	if (selected_map == NULL) {
		uint32_t board_id = platform_get_board_id();
		for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
			if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
				selected_map = &cfg_map[i];
				break;
			}
		}

		if (selected_map == NULL)
			panic("no default pinconfig for board id %u", board_id);
	}

	ASSERT(gpioc < GPIOC_COUNT);
	return selected_map->pinconfigs[gpioc];
}
