/* 
 * Automatically generated by socgen. DO NOT EDIT!
 * 
 * Copyright (c) 2015 Apple Inc. All rights reserved.
 * 
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 * 
 * This document may not be reproduced or transmitted in any form
 * in whole or in part, without the express written permission of
 * Apple inc.
 */

#ifndef SPDS_S8000_C0_TUNABLE_AUSR_CFG_H
#define SPDS_S8000_C0_TUNABLE_AUSR_CFG_H

#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xfc)
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xa0)

#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf000)
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5000)

#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_C0   (0x7eff)
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_C0   (0x18)

#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xc0)
#define PCIE_APCIE_PHY_AUSR0_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)

#define PCIE_APCIE_PHY_AUSR0_CFG_DEFAULT_TUNABLES_S8000_C0 \
/* Key = default_tunable_key                                                   */ \
/* Register Macro Identifier    Register Offset Register Size     Tunable Mask Tunable Value */ \
{  /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24,           sizeof(uint32_t), 0xfc,        0xa0          }, \
{  /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34,           sizeof(uint32_t), 0xf000,      0x5000        }, \
{  /* AUSR_CFG_BLK_CFG_COM */   0x40,           sizeof(uint32_t), 0x7eff,      0x18          }, \
{  /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44,           sizeof(uint32_t), 0xc0,        0x40          }, \
{                               -1,             -1,               -1,          -1            }

#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xfc)
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xa0)

#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf000)
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5000)

#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_C0   (0x7eff)
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_C0   (0x18)

#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xc0)
#define PCIE_APCIE_PHY_AUSR1_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)

#define PCIE_APCIE_PHY_AUSR1_CFG_DEFAULT_TUNABLES_S8000_C0 \
/* Key = default_tunable_key                                                   */ \
/* Register Macro Identifier    Register Offset Register Size     Tunable Mask Tunable Value */ \
{  /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24,           sizeof(uint32_t), 0xfc,        0xa0          }, \
{  /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34,           sizeof(uint32_t), 0xf000,      0x5000        }, \
{  /* AUSR_CFG_BLK_CFG_COM */   0x40,           sizeof(uint32_t), 0x7eff,      0x18          }, \
{  /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44,           sizeof(uint32_t), 0xc0,        0x40          }, \
{                               -1,             -1,               -1,          -1            }

#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xfc)
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xa0)

#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf000)
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5000)

#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_C0   (0x7eff)
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_C0   (0x18)

#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xc0)
#define PCIE_APCIE_PHY_AUSR2_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)

#define PCIE_APCIE_PHY_AUSR2_CFG_DEFAULT_TUNABLES_S8000_C0 \
/* Key = default_tunable_key                                                   */ \
/* Register Macro Identifier    Register Offset Register Size     Tunable Mask Tunable Value */ \
{  /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24,           sizeof(uint32_t), 0xfc,        0xa0          }, \
{  /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34,           sizeof(uint32_t), 0xf000,      0x5000        }, \
{  /* AUSR_CFG_BLK_CFG_COM */   0x40,           sizeof(uint32_t), 0x7eff,      0x18          }, \
{  /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44,           sizeof(uint32_t), 0xc0,        0x40          }, \
{                               -1,             -1,               -1,          -1            }

#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xfc)
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xa0)

#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf000)
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5000)

#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_C0   (0x7eff)
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_C0   (0x18)

#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xc0)
#define PCIE_APCIE_PHY_AUSR3_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)

#define PCIE_APCIE_PHY_AUSR3_CFG_DEFAULT_TUNABLES_S8000_C0 \
/* Key = default_tunable_key                                                   */ \
/* Register Macro Identifier    Register Offset Register Size     Tunable Mask Tunable Value */ \
{  /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24,           sizeof(uint32_t), 0xfc,        0xa0          }, \
{  /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34,           sizeof(uint32_t), 0xf000,      0x5000        }, \
{  /* AUSR_CFG_BLK_CFG_COM */   0x40,           sizeof(uint32_t), 0x7eff,      0x18          }, \
{  /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44,           sizeof(uint32_t), 0xc0,        0x40          }, \
{                               -1,             -1,               -1,          -1            }

#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xfc)
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG1W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0xa0)

#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xf000)
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG5W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x5000)

#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_UMASK_S8000_C0   (0x7eff)
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG_COM_DEFAULT_TUNABLE_VALUE_S8000_C0   (0x18)

#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_UMASK_S8000_C0 (0xc0)
#define PCIE_APCIE_PHY_AUSR4_CFG_BLK_CFG6W_CDR_DEFAULT_TUNABLE_VALUE_S8000_C0 (0x40)

#define PCIE_APCIE_PHY_AUSR4_CFG_DEFAULT_TUNABLES_S8000_C0 \
/* Key = default_tunable_key                                                   */ \
/* Register Macro Identifier    Register Offset Register Size     Tunable Mask Tunable Value */ \
{  /* AUSR_CFG_BLK_CFG1W_CDR */ 0x24,           sizeof(uint32_t), 0xfc,        0xa0          }, \
{  /* AUSR_CFG_BLK_CFG5W_CDR */ 0x34,           sizeof(uint32_t), 0xf000,      0x5000        }, \
{  /* AUSR_CFG_BLK_CFG_COM */   0x40,           sizeof(uint32_t), 0x7eff,      0x18          }, \
{  /* AUSR_CFG_BLK_CFG6W_CDR */ 0x44,           sizeof(uint32_t), 0xc0,        0x40          }, \
{                               -1,             -1,               -1,          -1            }

#endif /* SPDS_S8000_C0_TUNABLE_AUSR_CFG_H */