/*
 * Copyright (C) 2011-2014 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */

/* Default iPhone5b (iPhone5,3/4) SoC Pin Configuration */

#if PIN_CFG_AP
#define HI_DRIVE_STR    DRIVE_X4
#elif PIN_CFG_DEV
#define HI_DRIVE_STR    DRIVE_X6
#endif

#define	BB_UART_DRIVE_STR	DRIVE_X2
#define	BT_UART_DRIVE_STR	DRIVE_X2
#define	DOCK_UART_DRIVE_STR	DRIVE_X2
#define	SWI_UART_DRIVE_STR	DRIVE_X1
#define	WIFI_UART_DRIVE_STR	DRIVE_X2
#define	FMI_LO_SPEED_DRIVE_STR	(DRIVE_X2 | SLOW_SLEW)
#define	FMI_HI_SPEED_DRIVE_STR	(DRIVE_X2 | SLOW_SLEW)
#define	GRAPE_IO_DRIVE_STR	DRIVE_X1
#define	GRAPE_CLK_DRIVE_STR	DRIVE_X2
#define	DWI_DRIVE_STR		DRIVE_X2
#define	I2C_DRIVE_STR		DRIVE_X1
#define	I2S_DRIVE_STR		DRIVE_X2
#define	CAM_I2C_DRIVE_STR	DRIVE_X1
#define	CAM_STROBE_DRIVE_STR	DRIVE_X1
#define	CAM_CLK_DRIVE_STR	DRIVE_X2

#define DISABLE_OPTIONAL_SIGNALS (1)

#if PIN_CFG_AP
static const uint32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#elif PIN_CFG_DEV
static const uint32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#endif
/* Port  0 */
	CFG_IN,								// GPIO0		-> BUTTON_TO_AP_MENU_KEY_BUFF_L (REQUEST_DFU2)
	CFG_IN,								// GPIO1		-> BUTTON_TO_AP_HOLD_KEY_BUFF_L (REQUEST_DFU1)
	CFG_IN | PULL_UP,						// GPIO2		-> BUTTON_TO_AP_VOL_UP_L
	CFG_IN | PULL_UP,						// GPIO3		-> BUTTON_TO_AP_VOL_DOWN_L
	CFG_IN,								// GPIO4		-> BUTTON_TO_AP_RINGER_A
	CFG_IN | PULL_UP,						// GPIO5		-> SPKAMP_TO_AP_INT_L
	CFG_IN | PULL_UP,						// GPIO6		-> PMU_IRQ_L
	CFG_OUT_0,							// GPIO7		-> AP_TO_BT_WAKE

/* Port  1 */
	CFG_DISABLED | PULL_DOWN,					// GPIO8		-> N/C
	CFG_OUT_0,							// GPIO9		-> AP_TO_APKAMP_BEE_GEES
	CFG_DISABLED | PULL_DOWN,					// GPIO10		-> BB_TO_AP_HSIC1_REMOTE_WAKE
	CFG_DISABLED,							// GPIO11		-> AP_TO_BB_JTAG_TCK
	CFG_DISABLED,							// GPIO12		-> AP_TO_BB_BB_JTAG_TDI
	CFG_IN | PULL_UP,						// GPIO13		-> AP_TO_BB_JTAG_TMS
	CFG_DISABLED | PULL_DOWN,					// GPIO14		-> BB_TO_AP_JTAG_TDO
	CFG_DISABLED | PULL_DOWN,					// GPIO15		-> N/C

/* Port  2 */
	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
	CFG_OUT_0,							// GPIO17		-> AP_TO_BB_HSIC1_RDY
	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
	CFG_OUT_0,							// GPIO19		-> KEEPACT
	CFG_DISABLED,							// EHCI_PORT_PWR[0]	-> BOARD_REV[0]
	CFG_DISABLED,							// EHCI_PORT_PWR[1]	-> BOARD_REV[1]
	CFG_DISABLED,							// EHCI_PORT_PWR[2]	-> BOARD_REV[2]
	CFG_DISABLED,							// EHCI_PORT_PWR[3]	-> BOARD_REV[3]

/* Port  3 */
	CFG_OUT_0 | BB_UART_DRIVE_STR,					// UART1_TXD		-> AP_TO_BB_UART1_TXD
	CFG_FUNC0,							// UART1_RXD		-> AP_TO_BB_UART1_RXD
	CFG_OUT_0 | BB_UART_DRIVE_STR,					// UART1_RTSN		-> AP_TO_BB_UART1_RTS_L
	CFG_FUNC0,							// UART1_CTSN		-> AP_TO_BB_UART1_CTS_L
	CFG_FUNC0 | DOCK_UART_DRIVE_STR,				// UART2_TXD		-> AP_TO_TRISTAR_ACC_UART2_TXD
	CFG_FUNC0,							// UART2_RXD		-> AP_TO_TRISTAR_ACC_UART2_RXD
	CFG_IN | PULL_DOWN,						// UART2_RTSN		-> AP_TO_ACCEL_INT1
	CFG_IN,								// UART2_CTSN		-> AP_TO_TRISTAR_INT

/* Port  4 */
	CFG_FUNC0 | BT_UART_DRIVE_STR,					// UART3_TXD		-> AP_TO_BT_UART3_TXD
	CFG_FUNC0,							// UART3_RXD		-> BT_TO_AP_UART3_RXD
	CFG_OUT_1 | BT_UART_DRIVE_STR,					// UART3_RTSN		-> AP_TO_BT_UART3_RTS_L
	CFG_FUNC0,							// UART3_CTSN		-> BT_TO_AP_UART3_CTS_L
	CFG_FUNC0 | WIFI_UART_DRIVE_STR,				// UART4_TXD/SPI4_MOSI	-> AP_TO_WLAN_UART4_TXD
	CFG_FUNC0,							// UART4_RXD/SPI4_MISO	-> AP_TO_WLAN_UART4_RXD
	CFG_OUT_0,							// UART4_RTSN/SPI4_SCLK	-> AP_TO_CAM0_VDDCORE_EN
	CFG_DISABLED,							// UART4_CTSN/SPI4_SSIN	-> AP_TO_BB_JTAG_TRST_L

/* Port  5 */
	CFG_FUNC0 | DOCK_UART_DRIVE_STR,				// UART6_TXD		-> AP_TO_TRISTAR_DEBUG_UART6_TXD
	CFG_FUNC0,							// UART6_RXD		-> AP_TO_TRISTAR_DEBUG_UART6_RXD
	CFG_OUT_0,							// UART6_RTSN		-> AP_TO_SPKAMP_RESET_L
	CFG_IN | PULL_DOWN,						// UART6_CTSN		-> BB_TO_AP_PP_SYNC
	CFG_FUNC1 | SWI_UART_DRIVE_STR,					// UART5_RXD/UART5_RTXD	-> AP_BI_BATTERY_SWI
	CFG_IN | PULL_DOWN,						// UART5_TXD		-> BB_TO_AP_RESET_DET_L
	CFG_FUNC0 | GRAPE_CLK_DRIVE_STR,				// SPI1_SCLK		-> AP_TO_TOUCH_SPI1_CLK
	CFG_FUNC0 | GRAPE_IO_DRIVE_STR,					// SPI1_MOSI		-> AP_TO_TOUCH_SPI1_MOSI

/* Port  6 */
	CFG_FUNC0,							// SPI1_MISO		-> AP_TO_TOUCH_SPI1_MISO
	CFG_OUT_0 | GRAPE_IO_DRIVE_STR,					// SPI1_SSIN		-> AP_TO_TOUCH_API1_CS_L
	CFG_DISABLED,							// SPI0_SCLK		-> BOARD_ID[0]/SPI0_SCLK
	CFG_DISABLED,							// SPI0_MOSI		-> BOARD_ID[1]/SPI0_MOSI
	CFG_DISABLED,							// SPI0_MISO		-> BOARD_ID[2]/SPI0_MISO
	CFG_DISABLED,							// SPI0_SSIN		-> LCD_TO_AP_PIFA
	CFG_OUT_0,							// SPI2_SCLK		-> AP_TO_WLAN_HSIC2_RDY
	CFG_DISABLED,							// SPI2_MOSI		-> BB_TO_AP_IPC_GPIO

/* Port  7 */
	CFG_OUT_0,							// SPI2_MISO		-> FCAM_TO_AP_ALS_INT_L
	CFG_IN | PULL_DOWN,						// SPI2_SSIN		-> WLAN_TO_AP_HSIC2_RDY
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C0_SDA		-> AP_TO_I2C0_SDA_1V8
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C0_SCL		-> AP_BI_I2C0_SCL_1V8
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C1_SDA		-> AP_TO_I2C1_SDA_1V8
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C1_SCL		-> AP_BI_I2C1_SCL_1V8
	CFG_FUNC0 | CAM_I2C_DRIVE_STR,					// ISP0_SDA		-> AP_BI_CAM_RF_SDA
	CFG_FUNC0 | CAM_I2C_DRIVE_STR,					// ISP0_SCL		-> AP_TO_CAM_RF_SCL

/* Port  8 */
	CFG_FUNC0 | CAM_I2C_DRIVE_STR,					// ISP1_SDA		-> AP_BI_CAM_FF_SDA
	CFG_FUNC0 | CAM_I2C_DRIVE_STR,					// ISP1_SCL		-> AP_TO_CAM_FF_SCL
	CFG_DISABLED | PULL_DOWN,					// MIPI_VSYNC		-> MIPI_VSYNC
	CFG_FUNC0 | PULL_DOWN,						// TMR32_PWM0		-> GYRO_TO_AP_INT2
	CFG_FUNC0,							// TMR32_PWM1		-> VIB_PWM
	CFG_FUNC0,							// TMR32_PWM2		-> 45_AP_TO_TOUCH_CLK32K_RESET_L
	CFG_DISABLED | PULL_DOWN,					// SWI_DATA		-> N/C
	CFG_FUNC0,							// DWI_DI		-> 45_AP_TO_PMU_DWI_DI

/* Port  9 */
	CFG_FUNC0 | DWI_DRIVE_STR,					// DWI_DO		-> 45_AP_TO_PMU_DWI_DO
	CFG_FUNC0 | DWI_DRIVE_STR,					// DWI_CLK		-> 45_AP_TO_PMU_DWI_CLK
	CFG_OUT_0,							// SENSOR0_RST		-> AP_TO_CAM_RF_SHUTDOWN
	CFG_FUNC0 | CAM_CLK_DRIVE_STR,					// SENSOR0_CLK		-> 45_CAM0_CLK_R
	CFG_OUT_0,							// SENSOR1_RST		-> AP_TO_CAM_FF_SHUTDOWN
	CFG_FUNC0 | CAM_CLK_DRIVE_STR,					// SENSOR1_CLK		-> 45_CAM1_CLK_R
	CFG_FUNC0,							// CPU0_SWITCH		-> CPU0_SWITCH
	CFG_FUNC0,							// CPU1_SWITCH		-> CPU1_SWITCH

/* Port 10 */
	CFG_OUT_0,							// ISP0_PRE_FLASH	-> CAM0_TORCH
	CFG_DISABLED | PULL_DOWN,					// ISP0_FLASH		-> N/C
	CFG_DISABLED | PULL_DOWN,					// ISP1_PRE_FLASH	-> N/C
	CFG_DISABLED | PULL_DOWN,					// ISP1_FLASH		-> N/C
	CFG_FUNC0,							// SPI3_MOSI		-> AP_TO_CODEC_SPI3_MOSI
	CFG_FUNC0,							// SPI3_MISO		-> AP_TO_CODEC_SPI3_MISO
	CFG_FUNC0,							// SPI3_SCLK		-> AP_TO_CODEC_SPI3_CLK
	CFG_OUT_1,							// SPI3_SSIN		-> AP_TO_CODEC_SPI3_CS_L

/* Port 11 */
	CFG_FUNC0,							// I2C2_SDA		-> AP_BI_I2C2_SDA
	CFG_FUNC0,							// I2C2_SCL		-> AP_TO_I2C2_SCL
	CFG_OUT_0,							// GPIO_3V0		-> AP_TO_HEADSET_HS3_CONTROL
	CFG_OUT_0,							// GPIO_3V1		-> AP_TO_HEADSET_HS4_CONTROL
	CFG_DISABLED | PULL_DOWN,					// DP_HPD		-> N/C
	CFG_DISABLED | PULL_DOWN,					// LPDP_HPD		-> N/C
	CFG_OUT_1,							// UART0_TXD		-> AP_TO_LEDDRV_EN
	CFG_OUT_0,							// UART0_RXD		-> VIB_LDO_EN

/* Port 12 */
	CFG_DISABLED,							// TST_CLKOUT		-> AP_TO_PMU_TEST_CLKOUT
	CFG_DISABLED,							// TST_STPCLK		-> GND
	CFG_FUNC0,							// WDOG			-> WDOG
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 

/* Port 13 */
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 

/* Port 14 */
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 

/* Port 15 */
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 
	CFG_DISABLED,							// 			-> 

/* Port 16 */
	CFG_FUNC0 | SLOW_SLEW,						// I2S0_MCK		-> AP_TO_CODEC_I2S0_MCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S0_LRCK		-> AP_TO_CODEC_I2S0_LRCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S0_BCLK		-> AP_TO_CODEC_I2S0_BCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S0_DOUT		-> AP_TO_CODEC_I2S0_DOUT
	CFG_FUNC0,							// I2S0_DIN		-> AP_TO_CODEC_I2S0_DIN
	CFG_DISABLED | PULL_DOWN,					// I2S1_MCK		-> N/C
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S1_LRCK		-> AP_TO_BB_I2S1_LRCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S1_BCLK		-> AP_TO_BB_I2S1_BCLK

/* Port 17 */
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S1_DOUT		-> AP_TO_BB_I2S1_DOUT
	CFG_FUNC0,							// I2S1_DIN		-> AP_TO_BB_I2S1_DIN
	CFG_FUNC0 | SLOW_SLEW,						// I2S2_MCK		-> 45_AP_TO_SPKAMP_I2S2_MCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S2_LRCK		-> AP_TO_CODEC_XSP_I2S2_LRCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S2_BCLK		-> 45_AP_TO_CODEC_XSP_I2S2_BCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S2_DOUT		-> AP_TO_CODEC_XSP_I2S2_DOUT
	CFG_FUNC0,							// I2S2_DIN		-> AP_TO_CODEC_XSP_I2S2_DIN
	CFG_DISABLED | PULL_DOWN,					// I2S3_MCK		-> N/C

/* Port 18 */
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S3_LRCK		-> AP_TO_BT_I2S3_BCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S3_BCLK		-> 45_AP_TO_BT_I2S3_LRCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S3_DOUT		-> AP_TO_BT_I2S3_DOUT
	CFG_FUNC0,							// I2S3_DIN		-> AP_TO_BT_I2S3_DIN
	CFG_DISABLED | PULL_DOWN,					// I2S4_MCK		-> N/C
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S4_LRCK		-> AP_TO_CODEC_VSP_I2S2_LRCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S4_BCLK		-> 45_AP_TO_CODEC_VSP_I2S2_BCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S4_DOUT		-> AP_TO_CODEC_VSP_I2S2_DOUT

/* Port 19 */
	CFG_FUNC0,							// I2S4_DIN		-> AP_TO_CODEC_VSP_I2S2_DIN
	CFG_DISABLED | PULL_DOWN,					// SPDIF		-> N/C
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI0_CEN3		->
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI0_CEN2		->
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI0_CEN1		->
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI0_CEN0		-> FMI0_CEN0_L
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI0_CLE		-> FMI0_CLE
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI0_ALE		-> FMI0_ALE

/* Port 20 */
	CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR,				// FMI0_REN		-> FMI0_RE_N
	CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR,				// FMI0_WEN		-> FMI0_WE_L
#if DISABLE_OPTIONAL_SIGNALS
	CFG_DISABLED | PULL_DOWN | FMI_HI_SPEED_DRIVE_STR,		// FMI0_WENN		-> FMI0_RE_P
#else
	CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR,				// FMI0_WENN		-> FMI0_RE_P
#endif
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI0_IO7		-> FMI0_IO[7]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI0_IO6		-> FMI0_IO[6]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI0_IO5		-> FMI0_IO[5]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI0_IO4		-> FMI0_IO[4]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI0_DQS		-> FMI0_DQS_P

/* Port 21 */
#if DISABLE_OPTIONAL_SIGNALS
	CFG_DISABLED | PULL_UP | FMI_HI_SPEED_DRIVE_STR,		// FMI0_DQSN		-> FMI0_DQS_N
#else
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI0_DQSN		-> FMI0_DQS_N
#endif
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI0_IO3		-> FMI0_IO[3]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI0_IO2		-> FMI0_IO[2]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI0_IO1		-> FMI0_IO[1]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI0_IO0		-> FMI0_IO[0]
	CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR,				// FMI0_CEN7		-> 
	CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR,				// FMI0_CEN6		-> 
	CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR,				// FMI0_CEN5		-> 

/* Port 22 */
	CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR,				// FMI0_CEN4		-> 
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI1_CEN3		->
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI1_CEN2		->
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI1_CEN1		->
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI1_CEN0		-> FMI1_CEN0_L
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI1_CLE		-> FMI1_CLE
	CFG_FUNC0 | FMI_LO_SPEED_DRIVE_STR,				// FMI1_ALE		-> FMI1_ALE
	CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR,				// FMI1_REN		-> FMI1_RE_N

/* Port 23 */
	CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR,				// FMI1_WEN		-> FMI1_WE_L
#if DISABLE_OPTIONAL_SIGNALS
	CFG_DISABLED | PULL_DOWN | FMI_HI_SPEED_DRIVE_STR,		// FMI1_WENN		-> FMI1_RE_P
#else
	CFG_FUNC0 | FMI_HI_SPEED_DRIVE_STR,				// FMI1_WENN		-> FMI1_RE_P
#endif
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI1_IO7		-> FMI1_IO[7]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI1_IO6		-> FMI1_IO[6]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI1_IO5		-> FMI1_IO[5]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI1_IO4		-> FMI1_IO[4]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI1_DQS		-> FMI1_DQS_P
#if DISABLE_OPTIONAL_SIGNALS
	CFG_DISABLED | PULL_UP | FMI_HI_SPEED_DRIVE_STR,		// FMI1_DQSN		-> FMI1_DQS_N
#else
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI1_DQSN		-> FMI1_DQS_N
#endif

/* Port 24 */
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI1_IO3		-> FMI1_IO[3]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI1_IO2		-> FMI1_IO[2]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI1_IO1		-> FMI1_IO[1]
	CFG_FUNC0 | BUS_HOLD | FMI_HI_SPEED_DRIVE_STR,			// FMI1_IO0		-> FMI1_IO[0]
	CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR,				// FMI1_CEN7		-> 
	CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR,				// FMI1_CEN6		-> 
	CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR,				// FMI1_CEN5		-> 
	CFG_DISABLED | FMI_LO_SPEED_DRIVE_STR,				// FMI1_CEN4		-> 

/* Port 25 */
	CFG_OUT_0 | PULL_DOWN,						// GPIO20		-> WLAN_HSIC3_RESUME
	CFG_IN | PULL_DOWN,						// GPIO21		-> TOUCH_TO_AP_INT_L
	CFG_OUT_0,							// GPIO22		-> LCD_RESET_L
	CFG_IN,								// GPIO23		-> LCD_HIFA_BSYNC
	CFG_IN,								// GPIO24		-> BB_RESET_L
	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS

/* Port 26 */
	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
	CFG_IN | PULL_UP,						// GPIO30		-> CODEC_INT_L
	CFG_IN | PULL_DOWN,						// GPIO31		-> PBL_RUN_BB_HSIC1_RDY
	CFG_DISABLED,							//			-> 
	CFG_DISABLED,							//			-> 
	CFG_DISABLED,							//			-> 
	CFG_DISABLED,							//			-> 

/* Port 27 */
	CFG_DISABLED,							//			-> 
	CFG_DISABLED,							//			-> 
	CFG_DISABLED,							//			-> 
	CFG_DISABLED,							//			-> 
	CFG_DISABLED,							//			-> 
	CFG_DISABLED,							//			-> 
	CFG_DISABLED,							//			-> 
	CFG_DISABLED,							//			-> 

/* Port 28 */
	CFG_IN,								// GPIO32		-> AP_TO_RADIO_ON_L
	CFG_IN | PULL_DOWN,						// GPIO33		-> GYRO_TO_AP_INT1
	CFG_IN | PULL_UP,						// GPIO34		-> COMPASS_INT_2
	CFG_OUT_0,							// GPIO35		-> AP_TO_BB_WAKE_MODEM
	CFG_IN | PULL_DOWN,						// GPIO36		-> AP_TO_ACCEL_INT2_L
	CFG_DISABLED | PULL_DOWN,					// GPIO37		-> N/C
	CFG_IN | PULL_UP,						// GPIO38		-> ALS_TO_AP_INT_L
	CFG_OUT_0,							// GPIO39		-> AP_TO_TOUCH_GRAPE_RESET
};

#undef HI_DRIVE_STR
#undef BB_UART_DRIVE_STR
#undef BT_UART_DRIVE_STR
#undef DOCK_UART_DRIVE_STR
#undef SWI_UART_DRIVE_STR
#undef WIFI_UART_DRIVE_STR
#undef FMI_LO_SPEED_DRIVE_STR
#undef FMI_HI_SPEED_DRIVE_STR
#undef GRAPE_IO_DRIVE_STR
#undef GRAPE_CLK_DRIVE_STR
#undef DWI_DRIVE_STR
#undef I2C_DRIVE_STR
#undef I2S_DRIVE_STR
#undef CAM_I2C_DRIVE_STR
#undef CAM_STROBE_DRIVE_STR
#undef CAM_CLK_DRIVE_STR
#undef DISABLE_OPTIONAL_SIGNALS
