/*
 * Copyright (C) 2011 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */
#ifndef __PLATFORM_SOC_MIU_H
#define __PLATFORM_SOC_MIU_H

#include <lib/devicetree.h>
#include <platform/soc/hwregbase.h>

#define	rTZSROMCTRL_ROMADDRREMAP		(*(volatile u_int32_t *)(AMC_BASE_ADDR + 0x0904))
#define	rTZSROMCTRL_TZ0REGIONADDR		(*(volatile u_int32_t *)(AMC_BASE_ADDR + 0x0908))
#define	rTZSROMCTRL_TZ1REGIONADDR		(*(volatile u_int32_t *)(AMC_BASE_ADDR + 0x090C))
#define	rTZSROMCTRL_TZ0LOCK			(*(volatile u_int32_t *)(AMC_BASE_ADDR + 0x0910))
#define	rTZSROMCTRL_TZ1LOCK			(*(volatile u_int32_t *)(AMC_BASE_ADDR + 0x0914))


#define ASIO_CLK_CTRL				(0x100004)
#define rASIO_CLK_CTRL				(*(volatile u_int32_t *)(SB_BASE_ADDR + ASIO_CLK_CTRL))
#define ASIO_AKF_IDLE_CTRL			(0xe00024)
#define rASIO_AKF_IDLE_CTRL			(*(volatile u_int32_t *)(SB_BASE_ADDR + ASIO_AKF_IDLE_CTRL))
#define DYN_CLK_GATING				(0x49a0000)
#define rDYN_CLK_GATING				(*(volatile u_int32_t *)(SB_BASE_ADDR + DYN_CLK_GATING))
#define SIO_ASYNC_FIFO_SB_RD_RATE_LIMIT		(0x49c0000)
#define rSIO_ASYNC_FIFO_SB_RD_RATE_LIMIT	(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_RD_RATE_LIMIT))
#define SIO_ASYNC_FIFO_SB_WR_RATE_LIMIT		(0x49c0004)
#define rSIO_ASYNC_FIFO_SB_WR_RATE_LIMIT	(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_WR_RATE_LIMIT))
#define SIO_ASYNC_FIFO_SB_WGATHER		(0x49c0010)
#define rSIO_ASYNC_FIFO_SB_WGATHER		(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_WGATHER))
#define SIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT	(0x49e0000)
#define rSIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT	(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT))
#define SIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT	(0x49e0004)
#define rSIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT	(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT))
#define SIO_DAPASYNC_FIFO_SB_WGATHER		(0x49e0010)
#define rSIO_DAPASYNC_FIFO_SB_WGATHER		(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_WGATHER))
#define AIU_SB_ARBCFG				(0x5010000)
#define rAIU_SB_ARBCFG				(*(volatile u_int32_t *)(SB_BASE_ADDR + AIU_SB_ARBCFG))
#define AIU_SB_CPG_CNTL				(0x5010014)
#define rAIU_SB_CPG_CNTL			(*(volatile u_int32_t *)(SB_BASE_ADDR + AIU_SB_CPG_CNTL))


#define SOCBUSMUX_ARBCFG			(0x0000)
#define rSOCBUSMUX_ARBCFG			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + SOCBUSMUX_ARBCFG))
#define DWRRCFG_DISPMUX_BULK			(0x0008)
#define rDWRRCFG_DISPMUX_BULK			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + DWRRCFG_DISPMUX_BULK))
#define TLIMIT_LVL0_CAMERAMUX			(0x0034)
#define rTLIMIT_LVL0_CAMERAMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL0_CAMERAMUX))
#define TLIMIT_LVL1_CAMERAMUX			(0x0038)
#define rTLIMIT_LVL1_CAMERAMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_CAMERAMUX))
#define TLIMIT_LVL1_MEDIAMUX			(0x0048)
#define rTLIMIT_LVL1_MEDIAMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_MEDIAMUX))
#define TLIMIT_LVL2_MEDIAMUX			(0x004c)
#define rTLIMIT_LVL2_MEDIAMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL2_MEDIAMUX))
#define TLIMIT_LVL0_IOMUX			(0x0054)
#define rTLIMIT_LVL0_IOMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL0_IOMUX))
#define TLIMIT_LVL1_IOMUX			(0x0058)
#define rTLIMIT_LVL1_IOMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_IOMUX))
#define TLIMIT_LVL2_IOMUX			(0x005c)
#define rTLIMIT_LVL2_IOMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL2_IOMUX))
#define TLIMIT_LVL3_IOMUX			(0x0060)
#define rTLIMIT_LVL3_IOMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL3_IOMUX))
#define SOCBUSMUX_CPG_CNTL			(0x0088)
#define rSOCBUSMUX_CPG_CNTL			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + SOCBUSMUX_CPG_CNTL))


#define IOBUSMUX_ARBCFG				(0x0000)
#define rIOBUSMUX_ARBCFG			(*(volatile u_int32_t *)(IOBUSMUX_BASE_ADDR + IOBUSMUX_ARBCFG))
#define IOBUSMUX_CPG_CNTL			(0x001c)
#define rIOBUSMUX_CPG_CNTL			(*(volatile u_int32_t *)(IOBUSMUX_BASE_ADDR + IOBUSMUX_CPG_CNTL))


#define SWITCH_FAB_ARBCFG			(0x0004)
#define	rSWITCH_FAB_ARBCFG			(*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_ARBCFG))
#define	SWITCH_FAB_PIOLIMIT			(0x0028)
#define	rSWITCH_FAB_PIOLIMIT			(*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_PIOLIMIT))
#define	SWITCH_FAB_CPG_CNTL			(0x0074)
#define rSWITCH_FAB_CPG_CNTL			(*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_CPG_CNTL))


#define CP_DYN_CLK_GATING_CTRL			(0x000c)
#define rCP_DYN_CLK_GATING_CTRL			(*(volatile u_int32_t *)(CP_COM_BASE_ADDR + CP_DYN_CLK_GATING_CTRL))


#define CPCOM_INT_NORM_REQUEST			(0x0000)
#define rCP_COM_INT_NORM_REQUEST         (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_REQUEST))
#define CPCOM_INT_NORM_MASK_SET			(0x0004)
#define rCP_COM_INT_NORM_MASK_SET         (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_SET))
#define CPCOM_INT_NORM_MASK_CLR			(0x0008)
#define rCP_COM_INT_NORM_MASK_CLR         (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_CLR))

#define LIO_MEMCACHE_DATASETID_OVERRIDE		(0x1000)


#define MEDIABUSMUX_REGS_ARBCFG			(0x000000)
#define MEDIABUSMUX_REGS_DWRRCFG_JPEG_BULK	(0x000004)
#define MEDIABUSMUX_REGS_DWRRCFG_MSR_BULK	(0x000008)
#define MEDIABUSMUX_REGS_DWRRCFG_VXE_LLT	(0x00000c)
#define MEDIABUSMUX_REGS_DWRRCFG_VXE_BULK	(0x000010)
#define MEDIABUSMUX_REGS_DWRRCFG_VXD_LLT	(0x000014)
#define MEDIABUSMUX_REGS_DWRRCFG_VXD_BULK	(0x000018)
#define MEDIABUSMUX_REGS_CPG_CNTL		(0x00003c)
#define MEDIABUSMUX_REGS_CPG_CNTL		(0x00003c)

#define MSR_REGS_ARBCFG				(0x000000)
#define MSR_REGS_CPG_CNTL			(0x000014)
#define MSR_REGS_AW_TLIMIT			(0x00001c)
#define MSR_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)

#define AJPEG_REGS_ARBCFG			(0x000000)
#define AJPEG_REGS_CPG_CNTL			(0x000014)
#define AJPEG_REGS_MEMCACHE_DATASETID_OVERRIDE  (0x001000)

#define VXE_REGS_ARBCFG				(0x000000)
#define VXE_REGS_CPG_CNTL			(0x000014)
#define VXE_REGS_AR_TLIMIT			(0x000020)
#define VXE_REGS_MEMCACHE_HINT_OVERRIDE		(0x001004)
#define VXE_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)

#define VENC_INT_IDLE_CTRL			(0x030004)
#define VENC_INT_AxCACHE_REMAPPING_REG(_x,_n)	(0x030018 + ((_x) * 8) + ((_n) * 4))

#define VXD_REGS_ARBCFG				(0x000000)
#define VXD_REGS_CPG_CNTL			(0x000014)
#define VXD_REGS_MEMCACHE_HINT_OVERRIDE		(0x001004)
#define VXD_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)

#define VDEC_INT_IDLE_CTRL			(0x030004)
#define VDEC_INT_AxCACHE_REMAPPING_REG(_x,_n)	(0x030018 + ((_x) * 8) + ((_n) * 4))

#define CAMERABUSMUX_REGS_ARBCFG		(0x000000)
#define CAMERABUSMUX_REGS_ISPKF_RT		(0x000004)
#define CAMERABUSMUX_REGS_CPG_CNTL		(0x00002c)

#define ISP_DMA_REGS_ARBCFG			(0x000000)
#define ISP_DMA_REGS_CPG_CNTL			(0x000014)
#define ISP_DMA_REGS_BW_THRESHOLD		(0x000018)
#define ISP_DMA_REGS_AW_LIMIT			(0x00001c)
#define ISP_DMA_REGS_AR_LIMIT			(0x000020)
#define ISP_DMA_REGS_MEMCACHE_DATASETID_OVERRIDE (0x01000)

#define ISP_KF_REGS_ARBCFG			(0x010000)
#define ISP_KF_REGS_CPG_CNTL			(0x010014)
#define ISP_KF_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x011000)

#define DISPBUSMUX_REGS_ARBCFG			(0x000000)
#define DISPBUSMUX_REGS_DWRRCFG_DP1_BULK	(0x000008)
#define DISPBUSMUX_REGS_CPG_CNTL		(0x00001c)

#define DISPLAYPIPE0_REGS_ARBCFG		(0x000000)
#define DISPLAYPIPE0_REGS_CPG_CNTL		(0x000014)
#define DISPLAYPIPE0_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)

#define DISPLAYPIPE1_REGS_ARBCFG		(0x000000)
#define DISPLAYPIPE1_REGS_CPG_CNTL		(0x000014)
#define DISPLAYPIPE1_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)

#define ANS_REGS_ARBCFG				(0x000000)
#define ANS_REGS_CPG_CNTL			(0x000014)
#define ANS_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)
#define ANS_KF_TLIMIT_RD			(0x020008)
#define ANS_KF_TLIMIT_WR			(0x02000c)
#define ANS_ANC0_TLIMIT_RD			(0x030008)
#define ANS_ANC0_TLIMIT_WR			(0x03000c)
#define ANS_ANC1_TLIMIT_RD			(0x031008)
#define ANS_ANC1_TLIMIT_WR			(0x03100c)

#define GFX_REGS_ARBCFG				(0x000000)
#define GFX_REGS_CPG_CNTL			(0x000014)

#define GFX_IMG4_AFUSER_REGS_MCCFG_0	(0x000000)
#define GFX_IMG4_AFUSER_REGS_MCCFG_1	(0x000004)
#define GFX_IMG4_AFUSER_REGS_MCCFG_2	(0x000008)
#define GFX_IMG4_AFUSER_REGS_MCCFG_3	(0x00000C)
#define GFX_IMG4_AFUSER_REGS_MCCFG_4	(0x000010)
#define GFX_IMG4_AFUSER_REGS_MCCFG_5	(0x000014)
#define GFX_IMG4_AFUSER_REGS_MCCFG_6	(0x000018)
#define GFX_IMG4_AFUSER_REGS_MCCFG_7	(0x00001C)
#define GFX_IMG4_AFUSER_REGS_MCCFG_8	(0x000020)
#define GFX_IMG4_AFUSER_REGS_MCCFG_9	(0x000024)
#define GFX_IMG4_AFUSER_REGS_MCCFG_10	(0x000028)
#define GFX_IMG4_AFUSER_REGS_MCCFG_11	(0x00002C)
#define GFX_IMG4_AFUSER_REGS_MCCFG_12	(0x000030)
#define GFX_IMG4_AFUSER_REGS_MCCFG_13	(0x000034)
#define GFX_IMG4_AFUSER_REGS_MCCFG_14	(0x000038)
#define GFX_IMG4_AFUSER_REGS_MCCFG_15	(0x00003C)
#define GFX_IMG4_AFUSER_REGS_MCCFG_16	(0x000040)
#define GFX_IMG4_AFUSER_REGS_MCCFG_17	(0x000044)
#define GFX_IMG4_AFUSER_REGS_MCCFG_18	(0x000048)
#define GFX_IMG4_AFUSER_REGS_MCCFG_19	(0x00004C)
#define GFX_IMG4_AFUSER_REGS_MCCFG_20	(0x000050)
#define GFX_IMG4_AFUSER_REGS_MCCFG_21	(0x000054)
#define GFX_IMG4_AFUSER_REGS_MCCFG_22	(0x000058)
#define GFX_IMG4_AFUSER_REGS_MCCFG_23	(0x00005C)
#define GFX_IMG4_AFUSER_REGS_MCCFG_24	(0x000060)
#define GFX_IMG4_AFUSER_REGS_MCCFG_25	(0x000064)
#define GFX_IMG4_AFUSER_REGS_MCCFG_26	(0x000068)
#define GFX_IMG4_AFUSER_REGS_MCCFG_27	(0x00006C)
#define GFX_IMG4_AFUSER_REGS_MCCFG_28	(0x000070)
#define GFX_IMG4_AFUSER_REGS_MCCFG_29	(0x000074)
#define GFX_IMG4_AFUSER_REGS_MCCFG_30	(0x000078)
#define GFX_IMG4_AFUSER_REGS_MCCFG_31	(0x00007C)

#define AUSB_REGS_RD_RATE_LIMIT			(0x001000)
#define AUSB_REGS_WRALIMIT			(0x001004)
#define AUSB_REGS_WGATHER			(0x001010)


enum remap_select {
  REMAP_SRAM = 0,
  REMAP_SDRAM
};

extern void miu_select_remap(enum remap_select sel);
extern void miu_bypass_prep(void);
extern void miu_update_device_tree(DTNode *pmgr_node);

#endif /* ! __PLATFORM_SOC_MIU_H */
