/*
 * Copyright (C) 2012 - 2013 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */

/* Default iPad4,x SoC Pin Configuration from I/O spreadsheet rev 0.17
   The pin configuration is tracked in the I/O spreadsheet:
   <rdar://problem/12902078> J85: IOSpreadsheet 

   The I/O spreadsheet should be updated before updating the pin configuration */

/* Different drive strength for AP and DEV. */
#if PIN_CFG_AP
#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##ap
#elif PIN_CFG_DEV
#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##dev
#endif

/* Different slew rate for AP and DEV. */
#if PIN_CFG_AP
#define AP_DEV_SLEW(ap, dev) ap##_SLEW
#elif PIN_CFG_DEV
#define AP_DEV_SLEW(ap, dev) dev##_SLEW
#endif

#if TARGET_HAS_BASEBAND
#       define IFF_BB(cfg)  cfg
#else
#       define IFF_BB(cfg)  CFG_DISABLED | PULL_DOWN
#endif


#if PIN_CFG_AP
static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#elif PIN_CFG_DEV
static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#endif

/* Port  0 */
	CFG_DISABLED,								//   0 : TST_CLKOUT		-> SOC_TST_CLKOUT
	CFG_FUNC0 | DRIVE_X1 | FAST_SLEW,					//   1 : WDOG			-> WDOG_SOC
	CFG_IN,									//   2 : GPIO[0]		-> GPIO_BTN_HOME_L
	CFG_IN,									//   3 : GPIO[1]		-> GPIO_BTN_ONOFF_L
	CFG_IN | PULL_UP,							//   4 : GPIO[2]		-> GPIO_BTN_VOL_UP_L
	CFG_IN | PULL_UP,							//   5 : GPIO[3]		-> GPIO_BTN_VOL_DOWN_L
	CFG_IN,									//   6 : GPIO[4]		-> GPIO_BTN_SRL_L
	CFG_DISABLED,								//   7 : GPIO[5]		-> GPIO_SOC2BEACON_EN

/* Port  1 */
	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					//   8 : GPIO[6]		-> GPIO_SOC2AJ_HS4_SHUNT_EN
	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					//   9 : GPIO[7]		-> GPIO_SOC2AJ_HS3_SHUNT_EN
	CFG_DISABLED,								//  10 : GPIO[8]		-> GPIO_BOARD_REV0
	CFG_DISABLED,								//  11 : GPIO[9]		-> GPIO_BOARD_REV1
	CFG_DISABLED,								//  12 : GPIO[10]		-> GPIO_BOARD_REV2
	CFG_IN | PULL_UP,							//  13 : GPIO[11]		-> GPIO_CODEC_IRQ_L
	IFF_BB(CFG_OUT_0) | DRIVE_X1 | FAST_SLEW,				//  14 : GPIO[12]		-> GPIO_SOC2BB_WAKE_MODEM
	CFG_IN | PULL_UP,							//  15 : GPIO[13]		-> GPIO_GRAPE_IRQ_L

/* Port  2 */
	CFG_DISABLED,								//  16 : GPIO[14]		-> BB_IPC_GPIO
	CFG_IN | PULL_UP,							//  17 : GPIO[15]		-> GPIO_ALS_IRQ_L
	CFG_DISABLED,								//  18 : GPIO[16]		-> GPIO_BOARD_ID3
	IFF_BB(CFG_IN | PULL_DOWN),						//  19 : GPIO[17]		-> GPIO_BB2SOC_RESET_DET_L
	CFG_DISABLED,								//  20 : GPIO[18]		-> GPIO_BOOT_CONFIG0
	CFG_IN | PULL_UP,							//  21 : GPIO[19]		-> GPIO_PMU2SOC_IRQ_L
	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					//  22 : GPIO[20]		-> GPIO_SOC2PMU_KEEPACT
	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					//  23 : GPIO[21]		-> GPIO_GRAPE_RST_L

/* Port  3 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  4 */
	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X4) | AP_DEV_SLEW(SLOW, FAST),		//  32 : UART1_TXD		-> UART1_SOC2BT_TX
	CFG_FUNC0,								//  33 : UART1_RXD		-> UART1_BT2SOC_TX
	CFG_OUT_1 | AP_DEV_DRIVE_STR(X1, X4) | AP_DEV_SLEW(SLOW, FAST),		//  34 : UART1_RTSN		-> UART1_SOC2BT_RTS_L
	CFG_FUNC0,								//  35 : UART1_CTSN		-> UART1_BT2SOC_RTS_L
	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X4) | AP_DEV_SLEW(SLOW, FAST),		//  36 : UART2_TXD		-> UART2_SOC2WLAN_TX
	CFG_FUNC0,								//  37 : UART2_RXD		-> UART2_WLAN2SOC_TX
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  5 */
	IFF_BB(CFG_IN) | AP_DEV_DRIVE_STR(X1, X4) | AP_DEV_SLEW(SLOW, FAST),	//  40 : UART3_TXD		-> UART3_SOC2BB_TX
	IFF_BB(CFG_FUNC0),							//  41 : UART3_RXD		-> UART3_BB2SOC_TX
	IFF_BB(CFG_IN) | AP_DEV_DRIVE_STR(X1, X4) | AP_DEV_SLEW(SLOW, FAST),	//  42 : UART3_RTSN		-> UART3_SOC2BB_RTS_L
	IFF_BB(CFG_FUNC0),							//  43 : UART3_CTSN		-> UART3_BB2SOC_RTS_L
	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | FAST_SLEW,			//  44 : UART5_RTXD		-> UART5_BATT_RTXD
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  6 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  7 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  8 */
	CFG_FUNC0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				//  64 : UART4_TXD		-> UART4_SOC2OSCAR_TXD
	CFG_FUNC0,								//  65 : UART4_RXD		-> UART4_OSCAR2SOC_RXD
	CFG_OUT_1 | DRIVE_X1 | FAST_SLEW,					//  66 : UART4_RTSN		-> GPIO_OSCAR_RESET_L
	CFG_IN,									//  67 : UART4_CTSN		-> PMU_GPIO_OSCAR2PMU_HOST_WAKE
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  68 : SPI1_SCLK		-> SPI1_GRAPE_SCLK
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  69 : SPI1_MOSI		-> SPI1_GRAPE_MOSI
	CFG_FUNC0,								//  70 : SPI1_MISO		-> SPI1_GRAPE_MISO
	CFG_OUT_1 | DRIVE_X1 | FAST_SLEW,					//  71 : SPI1_SSIN		-> SPI1_GRAPE_CS_L

/* Port  9 */
	CFG_DISABLED,								//  72 : SPI0_SCLK		-> GPIO_BOARD_ID0
	CFG_DISABLED,								//  73 : SPI0_MOSI		-> GPIO_BOARD_ID1
	CFG_DISABLED,								//  74 : SPI0_MISO		-> GPIO_BOARD_ID2
	CFG_DISABLED,
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  76 : SPI2_SCLK		-> SPI2_CODEC_SCLK
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  77 : SPI2_MOSI		-> SPI2_CODEC_MOSI
	CFG_FUNC0,								//  78 : SPI2_MISO		-> SPI2_CODEC_MISO
	CFG_OUT_1 | DRIVE_X1 | FAST_SLEW,					//  79 : SPI2_SSIN		-> SPI2_CODEC_CS_L

/* Port 10 */
	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | AP_DEV_SLEW(SLOW, FAST),		//  80 : I2C0_SDA		-> I2C0_SDA_1V8
	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | AP_DEV_SLEW(SLOW, FAST),		//  81 : I2C0_SCL		-> I2C0_SCL_1V8
	CFG_DISABLED,								//  82 : I2C1_SDA		-> I2C1_SOC2OSCAR_SWDIO_1V8
	CFG_DISABLED,								//  83 : I2C1_SCL		-> I2C1_SOC2OSCAR_SWDCLK_1V8
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  84 : ISP0_SDA		-> ISP0_CAM_REAR_SDA
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  85 : ISP0_SCL		-> ISP0_CAM_REAR_SCL
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  86 : ISP1_SDA		-> ISP1_CAM_FRONT_SDA
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					//  87 : ISP1_SCL		-> ISP1_CAM_FRONT_SCL

/* Port 11 */
	CFG_OUT_0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				//  88 : SENSOR0_RST		-> ISP0_CAM_REAR_SHUTDOWN_L
	CFG_OUT_0 | DRIVE_X4 | FAST_SLEW,					//  89 : SENSOR0_CLK		-> ISP0_CAM_REAR_CLK_R
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_OUT_0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				//  92 : SENSOR1_RST		-> ISP1_CAM_FRONT_SHUTDOWN_L
	CFG_OUT_0 | DRIVE_X4 | FAST_SLEW,					//  93 : SENSOR1_CLK		-> ISP1_CAM_FRONT_CLK_R
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 12 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 100 : I2C2_SDA		-> I2C2_SDA_1V8
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 101 : I2C2_SCL		-> I2C2_SCL_1V8
	CFG_DISABLED | PULL_DOWN,						// 102 : GPIO[22]		-> GPIO_BB2SOC_GPS_SYNC
	IFF_BB(CFG_IN) | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),			// 103 : GPIO[23]		-> GPIO_SOC2BB_RADIO_ON_L

/* Port 13 */
	CFG_DISABLED,
	CFG_DISABLED,								// 105 : GPIO[25]		-> GPIO_BOOT_CONFIG1
	CFG_IN,									// 106 : GPIO[26]		-> GPIO_FORCE_DFU
	CFG_DISABLED,								// 107 : GPIO[27]		-> TP_GPIO_DFU_STATUS
	CFG_DISABLED,								// 108 : GPIO[28]		-> GPIO_BOOT_CONFIG2
	CFG_DISABLED,								// 109 : GPIO[29]		-> GPIO_BOOT_CONFIG3
	CFG_IN | DRIVE_X1 | FAST_SLEW,						// 110 : GPIO[30]		-> GPIO_SOC2OSCAR_DBGEN
	IFF_BB(CFG_IN) | AP_DEV_SLEW(SLOW, FAST),				// 111 : GPIO[31]		-> GPIO_SOC2BB_RST_L


/* Port 14 */
	IFF_BB(CFG_IN),								// 112 : GPIO[32]		-> GPIO_PROX_IRQ_L
	CFG_DISABLED | PULL_DOWN,						// 113 : GPIO[33]		-> GPIO_BB2SOC_GSM_TXBURST
	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					// 114 : GPIO[34]		-> GPIO_SPKAMP_RST_L
	CFG_OUT_0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				// 115 : GPIO[35]		-> GPIO_BT_WAKE
	CFG_IN,									// 116 : GPIO[36]		-> GPIO_TS2SOC2PMU_INT
	CFG_IN | PULL_UP,							// 117 : GPIO[37]		-> GPIO_SPKAMP_LEFT_IRQ_L
	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					// 118 : GPIO[38]		-> GPIO_SOC2LCD_PWREN
	CFG_OUT_0 | PULL_DOWN,							// 119 : DISP_VSYNC		-> DISPLAY_SYNC

/* Port 15 */
	CFG_FUNC0 | DRIVE_X1 | FAST_SLEW,					// 120 : SOCHOT0		-> SOCHOT0_L
	CFG_FUNC0 | DRIVE_X1 | FAST_SLEW,					// 121 : SOCHOT1		-> SOCHOT1_L
	CFG_FUNC0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				// 122 : UART0_TXD		-> UART0_SOC_TXD
	CFG_FUNC0,								// 123 : UART0_RXD		-> UART0_SOC_RXD
	CFG_DISABLED,
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					// 125 : DWI_DO			-> DWI_AP_DO
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					// 126 : DWI_CLK		-> DWI_AP_CLK
	CFG_DISABLED,

/* Port 16 */
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 128 : I2S0_LRCK		-> I2S0_CODEC_ASP_LRCK
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 129 : I2S0_BCLK		-> I2S0_CODEC_ASP_BCLK
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 130 : I2S0_DOUT		-> I2S0_CODEC_ASP_DOUT
	CFG_FUNC0,								// 131 : I2S0_DIN		-> I2S0_CODEC_ASP_DIN
	CFG_FUNC0 | DRIVE_X4 | FAST_SLEW,					// 132 : I2S1_MCK		-> I2S1_SPKAMP_MCK_R
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 133 : I2S1_LRCK		-> I2S1_SPKAMP_LRCK
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 134 : I2S1_BCLK		-> I2S1_SPKAMP_BCLK
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 135 : I2S1_DOUT		-> I2S1_SPKAMP_DOUT

/* Port 17 */
	CFG_FUNC0,								// 136 : I2S1_DIN		-> I2S1_SPKAMP_DIN
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 137 : I2S2_LRCK		-> I2S2_CODEC_XSP_LRCK
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 138 : I2S2_BCLK		-> I2S2_CODEC_XSP_BCLK
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 139 : I2S2_DOUT		-> I2S2_CODEC_XSP_DOUT
	CFG_FUNC0,								// 140 : I2S2_DIN		-> I2S2_CODEC_XSP_DIN
	CFG_IN | PULL_UP,							// 141 : I2S3_MCK		-> GPIO_SPKAMP_RIGHT_IRQ_L
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 142 : I2S3_LRCK		-> I2S3_SOC2BT_LRCK
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 143 : I2S3_BCLK		-> I2S3_SOC2BT_BCLK

/* Port 18 */
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 144 : I2S3_DOUT		-> I2S3_SOC2BT_DATA
	CFG_FUNC0,								// 145 : I2S3_DIN		-> I2S3_BT2SOC_DATA
	IFF_BB(CFG_DISABLED),							// 146 : I2S4_MCK		-> BB_JTAG_TCK
	IFF_BB(CFG_DISABLED),							// 147 : I2S4_LRCK		-> BB_JTAG_TDI
	IFF_BB(CFG_DISABLED),							// 148 : I2S4_BCLK		-> BB_JTAG_TMS
	IFF_BB(CFG_DISABLED),							// 149 : I2S4_DOUT		-> BB_JTAG_TRST_L
	IFF_BB(CFG_DISABLED),							// 150 : I2S4_DIN		-> BB_JTAG_TDO
	CFG_DISABLED,

/* Port 19 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 20 */
	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					// 160 : TMR32_PWM0		-> OSCAR_TIME_SYNC_HOST_INT
	CFG_OUT_0 | DRIVE_X1 | FAST_SLEW,					// 161 : TMR32_PWM1		-> GPIO_SPKAMP_KEEPALIVE
	CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,					// 162 : TMR32_PWM2		-> CLK_32K_SOC2CUMULUS
	CFG_OUT_0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				// 163 : SIO_7816UART0_SDA	-> HSIC1_SOC2WLAN_HOST_RDY
	CFG_IN,									// 164 : SIO_7816UART0_SCL	-> HSIC1_WLAN2SOC_DEVICE_RDY
	CFG_IN | PULL_DOWN,							// 165 : SIO_7816UART0_RST	-> HSIC1_WLAN2SOC_REMOTE_WAKE
	IFF_BB(CFG_OUT_0) | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),			// 166 : SIO_7816UART1_SDA	-> HSIC2_SOC2BB_HOST_RDY
	IFF_BB(CFG_IN | PULL_DOWN),						// 167 : SIO_7816UART1_SCL	-> HSIC2_BB2SOC_DEVICE_RDY

/* Port 21 */
	IFF_BB(CFG_IN | PULL_DOWN),						// 168 : SIO_7816UART1_RST	-> HSIC2_BB2SOC_REMOTE_WAKE
	CFG_FUNC0 | DRIVE_X1 | AP_DEV_SLEW(SLOW, FAST),				// 169 : UART6_TXD		-> UART6_TS_ACC_TXD
	CFG_FUNC0,								// 170 : UART6_RXD		-> UART6_TS_ACC_RXD
	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | AP_DEV_SLEW(SLOW, FAST),		// 171 : I2C3_SDA		-> I2C3_SDA_1V8
	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X2) | AP_DEV_SLEW(SLOW, FAST),		// 172 : I2C3_SCL		-> I2C3_SCL_1V8
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 22 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 23 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 24 */
	CFG_FUNC0,								// 192 : EDP_HPD		-> EDP_HPD
	CFG_FUNC0 | DRIVE_X4 | FAST_SLEW,					// 193 : I2S0_MCK		-> I2S0_CODEC_ASP_MCK_R
	CFG_DISABLED,
};

#undef AP_DEV_DRIVE_STR
#undef AP_DEV_SLEW
#undef IFF_BB
