/*
 * Copyright (C) YEAR Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */

/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
   I/O Spreadsheet version: rev 0v2
   I/O Spreadsheet tracker: None
   Conversion command: csvtopinconfig.py --soc maui <filename>
*/

#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>

static const uint32_t pinconfig_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	CFG_FUNC0 | SLOW_SLEW,						//   0 : SWD_TMS2		-> SWD_AP_TO_NAND_SWDIO
	CFG_DISABLED | SLOW_SLEW,					//   1 : SWD_TMS3		-> -
	CFG_DISABLED | SLOW_SLEW,					//   2 : UART5_RTXD		-> -
	CFG_IN | SLOW_SLEW,						//   3 : I2S4_MCK		-> TRISTAR_TO_AP_INT
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//   4 : I2S4_BCLK		-> I2S_AP_TO_CODEC_MSP_BCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//   5 : I2S4_LRCK		-> I2S_AP_TO_CODEC_MSP_LRCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//   6 : I2S4_DIN		-> I2S_CODEC_TO_AP_MSP_DIN
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//   7 : I2S4_DOUT		-> I2S_AP_TO_CODEC_MSP_DOUT

/* Port  1 */
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//   8 : I2S2_MCK		-> I2S_AP_TO_SPEAKERAMP_MCLK_R
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//   9 : I2S2_BCLK		-> I2S_AP_TO_CODEC_ASP_BCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  10 : I2S2_LRCK		-> I2S_AP_TO_CODEC_ASP_LRCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  11 : I2S2_DIN		-> I2S_CODEC_TO_AP_ASP_DIN
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  12 : I2S2_DOUT		-> I2S_AP_TO_CODEC_ASP_DOUT
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  13 : SPI1_SCLK		-> SPI_AP_TO_CODEC_SCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  14 : SPI1_MOSI		-> SPI_AP_TO_CODEC_MOSI
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  15 : SPI1_MISO		-> SPI_CODEC_TO_AP_MISO

/* Port  2 */
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  16 : SPI1_SSIN		-> SPI_AP_TO_CODEC_CS_L
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  17 : I2S0_MCK		-> I2S_AP_TO_CODEC_MCLK_R
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  18 : I2S0_BCLK		-> I2S_AP_OWL_TO_CODEC_XSP_BCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  19 : I2S0_LRCK		-> I2S_AP_OWL_TO_CODEC_XSP_LRCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  20 : I2S0_DIN		-> I2S_CODEC_TO_AP_OWL_XSP_DIN
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  21 : I2S0_DOUT		-> I2S_AP_TO_CODEC_XSP_DOUT
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		//  22 : I2C2_SDA		-> I2C2_AP_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		//  23 : I2C2_SCL		-> I2C2_AP_SCL

/* Port  3 */
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				//  24 : UART1_TXD		-> UART_AP_TO_BT_TXD
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		//  25 : UART1_RXD		-> UART_BT_TO_AP_RXD
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  26 : UART1_RTS_L		-> UART_AP_TO_BT_RTS_L
	CFG_FUNC0 | SLOW_SLEW,						//  27 : UART1_CTS_L		-> UART_BT_TO_AP_CTS_L
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				//  28 : UART4_TXD		-> OSCAR_UART2_RXD
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		//  29 : UART4_RXD		-> OSCAR_UART2_TXD
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  30 : UART4_RTS_L		-> -
	CFG_DISABLED | SLOW_SLEW,					//  31 : UART4_CTS_L		-> -

/* Port  4 */
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				//  32 : UART7_TXD		-> OSCAR_UART0_TXD
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				//  33 : UART7_RXD		-> OSCAR_UART0_TXD
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  34 : CLK32K_OUT		-> AP_TO_TOUCH_CLK32K_RESET_L
	CFG_DISABLED | SLOW_SLEW,					//  35 : DP_WAKEUP		-> -
	CFG_DISABLED | SLOW_SLEW,					//  36 : MIPICSI_MUXSEL		-> -
	CFG_FUNC0 | SLOW_SLEW,						//  37 : ISP_I2C1_SDA		-> I2C_ISP_BI_FCAM_SDA
	CFG_FUNC0 | SLOW_SLEW,						//  38 : ISP_I2C1_SCL		-> I2C_ISP_TO_FCAM_SCL
	CFG_FUNC0 | SLOW_SLEW,						//  39 : ISP_I2C0_SDA		-> I2C_ISP_BI_RCAM_SDA

/* Port  5 */
	CFG_FUNC0 | SLOW_SLEW,						//  40 : ISP_I2C0_SCL		-> I2C_ISP_TO_RCAM_SCL
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,	//  41 : SPI2_SCLK		-> DUT_SPI2_SCLK_TOU
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  42 : SPI2_MOSI		-> DUT_SPI2_MOSI_TOU
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  43 : SPI2_MISO		-> DUT_SPI2_MISO_TOU
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				//  44 : SPI2_SSIN		-> SPI_AP_TO_TOUCH_CS_L
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,				//  45 : I2C0_SDA		-> I2C0_AP_SDA
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,				//  46 : I2C0_SCL		-> I2C0_AP_SCL
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,		//  47 : SENSOR0_ISTRB		-> -

/* Port  6 */
	CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//  48 : SENSOR0_RST		-> AP_TO_RCAM_SHUTDOWN
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//  49 : SENSOR0_CLK		-> AP_TO_RCAM_CLK_R
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  50 : SENSOR0_XSHUTDOWN	-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  51 : SENSOR1_ISTRB		-> -
	CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//  52 : SENSOR1_RST		-> AP_TO_FCAM_SHUTDOWN
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//  53 : SENSOR1_CLK		-> AP_TO_FCAM_CLK_R
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  54 : SENSOR1_XSHUTDOWN	-> -
	CFG_DISABLED,

/* Port  7 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  8 */
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  64 : GPIO[0]		-> NC_AP_TO_HP_HS3_CTRL
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  65 : GPIO[1]		-> NC_AP_TO_HP_HS4_CTRL
	CFG_IN | PULL_UP | SLOW_SLEW,					//  66 : GPIO[2]		-> BUTTON_VOL_UP_L
	CFG_IN | PULL_UP | SLOW_SLEW,					//  67 : GPIO[3]		-> BUTTON_VOL_DOWN_L
	CFG_IN | PULL_UP | SLOW_SLEW,					//  68 : GPIO[4]		-> SPEAKERAMP_TO_AP_INT_L
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,				//  69 : GPIO[5]		-> AP_TO_SPEAKERAMP_STAYIN_ALIVE
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,				//  70 : GPIO[6]		-> AP_TO_SPEAKERAMP_RESET_L
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,				//  71 : GPIO[7]		-> -

/* Port  9 */
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,				//  72 : GPIO[8]		-> -
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,				//  73 : GPIO[9]		-> PCIE_AP_TO_WLAN_DEV_WAKE
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,				//  74 : GPIO[10]		-> AP_TO_LED_DRIVER_EN
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,				//  75 : GPIO[11]		-> AP_TO_TOUCH_RESET_L
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,				//  76 : GPIO[12]		-> AP_TO_LCM_RESET_L
	CFG_IN | PULL_UP | SLOW_SLEW,					//  77 : GPIO[13]		-> PMU_TO_AP_IRQ_L
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,				//  78 : GPIO[14]		-> AP_TO_BB_PCIE_DEV_WAKE
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  79 : GPIO[15]		-> -

/* Port 10 */
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  80 : GPIO[16]		-> BOARD_ID3
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  81 : GPIO[17]		-> -
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  82 : GPIO[18]		-> BOOT_CONFIG0
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  83 : I2S1_MCK		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  84 : I2S1_BCLK		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  85 : I2S1_LRCK		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  86 : I2S1_DIN		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  87 : I2S1_DOUT		-> -

/* Port 11 */
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//  88 : UART3_TXD		-> -
	CFG_DISABLED | SLOW_SLEW | INPUT_SCHMITT,			//  89 : UART3_RXD		-> -
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  90 : UART3_RTS_L		-> UART_AP_TO_STOCKHOLM_RTS_L
	CFG_FUNC0 | SLOW_SLEW,						//  91 : UART3_CTS_L		-> UART_STOCKHOLM_TO_AP_CTS_L
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 12 */
	CFG_FUNC0 | SLOW_SLEW,						//  96 : MENU_KEY_L		-> BUTTON_MENU_KEY_L
	CFG_FUNC0 | SLOW_SLEW,						//  97 : HOLD_KEY_L		-> BUTTON_HOLD_KEY_L
	CFG_DISABLED | PULL_DOWN,					//  98 : SKEY_L			-> NC
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		//  99 : SPI3_SCLK		-> SPI_AP_TO_MESA_SCLK_R
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				// 100 : SPI3_MOSI		-> SPI_AP_TO_MESA_MOSI
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		// 101 : SPI3_MISO		-> SPI_MESA_TO_AP_MISO
	CFG_IN | PULL_DOWN | SLOW_SLEW,					// 102 : SPI3_SSIN		-> MESA_TO_AP_INT
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 103 : SPI0_SCLK		-> BOARD_ID0

/* Port 13 */
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 104 : SPI0_MOSI		-> BOARD_ID1
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 105 : SPI0_MISO		-> BOARD_ID2
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,		// 106 : SPI0_SSIN		-> -
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				// 107 : UART0_TXD		-> UART_AP_DEBUG_TXD
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		// 108 : UART0_RXD		-> UART_AP_DEBUG_RXD
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				// 109 : UART6_TXD		-> UART_AP_TO_ACCESSORY_TXD
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		// 110 : UART6_RXD		-> UART_ACCESSORY_TO_AP_RXD
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 111 : TMR32_PWM0		-> OSCAR_BI_AP_TIME_SYNC_HOST_INT

/* Port 14 */
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,				// 112 : TMR32_PWM1		-> AP_TO_VIBE_TRIGGER
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,				// 113 : TMR32_PWM2		-> -
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 114 : I2C1_SDA		-> I2C1_AP_SDA
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 115 : I2C1_SCL		-> I2C1_AP_SCL
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 116 : GPIO[19]		-> -
	CFG_IN | PULL_DOWN | SLOW_SLEW,					// 117 : GPIO[20]		-> LCM_TO_OWL_BSYNC
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 118 : GPIO[21]		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 119 : GPIO[22]		-> -

/* Port 15 */
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 120 : GPIO[23]		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 121 : GPIO[24]		-> -
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 122 : GPIO[25]		-> BOOT_CONFIG1
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 123 : GPIO[26]		-> FORCE_DFU
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				// 124 : PMGR_MOSI		-> DWI_PMGR_TO_PMU_BACKLIGHT_MOSI
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				// 125 : PMGR_MISO		-> DWI_PMU_TO_PMGR_MISO
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				// 126 : PMGR_SCLK0		-> DWI_PMGR_TO_PMU_SCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				// 127 : PMGR_SSCLK1		-> DWI_PMGR_TO_BACKLIGHT_SCLK

/* Port 16 */
	CFG_FUNC0 | SLOW_SLEW,						// 128 : SOCHOT0		-> PMU_TO_AP_SOCHOT0_R_L
	CFG_FUNC0 | SLOW_SLEW,						// 129 : SOCHOT1		-> AP_TO_PMU_SOCHOT1_R_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 130 : EDP_HPD		-> -
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 131 : I2S3_MCK		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		// 132 : I2S3_BCLK		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		// 133 : I2S3_LRCK		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 134 : I2S3_DOUT		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,		// 135 : I2S3_DIN		-> -

/* Port 17 */
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 136 : GPIO[27]		-> DFU_STATUS
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 137 : GPIO[28]		-> BOOT_CONFIG2
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 138 : GPIO[29]		-> BOARD_ID4
	CFG_IN | SLOW_SLEW,						// 139 : GPIO[30]		-> CODEC_TO_AP_PMU_INT_L
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 140 : GPIO[31]		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 141 : GPIO[32]		-> AP_TO_NAND_FW_STRAP
	CFG_IN | PULL_UP | SLOW_SLEW,					// 142 : GPIO[33]		-> TOUCH_TO_AP_INT_L
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 143 : GPIO[34]		-> BOARD_REV3

/* Port 18 */
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 144 : GPIO[35]		-> BOARD_REV2
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 145 : GPIO[36]		-> BOARD_REV1
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				// 146 : GPIO[37]		-> BOARD_REV0
	CFG_DISABLED | SLOW_SLEW,					// 147 : GPIO[38]		-> -
	CFG_DISABLED | SLOW_SLEW,					// 148 : GPIO[39]		-> AP_TO_OSCAR_SWDCLK_1V8
	CFG_IN | SLOW_SLEW,						// 149 : GPIO[40]		-> BUTTON_RINGER_A
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 150 : GPIO[41]		-> AP_BI_OSCAR_SWDIO_1V8
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 151 : GPIO[42]		-> AP_TO_VIBE_EN

/* Port 19 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 20 */
	CFG_FUNC0 | SLOW_SLEW,						// 160 : PCIE_PERST0_L		-> PCIE_AP_TO_NAND_RESET_L
	CFG_FUNC0 | SLOW_SLEW,						// 161 : PCIE_PERST1_L		-> PCIE_AP_TO_WLAN_RESET_L
	CFG_FUNC0 | SLOW_SLEW,						// 162 : PCIE_PERST2_L		-> PCIE_AP_TO_BB_RESET_L
	CFG_FUNC0 | SLOW_SLEW,						// 163 : PCIE_PERST3_L		-> -
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 164 : PCIE_CLKREQ0_L		-> PCIE_NAND_TO_AP_CLKREQ_L
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 165 : PCIE_CLKREQ1_L		-> PCIE_WLAN_TO_AP_CLKREQ_L
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		// 166 : PCIE_CLKREQ2_L		-> PCIE_BB_BI_AP_CLKREQ_L
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 167 : PCIE_CLKREQ3_L		-> -

/* Port 21 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 22 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 23 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 24 */
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				// 192 : UART2_TXD		-> -
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,		// 193 : UART2_RXD		-> -
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				// 194 : UART2_RTS_L		-> -
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				// 195 : UART2_CTS_L		-> -
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				// 196 : NAND_SYS_CLK		-> AP_TO_NAND_SYS_CLK_R
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,				// 197 : S3E_RESET_L		-> AP_TO_NAND_RESET_L
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				// 198 : TST_CLKOUT		-> AP_TO_PMU_TEST_CLKOUT
	CFG_DISABLED,
};

static const uint32_t pinconfig_ap_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//   0 : OWL_SPI_SCLK		-> SPI_OWL_TO_IMU_SCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//   1 : OWL_SPI_MOSI		-> SPI_OWL_TO_IMU_MOSI
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//   2 : OWL_SPI_MISO		-> SPI_IMU_TO_OWL_MISO
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//   3 : OWL_UART1_TXD		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//   4 : OWL_UART1_RXD		-> -
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//   5 : OWL_UART0_TXD		-> -
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//   6 : OWL_UART0_RXD		-> -
	CFG_DISABLED | PULL_UP | SLOW_SLEW,				//   7 : OWL_UART2_TXD		-> -

/* Port  1 */
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//   8 : OWL_UART2_RXD		-> -
	CFG_FUNC0 | SLOW_SLEW,						//   9 : OWL_I2CM_SDA		-> TP_I2C_OWL_SDA
	CFG_FUNC0 | SLOW_SLEW,						//  10 : OWL_I2CM_SCL		-> TP_I2C_OWL_SCL
	CFG_OUT_1 | PULL_UP | SLOW_SLEW,				//  11 : OWL_FUNC[0]		-> SPI_OWL_TO_COMPASS_CS_L
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  12 : OWL_FUNC[1]		-> COMPASS_TO_OWL_INT
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  13 : OWL_FUNC[2]		-> NC
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  14 : OWL_FUNC[3]		-> ACCEL_GYRO_TO_OWL_INT1
	CFG_OUT_1 | PULL_UP | SLOW_SLEW,				//  15 : OWL_FUNC[4]		-> SPI_OWL_TO_ACCEL_GYRO_CS_L

/* Port  2 */
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  16 : OWL_FUNC[5]		-> ACCEL_GYRO_TO_OWL_INT2
	CFG_OUT_1 | PULL_UP | SLOW_SLEW,				//  17 : OWL_FUNC[6]		-> SPI_OWL_TO_PHOSPHOROUS_CS_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  18 : OWL_FUNC[7]		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  19 : OWL_FUNC[8]		-> -
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  20 : OWL_FUNC[9]		-> OWL_LPO_BACKUP_CLK_48M
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  21 : OWL_SWD_TCK_OUT	-> SWD_AP_PERIPHERAL_SWCLK
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  22 : OWL_SWD_TMS0		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  23 : OWL_SWD_TMS1		-> -

/* Port  3 */
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  24 : OWL_I2S_MCK		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  25 : OWL_I2S_BCLK		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  26 : OWL_I2S_LRCK		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  27 : OWL_I2S_DIN		-> -
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
};

static const uint32_t pinconfig_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					//   0 : SWD_TMS2		-> SWD_AP_TO_NAND_SWDIO
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,					//   1 : SWD_TMS3		-> -
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,					//   2 : UART5_RTXD		-> -
	CFG_IN | SLOW_SLEW,							//   3 : I2S4_MCK		-> TRISTAR_TO_AP_INT
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//   4 : I2S4_BCLK		-> I2S_AP_TO_CODEC_MSP_BCLK
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//   5 : I2S4_LRCK		-> I2S_AP_TO_CODEC_MSP_LRCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,			//   6 : I2S4_DIN		-> I2S_CODEC_TO_AP_MSP_DIN
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//   7 : I2S4_DOUT		-> I2S_AP_TO_CODEC_MSP_DOUT

/* Port  1 */
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//   8 : I2S2_MCK		-> I2S_AP_TO_SPEAKERAMP_MCLK_R
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//   9 : I2S2_BCLK		-> I2S_AP_TO_CODEC_ASP_BCLK
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//  10 : I2S2_LRCK		-> I2S_AP_TO_CODEC_ASP_LRCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,			//  11 : I2S2_DIN		-> I2S_CODEC_TO_AP_ASP_DIN
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  12 : I2S2_DOUT		-> I2S_AP_TO_CODEC_ASP_DOUT
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,			//  13 : SPI1_SCLK		-> SPI_AP_TO_CODEC_SCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,					//  14 : SPI1_MOSI		-> SPI_AP_TO_CODEC_MOSI
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,			//  15 : SPI1_MISO		-> SPI_CODEC_TO_AP_MISO

/* Port  2 */
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,					//  16 : SPI1_SSIN		-> SPI_AP_TO_CODEC_CS_L
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//  17 : I2S0_MCK		-> I2S_AP_TO_CODEC_MCLK_R
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//  18 : I2S0_BCLK		-> I2S_AP_OWL_TO_CODEC_XSP_BCLK
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//  19 : I2S0_LRCK		-> I2S_AP_OWL_TO_CODEC_XSP_LRCLK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,			//  20 : I2S0_DIN		-> I2S_CODEC_TO_AP_OWL_XSP_DIN
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  21 : I2S0_DOUT		-> I2S_AP_TO_CODEC_XSP_DOUT
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,			//  22 : I2C2_SDA		-> I2C2_AP_SDA
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,			//  23 : I2C2_SCL		-> I2C2_AP_SCL

/* Port  3 */
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,				//  24 : UART1_TXD		-> UART_AP_TO_BT_TXD
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,			//  25 : UART1_RXD		-> UART_BT_TO_AP_RXD
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  26 : UART1_RTS_L		-> UART_AP_TO_BT_RTS_L
	CFG_FUNC0 | SLOW_SLEW,							//  27 : UART1_CTS_L		-> UART_BT_TO_AP_CTS_L
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,				//  28 : UART4_TXD		-> OSCAR_UART2_RXD
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,			//  29 : UART4_RXD		-> OSCAR_UART2_TXD
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  30 : UART4_RTS_L		-> -
	CFG_DISABLED | SLOW_SLEW,						//  31 : UART4_CTS_L		-> -

/* Port  4 */
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,				//  32 : UART7_TXD		-> OSCAR_UART0_TXD
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,					//  33 : UART7_RXD		-> OSCAR_UART0_TXD
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  34 : CLK32K_OUT		-> AP_TO_TOUCH_CLK32K_RESET_L
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,					//  35 : DP_WAKEUP		-> -
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,					//  36 : MIPICSI_MUXSEL		-> -
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					//  37 : ISP_I2C1_SDA		-> I2C_ISP_BI_FCAM_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					//  38 : ISP_I2C1_SCL		-> I2C_ISP_TO_FCAM_SCL
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					//  39 : ISP_I2C0_SDA		-> I2C_ISP_BI_RCAM_SDA

/* Port  5 */
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					//  40 : ISP_I2C0_SCL		-> I2C_ISP_TO_RCAM_SCL
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		//  41 : SPI2_SCLK		-> SPI_AP_TO_TOUCH_SCLK
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  42 : SPI2_MOSI		-> SPI_AP_TO_TOUCH_MOSI
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,			//  43 : SPI2_MISO		-> SPI_TOUCH_TO_AP_MISO
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,				//  44 : SPI2_SSIN		-> SPI_AP_TO_TOUCH_CS_L
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,			//  45 : I2C0_SDA		-> I2C0_AP_SDA
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,			//  46 : I2C0_SCL		-> I2C0_AP_SCL
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  47 : SENSOR0_ISTRB		-> -

/* Port  6 */
	CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,				//  48 : SENSOR0_RST		-> AP_TO_RCAM_SHUTDOWN
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  49 : SENSOR0_CLK		-> AP_TO_RCAM_CLK_R
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,					//  50 : SENSOR0_XSHUTDOWN	-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  51 : SENSOR1_ISTRB		-> -
	CFG_OUT_0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,				//  52 : SENSOR1_RST		-> AP_TO_FCAM_SHUTDOWN
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  53 : SENSOR1_CLK		-> AP_TO_FCAM_CLK_R
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  54 : SENSOR1_XSHUTDOWN	-> -
	CFG_DISABLED,

/* Port  7 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  8 */
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  64 : GPIO[0]		-> NC_AP_TO_HP_HS3_CTRL
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  65 : GPIO[1]		-> NC_AP_TO_HP_HS4_CTRL
	CFG_IN | PULL_UP | SLOW_SLEW,						//  66 : GPIO[2]		-> BUTTON_VOL_UP_L
	CFG_IN | PULL_UP | SLOW_SLEW,						//  67 : GPIO[3]		-> BUTTON_VOL_DOWN_L
	CFG_IN | PULL_UP | SLOW_SLEW,						//  68 : GPIO[4]		-> SPEAKERAMP_TO_AP_INT_L
	CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  69 : GPIO[5]		-> AP_TO_SPEAKERAMP_STAYIN_ALIVE
	CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  70 : GPIO[6]		-> AP_TO_SPEAKERAMP_RESET_L
	CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  71 : GPIO[7]		-> -

/* Port  9 */
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,					//  72 : GPIO[8]		-> -
	CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  73 : GPIO[9]		-> PCIE_AP_TO_WLAN_DEV_WAKE
	CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  74 : GPIO[10]		-> AP_TO_LED_DRIVER_EN
	CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  75 : GPIO[11]		-> AP_TO_TOUCH_RESET_L
	CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  76 : GPIO[12]		-> AP_TO_LCM_RESET_L
	CFG_IN | PULL_UP | SLOW_SLEW,						//  77 : GPIO[13]		-> PMU_TO_AP_IRQ_L
	CFG_OUT_0 | PULL_DOWN | SLOW_SLEW,					//  78 : GPIO[14]		-> AP_TO_BB_PCIE_DEV_WAKE
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,					//  79 : GPIO[15]		-> -

/* Port 10 */
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					//  80 : GPIO[16]		-> BOARD_ID3
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,					//  81 : GPIO[17]		-> -
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					//  82 : GPIO[18]		-> BOOT_CONFIG0
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  83 : I2S1_MCK		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,	//  84 : I2S1_BCLK		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,	//  85 : I2S1_LRCK		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,			//  86 : I2S1_DIN		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			//  87 : I2S1_DOUT		-> -

/* Port 11 */
	CFG_DISABLED | PULL_UP | DRIVE_X4 | SLOW_SLEW,				//  88 : UART3_TXD		-> -
	CFG_DISABLED | SLOW_SLEW | INPUT_SCHMITT,				//  89 : UART3_RXD		-> -
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				//  90 : UART3_RTS_L		-> UART_AP_TO_STOCKHOLM_RTS_L
	CFG_FUNC0 | SLOW_SLEW,							//  91 : UART3_CTS_L		-> UART_STOCKHOLM_TO_AP_CTS_L
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 12 */
	CFG_FUNC0 | SLOW_SLEW,							//  96 : MENU_KEY_L		-> BUTTON_MENU_KEY_L
	CFG_FUNC0 | SLOW_SLEW,							//  97 : HOLD_KEY_L		-> BUTTON_HOLD_KEY_L
	CFG_DISABLED | PULL_DOWN | DRIVE_X2,					//  98 : SKEY_L			-> -
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		//  99 : SPI3_SCLK		-> SPI_AP_TO_MESA_SCLK_R
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				// 100 : SPI3_MOSI		-> SPI_AP_TO_MESA_MOSI
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,		// 101 : SPI3_MISO		-> SPI_MESA_TO_AP_MISO
	CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,				// 102 : SPI3_SSIN		-> MESA_TO_AP_INT
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					// 103 : SPI0_SCLK		-> BOARD_ID0

/* Port 13 */
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					// 104 : SPI0_MOSI		-> BOARD_ID1
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					// 105 : SPI0_MISO		-> BOARD_ID2
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			// 106 : SPI0_SSIN		-> -
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,				// 107 : UART0_TXD		-> UART_AP_DEBUG_TXD
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,			// 108 : UART0_RXD		-> UART_AP_DEBUG_RXD
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,				// 109 : UART6_TXD		-> UART_AP_TO_ACCESSORY_TXD
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,			// 110 : UART6_RXD		-> UART_ACCESSORY_TO_AP_RXD
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			// 111 : TMR32_PWM0		-> OSCAR_BI_AP_TIME_SYNC_HOST_INT

/* Port 14 */
	CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				// 112 : TMR32_PWM1		-> AP_TO_VIBE_TRIGGER
	CFG_OUT_0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				// 113 : TMR32_PWM2		-> -
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,			// 114 : I2C1_SDA		-> I2C1_AP_SDA
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,			// 115 : I2C1_SCL		-> I2C1_AP_SCL
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			// 116 : GPIO[19]		-> -
	CFG_IN | PULL_DOWN | SLOW_SLEW,						// 117 : GPIO[20]		-> LCM_TO_OWL_BSYNC
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,					// 118 : GPIO[21]		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,					// 119 : GPIO[22]		-> -

/* Port 15 */
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			// 120 : GPIO[23]		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,					// 121 : GPIO[24]		-> -
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					// 122 : GPIO[25]		-> BOOT_CONFIG1
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,					// 123 : GPIO[26]		-> FORCE_DFU
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				// 124 : PMGR_MOSI		-> DWI_PMGR_TO_PMU_BACKLIGHT_MOSI
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,					// 125 : PMGR_MISO		-> DWI_PMU_TO_PMGR_MISO
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				// 126 : PMGR_SCLK0		-> DWI_PMGR_TO_PMU_SCLK
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				// 127 : PMGR_SSCLK1		-> DWI_PMGR_TO_BACKLIGHT_SCLK

/* Port 16 */
	CFG_FUNC0 | SLOW_SLEW,							// 128 : SOCHOT0		-> PMU_TO_AP_SOCHOT0_R_L
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW,					// 129 : SOCHOT1		-> AP_TO_PMU_SOCHOT1_R_L
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			// 130 : EDP_HPD		-> -
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					// 131 : I2S3_MCK		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,	// 132 : I2S3_BCLK		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,	// 133 : I2S3_LRCK		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			// 134 : I2S3_DOUT		-> -
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,			// 135 : I2S3_DIN		-> -

/* Port 17 */
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			// 136 : GPIO[27]		-> DFU_STATUS
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					// 137 : GPIO[28]		-> BOOT_CONFIG2
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					// 138 : GPIO[29]		-> BOARD_ID4
	CFG_IN | SLOW_SLEW,							// 139 : GPIO[30]		-> CODEC_TO_AP_PMU_INT_L
	CFG_DISABLED | PULL_UP | DRIVE_X4 | SLOW_SLEW,				// 140 : GPIO[31]		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			// 141 : GPIO[32]		-> AP_TO_NAND_FW_STRAP
	CFG_IN | PULL_UP | SLOW_SLEW,						// 142 : GPIO[33]		-> TOUCH_TO_AP_INT_L
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					// 143 : GPIO[34]		-> BOARD_REV3

/* Port 18 */
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					// 144 : GPIO[35]		-> BOARD_REV2
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					// 145 : GPIO[36]		-> BOARD_REV1
	CFG_DISABLED | PULL_UP | SLOW_SLEW,					// 146 : GPIO[37]		-> BOARD_REV0
	CFG_DISABLED | SLOW_SLEW,						// 147 : GPIO[38]		-> -
	CFG_DISABLED | DRIVE_X4 | SLOW_SLEW,					// 148 : GPIO[39]		-> AP_TO_OSCAR_SWDCLK_1V8
	CFG_IN | SLOW_SLEW,							// 149 : GPIO[40]		-> BUTTON_RINGER_A
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			// 150 : GPIO[41]		-> AP_BI_OSCAR_SWDIO_1V8
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,			// 151 : GPIO[42]		-> AP_TO_VIBE_EN

/* Port 19 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 20 */
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					// 160 : PCIE_PERST0_L		-> PCIE_AP_TO_NAND_RESET_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					// 161 : PCIE_PERST1_L		-> PCIE_AP_TO_WLAN_RESET_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					// 162 : PCIE_PERST2_L		-> PCIE_AP_TO_BB_RESET_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,					// 163 : PCIE_PERST3_L		-> -
	CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,			// 164 : PCIE_CLKREQ0_L		-> PCIE_NAND_TO_AP_CLKREQ_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,			// 165 : PCIE_CLKREQ1_L		-> PCIE_WLAN_TO_AP_CLKREQ_L
	CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		// 166 : PCIE_CLKREQ2_L		-> PCIE_BB_BI_AP_CLKREQ_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,			// 167 : PCIE_CLKREQ3_L		-> -

/* Port 21 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 22 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 23 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port 24 */
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,				// 192 : UART2_TXD		-> -
	CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,			// 193 : UART2_RXD		-> -
	CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,				// 194 : UART2_RTS_L		-> -
	CFG_FUNC0 | PULL_UP | SLOW_SLEW,					// 195 : UART2_CTS_L		-> -
	CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,				// 196 : NAND_SYS_CLK		-> AP_TO_NAND_SYS_CLK_R
	CFG_FUNC0 | PULL_UP | DRIVE_X2 | SLOW_SLEW,				// 197 : S3E_RESET_L		-> AP_TO_NAND_RESET_L
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,				// 198 : TST_CLKOUT		-> AP_TO_PMU_TEST_CLKOUT
	CFG_DISABLED,
};

static const uint32_t pinconfig_dev_1[GPIO_1_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//   0 : OWL_SPI_SCLK		-> SPI_OWL_TO_IMU_SCLK
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//   1 : OWL_SPI_MOSI		-> SPI_OWL_TO_IMU_MOSI
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//   2 : OWL_SPI_MISO		-> SPI_IMU_TO_OWL_MISO
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//   3 : OWL_UART1_TXD		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//   4 : OWL_UART1_RXD		-> -
	CFG_DISABLED | PULL_UP | DRIVE_X2 | SLOW_SLEW,			//   5 : OWL_UART0_TXD		-> -
	CFG_DISABLED | PULL_UP | DRIVE_X2 | SLOW_SLEW,			//   6 : OWL_UART0_RXD		-> -
	CFG_DISABLED | PULL_UP | DRIVE_X2 | SLOW_SLEW,			//   7 : OWL_UART2_TXD		-> -

/* Port  1 */
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//   8 : OWL_UART2_RXD		-> -
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   9 : OWL_I2CM_SDA		-> TP_I2C_OWL_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  10 : OWL_I2CM_SCL		-> TP_I2C_OWL_SCL
	CFG_OUT_1 | PULL_UP | DRIVE_X2 | SLOW_SLEW,			//  11 : OWL_FUNC[0]		-> SPI_OWL_TO_COMPASS_CS_L
	CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//  12 : OWL_FUNC[1]		-> COMPASS_TO_OWL_INT
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//  13 : OWL_FUNC[2]		-> NC
	CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//  14 : OWL_FUNC[3]		-> ACCEL_GYRO_TO_OWL_INT1
	CFG_OUT_1 | PULL_UP | DRIVE_X2 | SLOW_SLEW,			//  15 : OWL_FUNC[4]		-> SPI_OWL_TO_ACCEL_GYRO_CS_L

/* Port  2 */
	CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//  16 : OWL_FUNC[5]		-> ACCEL_GYRO_TO_OWL_INT2
	CFG_OUT_1 | PULL_UP | DRIVE_X2 | SLOW_SLEW,			//  17 : OWL_FUNC[6]		-> SPI_OWL_TO_PHOSPHOROUS_CS_L
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//  18 : OWL_FUNC[7]		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//  19 : OWL_FUNC[8]		-> -
	CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//  20 : OWL_FUNC[9]		-> OWL_LPO_BACKUP_CLK_48M
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//  21 : OWL_SWD_TCK_OUT	-> SWD_AP_PERIPHERAL_SWCLK
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//  22 : OWL_SWD_TMS0		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//  23 : OWL_SWD_TMS1		-> -

/* Port  3 */
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,		//  24 : OWL_I2S_MCK		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,		//  25 : OWL_I2S_BCLK		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,		//  26 : OWL_I2S_LRCK		-> -
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//  27 : OWL_I2S_DIN		-> -
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
};

struct pinconfig_map {
	uint32_t board_id;
	uint32_t board_id_mask;
	const uint32_t *pinconfigs[GPIOC_COUNT];
};

static const struct pinconfig_map cfg_map[] = {
	{ 0, 1, { pinconfig_ap_0, pinconfig_ap_1 } },
	{ 1, 1, { pinconfig_dev_0, pinconfig_dev_1 } },
};

const uint32_t * target_get_default_gpio_cfg(int gpioc)
{
	static const struct pinconfig_map *selected_map = NULL;

	if (selected_map == NULL) {
		uint32_t board_id = platform_get_board_id();
		for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
			if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
				selected_map = &cfg_map[i];
				break;
			}
		}

		if (selected_map == NULL)
			panic("no default pinconfig for board id %u", board_id);
	}

	ASSERT(gpioc < GPIOC_COUNT);
	return selected_map->pinconfigs[gpioc];
}
