/*
 * Copyright (C) 2015 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */

/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
   I/O Spreadsheet version: rev 4.3.0
   I/O Spreadsheet tracker: 19473089
   Conversion command: csvtopinconfig.py --soc capri --prefix evt2 --config-column 'j99:J99 Config' --config-column 'j98:J98 Config' --pupd-column 'j99:J99 PU/PD' --pupd-column 'j98:J98 PU/PD' --copyright 2015 --radar 19473089 <filename>
*/

#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>
#include <target/boardid.h>

static const uint32_t pinconfig_evt2_j98ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	CFG_IN,								//   0 : MENU_KEY_L		-> GPIO_BTN_HOME_L
	CFG_IN,								//   1 : HOLD_KEY_L		-> GPIO_BTN_ONOFF_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   2 : ISP0_SDA		-> ISP_CAM_REAR_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   3 : ISP0_SCL		-> ISP_CAM_REAR_SCL
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   4 : ISP1_SDA		-> ISP_CAM_FRONT_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   5 : ISP1_SCL		-> ISP_CAM_FRONT_SCL
	CFG_OUT_0 | SLOW_SLEW,						//   6 : SENSOR0_RST		-> ISP_CAM_REAR_SHUTDOWN_L
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//   7 : SENSOR0_CLK		-> ISP_CAM_REAR_CLK_R

/* Port  1 */
	CFG_IN | PULL_UP,						//   8 : SENSOR0_XSHUTDOWN	-> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
	CFG_IN | PULL_UP,						//   9 : SENSOR0_ISTRB		-> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
	CFG_OUT_0 | SLOW_SLEW,						//  10 : SENSOR1_RST		-> ISP_CAM_FRONT_SHUTDOWN_L
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//  11 : SENSOR1_CLK		-> ISP_CAM_FRONT_CLK_R
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  12 : SENSOR1_XSHUTDOWN	-> GPIO_SOC2ROTTERDAM_EN
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  13 : SENSOR1_ISTRB		-> GPIO_SOC2ROTTERDAM_DWLD_REQ
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  14 : UART3_TXD		-> UART_SOC2BB_TX
	CFG_DISABLED | PULL_DOWN,					//  15 : UART3_RXD		-> UART_BB2SOC_TX

/* Port  2 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  3 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  4 */
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  32 : UART3_RTSN		-> UART_SOC2BB_RTS_L
	CFG_DISABLED | PULL_DOWN,					//  33 : UART3_CTSN		-> UART_BB2SOC_RTS_L
	CFG_FUNC0 | SLOW_SLEW,						//  34 : UART5_RTXD		-> UART_BATT_HDQ
	CFG_FUNC0 | SLOW_SLEW,						//  35 : DWI0_DO		-> DWI_SOC2PMU_DO
	CFG_FUNC0 | SLOW_SLEW,						//  36 : DWI0_CLK		-> DWI_SOC2PMU_CLK
	CFG_FUNC0 | SLOW_SLEW,						//  37 : I2C0_SDA		-> I2C0_SDA_1V8
	CFG_FUNC0 | SLOW_SLEW,						//  38 : I2C0_SCL		-> I2C0_SCL_1V8
	CFG_FUNC0 | SLOW_SLEW,						//  39 : I2S0_LRCK		-> I2S_SOC2CODEC_ASP_LRCK

/* Port  5 */
	CFG_FUNC0 | SLOW_SLEW,						//  40 : I2S0_BCLK		-> I2S_SOC2CODEC_ASP_BCLK
	CFG_FUNC0 | SLOW_SLEW,						//  41 : I2S0_DOUT		-> I2S_SOC2CODEC_ASP_DOUT
	CFG_FUNC0,							//  42 : I2S0_DIN		-> I2S_CODEC2SOC_ASP_DOUT
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,				//  43 : I2S1_MCK		-> SWD_KONA_CLK
	CFG_FUNC0 | SLOW_SLEW,						//  44 : I2S1_LRCK		-> I2S_SOC2CODEC_XSP_LRCK
	CFG_FUNC0 | SLOW_SLEW,						//  45 : I2S1_BCLK		-> I2S_SOC2CODEC_XSP_BCLK
	CFG_FUNC0 | SLOW_SLEW,						//  46 : I2S1_DOUT		-> I2S_SOC2CODEC_XSP_DOUT
	CFG_FUNC0,							//  47 : I2S1_DIN		-> I2S_CODEC2SOC_XSP_DOUT

/* Port  6 */
	CFG_FUNC0 | SLOW_SLEW,						//  48 : SPI3_MOSI		-> SPI_CODEC_MOSI
	CFG_FUNC0,							//  49 : SPI3_MISO		-> SPI_CODEC_MISO
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				//  50 : SPI3_SCLK		-> SPI_CODEC_SCLK_R
	CFG_OUT_1 | SLOW_SLEW,						//  51 : SPI3_SSIN		-> SPI_CODEC_CS_L
	CFG_OUT_0 | SLOW_SLEW,						//  52 : TMR32_PWM0		-> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//  53 : TMR32_PWM1		-> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
	CFG_IN,								//  54 : TMR32_PWM2		-> GPUUVD2SOC_OUT_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  55 : DISP_VSYNC		-> ORIONMCU_SWDIO_1V8

/* Port  7 */
	CFG_FUNC0 | SLOW_SLEW,						//  56 : WDOG			-> WDOG_SOC
	CFG_FUNC0,							//  57 : SOCHOT0		-> SOCHOT0_L
	CFG_FUNC0 | SLOW_SLEW,						//  58 : SOCHOT1		-> SOCHOT1_L
	CFG_DISABLED,							//  59 : CPU_SLEEP_STATUS	-> NC
	CFG_DISABLED | SLOW_SLEW,					//  60 : TST_CLKOUT		-> SOC_TST_CLKOUT
	CFG_IN | PULL_UP,						//  61 : ISP_UART0_TXD		-> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
	CFG_IN | PULL_UP,						//  62 : ISP_UART0_RXD		-> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  63 : UART7_TXD		-> UART_SOC2OSCAR_TX

/* Port  8 */
	CFG_FUNC0,							//  64 : UART7_RXD		-> UART_OSCAR2SOC_TX
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  65 : I2C1_SDA		-> I2C1_SDA_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  66 : I2C1_SCL		-> I2C1_SCL_1V8
	CFG_DISABLED,							//  67 : SPI0_SCLK		-> GPIO_BRD_ID0
	CFG_DISABLED,							//  68 : SPI0_MOSI		-> GPIO_BRD_ID1
	CFG_DISABLED,							//  69 : SPI0_MISO		-> GPIO_BRD_ID2
	CFG_IN,								//  70 : SPI0_SSIN		-> GPIO_TS2ORIONSOC2PMU_IRQ
	CFG_FUNC0 | SLOW_SLEW,						//  71 : I2S3_MCK		-> I2S_SOC2SPKRAMP_FH_MCK_R

/* Port  9 */
	CFG_FUNC0 | SLOW_SLEW,						//  72 : I2S3_LRCK		-> I2S_SOC2SPKRAMP_FH_LRCK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  73 : I2S3_BCLK		-> I2S_SOC2SPKRAMP_FH_BCLK
	CFG_FUNC0 | SLOW_SLEW,						//  74 : I2S3_DOUT		-> I2S_SOC2SPKRAMP_FH_DOUT
	CFG_FUNC0,							//  75 : I2S3_DIN		-> I2S_SPKRAMP2SOC_FH_DOUT
	CFG_IN | PULL_UP | SLOW_SLEW,					//  76 : UART4_TXD		-> UART_SOC2ROTTERDAM_TX
	CFG_FUNC0,							//  77 : UART4_RXD		-> UART_ROTTERDAM2SOC_TX
	CFG_IN | PULL_UP | SLOW_SLEW,					//  78 : UART4_RTSN		-> UART_SOC2ROTTERDAM_RTS_L
	CFG_FUNC0,							//  79 : UART4_CTSN		-> UART_ROTTERDAM2SOC_RTS_L

/* Port 10 */
	CFG_OUT_0 | SLOW_SLEW,						//  80 : GPIO[0]		-> GPIO_SOC2GPUUVD_EN
	CFG_OUT_1 | SLOW_SLEW,						//  81 : GPIO[1]		-> GPIO_SOC2TT_XBAR_EN_PULSE_L
	CFG_OUT_0 | SLOW_SLEW,						//  82 : GPIO[2]		-> GPIO_SOC2GRAPE_RESET_L
	CFG_IN,								//  83 : GPIO[3]		-> GPIO_TS2SOC2PMU_IRQ
	CFG_IN | PULL_UP,						//  84 : GPIO[4]		-> GPIO_GRAPE2SOC_IRQ_L
	CFG_OUT_1 | SLOW_SLEW,						//  85 : GPIO[5]		-> GPIO_SOC2TT_XBAR_DIS_PULSE_L
	CFG_IN | PULL_UP,						//  86 : GPIO[6]		-> GPIO_PMU2SOC_IRQ_L
	CFG_OUT_0 | SLOW_SLEW,						//  87 : GPIO[7]		-> GPIO_SOC2PMU_KEEPACT

/* Port 11 */
	CFG_IN,								//  88 : GPIO[8]		-> GPIO_GANGES2SOC2PMU_IRQ_L
	CFG_DISABLED,							//  89 : GPIO[9]		-> GPIO_TT2SOC_WAKE_L
	CFG_DISABLED,							//  90 : GPIO[10]		-> GPIO_SOC2CODEC_RESET_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  91 : GPIO[11]		-> GPIO_BB_IPC
	CFG_IN | PULL_UP,						//  92 : GPIO[12]		-> GPIO_BTN_VOL_UP_L
	CFG_IN | PULL_UP,						//  93 : GPIO[13]		-> GPIO_BTN_VOL_DOWN_L
	CFG_OUT_0 | SLOW_SLEW,						//  94 : GPIO[14]		-> GPIO_SOC2TT_SW_EN
	CFG_OUT_0 | SLOW_SLEW,						//  95 : GPIO[15]		-> GPIO_SOC2GRAPE_EXT_SW_ON

/* Port 12 */
	CFG_DISABLED,							//  96 : GPIO[16]		-> GPIO_BRD_ID3
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  97 : GPIO[17]		-> GPIO_SOC2BB_COREDUMP
	CFG_DISABLED,							//  98 : GPIO[18]		-> GPIO_BOOT_CFG0
	CFG_OUT_0 | SLOW_SLEW,						//  99 : GPIO[19]		-> GPIO_SOC2TT_LDO_EN
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 100 : GPIO[20]		-> GPIO_SOC2BB_WAKE_MODEM
	CFG_OUT_0 | SLOW_SLEW,						// 101 : GPIO[21]		-> GPIO_SOC2SPKRAMP_KEEPALIVE
	CFG_DISABLED | PULL_DOWN,					// 102 : GPIO[22]		-> GPIO_BB2SOC_GPS_SYNC
	CFG_IN | PULL_UP,						// 103 : GPIO[23]		-> GPIO_HP_ALS2SOC_IRQ_L

/* Port 13 */
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 104 : GPIO[24]		-> GPIO_SOC2BB_RADIO_ON_L
	CFG_DISABLED,							// 105 : GPIO[25]		-> GPIO_BOOT_CFG1
	CFG_IN,								// 106 : GPIO[26]		-> GPIO_FORCE_DFU
	CFG_DISABLED,							// 107 : GPIO[27]		-> TP_GPIO_DFU_STATUS
	CFG_DISABLED,							// 108 : GPIO[28]		-> GPIO_BOOT_CFG2
	CFG_DISABLED,							// 109 : GPIO[29]		-> GPIO_TT2SOC_SMI_L
	CFG_IN | PULL_UP,						// 110 : GPIO[30]		-> GPIO_RC_ALS2SOC_IRQ_L
	CFG_DISABLED,							// 111 : GPIO[31]		-> GPIO_BOOT_CFG3

/* Port 14 */
	CFG_IN,								// 112 : GPIO[32]		-> GPIO_OSCAR2PMU_HOST_WAKE
	CFG_DISABLED | PULL_DOWN,					// 113 : GPIO[33]		-> HSIC_BB2SOC_DEVICE_RDY
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 114 : GPIO[34]		-> HSIC_SOC2BB_HOST_RDY
	CFG_DISABLED | PULL_DOWN,					// 115 : GPIO[35]		-> GPIO_BB2SOC_RESET_DET_L
	CFG_IN | PULL_UP,						// 116 : GPIO[36]		-> GPIO_CODEC2SOC_IRQ_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 117 : GPIO[37]		-> GPIO_SOC2BB_RESET_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		// 118 : SPI2_SCLK		-> SPI_MESA_SCLK_R
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 119 : SPI2_MOSI		-> SPI_MESA_MOSI

/* Port 15 */
	CFG_FUNC0,							// 120 : SPI2_MISO		-> SPI_MESA_MISO
	CFG_IN | PULL_DOWN,						// 121 : SPI2_SSIN		-> GPIO_MESA2SOC_IRQ
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 122 : UART8_TXD		-> SOC2USBPDMCU_SWCLK
	CFG_DISABLED,							// 123 : UART8_RXD		-> SOC2USBPDMCU_SWDIO
	CFG_DISABLED,							// 124 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 125 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 126 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 127 : UNSPECIFIED		-> UNSPECIFIED

/* Port 16 */
	CFG_FUNC0 | SLOW_SLEW,						// 128 : UART0_TXD		-> UART_SOC2DEBUG_TX
	CFG_FUNC0,							// 129 : UART0_RXD		-> UART_DEBUG2SOC_TX
	CFG_FUNC0 | SLOW_SLEW,						// 130 : UART6_TXD		-> UART_SOC2ACC_TX
	CFG_FUNC0,							// 131 : UART6_RXD		-> UART_ACC2SOC_TX
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 132 : I2C2_SDA		-> I2C2_SDA_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 133 : I2C2_SCL		-> I2C2_SCL_1V8
	CFG_FUNC0 | SLOW_SLEW,						// 134 : I2C3_SDA		-> I2C3_SDA_1V8
	CFG_FUNC0 | SLOW_SLEW,						// 135 : I2C3_SCL		-> I2C3_SCL_1V8

/* Port 17 */
	CFG_FUNC0 | SLOW_SLEW,						// 136 : UART2_TXD		-> UART_SOC2WLAN_TX
	CFG_FUNC0,							// 137 : UART2_RXD		-> UART_WLAN2SOC_TX
	CFG_OUT_1 | SLOW_SLEW,						// 138 : UART2_RTSN		-> UART_SOC2WLAN_RTS_L
	CFG_FUNC0,							// 139 : UART2_CTSN		-> UART_WLAN2SOC_RTS_L
	CFG_FUNC0 | SLOW_SLEW,						// 140 : UART1_TXD		-> UART_SOC2BT_TX
	CFG_FUNC0,							// 141 : UART1_RXD		-> UART_BT2SOC_TX
	CFG_OUT_1 | SLOW_SLEW,						// 142 : UART1_RTSN		-> UART_SOC2BT_RTS_L
	CFG_FUNC0,							// 143 : UART1_CTSN		-> UART_BT2SOC_RTS_L

/* Port 18 */
	CFG_FUNC0,							// 144 : EDP_HPD		-> EDP_HPD
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,				// 145 : I2S4_MCK		-> SWD_KONA_IO
	CFG_FUNC0 | SLOW_SLEW,						// 146 : I2S4_LRCK		-> I2S_SOC2BT_LRCK
	CFG_FUNC0 | SLOW_SLEW,						// 147 : I2S4_BCLK		-> I2S_SOC2BT_BCLK
	CFG_FUNC0 | SLOW_SLEW,						// 148 : I2S4_DOUT		-> I2S_SOC2BT_DOUT
	CFG_FUNC0,							// 149 : I2S4_DIN		-> I2S_BT2SOC_DOUT
	CFG_FUNC0 | SLOW_SLEW,						// 150 : I2S2_LRCK		-> I2S_SOC2SPKRAMP_CN_LRCK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				// 151 : I2S2_BCLK		-> I2S_SOC2SPKRAMP_CN_BCLK

/* Port 19 */
	CFG_FUNC0 | SLOW_SLEW,						// 152 : I2S2_DOUT		-> I2S_SOC2SPKRAMP_CN_DOUT
	CFG_FUNC0,							// 153 : I2S2_DIN		-> I2S_SPKRAMP2SOC_CN_DOUT
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		// 154 : SPI1_SCLK		-> SPI_GRAPE_SCLK_R
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 155 : SPI1_MOSI		-> SPI_GRAPE_MOSI
	CFG_FUNC0,							// 156 : SPI1_MISO		-> SPI_GRAPE_MISO
	CFG_OUT_1 | SLOW_SLEW,						// 157 : SPI1_SSIN		-> SPI_GRAPE_CS_L
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,		// 158 : CLK32K_OUT		-> ORIONMCU_SWCLK_1V8
	CFG_DISABLED,							// 159 : ULPI_DIR		-> GPIO_BRD_REV1

/* Port 20 */
	CFG_OUT_0,							// 160 : ULPI_STP		-> SOC2USBPDMCU_RESET_L
	CFG_DISABLED,							// 161 : ULPI_NXT		-> GPIO_BRD_REV0
	CFG_OUT_0 | SLOW_SLEW,						// 162 : ULPI_DATA[7]		-> GPIO_SOC2AJ_HS3_SHUNT_EN
	CFG_DISABLED,							// 163 : ULPI_DATA[6]		-> GPIO_BRD_REV3
	CFG_OUT_0 | SLOW_SLEW,						// 164 : ULPI_DATA[5]		-> GPIO_SOC2BT_WAKE
	CFG_OUT_0 | SLOW_SLEW,						// 165 : ULPI_DATA[4]		-> GPIO_SOC2WLAN_WAKE
	CFG_OUT_0 | SLOW_SLEW,						// 166 : ULPI_CLK		-> GPIO_SOC2AJ_HS4_SHUNT_EN
	CFG_IN,								// 167 : ULPI_DATA[3]		-> USBPDMCU2SOC_IRQ

/* Port 21 */
	CFG_DISABLED,							// 168 : ULPI_DATA[2]		-> GPIO_BRD_REV2
	CFG_DISABLED,							// 169 : ULPI_DATA[1]		-> SWD_OSCAR_IO_1V8
	CFG_DISABLED,							// 170 : ULPI_DATA[0]		-> SWD_OSCAR_CLK_1V8
	CFG_FUNC0 | SLOW_SLEW,						// 171 : DWI1_DO		-> DWI_SOC2BEACON_DO
	CFG_FUNC0 | SLOW_SLEW,						// 172 : DWI1_CLK		-> DWI_SOC2BEACON_CLK
	CFG_DISABLED | INPUT_SCHMITT,					// 173 : PCIE_CLKREQ0_N		-> PCIE_TT2SOC_CLKREQ_L
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 174 : PCIE_CLKREQ1_N		-> PCIE_WLAN2SOC_CLKREQ_L
	CFG_DISABLED | INPUT_SCHMITT,					// 175 : PCIE_CLKREQ2_N		-> NC_PCIE_DEVBRD2SOC_CLKREQ_L

/* Port 22 */
	CFG_IN,								// 176 : PCIE_CLKREQ3_N		-> GPIO_TT2SOC_PWR_SW_OC
	CFG_DISABLED,							// 177 : NAND_SYS_CLK		-> NC
	CFG_OUT_0 | SLOW_SLEW,						// 178 : PCIE_PERST0_N		-> PCIE_SOC2TT_RESET_L
	CFG_IN | SLOW_SLEW,						// 179 : PCIE_PERST1_N		-> PCIE_SOC2WLAN_RESET_L
	CFG_DISABLED,							// 180 : PCIE_PERST2_N		-> NC_PCIE_SOC2DEVBRD_RESET_L
	CFG_DISABLED,							// 181 : PCIE_PERST3_N		-> GPIO_DEVDOG_DETECT
	CFG_FUNC0 | SLOW_SLEW,						// 182 : I2S0_MCK		-> I2S_SOC2CODEC_ASP_MCK_R
	CFG_FUNC0 | SLOW_SLEW,						// 183 : I2S2_MCK		-> I2S_SOC2SPKRAMP_CN_MCK_R
};

static const uint32_t pinconfig_evt2_j98dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	CFG_IN,								//   0 : MENU_KEY_L		-> GPIO_BTN_HOME_L
	CFG_IN,								//   1 : HOLD_KEY_L		-> GPIO_BTN_ONOFF_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   2 : ISP0_SDA		-> ISP_CAM_REAR_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   3 : ISP0_SCL		-> ISP_CAM_REAR_SCL
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   4 : ISP1_SDA		-> ISP_CAM_FRONT_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   5 : ISP1_SCL		-> ISP_CAM_FRONT_SCL
	CFG_OUT_0 | SLOW_SLEW,						//   6 : SENSOR0_RST		-> ISP_CAM_REAR_SHUTDOWN_L
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//   7 : SENSOR0_CLK		-> ISP_CAM_REAR_CLK_R

/* Port  1 */
	CFG_IN | PULL_UP,						//   8 : SENSOR0_XSHUTDOWN	-> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
	CFG_IN | PULL_UP,						//   9 : SENSOR0_ISTRB		-> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
	CFG_OUT_0 | SLOW_SLEW,						//  10 : SENSOR1_RST		-> ISP_CAM_FRONT_SHUTDOWN_L
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//  11 : SENSOR1_CLK		-> ISP_CAM_FRONT_CLK_R
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  12 : SENSOR1_XSHUTDOWN	-> GPIO_SOC2ROTTERDAM_EN
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  13 : SENSOR1_ISTRB		-> GPIO_SOC2ROTTERDAM_DWLD_REQ
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//  14 : UART3_TXD		-> UART_SOC2BB_TX
	CFG_DISABLED | PULL_DOWN,					//  15 : UART3_RXD		-> UART_BB2SOC_TX

/* Port  2 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  3 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  4 */
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		//  32 : UART3_RTSN		-> UART_SOC2BB_RTS_L
	CFG_DISABLED | PULL_DOWN,					//  33 : UART3_CTSN		-> UART_BB2SOC_RTS_L
	CFG_FUNC0 | SLOW_SLEW,						//  34 : UART5_RTXD		-> UART_BATT_HDQ
	CFG_FUNC0 | SLOW_SLEW,						//  35 : DWI0_DO		-> DWI_SOC2PMU_DO
	CFG_FUNC0 | SLOW_SLEW,						//  36 : DWI0_CLK		-> DWI_SOC2PMU_CLK
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  37 : I2C0_SDA		-> I2C0_SDA_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  38 : I2C0_SCL		-> I2C0_SCL_1V8
	CFG_FUNC0 | SLOW_SLEW,						//  39 : I2S0_LRCK		-> I2S_SOC2CODEC_ASP_LRCK

/* Port  5 */
	CFG_FUNC0 | SLOW_SLEW,						//  40 : I2S0_BCLK		-> I2S_SOC2CODEC_ASP_BCLK
	CFG_FUNC0 | SLOW_SLEW,						//  41 : I2S0_DOUT		-> I2S_SOC2CODEC_ASP_DOUT
	CFG_FUNC0,							//  42 : I2S0_DIN		-> I2S_CODEC2SOC_ASP_DOUT
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,				//  43 : I2S1_MCK		-> SWD_KONA_CLK
	CFG_FUNC0 | SLOW_SLEW,						//  44 : I2S1_LRCK		-> I2S_SOC2CODEC_XSP_LRCK
	CFG_FUNC0 | SLOW_SLEW,						//  45 : I2S1_BCLK		-> I2S_SOC2CODEC_XSP_BCLK
	CFG_FUNC0 | SLOW_SLEW,						//  46 : I2S1_DOUT		-> I2S_SOC2CODEC_XSP_DOUT
	CFG_FUNC0,							//  47 : I2S1_DIN		-> I2S_CODEC2SOC_XSP_DOUT

/* Port  6 */
	CFG_FUNC0 | SLOW_SLEW,						//  48 : SPI3_MOSI		-> SPI_CODEC_MOSI
	CFG_FUNC0,							//  49 : SPI3_MISO		-> SPI_CODEC_MISO
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				//  50 : SPI3_SCLK		-> SPI_CODEC_SCLK_R
	CFG_OUT_1 | SLOW_SLEW,						//  51 : SPI3_SSIN		-> SPI_CODEC_CS_L
	CFG_OUT_0 | SLOW_SLEW,						//  52 : TMR32_PWM0		-> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//  53 : TMR32_PWM1		-> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
	CFG_IN,								//  54 : TMR32_PWM2		-> GPUUVD2SOC_OUT_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  55 : DISP_VSYNC		-> ORIONMCU_SWDIO_1V8

/* Port  7 */
	CFG_FUNC0 | SLOW_SLEW,						//  56 : WDOG			-> WDOG_SOC
	CFG_FUNC0,							//  57 : SOCHOT0		-> SOCHOT0_L
	CFG_FUNC0 | SLOW_SLEW,						//  58 : SOCHOT1		-> SOCHOT1_L
	CFG_DISABLED,							//  59 : CPU_SLEEP_STATUS	-> NC
	CFG_DISABLED | SLOW_SLEW,					//  60 : TST_CLKOUT		-> SOC_TST_CLKOUT
	CFG_IN | PULL_UP,						//  61 : ISP_UART0_TXD		-> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
	CFG_IN | PULL_UP,						//  62 : ISP_UART0_RXD		-> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
	CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//  63 : UART7_TXD		-> UART_SOC2OSCAR_TX

/* Port  8 */
	CFG_FUNC0,							//  64 : UART7_RXD		-> UART_OSCAR2SOC_TX
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  65 : I2C1_SDA		-> I2C1_SDA_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  66 : I2C1_SCL		-> I2C1_SCL_1V8
	CFG_DISABLED,							//  67 : SPI0_SCLK		-> GPIO_BRD_ID0
	CFG_DISABLED,							//  68 : SPI0_MOSI		-> GPIO_BRD_ID1
	CFG_DISABLED,							//  69 : SPI0_MISO		-> GPIO_BRD_ID2
	CFG_IN,								//  70 : SPI0_SSIN		-> GPIO_TS2ORIONSOC2PMU_IRQ
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  71 : I2S3_MCK		-> I2S_SOC2SPKRAMP_FH_MCK_R

/* Port  9 */
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  72 : I2S3_LRCK		-> I2S_SOC2SPKRAMP_FH_LRCK
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//  73 : I2S3_BCLK		-> I2S_SOC2SPKRAMP_FH_BCLK
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  74 : I2S3_DOUT		-> I2S_SOC2SPKRAMP_FH_DOUT
	CFG_FUNC0,							//  75 : I2S3_DIN		-> I2S_SPKRAMP2SOC_FH_DOUT
	CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW,			//  76 : UART4_TXD		-> UART_SOC2ROTTERDAM_TX
	CFG_FUNC0,							//  77 : UART4_RXD		-> UART_ROTTERDAM2SOC_TX
	CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW,			//  78 : UART4_RTSN		-> UART_SOC2ROTTERDAM_RTS_L
	CFG_FUNC0,							//  79 : UART4_CTSN		-> UART_ROTTERDAM2SOC_RTS_L

/* Port 10 */
	CFG_OUT_0 | SLOW_SLEW,						//  80 : GPIO[0]		-> GPIO_SOC2GPUUVD_EN
	CFG_OUT_1 | SLOW_SLEW,						//  81 : GPIO[1]		-> GPIO_SOC2TT_XBAR_EN_PULSE_L
	CFG_OUT_0 | SLOW_SLEW,						//  82 : GPIO[2]		-> GPIO_SOC2GRAPE_RESET_L
	CFG_IN,								//  83 : GPIO[3]		-> GPIO_TS2SOC2PMU_IRQ
	CFG_IN | PULL_UP,						//  84 : GPIO[4]		-> GPIO_GRAPE2SOC_IRQ_L
	CFG_OUT_1 | SLOW_SLEW,						//  85 : GPIO[5]		-> GPIO_SOC2TT_XBAR_DIS_PULSE_L
	CFG_IN | PULL_UP,						//  86 : GPIO[6]		-> GPIO_PMU2SOC_IRQ_L
	CFG_OUT_0 | SLOW_SLEW,						//  87 : GPIO[7]		-> GPIO_SOC2PMU_KEEPACT

/* Port 11 */
	CFG_IN,								//  88 : GPIO[8]		-> GPIO_GANGES2SOC2PMU_IRQ_L
	CFG_DISABLED,							//  89 : GPIO[9]		-> GPIO_TT2SOC_WAKE_L
	CFG_DISABLED,							//  90 : GPIO[10]		-> GPIO_SOC2CODEC_RESET_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  91 : GPIO[11]		-> GPIO_BB_IPC
	CFG_IN | PULL_UP,						//  92 : GPIO[12]		-> GPIO_BTN_VOL_UP_L
	CFG_IN | PULL_UP,						//  93 : GPIO[13]		-> GPIO_BTN_VOL_DOWN_L
	CFG_OUT_0 | SLOW_SLEW,						//  94 : GPIO[14]		-> GPIO_SOC2TT_SW_EN
	CFG_OUT_0 | SLOW_SLEW,						//  95 : GPIO[15]		-> GPIO_SOC2GRAPE_EXT_SW_ON

/* Port 12 */
	CFG_DISABLED,							//  96 : GPIO[16]		-> GPIO_BRD_ID3
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  97 : GPIO[17]		-> GPIO_SOC2BB_COREDUMP
	CFG_DISABLED,							//  98 : GPIO[18]		-> GPIO_BOOT_CFG0
	CFG_OUT_0 | SLOW_SLEW,						//  99 : GPIO[19]		-> GPIO_SOC2TT_LDO_EN
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 100 : GPIO[20]		-> GPIO_SOC2BB_WAKE_MODEM
	CFG_OUT_0 | SLOW_SLEW,						// 101 : GPIO[21]		-> GPIO_SOC2SPKRAMP_KEEPALIVE
	CFG_DISABLED | PULL_DOWN,					// 102 : GPIO[22]		-> GPIO_BB2SOC_GPS_SYNC
	CFG_IN | PULL_UP,						// 103 : GPIO[23]		-> GPIO_HP_ALS2SOC_IRQ_L

/* Port 13 */
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 104 : GPIO[24]		-> GPIO_SOC2BB_RADIO_ON_L
	CFG_DISABLED,							// 105 : GPIO[25]		-> GPIO_BOOT_CFG1
	CFG_IN,								// 106 : GPIO[26]		-> GPIO_FORCE_DFU
	CFG_DISABLED,							// 107 : GPIO[27]		-> TP_GPIO_DFU_STATUS
	CFG_DISABLED,							// 108 : GPIO[28]		-> GPIO_BOOT_CFG2
	CFG_DISABLED,							// 109 : GPIO[29]		-> GPIO_TT2SOC_SMI_L
	CFG_IN | PULL_UP,						// 110 : GPIO[30]		-> GPIO_RC_ALS2SOC_IRQ_L
	CFG_DISABLED,							// 111 : GPIO[31]		-> GPIO_BOOT_CFG3

/* Port 14 */
	CFG_IN,								// 112 : GPIO[32]		-> GPIO_OSCAR2PMU_HOST_WAKE
	CFG_DISABLED | PULL_DOWN,					// 113 : GPIO[33]		-> HSIC_BB2SOC_DEVICE_RDY
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 114 : GPIO[34]		-> HSIC_SOC2BB_HOST_RDY
	CFG_DISABLED | PULL_DOWN,					// 115 : GPIO[35]		-> GPIO_BB2SOC_RESET_DET_L
	CFG_IN | PULL_UP,						// 116 : GPIO[36]		-> GPIO_CODEC2SOC_IRQ_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 117 : GPIO[37]		-> GPIO_SOC2BB_RESET_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		// 118 : SPI2_SCLK		-> SPI_MESA_SCLK_R
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 119 : SPI2_MOSI		-> SPI_MESA_MOSI

/* Port 15 */
	CFG_FUNC0,							// 120 : SPI2_MISO		-> SPI_MESA_MISO
	CFG_IN | PULL_DOWN,						// 121 : SPI2_SSIN		-> GPIO_MESA2SOC_IRQ
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		// 122 : UART8_TXD		-> SOC2USBPDMCU_SWCLK
	CFG_DISABLED,							// 123 : UART8_RXD		-> SOC2USBPDMCU_SWDIO
	CFG_DISABLED,							// 124 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 125 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 126 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 127 : UNSPECIFIED		-> UNSPECIFIED

/* Port 16 */
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 128 : UART0_TXD		-> UART_SOC2DEBUG_TX
	CFG_FUNC0,							// 129 : UART0_RXD		-> UART_DEBUG2SOC_TX
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 130 : UART6_TXD		-> UART_SOC2ACC_TX
	CFG_FUNC0,							// 131 : UART6_RXD		-> UART_ACC2SOC_TX
	CFG_FUNC0 | SLOW_SLEW,						// 132 : I2C2_SDA		-> I2C2_SDA_1V8
	CFG_FUNC0 | SLOW_SLEW,						// 133 : I2C2_SCL		-> I2C2_SCL_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 134 : I2C3_SDA		-> I2C3_SDA_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 135 : I2C3_SCL		-> I2C3_SCL_1V8

/* Port 17 */
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 136 : UART2_TXD		-> UART_SOC2WLAN_TX
	CFG_FUNC0,							// 137 : UART2_RXD		-> UART_WLAN2SOC_TX
	CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW,				// 138 : UART2_RTSN		-> UART_SOC2WLAN_RTS_L
	CFG_FUNC0,							// 139 : UART2_CTSN		-> UART_WLAN2SOC_RTS_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 140 : UART1_TXD		-> UART_SOC2BT_TX
	CFG_FUNC0,							// 141 : UART1_RXD		-> UART_BT2SOC_TX
	CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW,				// 142 : UART1_RTSN		-> UART_SOC2BT_RTS_L
	CFG_FUNC0,							// 143 : UART1_CTSN		-> UART_BT2SOC_RTS_L

/* Port 18 */
	CFG_FUNC0,							// 144 : EDP_HPD		-> EDP_HPD
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,				// 145 : I2S4_MCK		-> SWD_KONA_IO
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 146 : I2S4_LRCK		-> I2S_SOC2BT_LRCK
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 147 : I2S4_BCLK		-> I2S_SOC2BT_BCLK
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 148 : I2S4_DOUT		-> I2S_SOC2BT_DOUT
	CFG_FUNC0,							// 149 : I2S4_DIN		-> I2S_BT2SOC_DOUT
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 150 : I2S2_LRCK		-> I2S_SOC2SPKRAMP_CN_LRCK
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			// 151 : I2S2_BCLK		-> I2S_SOC2SPKRAMP_CN_BCLK

/* Port 19 */
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 152 : I2S2_DOUT		-> I2S_SOC2SPKRAMP_CN_DOUT
	CFG_FUNC0,							// 153 : I2S2_DIN		-> I2S_SPKRAMP2SOC_CN_DOUT
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		// 154 : SPI1_SCLK		-> SPI_GRAPE_SCLK_R
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 155 : SPI1_MOSI		-> SPI_GRAPE_MOSI
	CFG_FUNC0,							// 156 : SPI1_MISO		-> SPI_GRAPE_MISO
	CFG_OUT_1 | SLOW_SLEW,						// 157 : SPI1_SSIN		-> SPI_GRAPE_CS_L
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,		// 158 : CLK32K_OUT		-> ORIONMCU_SWCLK_1V8
	CFG_DISABLED,							// 159 : ULPI_DIR		-> GPIO_BRD_REV1

/* Port 20 */
	CFG_OUT_0,							// 160 : ULPI_STP		-> SOC2USBPDMCU_RESET_L
	CFG_DISABLED,							// 161 : ULPI_NXT		-> GPIO_BRD_REV0
	CFG_OUT_0 | SLOW_SLEW,						// 162 : ULPI_DATA[7]		-> GPIO_SOC2AJ_HS3_SHUNT_EN
	CFG_DISABLED,							// 163 : ULPI_DATA[6]		-> GPIO_BRD_REV3
	CFG_OUT_0 | SLOW_SLEW,						// 164 : ULPI_DATA[5]		-> GPIO_SOC2BT_WAKE
	CFG_OUT_0 | SLOW_SLEW,						// 165 : ULPI_DATA[4]		-> GPIO_SOC2WLAN_WAKE
	CFG_OUT_0 | SLOW_SLEW,						// 166 : ULPI_CLK		-> GPIO_SOC2AJ_HS4_SHUNT_EN
	CFG_IN,								// 167 : ULPI_DATA[3]		-> USBPDMCU2SOC_IRQ

/* Port 21 */
	CFG_DISABLED,							// 168 : ULPI_DATA[2]		-> GPIO_BRD_REV2
	CFG_DISABLED,							// 169 : ULPI_DATA[1]		-> SWD_OSCAR_IO_1V8
	CFG_DISABLED,							// 170 : ULPI_DATA[0]		-> SWD_OSCAR_CLK_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 171 : DWI1_DO		-> DWI_SOC2BEACON_DO
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 172 : DWI1_CLK		-> DWI_SOC2BEACON_CLK
	CFG_DISABLED | INPUT_SCHMITT,					// 173 : PCIE_CLKREQ0_N		-> PCIE_TT2SOC_CLKREQ_L
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 174 : PCIE_CLKREQ1_N		-> PCIE_WLAN2SOC_CLKREQ_L
	CFG_DISABLED | INPUT_SCHMITT,					// 175 : PCIE_CLKREQ2_N		-> NC_PCIE_DEVBRD2SOC_CLKREQ_L

/* Port 22 */
	CFG_IN,								// 176 : PCIE_CLKREQ3_N		-> GPIO_TT2SOC_PWR_SW_OC
	CFG_DISABLED,							// 177 : NAND_SYS_CLK		-> NC
	CFG_OUT_0 | SLOW_SLEW,						// 178 : PCIE_PERST0_N		-> PCIE_SOC2TT_RESET_L
	CFG_IN | SLOW_SLEW,						// 179 : PCIE_PERST1_N		-> PCIE_SOC2WLAN_RESET_L
	CFG_DISABLED,							// 180 : PCIE_PERST2_N		-> NC_PCIE_SOC2DEVBRD_RESET_L
	CFG_DISABLED,							// 181 : PCIE_PERST3_N		-> GPIO_DEVDOG_DETECT
	CFG_FUNC0 | SLOW_SLEW,						// 182 : I2S0_MCK		-> I2S_SOC2CODEC_ASP_MCK_R
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 183 : I2S2_MCK		-> I2S_SOC2SPKRAMP_CN_MCK_R
};

static const uint32_t pinconfig_evt2_j99ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	CFG_IN,								//   0 : MENU_KEY_L		-> GPIO_BTN_HOME_L
	CFG_IN,								//   1 : HOLD_KEY_L		-> GPIO_BTN_ONOFF_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   2 : ISP0_SDA		-> ISP_CAM_REAR_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   3 : ISP0_SCL		-> ISP_CAM_REAR_SCL
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   4 : ISP1_SDA		-> ISP_CAM_FRONT_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   5 : ISP1_SCL		-> ISP_CAM_FRONT_SCL
	CFG_OUT_0 | SLOW_SLEW,						//   6 : SENSOR0_RST		-> ISP_CAM_REAR_SHUTDOWN_L
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//   7 : SENSOR0_CLK		-> ISP_CAM_REAR_CLK_R

/* Port  1 */
	CFG_IN | PULL_UP,						//   8 : SENSOR0_XSHUTDOWN	-> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
	CFG_IN | PULL_UP,						//   9 : SENSOR0_ISTRB		-> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
	CFG_OUT_0 | SLOW_SLEW,						//  10 : SENSOR1_RST		-> ISP_CAM_FRONT_SHUTDOWN_L
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//  11 : SENSOR1_CLK		-> ISP_CAM_FRONT_CLK_R
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  12 : SENSOR1_XSHUTDOWN	-> GPIO_SOC2ROTTERDAM_EN
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  13 : SENSOR1_ISTRB		-> GPIO_SOC2ROTTERDAM_DWLD_REQ
	CFG_IN | SLOW_SLEW,						//  14 : UART3_TXD		-> UART_SOC2BB_TX
	CFG_FUNC0,							//  15 : UART3_RXD		-> UART_BB2SOC_TX

/* Port  2 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  3 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  4 */
	CFG_IN | SLOW_SLEW,						//  32 : UART3_RTSN		-> UART_SOC2BB_RTS_L
	CFG_FUNC0,							//  33 : UART3_CTSN		-> UART_BB2SOC_RTS_L
	CFG_FUNC0 | SLOW_SLEW,						//  34 : UART5_RTXD		-> UART_BATT_HDQ
	CFG_FUNC0 | SLOW_SLEW,						//  35 : DWI0_DO		-> DWI_SOC2PMU_DO
	CFG_FUNC0 | SLOW_SLEW,						//  36 : DWI0_CLK		-> DWI_SOC2PMU_CLK
	CFG_FUNC0 | SLOW_SLEW,						//  37 : I2C0_SDA		-> I2C0_SDA_1V8
	CFG_FUNC0 | SLOW_SLEW,						//  38 : I2C0_SCL		-> I2C0_SCL_1V8
	CFG_FUNC0 | SLOW_SLEW,						//  39 : I2S0_LRCK		-> I2S_SOC2CODEC_ASP_LRCK

/* Port  5 */
	CFG_FUNC0 | SLOW_SLEW,						//  40 : I2S0_BCLK		-> I2S_SOC2CODEC_ASP_BCLK
	CFG_FUNC0 | SLOW_SLEW,						//  41 : I2S0_DOUT		-> I2S_SOC2CODEC_ASP_DOUT
	CFG_FUNC0,							//  42 : I2S0_DIN		-> I2S_CODEC2SOC_ASP_DOUT
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,				//  43 : I2S1_MCK		-> SWD_KONA_CLK
	CFG_FUNC0 | SLOW_SLEW,						//  44 : I2S1_LRCK		-> I2S_SOC2CODEC_XSP_LRCK
	CFG_FUNC0 | SLOW_SLEW,						//  45 : I2S1_BCLK		-> I2S_SOC2CODEC_XSP_BCLK
	CFG_FUNC0 | SLOW_SLEW,						//  46 : I2S1_DOUT		-> I2S_SOC2CODEC_XSP_DOUT
	CFG_FUNC0,							//  47 : I2S1_DIN		-> I2S_CODEC2SOC_XSP_DOUT

/* Port  6 */
	CFG_FUNC0 | SLOW_SLEW,						//  48 : SPI3_MOSI		-> SPI_CODEC_MOSI
	CFG_FUNC0,							//  49 : SPI3_MISO		-> SPI_CODEC_MISO
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				//  50 : SPI3_SCLK		-> SPI_CODEC_SCLK_R
	CFG_OUT_1 | SLOW_SLEW,						//  51 : SPI3_SSIN		-> SPI_CODEC_CS_L
	CFG_OUT_0 | SLOW_SLEW,						//  52 : TMR32_PWM0		-> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//  53 : TMR32_PWM1		-> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
	CFG_IN,								//  54 : TMR32_PWM2		-> GPUUVD2SOC_OUT_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  55 : DISP_VSYNC		-> ORIONMCU_SWDIO_1V8

/* Port  7 */
	CFG_FUNC0 | SLOW_SLEW,						//  56 : WDOG			-> WDOG_SOC
	CFG_FUNC0,							//  57 : SOCHOT0		-> SOCHOT0_L
	CFG_FUNC0 | SLOW_SLEW,						//  58 : SOCHOT1		-> SOCHOT1_L
	CFG_DISABLED,							//  59 : CPU_SLEEP_STATUS	-> NC
	CFG_DISABLED | SLOW_SLEW,					//  60 : TST_CLKOUT		-> SOC_TST_CLKOUT
	CFG_IN | PULL_UP,						//  61 : ISP_UART0_TXD		-> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
	CFG_IN | PULL_UP,						//  62 : ISP_UART0_RXD		-> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  63 : UART7_TXD		-> UART_SOC2OSCAR_TX

/* Port  8 */
	CFG_FUNC0,							//  64 : UART7_RXD		-> UART_OSCAR2SOC_TX
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  65 : I2C1_SDA		-> I2C1_SDA_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  66 : I2C1_SCL		-> I2C1_SCL_1V8
	CFG_DISABLED,							//  67 : SPI0_SCLK		-> GPIO_BRD_ID0
	CFG_DISABLED,							//  68 : SPI0_MOSI		-> GPIO_BRD_ID1
	CFG_DISABLED,							//  69 : SPI0_MISO		-> GPIO_BRD_ID2
	CFG_IN,								//  70 : SPI0_SSIN		-> GPIO_TS2ORIONSOC2PMU_IRQ
	CFG_FUNC0 | SLOW_SLEW,						//  71 : I2S3_MCK		-> I2S_SOC2SPKRAMP_FH_MCK_R

/* Port  9 */
	CFG_FUNC0 | SLOW_SLEW,						//  72 : I2S3_LRCK		-> I2S_SOC2SPKRAMP_FH_LRCK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				//  73 : I2S3_BCLK		-> I2S_SOC2SPKRAMP_FH_BCLK
	CFG_FUNC0 | SLOW_SLEW,						//  74 : I2S3_DOUT		-> I2S_SOC2SPKRAMP_FH_DOUT
	CFG_FUNC0,							//  75 : I2S3_DIN		-> I2S_SPKRAMP2SOC_FH_DOUT
	CFG_IN | PULL_UP | SLOW_SLEW,					//  76 : UART4_TXD		-> UART_SOC2ROTTERDAM_TX
	CFG_FUNC0,							//  77 : UART4_RXD		-> UART_ROTTERDAM2SOC_TX
	CFG_IN | PULL_UP | SLOW_SLEW,					//  78 : UART4_RTSN		-> UART_SOC2ROTTERDAM_RTS_L
	CFG_FUNC0,							//  79 : UART4_CTSN		-> UART_ROTTERDAM2SOC_RTS_L

/* Port 10 */
	CFG_OUT_0 | SLOW_SLEW,						//  80 : GPIO[0]		-> GPIO_SOC2GPUUVD_EN
	CFG_OUT_1 | SLOW_SLEW,						//  81 : GPIO[1]		-> GPIO_SOC2TT_XBAR_EN_PULSE_L
	CFG_OUT_0 | SLOW_SLEW,						//  82 : GPIO[2]		-> GPIO_SOC2GRAPE_RESET_L
	CFG_IN,								//  83 : GPIO[3]		-> GPIO_TS2SOC2PMU_IRQ
	CFG_IN | PULL_UP,						//  84 : GPIO[4]		-> GPIO_GRAPE2SOC_IRQ_L
	CFG_OUT_1 | SLOW_SLEW,						//  85 : GPIO[5]		-> GPIO_SOC2TT_XBAR_DIS_PULSE_L
	CFG_IN | PULL_UP,						//  86 : GPIO[6]		-> GPIO_PMU2SOC_IRQ_L
	CFG_OUT_0 | SLOW_SLEW,						//  87 : GPIO[7]		-> GPIO_SOC2PMU_KEEPACT

/* Port 11 */
	CFG_IN,								//  88 : GPIO[8]		-> GPIO_GANGES2SOC2PMU_IRQ_L
	CFG_DISABLED,							//  89 : GPIO[9]		-> GPIO_TT2SOC_WAKE_L
	CFG_DISABLED,							//  90 : GPIO[10]		-> GPIO_SOC2CODEC_RESET_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  91 : GPIO[11]		-> GPIO_BB_IPC
	CFG_IN | PULL_UP,						//  92 : GPIO[12]		-> GPIO_BTN_VOL_UP_L
	CFG_IN | PULL_UP,						//  93 : GPIO[13]		-> GPIO_BTN_VOL_DOWN_L
	CFG_OUT_0 | SLOW_SLEW,						//  94 : GPIO[14]		-> GPIO_SOC2TT_SW_EN
	CFG_OUT_0 | SLOW_SLEW,						//  95 : GPIO[15]		-> GPIO_SOC2GRAPE_EXT_SW_ON

/* Port 12 */
	CFG_DISABLED,							//  96 : GPIO[16]		-> GPIO_BRD_ID3
	CFG_OUT_0 | SLOW_SLEW,						//  97 : GPIO[17]		-> GPIO_SOC2BB_COREDUMP
	CFG_DISABLED,							//  98 : GPIO[18]		-> GPIO_BOOT_CFG0
	CFG_OUT_0 | SLOW_SLEW,						//  99 : GPIO[19]		-> GPIO_SOC2TT_LDO_EN
	CFG_OUT_0 | SLOW_SLEW,						// 100 : GPIO[20]		-> GPIO_SOC2BB_WAKE_MODEM
	CFG_OUT_0 | SLOW_SLEW,						// 101 : GPIO[21]		-> GPIO_SOC2SPKRAMP_KEEPALIVE
	CFG_DISABLED,							// 102 : GPIO[22]		-> GPIO_BB2SOC_GPS_SYNC
	CFG_IN | PULL_UP,						// 103 : GPIO[23]		-> GPIO_HP_ALS2SOC_IRQ_L

/* Port 13 */
	CFG_IN | SLOW_SLEW,						// 104 : GPIO[24]		-> GPIO_SOC2BB_RADIO_ON_L
	CFG_DISABLED,							// 105 : GPIO[25]		-> GPIO_BOOT_CFG1
	CFG_IN,								// 106 : GPIO[26]		-> GPIO_FORCE_DFU
	CFG_DISABLED,							// 107 : GPIO[27]		-> TP_GPIO_DFU_STATUS
	CFG_DISABLED,							// 108 : GPIO[28]		-> GPIO_BOOT_CFG2
	CFG_DISABLED,							// 109 : GPIO[29]		-> GPIO_TT2SOC_SMI_L
	CFG_IN | PULL_UP,						// 110 : GPIO[30]		-> GPIO_RC_ALS2SOC_IRQ_L
	CFG_DISABLED,							// 111 : GPIO[31]		-> GPIO_BOOT_CFG3

/* Port 14 */
	CFG_IN,								// 112 : GPIO[32]		-> GPIO_OSCAR2PMU_HOST_WAKE
	CFG_IN | PULL_DOWN,						// 113 : GPIO[33]		-> HSIC_BB2SOC_DEVICE_RDY
	CFG_OUT_0 | SLOW_SLEW,						// 114 : GPIO[34]		-> HSIC_SOC2BB_HOST_RDY
	CFG_IN | PULL_DOWN,						// 115 : GPIO[35]		-> GPIO_BB2SOC_RESET_DET_L
	CFG_IN | PULL_UP,						// 116 : GPIO[36]		-> GPIO_CODEC2SOC_IRQ_L
	CFG_IN | SLOW_SLEW,						// 117 : GPIO[37]		-> GPIO_SOC2BB_RESET_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		// 118 : SPI2_SCLK		-> SPI_MESA_SCLK_R
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 119 : SPI2_MOSI		-> SPI_MESA_MOSI

/* Port 15 */
	CFG_FUNC0,							// 120 : SPI2_MISO		-> SPI_MESA_MISO
	CFG_IN | PULL_DOWN,						// 121 : SPI2_SSIN		-> GPIO_MESA2SOC_IRQ
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				// 122 : UART8_TXD		-> SOC2USBPDMCU_SWCLK
	CFG_DISABLED,							// 123 : UART8_RXD		-> SOC2USBPDMCU_SWDIO
	CFG_DISABLED,							// 124 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 125 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 126 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 127 : UNSPECIFIED		-> UNSPECIFIED

/* Port 16 */
	CFG_FUNC0 | SLOW_SLEW,						// 128 : UART0_TXD		-> UART_SOC2DEBUG_TX
	CFG_FUNC0,							// 129 : UART0_RXD		-> UART_DEBUG2SOC_TX
	CFG_FUNC0 | SLOW_SLEW,						// 130 : UART6_TXD		-> UART_SOC2ACC_TX
	CFG_FUNC0,							// 131 : UART6_RXD		-> UART_ACC2SOC_TX
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 132 : I2C2_SDA		-> I2C2_SDA_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 133 : I2C2_SCL		-> I2C2_SCL_1V8
	CFG_FUNC0 | SLOW_SLEW,						// 134 : I2C3_SDA		-> I2C3_SDA_1V8
	CFG_FUNC0 | SLOW_SLEW,						// 135 : I2C3_SCL		-> I2C3_SCL_1V8

/* Port 17 */
	CFG_FUNC0 | SLOW_SLEW,						// 136 : UART2_TXD		-> UART_SOC2WLAN_TX
	CFG_FUNC0,							// 137 : UART2_RXD		-> UART_WLAN2SOC_TX
	CFG_OUT_1 | SLOW_SLEW,						// 138 : UART2_RTSN		-> UART_SOC2WLAN_RTS_L
	CFG_FUNC0,							// 139 : UART2_CTSN		-> UART_WLAN2SOC_RTS_L
	CFG_FUNC0 | SLOW_SLEW,						// 140 : UART1_TXD		-> UART_SOC2BT_TX
	CFG_FUNC0,							// 141 : UART1_RXD		-> UART_BT2SOC_TX
	CFG_OUT_1 | SLOW_SLEW,						// 142 : UART1_RTSN		-> UART_SOC2BT_RTS_L
	CFG_FUNC0,							// 143 : UART1_CTSN		-> UART_BT2SOC_RTS_L

/* Port 18 */
	CFG_FUNC0,							// 144 : EDP_HPD		-> EDP_HPD
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,				// 145 : I2S4_MCK		-> SWD_KONA_IO
	CFG_FUNC0 | SLOW_SLEW,						// 146 : I2S4_LRCK		-> I2S_SOC2BT_LRCK
	CFG_FUNC0 | SLOW_SLEW,						// 147 : I2S4_BCLK		-> I2S_SOC2BT_BCLK
	CFG_FUNC0 | SLOW_SLEW,						// 148 : I2S4_DOUT		-> I2S_SOC2BT_DOUT
	CFG_FUNC0,							// 149 : I2S4_DIN		-> I2S_BT2SOC_DOUT
	CFG_FUNC0 | SLOW_SLEW,						// 150 : I2S2_LRCK		-> I2S_SOC2SPKRAMP_CN_LRCK
	CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,				// 151 : I2S2_BCLK		-> I2S_SOC2SPKRAMP_CN_BCLK

/* Port 19 */
	CFG_FUNC0 | SLOW_SLEW,						// 152 : I2S2_DOUT		-> I2S_SOC2SPKRAMP_CN_DOUT
	CFG_FUNC0,							// 153 : I2S2_DIN		-> I2S_SPKRAMP2SOC_CN_DOUT
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		// 154 : SPI1_SCLK		-> SPI_GRAPE_SCLK_R
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 155 : SPI1_MOSI		-> SPI_GRAPE_MOSI
	CFG_FUNC0,							// 156 : SPI1_MISO		-> SPI_GRAPE_MISO
	CFG_OUT_1 | SLOW_SLEW,						// 157 : SPI1_SSIN		-> SPI_GRAPE_CS_L
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,		// 158 : CLK32K_OUT		-> ORIONMCU_SWCLK_1V8
	CFG_DISABLED,							// 159 : ULPI_DIR		-> GPIO_BRD_REV1

/* Port 20 */
	CFG_OUT_0,							// 160 : ULPI_STP		-> SOC2USBPDMCU_RESET_L
	CFG_DISABLED,							// 161 : ULPI_NXT		-> GPIO_BRD_REV0
	CFG_OUT_0 | SLOW_SLEW,						// 162 : ULPI_DATA[7]		-> GPIO_SOC2AJ_HS3_SHUNT_EN
	CFG_DISABLED,							// 163 : ULPI_DATA[6]		-> GPIO_BRD_REV3
	CFG_OUT_0 | SLOW_SLEW,						// 164 : ULPI_DATA[5]		-> GPIO_SOC2BT_WAKE
	CFG_OUT_0 | SLOW_SLEW,						// 165 : ULPI_DATA[4]		-> GPIO_SOC2WLAN_WAKE
	CFG_OUT_0 | SLOW_SLEW,						// 166 : ULPI_CLK		-> GPIO_SOC2AJ_HS4_SHUNT_EN
	CFG_IN,								// 167 : ULPI_DATA[3]		-> USBPDMCU2SOC_IRQ

/* Port 21 */
	CFG_DISABLED,							// 168 : ULPI_DATA[2]		-> GPIO_BRD_REV2
	CFG_DISABLED,							// 169 : ULPI_DATA[1]		-> SWD_OSCAR_IO_1V8
	CFG_DISABLED,							// 170 : ULPI_DATA[0]		-> SWD_OSCAR_CLK_1V8
	CFG_FUNC0 | SLOW_SLEW,						// 171 : DWI1_DO		-> DWI_SOC2BEACON_DO
	CFG_FUNC0 | SLOW_SLEW,						// 172 : DWI1_CLK		-> DWI_SOC2BEACON_CLK
	CFG_DISABLED | INPUT_SCHMITT,					// 173 : PCIE_CLKREQ0_N		-> PCIE_TT2SOC_CLKREQ_L
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 174 : PCIE_CLKREQ1_N		-> PCIE_WLAN2SOC_CLKREQ_L
	CFG_DISABLED | INPUT_SCHMITT,					// 175 : PCIE_CLKREQ2_N		-> NC_PCIE_DEVBRD2SOC_CLKREQ_L

/* Port 22 */
	CFG_IN,								// 176 : PCIE_CLKREQ3_N		-> GPIO_TT2SOC_PWR_SW_OC
	CFG_DISABLED,							// 177 : NAND_SYS_CLK		-> NC
	CFG_OUT_0 | SLOW_SLEW,						// 178 : PCIE_PERST0_N		-> PCIE_SOC2TT_RESET_L
	CFG_IN | SLOW_SLEW,						// 179 : PCIE_PERST1_N		-> PCIE_SOC2WLAN_RESET_L
	CFG_DISABLED,							// 180 : PCIE_PERST2_N		-> NC_PCIE_SOC2DEVBRD_RESET_L
	CFG_DISABLED,							// 181 : PCIE_PERST3_N		-> GPIO_DEVDOG_DETECT
	CFG_FUNC0 | SLOW_SLEW,						// 182 : I2S0_MCK		-> I2S_SOC2CODEC_ASP_MCK_R
	CFG_FUNC0 | SLOW_SLEW,						// 183 : I2S2_MCK		-> I2S_SOC2SPKRAMP_CN_MCK_R
};

static const uint32_t pinconfig_evt2_j99dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	CFG_IN,								//   0 : MENU_KEY_L		-> GPIO_BTN_HOME_L
	CFG_IN,								//   1 : HOLD_KEY_L		-> GPIO_BTN_ONOFF_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   2 : ISP0_SDA		-> ISP_CAM_REAR_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   3 : ISP0_SCL		-> ISP_CAM_REAR_SCL
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   4 : ISP1_SDA		-> ISP_CAM_FRONT_SDA
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//   5 : ISP1_SCL		-> ISP_CAM_FRONT_SCL
	CFG_OUT_0 | SLOW_SLEW,						//   6 : SENSOR0_RST		-> ISP_CAM_REAR_SHUTDOWN_L
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//   7 : SENSOR0_CLK		-> ISP_CAM_REAR_CLK_R

/* Port  1 */
	CFG_IN | PULL_UP,						//   8 : SENSOR0_XSHUTDOWN	-> GPIO_SPKRAMP2SOC_CN_LEFT_IRQ_L
	CFG_IN | PULL_UP,						//   9 : SENSOR0_ISTRB		-> GPIO_SPKRAMP2SOC_CN_RIGHT_IRQ_L
	CFG_OUT_0 | SLOW_SLEW,						//  10 : SENSOR1_RST		-> ISP_CAM_FRONT_SHUTDOWN_L
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//  11 : SENSOR1_CLK		-> ISP_CAM_FRONT_CLK_R
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  12 : SENSOR1_XSHUTDOWN	-> GPIO_SOC2ROTTERDAM_EN
	CFG_IN | PULL_DOWN | SLOW_SLEW,					//  13 : SENSOR1_ISTRB		-> GPIO_SOC2ROTTERDAM_DWLD_REQ
	CFG_IN | DRIVE_X2 | SLOW_SLEW,					//  14 : UART3_TXD		-> UART_SOC2BB_TX
	CFG_FUNC0,							//  15 : UART3_RXD		-> UART_BB2SOC_TX

/* Port  2 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  3 */
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,
	CFG_DISABLED,

/* Port  4 */
	CFG_IN | DRIVE_X2 | SLOW_SLEW,					//  32 : UART3_RTSN		-> UART_SOC2BB_RTS_L
	CFG_FUNC0,							//  33 : UART3_CTSN		-> UART_BB2SOC_RTS_L
	CFG_FUNC0 | SLOW_SLEW,						//  34 : UART5_RTXD		-> UART_BATT_HDQ
	CFG_FUNC0 | SLOW_SLEW,						//  35 : DWI0_DO		-> DWI_SOC2PMU_DO
	CFG_FUNC0 | SLOW_SLEW,						//  36 : DWI0_CLK		-> DWI_SOC2PMU_CLK
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  37 : I2C0_SDA		-> I2C0_SDA_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  38 : I2C0_SCL		-> I2C0_SCL_1V8
	CFG_FUNC0 | SLOW_SLEW,						//  39 : I2S0_LRCK		-> I2S_SOC2CODEC_ASP_LRCK

/* Port  5 */
	CFG_FUNC0 | SLOW_SLEW,						//  40 : I2S0_BCLK		-> I2S_SOC2CODEC_ASP_BCLK
	CFG_FUNC0 | SLOW_SLEW,						//  41 : I2S0_DOUT		-> I2S_SOC2CODEC_ASP_DOUT
	CFG_FUNC0,							//  42 : I2S0_DIN		-> I2S_CODEC2SOC_ASP_DOUT
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,				//  43 : I2S1_MCK		-> SWD_KONA_CLK
	CFG_FUNC0 | SLOW_SLEW,						//  44 : I2S1_LRCK		-> I2S_SOC2CODEC_XSP_LRCK
	CFG_FUNC0 | SLOW_SLEW,						//  45 : I2S1_BCLK		-> I2S_SOC2CODEC_XSP_BCLK
	CFG_FUNC0 | SLOW_SLEW,						//  46 : I2S1_DOUT		-> I2S_SOC2CODEC_XSP_DOUT
	CFG_FUNC0,							//  47 : I2S1_DIN		-> I2S_CODEC2SOC_XSP_DOUT

/* Port  6 */
	CFG_FUNC0 | SLOW_SLEW,						//  48 : SPI3_MOSI		-> SPI_CODEC_MOSI
	CFG_FUNC0,							//  49 : SPI3_MISO		-> SPI_CODEC_MISO
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				//  50 : SPI3_SCLK		-> SPI_CODEC_SCLK_R
	CFG_OUT_1 | SLOW_SLEW,						//  51 : SPI3_SSIN		-> SPI_CODEC_CS_L
	CFG_OUT_0 | SLOW_SLEW,						//  52 : TMR32_PWM0		-> OSCAR_BIDIR_TIME_SYNC_HOST_IRQ
	CFG_OUT_0 | DRIVE_X2 | SLOW_SLEW,				//  53 : TMR32_PWM1		-> GPIO_SOC2BT2GRAPE_TIMESTAMP_SYNC
	CFG_IN,								//  54 : TMR32_PWM2		-> GPUUVD2SOC_OUT_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  55 : DISP_VSYNC		-> ORIONMCU_SWDIO_1V8

/* Port  7 */
	CFG_FUNC0 | SLOW_SLEW,						//  56 : WDOG			-> WDOG_SOC
	CFG_FUNC0,							//  57 : SOCHOT0		-> SOCHOT0_L
	CFG_FUNC0 | SLOW_SLEW,						//  58 : SOCHOT1		-> SOCHOT1_L
	CFG_DISABLED,							//  59 : CPU_SLEEP_STATUS	-> NC
	CFG_DISABLED | SLOW_SLEW,					//  60 : TST_CLKOUT		-> SOC_TST_CLKOUT
	CFG_IN | PULL_UP,						//  61 : ISP_UART0_TXD		-> GPIO_SPKRAMP2SOC_FH_RIGHT_IRQ_L
	CFG_IN | PULL_UP,						//  62 : ISP_UART0_RXD		-> GPIO_SPKRAMP2SOC_FH_LEFT_IRQ_L
	CFG_IN | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//  63 : UART7_TXD		-> UART_SOC2OSCAR_TX

/* Port  8 */
	CFG_FUNC0,							//  64 : UART7_RXD		-> UART_OSCAR2SOC_TX
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  65 : I2C1_SDA		-> I2C1_SDA_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  66 : I2C1_SCL		-> I2C1_SCL_1V8
	CFG_DISABLED,							//  67 : SPI0_SCLK		-> GPIO_BRD_ID0
	CFG_DISABLED,							//  68 : SPI0_MOSI		-> GPIO_BRD_ID1
	CFG_DISABLED,							//  69 : SPI0_MISO		-> GPIO_BRD_ID2
	CFG_IN,								//  70 : SPI0_SSIN		-> GPIO_TS2ORIONSOC2PMU_IRQ
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  71 : I2S3_MCK		-> I2S_SOC2SPKRAMP_FH_MCK_R

/* Port  9 */
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  72 : I2S3_LRCK		-> I2S_SOC2SPKRAMP_FH_LRCK
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			//  73 : I2S3_BCLK		-> I2S_SOC2SPKRAMP_FH_BCLK
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				//  74 : I2S3_DOUT		-> I2S_SOC2SPKRAMP_FH_DOUT
	CFG_FUNC0,							//  75 : I2S3_DIN		-> I2S_SPKRAMP2SOC_FH_DOUT
	CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW,			//  76 : UART4_TXD		-> UART_SOC2ROTTERDAM_TX
	CFG_FUNC0,							//  77 : UART4_RXD		-> UART_ROTTERDAM2SOC_TX
	CFG_IN | PULL_UP | DRIVE_X2 | SLOW_SLEW,			//  78 : UART4_RTSN		-> UART_SOC2ROTTERDAM_RTS_L
	CFG_FUNC0,							//  79 : UART4_CTSN		-> UART_ROTTERDAM2SOC_RTS_L

/* Port 10 */
	CFG_OUT_0 | SLOW_SLEW,						//  80 : GPIO[0]		-> GPIO_SOC2GPUUVD_EN
	CFG_OUT_1 | SLOW_SLEW,						//  81 : GPIO[1]		-> GPIO_SOC2TT_XBAR_EN_PULSE_L
	CFG_OUT_0 | SLOW_SLEW,						//  82 : GPIO[2]		-> GPIO_SOC2GRAPE_RESET_L
	CFG_IN,								//  83 : GPIO[3]		-> GPIO_TS2SOC2PMU_IRQ
	CFG_IN | PULL_UP,						//  84 : GPIO[4]		-> GPIO_GRAPE2SOC_IRQ_L
	CFG_OUT_1 | SLOW_SLEW,						//  85 : GPIO[5]		-> GPIO_SOC2TT_XBAR_DIS_PULSE_L
	CFG_IN | PULL_UP,						//  86 : GPIO[6]		-> GPIO_PMU2SOC_IRQ_L
	CFG_OUT_0 | SLOW_SLEW,						//  87 : GPIO[7]		-> GPIO_SOC2PMU_KEEPACT

/* Port 11 */
	CFG_IN,								//  88 : GPIO[8]		-> GPIO_GANGES2SOC2PMU_IRQ_L
	CFG_DISABLED,							//  89 : GPIO[9]		-> GPIO_TT2SOC_WAKE_L
	CFG_DISABLED,							//  90 : GPIO[10]		-> GPIO_SOC2CODEC_RESET_L
	CFG_DISABLED | PULL_DOWN | SLOW_SLEW,				//  91 : GPIO[11]		-> GPIO_BB_IPC
	CFG_IN | PULL_UP,						//  92 : GPIO[12]		-> GPIO_BTN_VOL_UP_L
	CFG_IN | PULL_UP,						//  93 : GPIO[13]		-> GPIO_BTN_VOL_DOWN_L
	CFG_OUT_0 | SLOW_SLEW,						//  94 : GPIO[14]		-> GPIO_SOC2TT_SW_EN
	CFG_OUT_0 | SLOW_SLEW,						//  95 : GPIO[15]		-> GPIO_SOC2GRAPE_EXT_SW_ON

/* Port 12 */
	CFG_DISABLED,							//  96 : GPIO[16]		-> GPIO_BRD_ID3
	CFG_OUT_0 | SLOW_SLEW,						//  97 : GPIO[17]		-> GPIO_SOC2BB_COREDUMP
	CFG_DISABLED,							//  98 : GPIO[18]		-> GPIO_BOOT_CFG0
	CFG_OUT_0 | SLOW_SLEW,						//  99 : GPIO[19]		-> GPIO_SOC2TT_LDO_EN
	CFG_OUT_0 | SLOW_SLEW,						// 100 : GPIO[20]		-> GPIO_SOC2BB_WAKE_MODEM
	CFG_OUT_0 | SLOW_SLEW,						// 101 : GPIO[21]		-> GPIO_SOC2SPKRAMP_KEEPALIVE
	CFG_DISABLED,							// 102 : GPIO[22]		-> GPIO_BB2SOC_GPS_SYNC
	CFG_IN | PULL_UP,						// 103 : GPIO[23]		-> GPIO_HP_ALS2SOC_IRQ_L

/* Port 13 */
	CFG_IN | SLOW_SLEW,						// 104 : GPIO[24]		-> GPIO_SOC2BB_RADIO_ON_L
	CFG_DISABLED,							// 105 : GPIO[25]		-> GPIO_BOOT_CFG1
	CFG_IN,								// 106 : GPIO[26]		-> GPIO_FORCE_DFU
	CFG_DISABLED,							// 107 : GPIO[27]		-> TP_GPIO_DFU_STATUS
	CFG_DISABLED,							// 108 : GPIO[28]		-> GPIO_BOOT_CFG2
	CFG_DISABLED,							// 109 : GPIO[29]		-> GPIO_TT2SOC_SMI_L
	CFG_IN | PULL_UP,						// 110 : GPIO[30]		-> GPIO_RC_ALS2SOC_IRQ_L
	CFG_DISABLED,							// 111 : GPIO[31]		-> GPIO_BOOT_CFG3

/* Port 14 */
	CFG_IN,								// 112 : GPIO[32]		-> GPIO_OSCAR2PMU_HOST_WAKE
	CFG_IN | PULL_DOWN,						// 113 : GPIO[33]		-> HSIC_BB2SOC_DEVICE_RDY
	CFG_OUT_0 | SLOW_SLEW,						// 114 : GPIO[34]		-> HSIC_SOC2BB_HOST_RDY
	CFG_IN | PULL_DOWN,						// 115 : GPIO[35]		-> GPIO_BB2SOC_RESET_DET_L
	CFG_IN | PULL_UP,						// 116 : GPIO[36]		-> GPIO_CODEC2SOC_IRQ_L
	CFG_IN | SLOW_SLEW,						// 117 : GPIO[37]		-> GPIO_SOC2BB_RESET_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		// 118 : SPI2_SCLK		-> SPI_MESA_SCLK_R
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 119 : SPI2_MOSI		-> SPI_MESA_MOSI

/* Port 15 */
	CFG_FUNC0,							// 120 : SPI2_MISO		-> SPI_MESA_MISO
	CFG_IN | PULL_DOWN,						// 121 : SPI2_SSIN		-> GPIO_MESA2SOC_IRQ
	CFG_DISABLED | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,		// 122 : UART8_TXD		-> SOC2USBPDMCU_SWCLK
	CFG_DISABLED,							// 123 : UART8_RXD		-> SOC2USBPDMCU_SWDIO
	CFG_DISABLED,							// 124 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 125 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 126 : UNSPECIFIED		-> UNSPECIFIED
	CFG_DISABLED,							// 127 : UNSPECIFIED		-> UNSPECIFIED

/* Port 16 */
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 128 : UART0_TXD		-> UART_SOC2DEBUG_TX
	CFG_FUNC0,							// 129 : UART0_RXD		-> UART_DEBUG2SOC_TX
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 130 : UART6_TXD		-> UART_SOC2ACC_TX
	CFG_FUNC0,							// 131 : UART6_RXD		-> UART_ACC2SOC_TX
	CFG_FUNC0 | SLOW_SLEW,						// 132 : I2C2_SDA		-> I2C2_SDA_1V8
	CFG_FUNC0 | SLOW_SLEW,						// 133 : I2C2_SCL		-> I2C2_SCL_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 134 : I2C3_SDA		-> I2C3_SDA_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 135 : I2C3_SCL		-> I2C3_SCL_1V8

/* Port 17 */
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 136 : UART2_TXD		-> UART_SOC2WLAN_TX
	CFG_FUNC0,							// 137 : UART2_RXD		-> UART_WLAN2SOC_TX
	CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW,				// 138 : UART2_RTSN		-> UART_SOC2WLAN_RTS_L
	CFG_FUNC0,							// 139 : UART2_CTSN		-> UART_WLAN2SOC_RTS_L
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 140 : UART1_TXD		-> UART_SOC2BT_TX
	CFG_FUNC0,							// 141 : UART1_RXD		-> UART_BT2SOC_TX
	CFG_OUT_1 | DRIVE_X2 | SLOW_SLEW,				// 142 : UART1_RTSN		-> UART_SOC2BT_RTS_L
	CFG_FUNC0,							// 143 : UART1_CTSN		-> UART_BT2SOC_RTS_L

/* Port 18 */
	CFG_FUNC0,							// 144 : EDP_HPD		-> EDP_HPD
	CFG_DISABLED | DRIVE_X2 | SLOW_SLEW,				// 145 : I2S4_MCK		-> SWD_KONA_IO
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 146 : I2S4_LRCK		-> I2S_SOC2BT_LRCK
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 147 : I2S4_BCLK		-> I2S_SOC2BT_BCLK
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 148 : I2S4_DOUT		-> I2S_SOC2BT_DOUT
	CFG_FUNC0,							// 149 : I2S4_DIN		-> I2S_BT2SOC_DOUT
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 150 : I2S2_LRCK		-> I2S_SOC2SPKRAMP_CN_LRCK
	CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | SLOW_SLEW,			// 151 : I2S2_BCLK		-> I2S_SOC2SPKRAMP_CN_BCLK

/* Port 19 */
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 152 : I2S2_DOUT		-> I2S_SOC2SPKRAMP_CN_DOUT
	CFG_FUNC0,							// 153 : I2S2_DIN		-> I2S_SPKRAMP2SOC_CN_DOUT
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW | INPUT_SCHMITT,		// 154 : SPI1_SCLK		-> SPI_GRAPE_SCLK_R
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 155 : SPI1_MOSI		-> SPI_GRAPE_MOSI
	CFG_FUNC0,							// 156 : SPI1_MISO		-> SPI_GRAPE_MISO
	CFG_OUT_1 | SLOW_SLEW,						// 157 : SPI1_SSIN		-> SPI_GRAPE_CS_L
	CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,		// 158 : CLK32K_OUT		-> ORIONMCU_SWCLK_1V8
	CFG_DISABLED,							// 159 : ULPI_DIR		-> GPIO_BRD_REV1

/* Port 20 */
	CFG_OUT_0,							// 160 : ULPI_STP		-> SOC2USBPDMCU_RESET_L
	CFG_DISABLED,							// 161 : ULPI_NXT		-> GPIO_BRD_REV0
	CFG_OUT_0 | SLOW_SLEW,						// 162 : ULPI_DATA[7]		-> GPIO_SOC2AJ_HS3_SHUNT_EN
	CFG_DISABLED,							// 163 : ULPI_DATA[6]		-> GPIO_BRD_REV3
	CFG_OUT_0 | SLOW_SLEW,						// 164 : ULPI_DATA[5]		-> GPIO_SOC2BT_WAKE
	CFG_OUT_0 | SLOW_SLEW,						// 165 : ULPI_DATA[4]		-> GPIO_SOC2WLAN_WAKE
	CFG_OUT_0 | SLOW_SLEW,						// 166 : ULPI_CLK		-> GPIO_SOC2AJ_HS4_SHUNT_EN
	CFG_IN,								// 167 : ULPI_DATA[3]		-> USBPDMCU2SOC_IRQ

/* Port 21 */
	CFG_DISABLED,							// 168 : ULPI_DATA[2]		-> GPIO_BRD_REV2
	CFG_DISABLED,							// 169 : ULPI_DATA[1]		-> SWD_OSCAR_IO_1V8
	CFG_DISABLED,							// 170 : ULPI_DATA[0]		-> SWD_OSCAR_CLK_1V8
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 171 : DWI1_DO		-> DWI_SOC2BEACON_DO
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 172 : DWI1_CLK		-> DWI_SOC2BEACON_CLK
	CFG_DISABLED | INPUT_SCHMITT,					// 173 : PCIE_CLKREQ0_N		-> PCIE_TT2SOC_CLKREQ_L
	CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,				// 174 : PCIE_CLKREQ1_N		-> PCIE_WLAN2SOC_CLKREQ_L
	CFG_DISABLED | INPUT_SCHMITT,					// 175 : PCIE_CLKREQ2_N		-> NC_PCIE_DEVBRD2SOC_CLKREQ_L

/* Port 22 */
	CFG_IN,								// 176 : PCIE_CLKREQ3_N		-> GPIO_TT2SOC_PWR_SW_OC
	CFG_DISABLED,							// 177 : NAND_SYS_CLK		-> NC
	CFG_OUT_0 | SLOW_SLEW,						// 178 : PCIE_PERST0_N		-> PCIE_SOC2TT_RESET_L
	CFG_IN | SLOW_SLEW,						// 179 : PCIE_PERST1_N		-> PCIE_SOC2WLAN_RESET_L
	CFG_DISABLED,							// 180 : PCIE_PERST2_N		-> NC_PCIE_SOC2DEVBRD_RESET_L
	CFG_DISABLED,							// 181 : PCIE_PERST3_N		-> GPIO_DEVDOG_DETECT
	CFG_FUNC0 | SLOW_SLEW,						// 182 : I2S0_MCK		-> I2S_SOC2CODEC_ASP_MCK_R
	CFG_FUNC0 | DRIVE_X2 | SLOW_SLEW,				// 183 : I2S2_MCK		-> I2S_SOC2SPKRAMP_CN_MCK_R
};

struct pinconfig_map {
	uint32_t board_id;
	uint32_t board_id_mask;
	const uint32_t *pinconfigs[GPIOC_COUNT];
};

static const struct pinconfig_map cfg_map[] = {
	{ TARGET_BOARD_ID_J98AP,  ~0, { pinconfig_evt2_j98ap_0  } },
	{ TARGET_BOARD_ID_J98DEV, ~0, { pinconfig_evt2_j98dev_0 } },
	{ TARGET_BOARD_ID_J99AP,  ~0, { pinconfig_evt2_j99ap_0  } },
	{ TARGET_BOARD_ID_J99DEV, ~0, { pinconfig_evt2_j99dev_0 } },
};

const uint32_t * target_get_evt2_gpio_cfg(int gpioc)
{
	static const struct pinconfig_map *selected_map = NULL;

	if (selected_map == NULL) {
		uint32_t board_id = platform_get_board_id();
		for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
			if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
				selected_map = &cfg_map[i];
				break;
			}
		}

		if (selected_map == NULL)
			panic("no default pinconfig for board id %u", board_id);
	}

	ASSERT(gpioc < GPIOC_COUNT);
	return selected_map->pinconfigs[gpioc];
}
