/*
 * Copyright (C) 2014-2015 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */

/* THIS FILE IS AUTOMATICALLY GENERATED BY tools/csvtopinconfig.py. DO NOT EDIT!
   I/O Spreadsheet version: rev 2v7
   I/O Spreadsheet tracker: <rdar://problem/22973757> J42d: GPIO 178 Configuration Change
   Conversion command: ./tools/csvtopinconfig.py --soc fiji --radar '<rdar://problem/22973757> J42d: GPIO 178 Configuration Change' --copyright 2014-2015 <filename>
*/

#include <debug.h>
#include <drivers/apple/gpio.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <stdint.h>

enum {
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED_DRIVE_X4_FAST_SLEW,
	GPIOCFG_CFG_DISABLED_FAST_SLEW,
	GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_DISABLED_PULL_UP_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,
	GPIOCFG_CFG_FUNC0,
	GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW,
	GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_FUNC0_DRIVE_X4,
	GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW,
	GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW,
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_FUNC0_FAST_SLEW,
	GPIOCFG_CFG_FUNC0_FAST_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_FAST_SLEW,
	GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_FAST_SLEW,
	GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW,
	GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW,
	GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_FAST_SLEW,
	GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW,
	GPIOCFG_CFG_FUNC0_PULL_UP_FAST_SLEW,
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW,
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,
	GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW,
	GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_IN_PULL_UP_DRIVE_X4_SLOW_SLEW,
	GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW,
	GPIOCFG_CFG_IN_SLOW_SLEW,
	GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT,
	GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW,
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,
	GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW,
	GPIOCFG_CFG_OUT_1_SLOW_SLEW,
};


static const uint32_t enum_map[] = {
	[GPIOCFG_CFG_DISABLED] = CFG_DISABLED,
	[GPIOCFG_CFG_DISABLED_DRIVE_X4_FAST_SLEW] = CFG_DISABLED | DRIVE_X4 | FAST_SLEW,
	[GPIOCFG_CFG_DISABLED_FAST_SLEW] = CFG_DISABLED | FAST_SLEW,
	[GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT] = CFG_DISABLED | PULL_DOWN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW] = CFG_DISABLED | PULL_DOWN | SLOW_SLEW,
	[GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT] = CFG_DISABLED | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_DISABLED_PULL_UP_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT] = CFG_DISABLED | PULL_UP | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW] = CFG_DISABLED | PULL_UP | SLOW_SLEW,
	[GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW_INPUT_SCHMITT] = CFG_DISABLED | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_DISABLED_SLOW_SLEW] = CFG_DISABLED | SLOW_SLEW,
	[GPIOCFG_CFG_FUNC0] = CFG_FUNC0,
	[GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW] = CFG_FUNC0 | DRIVE_X2 | FAST_SLEW,
	[GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | DRIVE_X2 | FAST_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_FUNC0_DRIVE_X4] = CFG_FUNC0 | DRIVE_X4,
	[GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW] = CFG_FUNC0 | DRIVE_X4 | FAST_SLEW,
	[GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | DRIVE_X4 | FAST_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW] = CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW,
	[GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_FUNC0_FAST_SLEW] = CFG_FUNC0 | FAST_SLEW,
	[GPIOCFG_CFG_FUNC0_FAST_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | FAST_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_FAST_SLEW] = CFG_FUNC0 | PULL_DOWN | DRIVE_X2 | FAST_SLEW,
	[GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_FAST_SLEW] = CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | FAST_SLEW,
	[GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW] = CFG_FUNC0 | PULL_DOWN | DRIVE_X4 | SLOW_SLEW,
	[GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW] = CFG_FUNC0 | PULL_DOWN | SLOW_SLEW,
	[GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_FAST_SLEW] = CFG_FUNC0 | PULL_UP | DRIVE_X4 | FAST_SLEW,
	[GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW] = CFG_FUNC0 | PULL_UP | DRIVE_X4 | SLOW_SLEW,
	[GPIOCFG_CFG_FUNC0_PULL_UP_FAST_SLEW] = CFG_FUNC0 | PULL_UP | FAST_SLEW,
	[GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW] = CFG_FUNC0 | PULL_UP | SLOW_SLEW,
	[GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | PULL_UP | SLOW_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_FUNC0_SLOW_SLEW] = CFG_FUNC0 | SLOW_SLEW,
	[GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT] = CFG_FUNC0 | SLOW_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT] = CFG_IN | DRIVE_X4 | SLOW_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW] = CFG_IN | PULL_DOWN | SLOW_SLEW,
	[GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT] = CFG_IN | PULL_DOWN | SLOW_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_IN_PULL_UP_DRIVE_X4_SLOW_SLEW] = CFG_IN | PULL_UP | DRIVE_X4 | SLOW_SLEW,
	[GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW] = CFG_IN | PULL_UP | SLOW_SLEW,
	[GPIOCFG_CFG_IN_SLOW_SLEW] = CFG_IN | SLOW_SLEW,
	[GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT] = CFG_IN | SLOW_SLEW | INPUT_SCHMITT,
	[GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW] = CFG_OUT_0 | DRIVE_X4 | SLOW_SLEW,
	[GPIOCFG_CFG_OUT_0_SLOW_SLEW] = CFG_OUT_0 | SLOW_SLEW,
	[GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW] = CFG_OUT_1 | DRIVE_X4 | SLOW_SLEW,
	[GPIOCFG_CFG_OUT_1_SLOW_SLEW] = CFG_OUT_1 | SLOW_SLEW,
};


static const uint8_t pinconfig_ap_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//   0 : ULPI_DIR		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//   1 : ULPI_STP		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//   2 : ULPI_NXT		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//   3 : ULPI_DATA[7]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//   4 : ULPI_DATA[6]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//   5 : ULPI_DATA[5]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//   6 : ULPI_DATA[4]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//   7 : ULPI_CLK		-> NC

/* Port  1 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//   8 : ULPI_DATA[3]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//   9 : ULPI_DATA[2]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  10 : ULPI_DATA[1]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  11 : ULPI_DATA[0]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  12 : SPI1_SCLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  13 : SPI1_MOSI		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  14 : SPI1_MISO		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  15 : SPI1_SSIN		-> NC

/* Port  2 */
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port  3 */
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port  4 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  32 : GPIO[11]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  33 : GPIO[12]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  34 : I2S3_MCK		-> NC
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,					//  35 : I2S3_LRCK		-> I2S3_SOC2BT_LRCK
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,					//  36 : I2S3_BCLK		-> I2S3_SOC2BT_BCLK
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,					//  37 : I2S3_DOUT		-> I2S3_SOC2BT_DOUT
	GPIOCFG_CFG_FUNC0,						//  38 : I2S3_DIN		-> I2S3_BT2SOC_DIN
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  39 : CLK32K_OUT		-> NC

/* Port  5 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  40 : PCIE_CLKREQ0_N		-> NC_PCIE0_DEBUG2SOC_CLKREQ_L
	GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,			//  41 : PCIE_CLKREQ1_N		-> PCIE1_WLAN2SOC_CLKREQ_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  42 : NAND_SYS_CLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  43 : GPIO[0]		-> NC
	GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT,				//  44 : GPIO[1]		-> MCU_PMU_WAKE_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  45 : GPIO[2]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  46 : GPIO[3]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  47 : GPIO[4]		-> NC

/* Port  6 */
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,					//  48 : GPIO[5]		-> GPIO_SOC2BT_WAKE
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,					//  49 : GPIO[6]		-> AP_MCU_INT_1V8
	GPIOCFG_CFG_IN_PULL_UP_SLOW_SLEW,				//  50 : GPIO[7]		-> AP_TO_MCU_TCK_1V8
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  51 : GPIO[14]		-> NC
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,			//  52 : GPIO[16]		-> GPIO_BOARD_ID_3
	GPIOCFG_CFG_IN_SLOW_SLEW,					//  53 : GPIO[17]		-> NC
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT,		//  54 : GPIO[18]		-> GPIO_BOOT_CONFIG_0
	GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT,				//  55 : GPIO[20]		-> PMON_TO_SOC_INT_1V8_L

/* Port  7 */
	GPIOCFG_CFG_DISABLED_FAST_SLEW,					//  56 : GPIO[21]		-> NC
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW_INPUT_SCHMITT,		//  57 : UART5_RTXD		-> AP_UART5_SIL_TUNING_1V8
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  58 : UART8_TXD		-> NC_AP_UART8_TXD_1V8
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  59 : UART8_RXD		-> NC_AP_UART8_RXD_1V8
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,			//  60 : SPI0_SCLK		-> GPIO_BOARD_ID_0
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,			//  61 : SPI0_MOSI		-> GPIO_BOARD_ID_1
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,			//  62 : SPI0_MISO		-> GPIO_BOARD_ID_2
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,					//  63 : SPI0_SSIN		-> GPIO_SOC2WLAN_WAKE

/* Port  8 */
	GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW_INPUT_SCHMITT,		//  64 : I2C2_SDA		-> I2C2_DEBUG_SDA
	GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW_INPUT_SCHMITT,		//  65 : I2C2_SCL		-> I2C2_DEBUG_SCL
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,					//  66 : GPIO[22]		-> GPIO_SOC2PMU_KEEPACT
	GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT,				//  67 : GPIO[23]		-> GPIO_PMU2SOC_IRQ_L
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,				//  68 : GPIO[25]		-> GPIO_BOOT_CONFIG_1
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,				//  69 : GPIO[28]		-> GPIO_BOOT_CONFIG_2
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,				//  70 : GPIO[29]		-> GPIO_BOARD_ID_4
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,				//  71 : GPIO[34]		-> GPIO_BRD_REV3

/* Port  9 */
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,				//  72 : GPIO[35]		-> GPIO_BRD_REV2
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,				//  73 : GPIO[36]		-> GPIO_BRD_REV1
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,				//  74 : GPIO[37]		-> GPIO_BRD_REV0
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  75 : GPIO[39]		-> NC_AP_TO_PCIE0_RST_1V8_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  76 : GPIO[42]		-> NC
	GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT,				//  77 : GPIO[43]		-> PCIE1_SOC2WLAN_RESET_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					//  78 : DISP_VSYNC		-> NC
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW,				//  79 : UART0_TXD		-> AP_UART0_MCU_BSL_TXD_1V8

/* Port 10 */
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT,		//  80 : UART0_RXD		-> AP_UART0_MCU_BSL_RXD_1V8_R
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,			//  81 : TMR32_PWM0		-> WLAN_TO_AP_TMR32_PWM0
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,			//  82 : TMR32_PWM1		-> NC
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,			//  83 : TMR32_PWM2		-> NC
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW,				//  84 : UART6_TXD		-> AP_UART6_DEBUG_TXD_1V8
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT,		//  85 : UART6_RXD		-> AP_UART6_DEBUG_RXD_1V8
	GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,			//  86 : I2C3_SDA		-> I2C3_HOOVR_SDA
	GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,			//  87 : I2C3_SCL		-> I2C3_HOOVR_SCL

/* Port 11 */
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port 12 */
	GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,			//  96 : I2C0_SDA		-> I2C0_PMU_SDA
	GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,			//  97 : I2C0_SCL		-> I2C0_PMU_SCL
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,			//  98 : GPIO[38]		-> AP_MCU_REQUEST_DFU_1V8
	GPIOCFG_CFG_FUNC0_FAST_SLEW,					//  99 : UART2_TXD		-> AP_UART2_WLAN_TXD_1V8
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,					// 100 : UART2_RXD		-> AP_UART2_WLAN_RXD_1V8
	GPIOCFG_CFG_OUT_1_SLOW_SLEW,					// 101 : UART2_RTSN		-> AP_UART2_WLAN_RTS_1V8_L
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,					// 102 : UART2_CTSN		-> AP_UART2_WLAN_CTS_1V8_L
	GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_FAST_SLEW,			// 103 : DWI_DO			-> DWI_AP_DO

/* Port 13 */
	GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X2_FAST_SLEW,			// 104 : DWI_CLK		-> DWI_AP_CLK
	GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW,				// 105 : WDOG			-> WDOG_SOC2PMU_RESET_IN
	GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT,		// 106 : GPIO[13]		-> HVR_IRQ
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,					// 107 : GPIO[19]		-> PMON_SWCLK
	GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT,				// 108 : GPIO[26]		-> MCU2SOC_FORCE_DFU_1V8
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,					// 109 : GPIO[27]		-> MCU_DFU_STATUS_1V8
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW,				// 110 : SOCHOT0		-> SOCHOT0_L
	GPIOCFG_CFG_FUNC0_FAST_SLEW_INPUT_SCHMITT,			// 111 : SOCHOT1		-> SOCHOT1_L

/* Port 14 */
	GPIOCFG_CFG_DISABLED,						// 112 : UNSPECIFIED		-> UNSPECIFIED
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,			// 113 : TST_CLKOUT		-> AP_TO_PMU_TEST_CLKOUT
	GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT,				// 114 : GPIO[8]		-> LAN_PHY_INT_1V8
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 115 : GPIO[9]		-> GPIO9_TEST_POINT
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,					// 116 : GPIO[10]		-> SOC2LAN_PME_MODE_1V8
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 117 : GPIO[15]		-> PMON_SWDIO
	GPIOCFG_CFG_FUNC0_PULL_UP_FAST_SLEW,				// 118 : UART4_TXD		-> AP_UART4_PMON_TXD_1V8
	GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,			// 119 : UART4_RXD		-> AP_UART4_PMON_RXD_1V8

/* Port 15 */
	GPIOCFG_CFG_DISABLED_FAST_SLEW,					// 120 : UART4_RTSN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 121 : UART4_CTSN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 122 : SPI3_MOSI		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 123 : SPI3_MISO		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 124 : SPI3_SCLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 125 : SPI3_SSIN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 126 : GPIO[24]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 127 : GPIO[30]		-> NC

/* Port 16 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 128 : GPIO[31]		-> PMON_RST_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 129 : GPIO[32]		-> PMON_ISP_EN_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 130 : GPIO[33]		-> SOC_TO_MCU_RESET_1V8_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 131 : GPIO[40]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 132 : GPIO[41]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 133 : I2S4_MCK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 134 : I2S4_LRCK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 135 : I2S4_BCLK		-> NC

/* Port 17 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 136 : I2S4_DOUT		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 137 : I2S4_DIN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 138 : I2C1_SDA		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 139 : I2C1_SCL		-> NC
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port 18 */
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port 19 */
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port 20 */
	GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW,				// 160 : I2S0_LRCK		-> I2S0_HOOVR_LRCK
	GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW,				// 161 : I2S0_BCLK		-> I2S0_HOOVR_BCLK
	GPIOCFG_CFG_FUNC0_PULL_DOWN_SLOW_SLEW,				// 162 : I2S0_DOUT		-> I2S0_HOOVR_DOUT
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 163 : I2S0_DIN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 164 : I2S1_MCK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 165 : I2S1_LRCK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 166 : I2S1_BCLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 167 : I2S1_DOUT		-> NC

/* Port 21 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 168 : I2S1_DIN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 169 : I2S2_LRCK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 170 : I2S2_BCLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 171 : I2S2_DOUT		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 172 : I2S2_DIN		-> NC
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,					// 173 : UART1_TXD		-> AP_UART1_BT_TXD_1V8
	GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,			// 174 : UART1_RXD		-> AP_UART1_BT_RXD_1V8
	GPIOCFG_CFG_OUT_1_SLOW_SLEW,					// 175 : UART1_RTSN		-> AP_UART1_BT_RTS_1V8_L

/* Port 22 */
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW,				// 176 : UART1_CTSN		-> AP_UART1_BT_CTS_1V8_L
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,					// 177 : EDP_HPD		-> EPD_HPD_1V8
	GPIOCFG_CFG_FUNC0_DRIVE_X2_FAST_SLEW,				// 178 : UART3_TXD		-> AP_UART3_MCU_COMMS_TXD_1V8
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,					// 179 : UART3_RXD		-> AP_UART3_MCU_COMMS_RXD_1V8_R
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 180 : UART3_RTSN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 181 : UART3_CTSN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 182 : SPI2_SCLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 183 : SPI2_MOSI		-> NC

/* Port 23 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 184 : SPI2_MISO		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 185 : SPI2_SSIN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 186 : ISP0_SDA		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 187 : ISP0_SCL		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 188 : ISP1_SDA		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 189 : ISP1_SCL		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 190 : SENSOR0_RST		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 191 : SENSOR0_CLK		-> NC

/* Port 24 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 192 : SENSOR0_XSHUTDOWN	-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 193 : SENSOR0_ISTRB		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 194 : ISP_UART0_TXD		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 195 : ISP_UART0_RXD		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 196 : SENSOR1_RST		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 197 : SENSOR1_CLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 198 : SENSOR1_XSHUTDOWN	-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 199 : SENSOR1_ISTRB		-> NC

/* Port 25 */
	GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW,				// 200 : UART7_TXD		-> NC_AP_UART7_ASTRIS_TXD_1V8
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,					// 201 : UART7_RXD		-> NC_AP_UART7_ASTRIS_RXD_1V8
	GPIOCFG_CFG_FUNC0_FAST_SLEW,					// 202 : I2S0_MCK		-> I2S0_HOOVR_MCK
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,					// 203 : I2S2_MCK		-> NC
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
};

static const uint8_t pinconfig_dev_0[GPIO_GROUP_COUNT * GPIOPADPINS] = {

/* Port  0 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//   0 : ULPI_DIR		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//   1 : ULPI_STP		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//   2 : ULPI_NXT		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//   3 : ULPI_DATA[7]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//   4 : ULPI_DATA[6]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//   5 : ULPI_DATA[5]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//   6 : ULPI_DATA[4]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//   7 : ULPI_CLK		-> NC

/* Port  1 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//   8 : ULPI_DATA[3]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//   9 : ULPI_DATA[2]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  10 : ULPI_DATA[1]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  11 : ULPI_DATA[0]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  12 : SPI1_SCLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  13 : SPI1_MOSI		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  14 : SPI1_MISO		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  15 : SPI1_SSIN		-> NC

/* Port  2 */
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port  3 */
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port  4 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  32 : GPIO[11]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  33 : GPIO[12]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  34 : I2S3_MCK		-> NC
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW,					//  35 : I2S3_LRCK		-> I2S3_SOC2BT_LRCK
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW,					//  36 : I2S3_BCLK		-> I2S3_SOC2BT_BCLK
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW,					//  37 : I2S3_DOUT		-> I2S3_SOC2BT_DOUT
	GPIOCFG_CFG_FUNC0_DRIVE_X4,						//  38 : I2S3_DIN		-> I2S3_BT2SOC_DIN
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  39 : CLK32K_OUT		-> NC

/* Port  5 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  40 : PCIE_CLKREQ0_N		-> NC_PCIE0_DEBUG2SOC_CLKREQ_L
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,			//  41 : PCIE_CLKREQ1_N		-> PCIE1_WLAN2SOC_CLKREQ_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  42 : NAND_SYS_CLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  43 : GPIO[0]		-> NC
	GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,			//  44 : GPIO[1]		-> MCU_PMU_WAKE_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  45 : GPIO[2]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  46 : GPIO[3]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  47 : GPIO[4]		-> NC

/* Port  6 */
	GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW,					//  48 : GPIO[5]		-> GPIO_SOC2BT_WAKE
	GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW,					//  49 : GPIO[6]		-> AP_MCU_INT_1V8
	GPIOCFG_CFG_IN_PULL_UP_DRIVE_X4_SLOW_SLEW,				//  50 : GPIO[7]		-> AP_TO_MCU_TCK_1V8
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  51 : GPIO[14]		-> NC
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,				//  52 : GPIO[16]		-> GPIO_BOARD_ID_3
	GPIOCFG_CFG_IN_SLOW_SLEW,						//  53 : GPIO[17]		-> NC
	GPIOCFG_CFG_DISABLED_PULL_DOWN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,	//  54 : GPIO[18]		-> GPIO_BOOT_CONFIG_0
	GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,			//  55 : GPIO[20]		-> PMON_TO_SOC_INT_1V8_L

/* Port  7 */
	GPIOCFG_CFG_DISABLED_DRIVE_X4_FAST_SLEW,				//  56 : GPIO[21]		-> NC
	GPIOCFG_CFG_DISABLED_PULL_UP_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,		//  57 : UART5_RTXD		-> AP_UART5_SIL_TUNING_1V8
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  58 : UART8_TXD		-> NC_AP_UART8_TXD_1V8
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  59 : UART8_RXD		-> NC_AP_UART8_RXD_1V8
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,				//  60 : SPI0_SCLK		-> GPIO_BOARD_ID_0
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,				//  61 : SPI0_MOSI		-> GPIO_BOARD_ID_1
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,				//  62 : SPI0_MISO		-> GPIO_BOARD_ID_2
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,						//  63 : SPI0_SSIN		-> GPIO_SOC2WLAN_WAKE

/* Port  8 */
	GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW_INPUT_SCHMITT,			//  64 : I2C2_SDA		-> I2C2_DEBUG_SDA
	GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW_INPUT_SCHMITT,			//  65 : I2C2_SCL		-> I2C2_DEBUG_SCL
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,						//  66 : GPIO[22]		-> GPIO_SOC2PMU_KEEPACT
	GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,			//  67 : GPIO[23]		-> GPIO_PMU2SOC_IRQ_L
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,					//  68 : GPIO[25]		-> GPIO_BOOT_CONFIG_1
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,					//  69 : GPIO[28]		-> GPIO_BOOT_CONFIG_2
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,					//  70 : GPIO[29]		-> GPIO_BOARD_ID_4
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,					//  71 : GPIO[34]		-> GPIO_BRD_REV3

/* Port  9 */
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,					//  72 : GPIO[35]		-> GPIO_BRD_REV2
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,					//  73 : GPIO[36]		-> GPIO_BRD_REV1
	GPIOCFG_CFG_DISABLED_PULL_UP_SLOW_SLEW,					//  74 : GPIO[37]		-> GPIO_BRD_REV0
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  75 : GPIO[39]		-> NC_AP_TO_PCIE0_RST_1V8_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  76 : GPIO[42]		-> NC
	GPIOCFG_CFG_IN_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,			//  77 : GPIO[43]		-> PCIE1_SOC2WLAN_RESET_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						//  78 : DISP_VSYNC		-> NC
	GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW,				//  79 : UART0_TXD		-> AP_UART0_MCU_BSL_TXD_1V8

/* Port 10 */
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT,			//  80 : UART0_RXD		-> AP_UART0_MCU_BSL_RXD_1V8_R
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,				//  81 : TMR32_PWM0		-> WLAN_TO_AP_TMR32_PWM0
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,				//  82 : TMR32_PWM1		-> NC
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,				//  83 : TMR32_PWM2		-> NC
	GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_SLOW_SLEW,				//  84 : UART6_TXD		-> AP_UART6_DEBUG_TXD_1V8
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW_INPUT_SCHMITT,			//  85 : UART6_RXD		-> AP_UART6_DEBUG_RXD_1V8
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,			//  86 : I2C3_SDA		-> I2C3_HOOVR_SDA
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,			//  87 : I2C3_SCL		-> I2C3_HOOVR_SCL

/* Port 11 */
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port 12 */
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,			//  96 : I2C0_SDA		-> I2C0_PMU_SDA
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW_INPUT_SCHMITT,			//  97 : I2C0_SCL		-> I2C0_PMU_SCL
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,				//  98 : GPIO[38]		-> AP_MCU_REQUEST_DFU_1V8
	GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW,					//  99 : UART2_TXD		-> AP_UART2_WLAN_TXD_1V8
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW,					// 100 : UART2_RXD		-> AP_UART2_WLAN_RXD_1V8
	GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW,					// 101 : UART2_RTSN		-> AP_UART2_WLAN_RTS_1V8_L
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW,					// 102 : UART2_CTSN		-> AP_UART2_WLAN_CTS_1V8_L
	GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_FAST_SLEW,				// 103 : DWI_DO			-> DWI_AP_DO

/* Port 13 */
	GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_FAST_SLEW,				// 104 : DWI_CLK		-> DWI_AP_CLK
	GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW,				// 105 : WDOG			-> WDOG_SOC2PMU_RESET_IN
	GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW_INPUT_SCHMITT,			// 106 : GPIO[13]		-> HVR_IRQ
	GPIOCFG_CFG_OUT_0_DRIVE_X4_SLOW_SLEW,					// 107 : GPIO[19]		-> PMON_SWCLK
	GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT,					// 108 : GPIO[26]		-> MCU2SOC_FORCE_DFU_1V8
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,						// 109 : GPIO[27]		-> MCU_DFU_STATUS_1V8
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW,					// 110 : SOCHOT0		-> SOCHOT0_L
	GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW_INPUT_SCHMITT,			// 111 : SOCHOT1		-> SOCHOT1_L

/* Port 14 */
	GPIOCFG_CFG_DISABLED,							// 112 : UNSPECIFIED		-> UNSPECIFIED
	GPIOCFG_CFG_DISABLED_PULL_DOWN_SLOW_SLEW,				// 113 : TST_CLKOUT		-> AP_TO_PMU_TEST_CLKOUT
	GPIOCFG_CFG_IN_SLOW_SLEW_INPUT_SCHMITT,					// 114 : GPIO[8]		-> LAN_PHY_INT_1V8
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 115 : GPIO[9]		-> GPIO9_TEST_POINT
	GPIOCFG_CFG_OUT_0_SLOW_SLEW,						// 116 : GPIO[10]		-> SOC2LAN_PME_MODE_1V8
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 117 : GPIO[15]		-> PMON_SWDIO
	GPIOCFG_CFG_FUNC0_PULL_UP_DRIVE_X4_FAST_SLEW,				// 118 : UART4_TXD		-> AP_UART4_PMON_TXD_1V8
	GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,				// 119 : UART4_RXD		-> AP_UART4_PMON_RXD_1V8

/* Port 15 */
	GPIOCFG_CFG_DISABLED_FAST_SLEW,						// 120 : UART4_RTSN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 121 : UART4_CTSN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 122 : SPI3_MOSI		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 123 : SPI3_MISO		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 124 : SPI3_SCLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 125 : SPI3_SSIN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 126 : GPIO[24]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 127 : GPIO[30]		-> NC

/* Port 16 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 128 : GPIO[31]		-> PMON_RST_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 129 : GPIO[32]		-> PMON_ISP_EN_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 130 : GPIO[33]		-> SOC_TO_MCU_RESET_1V8_L
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 131 : GPIO[40]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 132 : GPIO[41]		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 133 : I2S4_MCK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 134 : I2S4_LRCK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 135 : I2S4_BCLK		-> NC

/* Port 17 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 136 : I2S4_DOUT		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 137 : I2S4_DIN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 138 : I2C1_SDA		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 139 : I2C1_SCL		-> NC
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port 18 */
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port 19 */
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,

/* Port 20 */
	GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW,				// 160 : I2S0_LRCK		-> I2S0_HOOVR_LRCK
	GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW,				// 161 : I2S0_BCLK		-> I2S0_HOOVR_BCLK
	GPIOCFG_CFG_FUNC0_PULL_DOWN_DRIVE_X4_SLOW_SLEW,				// 162 : I2S0_DOUT		-> I2S0_HOOVR_DOUT
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 163 : I2S0_DIN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 164 : I2S1_MCK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 165 : I2S1_LRCK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 166 : I2S1_BCLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 167 : I2S1_DOUT		-> NC

/* Port 21 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 168 : I2S1_DIN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 169 : I2S2_LRCK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 170 : I2S2_BCLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 171 : I2S2_DOUT		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 172 : I2S2_DIN		-> NC
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW,					// 173 : UART1_TXD		-> AP_UART1_BT_TXD_1V8
	GPIOCFG_CFG_FUNC0_SLOW_SLEW_INPUT_SCHMITT,				// 174 : UART1_RXD		-> AP_UART1_BT_RXD_1V8
	GPIOCFG_CFG_OUT_1_DRIVE_X4_SLOW_SLEW,					// 175 : UART1_RTSN		-> AP_UART1_BT_RTS_1V8_L

/* Port 22 */
	GPIOCFG_CFG_FUNC0_PULL_UP_SLOW_SLEW,					// 176 : UART1_CTSN		-> AP_UART1_BT_CTS_1V8_L
	GPIOCFG_CFG_FUNC0_DRIVE_X4_SLOW_SLEW,					// 177 : EDP_HPD		-> EPD_HPD_1V8
	GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW,					// 178 : UART3_TXD		-> AP_UART3_MCU_COMMS_TXD_1V8
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,						// 179 : UART3_RXD		-> AP_UART3_MCU_COMMS_RXD_1V8_R
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 180 : UART3_RTSN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 181 : UART3_CTSN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 182 : SPI2_SCLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 183 : SPI2_MOSI		-> NC

/* Port 23 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 184 : SPI2_MISO		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 185 : SPI2_SSIN		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 186 : ISP0_SDA		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 187 : ISP0_SCL		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 188 : ISP1_SDA		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 189 : ISP1_SCL		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 190 : SENSOR0_RST		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 191 : SENSOR0_CLK		-> NC

/* Port 24 */
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 192 : SENSOR0_XSHUTDOWN	-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 193 : SENSOR0_ISTRB		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 194 : ISP_UART0_TXD		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 195 : ISP_UART0_RXD		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 196 : SENSOR1_RST		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 197 : SENSOR1_CLK		-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 198 : SENSOR1_XSHUTDOWN	-> NC
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 199 : SENSOR1_ISTRB		-> NC

/* Port 25 */
	GPIOCFG_CFG_IN_PULL_DOWN_SLOW_SLEW,					// 200 : UART7_TXD		-> NC_AP_UART7_ASTRIS_TXD_1V8
	GPIOCFG_CFG_FUNC0_SLOW_SLEW,						// 201 : UART7_RXD		-> NC_AP_UART7_ASTRIS_RXD_1V8
	GPIOCFG_CFG_FUNC0_DRIVE_X4_FAST_SLEW,					// 202 : I2S0_MCK		-> I2S0_HOOVR_MCK
	GPIOCFG_CFG_DISABLED_SLOW_SLEW,						// 203 : I2S2_MCK		-> NC
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
	GPIOCFG_CFG_DISABLED,
};

struct pinconfig_map {
	uint32_t board_id;
	uint32_t board_id_mask;
	const uint8_t *pinconfigs[GPIOC_COUNT];
};

static const struct pinconfig_map cfg_map[] = {
	{ 0, 1, { pinconfig_ap_0 } },
	{ 1, 1, { pinconfig_dev_0 } },
};

static uint32_t *expanded_pinconfigs[GPIOC_COUNT];

static const uint32_t controller_pins[GPIOC_COUNT] = {
	GPIO_GROUP_COUNT * GPIOPADPINS,
};

const uint32_t * target_get_default_gpio_cfg(uint32_t gpioc)
{
	static const struct pinconfig_map *selected_map = NULL;

	/* Cannot use malloc as chunk manager is yet to be intialized */
	static uint32_t pinconfig_buf[GPIO_GROUP_COUNT * GPIOPADPINS];
	expanded_pinconfigs[0] = pinconfig_buf;

	ASSERT(gpioc < GPIOC_COUNT);

	if (selected_map == NULL) {
		uint32_t board_id = platform_get_board_id();
		for (unsigned i = 0; i < sizeof(cfg_map)/sizeof(cfg_map[0]); i++) {
			if ((board_id & cfg_map[i].board_id_mask) == cfg_map[i].board_id) {
				selected_map = &cfg_map[i];
				break;
			}
		}

		if (selected_map == NULL)
			panic("no default pinconfig for board id %u", board_id);

		for (unsigned i = 0; i < GPIOC_COUNT; i++) {
			uint32_t num_pins = controller_pins[i];

			for (uint32_t j = 0; j < num_pins; j++) {
				uint8_t enum_key = selected_map->pinconfigs[i][j];
				expanded_pinconfigs[i][j] = enum_map[enum_key];
			}
		}
	}

	return expanded_pinconfigs[gpioc];
}
