/*
 * Copyright (C) 2009-2013 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */

/* Default n78 SoC Pin Configuration */

/* Same drive strength for AP and DEV */
#define AUD_SPKRAMP_MUTE_L_DRIVE_STR	DRIVE_X1
#define DFU_STATUS_DRIVE_STR		DRIVE_X1
#define DWI_DRIVE_STR			DRIVE_X1
#define FMI_DRIVE_STR			DRIVE_X2	// SecureROM is X2
#define GRAPE_DRIVE_STR			DRIVE_X1
#define MLC_DRIVE_STR			DRIVE_X1
#define PM_BT_WAKE_DRIVE_STR		DRIVE_X1
#define PM_CAM_SHUTDOWN_DRIVE_STR	DRIVE_X1
#define CLK_CAM_DRIVE_STR		DRIVE_X1
#define PM_KEEPACT_DRIVE_STR		DRIVE_X1
#define RST_PMU_IN_DRIVE_STR		DRIVE_X1
#define SDIO_WL_DRIVE_STR		DRIVE_X1
#define VIDEO_AMP_EN_DRIVE_STR		DRIVE_X1
#define I2C_DRIVE_STR			DRIVE_X1
#define UART_5_DRIVE_STR		DRIVE_X2
#define I2S_DRIVE_STR			DRIVE_X1
#define I2S_MCK_DRIVE_STR		DRIVE_X1
#define SPI_CS_DRIVE_STR		DRIVE_X1
#define SPI_DATA_DRIVE_STR		DRIVE_X1

/* Different drive strength for AP and DEV.		// AP DEV */
#if PIN_CFG_AP
#define BT_UART_DRIVE_STR		DRIVE_X1	// X2 X3
#define UART_0_DRIVE_STR		DRIVE_X1	// X2 X3
#else
#define BT_UART_DRIVE_STR		DRIVE_X1	// X2 X3
#define UART_0_DRIVE_STR		DRIVE_X1	// X2 X2
#endif

#define FMI_SLEW_RATE			SLEW_RATE_SLOW

#if PIN_CFG_AP
static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#elif PIN_CFG_DEV
static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#endif
/* Port  0 */
	CFG_IN,								// GPIO0		-> MENU_KEY (REQUEST_DFU2)
	CFG_IN,								// GPIO1		-> HOLD_KEY (REQUEST_DFU1)
	CFG_IN | PULL_UP,						// GPIO2		-> VOL_UP_L
	CFG_IN | PULL_UP,						// GPIO3		-> VOL_DOWN_L
	CFG_OUT_0,							// GPIO4		-> ACC_UHPM_EN
	CFG_IN | PULL_UP,						// GPIO5		-> SPKR_AMP_INT_L
	CFG_IN | PULL_DOWN,						// GPIO6		-> WLAN_HSIC_OOB
	CFG_OUT_0,							// GPIO7		-> BT_WAKE

/* Port  1 */
	CFG_OUT_0,							// GPIO8		-> WLAN_HSIC_AP_RDY
	CFG_IN | PULL_DOWN,						// GPIO9		-> WLAN_HSIC_DEV_RDY
	CFG_OUT_0,							// GPIO10		-> STAYIN_ALIVE
	CFG_OUT_1,							// GPIO11		-> CAM_REAR_EXT_LDO_EN
	CFG_OUT_1,							// GPIO12		-> CAM_FRONT_EXT_LDO_EN
	CFG_IN | PULL_UP,						// GPIO13		-> IRQ_PMU_L
	CFG_OUT_0,							// GPIO14		-> GRAPE_RESET_L
	CFG_OUT_0,							// GPIO15		-> SPKR_AMP_RESET_L

/* Port  2 */
	CFG_IN,								// GPIO16		-> BOARD_ID_3
	CFG_IN,								// GPIO17		-> BRD_REV3
	CFG_IN | PULL_DOWN,						// GPIO18		-> BOOT_CONFIG_0
	CFG_OUT_0 | PM_KEEPACT_DRIVE_STR,				// GPIO19		-> PM_KEEPACT
	CFG_IN,						// GPIO20		-> TRISTAR_INT
	CFG_IN | PULL_UP,						// GPIO21		-> GRAPE_INT_L
	CFG_OUT_0 | GRAPE_DRIVE_STR,					// GPIO22		-> LCD_RESET_L
	CFG_IN,						// GPIO23		-> LCD_HIFA_BSYNC

/* Port  3 */
	CFG_DISABLED | PULL_DOWN,							// GPIO24		->
	CFG_IN | PULL_DOWN,						// GPIO25		-> BOOT_CONFIG_1
	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
	CFG_OUT_0 | DFU_STATUS_DRIVE_STR,			// GPIO27		-> DFU_STATUS
	CFG_IN,								// GPIO28		-> BOOT_CONFIG_2
	CFG_IN,								// GPIO29		-> BOOT_CONFIG_3
	CFG_IN | PULL_UP,						// GPIO30		-> CODEC_INT_L
	CFG_DISABLED | PULL_DOWN,							// GPIO31		->

/* Port  4 */
	CFG_DISABLED | PULL_DOWN,							// GPIO32		->
	CFG_IN,						// GPIO33		-> IRQ_GYRO_INT1
	CFG_IN,								// GPIO34		-> ACC_UHPM_POK
	CFG_DISABLED | PULL_DOWN,							// GPIO35		->
	CFG_IN,						// GPIO36		-> ACCEL_INT2_L
	CFG_IN,								// EHCI_PORT_PWR[0]	-> AP_GPIO37_BRD_REV0
	CFG_IN,								// EHCI_PORT_PWR[1]	-> AP_GPIO38_BRD_REV1
	CFG_IN,								// EHCI_PORT_PWR[2]	-> AP_GPIO39_BRD_REV2

/* Port  5 */
	CFG_FUNC0,							// UART1_TXD		-> UART1_TXD_AP_DBG
	CFG_FUNC0,							// UART1_RXD		-> UART1_RXD_AP_DBG
	CFG_DISABLED | PULL_DOWN,					// UART1_RTSN		->
	CFG_DISABLED | PULL_DOWN,					// UART1_CTSN		->
	CFG_FUNC0,							// UART2_TXD		-> UART2_TXD_ACC
	CFG_FUNC0,							// UART2_RXD		-> UART2_RXD_ACC
	CFG_IN,								// UART2_RTSN		-> CAM_STROBE_EN
	CFG_DISABLED | PULL_DOWN,					// UART2_CTSN		->

/* Port  6 */
	CFG_FUNC0 | BT_UART_DRIVE_STR,					// UART3_TXD		-> UART_3_TXD_BT
	CFG_FUNC0,							// UART3_RXD		-> UART_3_RXD_BT
	CFG_OUT_1 | BT_UART_DRIVE_STR,					// UART3_RTSN		-> UART_3_CTS_L_BT
	CFG_FUNC0,							// UART3_CTSN		-> UART_3_RTS_L_BT
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C0_SDA		-> I2C0_SDA_1V8
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C0_SCL		-> I2C0_SCL_1V8
	CFG_DISABLED | PULL_DOWN,					// I2C1_SDA		->
	CFG_DISABLED | PULL_DOWN,					// I2C1_SCL		->

/* Port  7 */
	CFG_FUNC0 | I2C_DRIVE_STR,					// ISP0_SDA		-> I2C_CAM_REAR_SDA_1V8
	CFG_FUNC0 | I2C_DRIVE_STR,					// ISP0_SCL		-> I2C_CAM_REAR_SCL_1V8
	CFG_FUNC0 | I2C_DRIVE_STR,					// ISP1_SDA		-> I2C_FRONT_SDA_1V8
	CFG_FUNC0 | I2C_DRIVE_STR,					// ISP1_SCL		-> I2C_FRONT_SCL_1V8
	CFG_DISABLED | PULL_DOWN,					// UART5_TXD/MIPI_VSYNC	->
	CFG_FUNC0 | PULL_DOWN,						// TMR32_PWM0		-> GYRO_INT2
	CFG_FUNC0 | PULL_DOWN,						// TMR32_PWM1		-> ACCEL_INT1_L
	CFG_FUNC0 | GRAPE_DRIVE_STR,					// TMR32_PWM2		-> CLK32K_GRAPE_CLK

/* Port  8 */
	CFG_DISABLED | PULL_DOWN,					// SWI_DATA		->
	CFG_FUNC0 | DWI_DRIVE_STR,					// DWI_DI		-> DWI_AP_DI
	CFG_FUNC0 | DWI_DRIVE_STR,					// DWI_DO		-> DWI_AP_DO
	CFG_FUNC0 | DWI_DRIVE_STR,					// DWI_CLK		-> DWI_AP_CLK
	CFG_OUT_1 | PM_CAM_SHUTDOWN_DRIVE_STR,				// SENSOR0_RST		-> PM_REAR_CAM_SHUTDOWN_L
	CFG_OUT_0 | CLK_CAM_DRIVE_STR,					// SENSOR0_CLK		-> CLK_CAM_RF
	CFG_OUT_1 | PM_CAM_SHUTDOWN_DRIVE_STR,				// SENSOR1_RST		-> PM_FRONT_CAM_SHUTDOWN
	CFG_OUT_0 | CLK_CAM_DRIVE_STR,					// SENSOR1_CLK		-> CLK_CAM_FF

/* Port  9 */
	CFG_OUT_0,							// ISP0_PRE_FLASH	-> CAM_REAR_TORCH
	CFG_DISABLED | PULL_DOWN,							// ISP0_FLASH		-> CAM_REAR_RESET_L
	CFG_DISABLED | PULL_DOWN,							// ISP1_PRE_FLASH	->
	CFG_DISABLED | PULL_DOWN,							// ISP1_FLASH		-> CAM_FRONT_RESET_L
	CFG_FUNC0 | I2S_MCK_DRIVE_STR,					// I2S0_MCK		-> I2S_AP_0_MCK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S0_LRCK		-> I2S_AP_0_LRCK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S0_SCLK		-> I2S_AP_0_BCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S0_DOUT		-> I2S_AP_0_DOUT

/* Port 10 */
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S0_DIN		-> I2S_AP_0_DIN
	CFG_DISABLED | PULL_DOWN,							// I2S1_MCK		->
	CFG_FUNC0 | I2S_DRIVE_STR,							// I2S1_LRCK		-> BT_PCM_SYNC
	CFG_FUNC0 | I2S_DRIVE_STR,							// I2S1_SCLK		-> BT_PCM_CLK
	CFG_FUNC0 | I2S_DRIVE_STR,							// I2S1_DOUT		-> BT_PCM_IN
	CFG_FUNC0 | I2S_DRIVE_STR,							// I2S1_DIN		-> BT_PCM_OUT
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S2_MCK		-> SPKR_AMP_PCM_MCLK_R
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S2_LRCK		-> SPKR_AMP_PCM_FSYNC_R

/* Port 11 */
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S2_BCLK		-> SPKR_AMP_PCM_BITCLK_R
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S2_DOUT		-> SPKR_AMP_PCM_DOUT_R
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S2_DIN		-> SPKR_AMP_PCM_DIN_R
	CFG_DISABLED | PULL_DOWN,							// I2S3_MCK		->
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S3_LRCK		-> CODEC_XSP_MCLK_R
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S3_BCLK		-> CODEC_XSP_FSYNC_R
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S3_DOUT		-> CODEC_XSP_DOUT_R
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S3_DIN		-> CODEC_XSP_DIN_R

/* Port 12 */
	CFG_IN,								// SPI0_SCLK		-> BOARD_ID_0
	CFG_IN,								// SPI0_MOSI		-> BOARD_ID_1
	CFG_IN,								// SPI0_MISO		-> BOARD_ID_2
	CFG_OUT_1,						// SPI0_SSIN		-> LCD_PIFA_R
	CFG_FUNC0 | SPI_DATA_DRIVE_STR,					// SPI1_SCLK		-> SPI_GRAPE_SCLK
	CFG_FUNC0 | SPI_DATA_DRIVE_STR,					// SPI1_MOSI		-> SPI_GRAPE_MOSI
	CFG_FUNC0,							// SPI1_MISO		-> SPI_GRAPE_MISO
	CFG_FUNC0 | SPI_CS_DRIVE_STR,					// SPI1_SSIN		-> SPI_GRAPE_CS_L

/* Port 13 */
	CFG_FUNC0,							// SPI2_SCLK		-> SPI_CODEC_CLK
	CFG_FUNC0,							// SPI2_MOSI		-> SPI_CODEC_MOSI
	CFG_FUNC0,							// SPI2_MISO		-> SPI_CODEC_MISO
	CFG_FUNC0,							// SPI2_SSIN		-> SPI_CODEC_SSN
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->

/* Port 14 */
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->

/* Port 15 */
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->

/* Port 16 */
	CFG_FUNC0 | MLC_DRIVE_STR,					// UART4_TXD		-> WLAN_DBG_UART_RXD
	CFG_FUNC0 | MLC_DRIVE_STR,						// UART4_RXD		-> WLAN_DBG_UART_TXD
	CFG_DISABLED | PULL_DOWN,							// UART4_RTSN		->
	CFG_OUT_0,							// UART4_CTSN		-> PMU_AMUX_AY_CTRL
	CFG_DISABLED | PULL_DOWN,							// SDIO0_DATA3		->
	CFG_DISABLED | PULL_DOWN,							// SDIO0_DATA2		->
	CFG_DISABLED | PULL_DOWN,							// SDIO0_DATA1		->
	CFG_DISABLED | PULL_DOWN,							// SDIO0_DATA0		->

/* Port 17 */
	CFG_DISABLED | PULL_DOWN,							// SDIO0_CMD		->
	CFG_DISABLED | PULL_DOWN,							// SDIO0_CLK		->
	CFG_DISABLED | PULL_DOWN,							// FMI0_CEN3		-> F0CE3_L
	CFG_DISABLED | PULL_DOWN,							// FMI0_CEN2		-> F0CE2_L
	CFG_DISABLED | PULL_DOWN,							// FMI0_CEN1		-> F0CE1_L
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI0_CEN0		-> F0CE0_L
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI0_CLE		-> F0CLE
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI0_ALE		-> F0ALE

/* Port 18 */
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI0_REN		-> F0RE_L
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI0_WEN		-> F0WE_L
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI0_IO7		-> F0AD<7>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI0_IO6		-> F0AD<6>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI0_IO5		-> F0AD<5>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI0_IO4		-> F0AD<4>
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->

/* Port 19 */
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->

/* Port 20 */
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI0_DQS		-> F0DQS
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI0_IO3		-> F0AD<3>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI0_IO2		-> F0AD<2>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI0_IO1		-> F0AD<1>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI0_IO0		-> F0AD<0>
	CFG_DISABLED | PULL_DOWN,							// FMI1_CEN3		->
	CFG_DISABLED | PULL_DOWN,							// FMI1_CEN2		->
	CFG_DISABLED | PULL_DOWN,							// FMI1_CEN1		->

/* Port 21 */
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI1_CEN0		-> F1CE0_L
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI1_CLE		-> F1CLE
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI1_ALE		-> F1ALE
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI1_REN		-> F1RE_L
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI1_WEN		-> F1WE_L
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI1_IO7		-> F1AD<7>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI1_IO6		-> F1AD<6>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI1_IO5		-> F1AD<5>

/* Port 22 */
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI1_IO4		-> F1AD<4>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI1_DQS		-> FMI1DQS
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI1_IO3		-> F1AD<3>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI1_IO2		-> F1AD<2>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI1_IO1		-> F1AD<1>
	CFG_FUNC0 | FMI_DRIVE_STR | BUS_HOLD,				// FMI1_IO0		-> F1AD<0>
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->

/* Port 23 */
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->

/* Port 24 */
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C2_SDA		-> I2C2_SDA_1V8
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C2_SCL		-> I2C2_SCL_1V8
	CFG_OUT_0,							// UART0_TXD		-> CAM_FLASH_EN
	CFG_DISABLED | PULL_DOWN,					// UART0_RXD		->
	CFG_DISABLED | PULL_DOWN,					// UART5_RTXD		->
	CFG_DISABLED | PULL_DOWN,							// DP_HPD		->
	CFG_DISABLED | PULL_DOWN,							// TST_CLKOUT		->
	CFG_DISABLED | PULL_DOWN,							// TST_STPCLK		-> GND

/* Port 25 */
	CFG_FUNC0 | RST_PMU_IN_DRIVE_STR,				// WDOG			-> RST_PMU_IN
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
	CFG_DISABLED | PULL_DOWN,							// 			->
};

#undef AUD_SPKRAMP_MUTE_L_DRIVE_STR
#undef DFU_STATUS_DRIVE_STR
#undef DWI_DRIVE_STR
#undef FMI_DRIVE_STR
#undef GRAPE_DRIVE_STR
#undef MLC_DRIVE_STR
#undef PM_BT_WAKE_DRIVE_STR
#undef PM_CAM_SHUTDOWN_DRIVE_STR
#undef CLK_CAM_DRIVE_STR
#undef PM_KEEPACT_DRIVE_STR
#undef RST_PMU_IN_DRIVE_STR
#undef SDIO_WL_DRIVE_STR
#undef VIDEO_AMP_EN_DRIVE_STR
#undef I2C_DRIVE_STR
#undef UART_5_DRIVE_STR
#undef I2S_DRIVE_STR
#undef I2S_MCK_DRIVE_STR
#undef SPI_CS_DRIVE_STR
#undef SPI_DATA_DRIVE_STR
#undef BT_UART_DRIVE_STR
#undef UART_0_DRIVE_STR
#undef FMI_SLEW_RATE
