/*
 * Copyright (C) 2011-2014 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */

/* Default J1/J2/J2A SoC Pin Configuration, IO spreadsheet v0.11 */

#if PIN_CFG_AP

#define GPIO_DRIVE_STR		DRIVE_X2

#define FMI_DRIVE_STR		DRIVE_X3
#define SPI_DRIVE_STR		DRIVE_X3
#define SPI_CS_DRIVE_STR	DRIVE_X2
#define I2C_DRIVE_STR		DRIVE_X3
#define I2S_DRIVE_STR		DRIVE_X3
#define CAM_DRIVE_STR		DRIVE_X3
#define CAM_RF_DRIVE_STR	DRIVE_X4
#define UART_DRIVE_STR		DRIVE_X3
#define DWI_DRIVE_STR		DRIVE_X3
#define BATTERY_SWI_DRIVE_STR	DRIVE_X3
#define ISP_DRIVE_STR		DRIVE_X3

#elif PIN_CFG_DEV

#define GPIO_DRIVE_STR		DRIVE_X2

#define FMI_DRIVE_STR		DRIVE_X4
#define SPI_DRIVE_STR		DRIVE_X4
#define SPI_CS_DRIVE_STR	DRIVE_X3
#define I2C_DRIVE_STR		DRIVE_X4
#define I2S_DRIVE_STR		DRIVE_X4
#define CAM_DRIVE_STR		DRIVE_X3
#define CAM_RF_DRIVE_STR	DRIVE_X4
#define UART_DRIVE_STR		DRIVE_X4
#define DWI_DRIVE_STR		DRIVE_X4
#define BATTERY_SWI_DRIVE_STR	DRIVE_X4
#define ISP_DRIVE_STR		DRIVE_X3

#endif

#if PIN_CFG_AP
static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#elif PIN_CFG_DEV
static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#endif
/* Port  0 */
	CFG_DISABLED,							// UART2_TXD		->
	CFG_DISABLED,							// UART2_RXD		->
	CFG_IN | GPIO_DRIVE_STR,					// UART2_RTSN		-> RST_BB_L
	CFG_IN,								// UART2_CTSN		-> SRL_L
	CFG_FUNC0 | UART_DRIVE_STR,					// UART6_TXD		-> UART6_WLAN_TXD
	CFG_FUNC0,							// UART6_RXD		-> UART6_WLAN_RXD
	CFG_DISABLED,							// UART6_RTSN		->
	CFG_DISABLED,							// UART6_CTSN		->

/* Port  1 */
	CFG_DISABLED,							// SPI0_SCLK		-> BOARD_ID[0]
	CFG_DISABLED,							// SPI0_MOSI		-> BOARD_ID[1]
	CFG_DISABLED,							// SPI0_MISO		-> BOARD_ID[2]
	CFG_DISABLED,							// SPI0_SSIN		->
	CFG_DISABLED,							// UART4_TXD		->
	CFG_DISABLED,							// UART4_RXD		->
	CFG_DISABLED,							// UART4_RTSN		->
	CFG_DISABLED,							// UART4_CTSN		->

/* Port  2 */
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->

/* Port  3 */
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->

/* Port  4 */
	CFG_FUNC0,							// DP_HPD		-> DP_AP_HPD
	CFG_FUNC0,							// EDP_HPD		-> EDP_AP_HPD
	CFG_FUNC0 | UART_DRIVE_STR,					// UART0_TXD		-> UART0_MUX_TXD
	CFG_FUNC0,							// UART0_RXD		-> UART0_MUX_RXD
	CFG_IN,								// GPIO0		-> HOME_L
	CFG_IN,								// GPIO1		-> ONOFF_L
#if SUB_TARGET_J2 || SUB_TARGET_J2A
	CFG_IN | PULL_DOWN,						// GPIO2		-> HSIC_BB_RDY
#elif  SUB_TARGET_J1
	CFG_DISABLED,							// GPIO2		-> HSIC_BB_RDY
#endif
	CFG_DISABLED,							// GPIO3		->

/* Port  5 */
	CFG_IN | PULL_UP,						// GPIO4		-> IRQ_PMU_L
	CFG_OUT_0 | GPIO_DRIVE_STR,					// GPIO5		-> PM_BT_WAKE
	CFG_IN | PULL_UP,						// GPIO6		-> IRQ_CODEC_L
	CFG_DISABLED,							// GPIO7		->
	CFG_DISABLED,							// GPIO8		->
	CFG_OUT_0 | GPIO_DRIVE_STR,					// GPIO9		-> PM_RADIO_ON
#if SUB_TARGET_J2 || SUB_TARGET_J2A
	CFG_IN | PULL_DOWN,						// GPIO10		-> RST_DET_L
#elif  SUB_TARGET_J1
	CFG_DISABLED,							// GPIO10		-> RST_DET_L
#endif
	CFG_DISABLED,							// GPIO11		->

/* Port  6 */
#if SUB_TARGET_J2 || SUB_TARGET_J2A
	CFG_IN,								// GPIO12		-> SPI2_IPC_SRDY
#elif  SUB_TARGET_J1
	CFG_DISABLED,							// GPIO12		-> SPI2_IPC_SRDY
#endif
	CFG_DISABLED,							// GPIO13		->
	CFG_IN | PULL_UP,						// GPIO14		-> AUD_VOL_DOWN_L
	CFG_IN | PULL_DOWN,						// GPIO15		-> GSM_TXBURST_IND
	CFG_DISABLED | PULL_DOWN,					// GPIO16		-> BOARD_ID[3]
	CFG_IN,								// GPIO17		-> IRQ_GYRO_INT2
	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
	CFG_DISABLED,							// GPIO19		->

/* Port  7 */
	CFG_IN | PULL_UP,						// GPIO20		-> AUD_VOL_UP_L
	CFG_IN | PULL_UP,						// GPIO21		-> IRQ_GRAPE_HOST_INT_L
	CFG_OUT_0 | GPIO_DRIVE_STR,					// GPIO22		-> PM_KEEPACT
	CFG_OUT_0 | GPIO_DRIVE_STR,					// GPIO23		-> BB_EMERGENCY_DWLD
	CFG_OUT_0,							// GPIO24		-> IPC_GPIO_X26
	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
	CFG_IN,								// GPIO26		-> FORCE_DFU
	CFG_OUT_0 | DRIVE_X1,						// GPIO27		-> DFU_STATUS

/* Port  8 */
	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
	CFG_IN,								// GPIO30		-> HSIC_WLAN_RDY
	CFG_DISABLED,							// GPIO31		->
	CFG_IN,								// GPIO32		-> IRQ_PROX_INT_L
	CFG_IN | PULL_DOWN,						// GPIO33		-> IRQ_GYRO_INT1
	CFG_OUT_0,							// GPIO34		-> HSIC_HOST_READY_WL
	CFG_DISABLED,							// GPIO35		->

/* Port  9 */
	CFG_IN | PULL_UP,						// GPIO36		-> IRQ_ACCEL_INT1_L
	CFG_IN | PULL_UP,						// GPIO37		-> IRQ_ALS_INT_L
	CFG_IN | PULL_UP,						// GPIO38		-> IRQ_ACCEL_INT2_L
	CFG_OUT_0 | GPIO_DRIVE_STR,					// GPIO39		-> AUD_SPKRAMP_MUTE_L
	CFG_FUNC0 | SPI_DRIVE_STR,					// SPI1_SCLK		-> SPI1_GRAPE_SCLK
	CFG_FUNC0 | SPI_DRIVE_STR,					// SPI1_MOSI		-> SPI1_GRAPE_MOSI
	CFG_FUNC0,							// SPI1_MISO		-> SPI1_GRAPE_MISO
	CFG_OUT_1 | SPI_CS_DRIVE_STR,					// SPI1_SSIN		-> SPI1_GRAPE_CS_L

/* Port  10 */
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C2_SDA		-> I2C2_SDA_3V0
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C2_SCL		-> I2C2_SCL_3V0
	CFG_IN | UART_DRIVE_STR,					// UART1_TXD		-> UART1_BB_TXD
	CFG_FUNC0,							// UART1_RXD		-> UART1_BB_RXD
	CFG_FUNC0 | UART_DRIVE_STR,					// UART1_RTSN		-> UART1_BB_RTS_L
	CFG_FUNC0,							// UART1_CTSN		-> UART1_BB_CTS_L
	CFG_FUNC0 | UART_DRIVE_STR,					// UART3_TXD		-> UART3_BT_TXD
	CFG_FUNC0,							// UART3_RXD		-> UART3_BT_RXD

/* Port  11 */
	CFG_OUT_1 | UART_DRIVE_STR,					// UART3_RTSN		-> UART3_BT_RTS_L
	CFG_FUNC0,							// UART3_CTSN		-> UART3_BT_CTS_L
	CFG_FUNC0 | BATTERY_SWI_DRIVE_STR,				// UART5_RTXD		-> BATTERY_SWI
	CFG_FUNC0 | ISP_DRIVE_STR,					// ISP0_SDA		-> ISP_AP_0_SDA
	CFG_FUNC0 | ISP_DRIVE_STR,					// ISP0_SCL		-> ISP_AP_0_SCL
	CFG_FUNC0 | ISP_DRIVE_STR,					// ISP1_SDA		-> ISP_AP_1_SDA
	CFG_FUNC0 | ISP_DRIVE_STR,					// ISP1_SCL		-> ISP_AP_1_SCL
	CFG_DISABLED,							// SPI2_SCLK		-> 

/* Port 12 */
	CFG_DISABLED,							// SPI2_MOSI		-> 
	CFG_DISABLED,
#if SUB_TARGET_J2 || SUB_TARGET_J2A
	CFG_OUT_0 | SPI_CS_DRIVE_STR,					// SPI2_SSIN		-> HSIC_HOST_RDY
#elif  SUB_TARGET_J1
	CFG_DISABLED | SPI_CS_DRIVE_STR,				// SPI2_SSIN		-> HSIC_HOST_RDY
#endif
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C0_SDA		-> I2C0_SDA_1V8
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C0_SCL		-> I2C0_SCL_1V8
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C1_SDA		-> I2C1_SDA_1V8
	CFG_FUNC0 | I2C_DRIVE_STR,					// I2C1_SCL		-> I2C1_SCL_1V8
	CFG_DISABLED,							// MIPI_VSYNC		->

/* Port 13 */
	CFG_DISABLED,							// TMR32_PWM0		->
	CFG_DISABLED,							// TMR32_PWM1		->
	CFG_DISABLED | GPIO_DRIVE_STR,					// TMR32_PWM2		-> LED_STROBE_EN
	CFG_DISABLED,							// SWI_DATA		->
	CFG_FUNC0 | PULL_DOWN,						// DWI_DI		-> DWI_AP_DI
	CFG_FUNC0 | DWI_DRIVE_STR,					// DWI_DO		-> DWI_AP_DO
	CFG_FUNC0 | DWI_DRIVE_STR,					// DWI_CLK		-> DWI_AP_CLK
	CFG_OUT_1 | GPIO_DRIVE_STR,					// SENSOR0_RST		-> PM_REAR_CAM_SHUTDOWN

/* Port 14 */
	CFG_OUT_0 | CAM_RF_DRIVE_STR,					// SENSOR0_CLK		-> CLK_CAM_RF_R
	CFG_OUT_1 | GPIO_DRIVE_STR,					// SENSOR1_RST		-> PM_FRONT_CAM_SHUTDOWN
	CFG_OUT_0 | CAM_DRIVE_STR,					// SENSOR1_CLK		-> CLK_CAM_FF_R
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S0_MCK		-> I2S0_ASP_MCK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S0_LRCK		-> I2S0_ASP_LRCK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S0_BCLK		-> I2S0_ASP_BCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S0_DOUT		-> I2S0_ASP_DOUT
	CFG_FUNC0,							// I2S0_DIN		-> I2S0_ASP_DIN

/* Port 15 */
	CFG_DISABLED,							// I2S1_MCK		->
	CFG_DISABLED,							// I2S1_LRCK		->
	CFG_DISABLED,							// I2S1_BCLK		->
	CFG_DISABLED,							// I2S1_DOUT		->
	CFG_DISABLED,							// I2S1_DIN		->
	CFG_DISABLED,							// I2S2_MCK		->
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S2_LRCK		-> I2S2_VSP_LRCK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S2_BCLK		-> I2S2_VSP_BCLK

/* Port 16 */
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S2_DOUT		-> I2S2_VSP_DOUT
	CFG_FUNC0,							// I2S2_DIN		-> I2S2_VSP_DIN
	CFG_DISABLED,							// I2S3_MCK		->
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S3_LRCK		-> I2S3_XSP_LRCK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S3_BCLK		-> I2S3_XSP_BCLK
	CFG_FUNC0 | I2S_DRIVE_STR,					// I2S3_DOUT		-> I2S3_XSP_DOUT
	CFG_FUNC0,							// I2S3_DIN		-> I2S3_XSP_DIN
	CFG_DISABLED,							// SPDIF		->

/* Port 17 */
	CFG_FUNC0,							// TST_CLKOUT		-> TP_AP_TST_CLKOUT
	CFG_FUNC0,							// TST_STPCLK		-> AP_TST_STPCLK
	CFG_FUNC0 | DRIVE_X3,						// WDOG			-> AP_WDOG
	CFG_DISABLED,							// EHCI_PORT_PWR[0]	-> GPIO40_BRD_REV0
	CFG_DISABLED,							// EHCI_PORT_PWR[1]	-> GPIO41_BRD_REV1
	CFG_DISABLED,							// EHCI_PORT_PWR[2]	-> GPIO42_BRD_REV2
	CFG_DISABLED,							// SDIO_CLK		->
	CFG_DISABLED,							// SDIO_CMD		->
	
/* Port 18 */
	CFG_DISABLED,							// SDIO_DATA0		->
	CFG_DISABLED,							// SDIO_DATA1		->
	CFG_DISABLED,							// SDIO_DATA2		->
	CFG_DISABLED,							// SDIO_DATA3		->
	CFG_OUT_0 | DRIVE_X3,						// GPIO_3V_0		-> PORT_DOCK_VIDEO_AMP_EN
	CFG_DISABLED,							// GPIO_3V_1		-> 
	CFG_OUT_0 | CAM_DRIVE_STR,					// ISP0_PRE_FLASH	-> CAM0_1V2_VDDCORE_EN
	CFG_OUT_0 | CAM_DRIVE_STR,					// ISP0_FLASH		-> CAM0_RESET_L
	
/* Port 19 */
	CFG_DISABLED,							// ISP1_PRE_FLASH	->
	CFG_DISABLED,							// ISP1_FLASH		->
	CFG_DISABLED,							// SPI3_MOSI		-> 
	CFG_DISABLED,							// SPI3_MISO		-> 
	CFG_DISABLED,							// SPI3_SCLK		-> 
	CFG_DISABLED,							// SPI3_SSIN		-> 
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN7		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN6		->
	
/* Port 20 */
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN5		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN4		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN7		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN6		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN5		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN4		->
	CFG_OUT_1 | GPIO_DRIVE_STR,					// FMI2_CEN7		-> GRAPE_FW_DNLD_EN_L
	CFG_OUT_0 | GPIO_DRIVE_STR, 					// FMI2_CEN6		-> RST_GRAPE_L
	
/* Port 21 */
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_CEN5		->
	CFG_OUT_0 | DRIVE_X3,						// FMI2_CEN4		-> PM_LCDVDD_PWR_EN
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_CEN7		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_CEN6		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_CEN5		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_CEN4		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI0_IO7		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI0_IO6		->

/* Port 22 */	
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI0_IO5		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI0_IO4		->
	CFG_DISABLED | PULL_DOWN,					// FMI0_DQS		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI0_IO3		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI0_IO2		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI0_IO1		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI0_IO0		->
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI0_REN		->
	
/* Port 23 */
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI0_WEN		->
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI0_ALE		->
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI0_CLE		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN3		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI0_CEN2		->
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI0_CEN1		->
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI0_CEN0		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI1_IO7		->
	
/* Port 24 */
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI1_IO6		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI1_IO5		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI1_IO4		->
	CFG_DISABLED | PULL_DOWN,					// FMI1_DQS		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI1_IO3		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI1_IO2		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI1_IO1		->
	CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR,				// FMI1_IO0		->
	
/* Port 25 */
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI1_REN		->
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI1_WEN		->
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI1_ALE		->
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI1_CLE		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN3		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI1_CEN2		->
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI1_CEN1		->
	CFG_FUNC0 | FMI_DRIVE_STR,					// FMI1_CEN0		->
	
/* Port 26 */
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_IO7		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_IO6		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_IO5		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_IO4		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_DQS		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_IO3		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_IO2		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_IO1		->
	
/* Port 27 */
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_IO0		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_REN		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_WEN		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_ALE		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_CLE		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_CEN3		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_CEN2		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI2_CEN1		->
	
/* Port 28 */
	CFG_IN,								// FMI2_CEN0		-> SPK_ID
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_IO7		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_IO6		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_IO5		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_IO4		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_DQS		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_IO3		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_IO2		->
	
/* Port 29 */
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_IO1		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_IO0		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_REN		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_WEN		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_ALE		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_CLE		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_CEN3		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_CEN2		->
	
/* Port 30 */
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_CEN1		->
	CFG_DISABLED | FMI_DRIVE_STR,					// FMI3_CEN0		->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
};

#undef GPIO_DRIVE_STR
#undef FMI_DRIVE_STR
#undef SPI_DRIVE_STR
#undef SPI_CS_DRIVE_STR
#undef I2C_DRIVE_STR
#undef I2S_DRIVE_STR
#undef CAM_DRIVE_STR
#undef CAM_RF_DRIVE_STR
#undef UART_DRIVE_STR
#undef DWI_DRIVE_STR
#undef BATTERY_SWI_DRIVE_STR
#undef ISP_DRIVE_STR
