/*
 * Copyright (C) 2013-2014 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */
#ifndef __APPLE_DISPLAY_FRONTEND_REGS_H
#define __APPLE_DISPLAY_FRONTEND_REGS_H

#include <platform/soc/hwregbase.h>

//General control registers
#define	rADPCSPARE			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1000))
#define	rADPCVERSION			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1018))
#define	rADPCSTATE			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x101c))
#define	rADPCGO				(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1020))
#define	rADPCRESTART			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1024))
#define	rADPCIRQENAB			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1028))
#define	 ADPCIRQ_WBPARTIRQ		(1 << 14)
#define	 ADPCIRQ_WBCMPLIRQ		(1 << 13)
#define	 ADPCIRQ_WRERRIRQ		(1 << 12)
#define	 ADPCIRQ_RDERRIRQ		(1 << 1)
#define	 ADPCIRQ_PFPROCIRQ		(1 << 10)
#define	 ADPCIRQ_PFOVERIRQ		(1 << 9)
#define	 ADPCIRQ_PFHDRIRQ		(1 << 8)
#define	 ADPCIRQ_PFEMPTYIRQ		(1 << 7)
#define	 ADPCIRQ_PFALIGNIRQ		(1 << 6)
#define	 ADPCIRQ_PFREPEATIRQ		(1 << 5)
#define	 ADPCIRQ_PFSYNCIRQ		(1 << 4)
#define	 ADPCIRQ_PFMISSIRQ		(1 << 3)
#define	 ADPCIRQ_PFUNDERIRQ		(1 << 2)
#define	 ADPCIRQ_OUTUNDERIRQ		(1 << 1)
#define	 ADPCIRQ_VBIIRQ			(1 << 0)
#define	rADPCIRQ			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x102c))
#define	rADPCFRAMESIZE			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1030))
#define	rADPCFRMCNT			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1034))
#define	rADPCENAB			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1038))
#define	 ADPCENAB_IDEAL_ARB_ENAB	(1 << 16)
#define	 ADPCENAB_SIDSEL_BYPASS		(1 << 12)
#define	rADPCPFSIZE			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x103c))
#define	rADPCPFSTAT			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1040))
#define	rADPCPFHEAD			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1044))
#define	rADPCPFMODE			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1048))
#define  ADPCPFMODE_AUTOEN		(1 << 0)
#define  ADPCPFMODE_VBIEN		(1 << 4)
#define	rADPCPFFLUSH			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104c))
#define	rADPCCLKCNTL			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1050))
#define	 ADPCCLKCNTL_FLOOR(n)		((n) << 16)
#define	 ADPCCLKCNTL_PIPE_ENABLE	(1 << 8)
#define	 ADPCCLKCNTL_LB_ENABLE		(1 << 4)
#define	 ADPCCLKCNTL_PIO_GATE_ENABLE	(1 << 3)
#define	 ADPCCLKCNTL_STAT_GATE_ENABLE	(1 << 2)
#define	 ADPCCLKCNTL_EXT_GATE_ENABLE	(1 << 1)
#define	 ADPCCLKCNTL_DYN_GATE_ENABLE	(1 << 0)
#define	rADPCCLKLVL			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1054))
#define  ADPCCLKLVL_ONLVL(n)		((n) << 16)
#define  ADPCCLKLVL_OFFLVL(n)		((n) << 0)
#define	rADPCQOSCFG			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1058))
#define  ADPCQOSCFG_QOS_TIMER(n)	((n) << 16)
#define  ADPCQOSCFG_PIPE_ENABLE		(1 << 8)
#define  ADPCQOSCFG_MINLVL_ENABLE	(1 << 6)
#define  ADPCQOSCFG_MON_MODE		(1 << 5)
#define  ADPCQOSCFG_MON_ENABLE		(1 << 4)
#define  ADPCQOSCFG_QOS_ENABLE		(1 << 0)
#define	rADPCQOSYLVL			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x105c))
#define	 ADPCQOSYLVL_YELLOW_OFF(n)	((n) << 16)
#define	 ADPCQOSYLVL_YELLOW_ON(n)	((n) << 0)
#define	rADPCQOSRLVL			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1060))
#define	 ADPCQOSRLVL_RED_OFF(n)		((n) << 16)
#define	 ADPCQOSRLVL_RED_ON(n)		((n) << 0)
#define	rADPCQOSGSNAP			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1064))
#define	rADPCQOSYSNAP			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1068))
#define	rADPCQOSRSNAP			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x106c))
#define	rADPCQOSMINLVLSNAP		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1070))
#define	rADPCCRCCTRL			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1074))
#define	rADPCLINKDOWN			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1078))
#define	 ADPCLINKDOWN_TEARDOWNNOSCL	(1 << 8)
#define	 ADPCLINKDOWN_TEARDOWNAGGR	(1 << 4)
#define	 ADPCLINKDOWN_TEARDOWNEN	(1 << 0)
#if ADP_VERSION > 1
#define rADPCAFCLKGATE			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x107C))
#define  ADPAFIDLECOUNT(n)		((n) << 16)
#define  ADPAFDYNCLKGATEEN		(1 << 0)
#endif
#define rADPCPFTOP(n)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x10c0 + (4 * (n))))

//Blend Unit registers
#define	rADPBSPARE			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2000))
#define	rADPBCFG			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2020))
#define	 ADPBCFG_BLEND_BYPASS		(1 << 0)
#define	rADPBBACKCOLOR			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2024))
#define	rADPBLAYCFG(n)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2028 + (4 * (n))))
#define	rADPBCRCDATA			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2030))
#define	rADPBCSCCFG			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2034))
#define	 ADPBCSCCFG_CSCBYPASS		(1 << 0)
#define	rADPBCSCINOFF(n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2038 + (4 * (n))))
#define	rADPBCSCCOEF(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2044 + (12 * (p)) + (4 * (n))))
#define	rADPBCSCOUTOFF(n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2068 + (4 * (n))))
#define	rADPBCMCFG			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2074))
#define	 ADPBCMCFG_CMBYPASS		(1 << 0)
#define	rADPBDEGAMMALINEAR		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2078))
#define	rADPBCMCOEF(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x207c  + (12 * (p)) + (4 * (n))))
#define	rADPBGAMMALINEAR		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x20a0))
#define	rADPBGAMMALINEAR_R		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x20a0))
#define	rADPBGAMMALINEAR_G		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x20a4))
#define	rADPBGAMMALINEAR_B		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x20a8))
#define	rADPBOUTFIFODEPTH		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x20ac))
#define	rADPBDEGAMMATABLE(n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2200 + (4 * (n))))
#define	rADPBGAMMATABLE(n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2800 + (4 * (n))))
#define	rADPBGAMMATABLE_R(n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2800 + (4 * (n))))
#define	rADPBGAMMATABLE_G(n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x3000 + (4 * (n))))
#define	rADPBGAMMATABLE_B(n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x3800 + (4 * (n))))

//Generic Pipe registers
#define	rADPGPSPARE(p)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4000 + ((p) * 0x2000)))
#define	rADPGPCFG(p)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4020 + ((p) * 0x2000)))
#define  ADPGPCFG_SCALE_BYPASS		(1 << 4)
#define  ADPGPCFG_NO_SCALE		(1 << 0)
#define	rADPGPREQAGGR(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4024 + ((p) * 0x2000) + (4 * (n))))
#define  ADPGPREQARRG_CACHEHINT_MASK	(0x0F0000)
#define	 ADPGPREQAGGR_CACHEHINT(n)	((n) << 16)
#define	 ADPGPREQAGGR_REQAGGRTHRESH(n)	((n) << 4)
#define  ADPGPREQARRG_OPPORTUNISMENAB	(1 << 1)
#define	 ADPGPREQAGGR_REQAGGRENAB	(1 << 0)
#define	rADPGPSRCFMT(p)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x402c + ((p) * 0x2000)))
#define	rADPGPSRCBASE(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4030 + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPSRCSTRD(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4038 + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPSRCXY(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4040 + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPSRCWH(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4048 + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPDSTXY(p)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4050 + ((p) * 0x2000)))
#define	rADPGPDSTWH(p)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4054 + ((p) * 0x2000)))
#define	rADPGPTBEDGEALPHA(p)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4058 + ((p) * 0x2000)))
#define	rADPGPLREDGEALPHA(p)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x405c + ((p) * 0x2000)))
#define	rADPGPTCEDGEALPHA(p)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4060 + ((p) * 0x2000)))
#define	rADPGPBCEDGEALPHA(p)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4064 + ((p) * 0x2000)))
#define	rADPGPSRCCFG(p)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4068 + ((p) * 0x2000)))
#define	rADPGPSRCACTXY(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x406c + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPSRCACTWH(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x407c + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPNOISECFG(p)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x408c + ((p) * 0x2000)))
#define	rADPGPNOISELFSR(p)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4090 + ((p) * 0x2000)))
#define	rADPGPDDAINITX(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4094 + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPDDASTEPX(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x409c + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPDDAINITY(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40a4 + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPDDASTEPY(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40ac + ((p) * 0x2000) + (4 * (n))))

#define	rADPGPCSCCFG(p)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40b4 + ((p) * 0x2000)))
#define	 ADPGPCSCCFG_CSC_BYPASS		(1 << 0)
#define	rADPGPCSCINOFF(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40b8 + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPCSCCOEF(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40c4 + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPCSCOUTOFF(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40e8 + ((p) * 0x2000) + (4 * (n))))

#define	rADPGPCMCFG(p)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40f4 + ((p) * 0x2000)))
#define	 ADPGPCMCFG_CM_BYPASS		(1 << 0)
#define	rADPGPDEGAMMALINEAR(p)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40f8 + ((p) * 0x2000)))
#define	rADPGPCMCOEF(p, r, c)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40fc + ((p) * 0x2000) + ((r) * 0xc) + (4 * (c))))

#define	rADPGPGAMMALINEAR(p)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4120 + ((p) * 0x2000)))
#define	rADPGPCRCCTRL(p)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4124 + ((p) * 0x2000)))
#define	rADPGPCRCDATA(p)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4128 + ((p) * 0x2000)))
#define	rADPGPINVDDASTEPX(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x412c + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPDEGAMMATABLE(p, n)	(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4200 + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPGAMMATABLE(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4800 + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPCOEFX(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x5000 + ((p) * 0x2000) + (4 * (n))))
#define	rADPGPCOEFY(p, n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x5800 + ((p) * 0x2000) + (4 * (n))))

//DP Noise RAM Registers
#define	rADPNOISEARRAY(n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x8000 + (4 * (n)))

//DP Write Back Registers
#define	rADPWBSPARE			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9000))
#define	rADPWBBASE(n)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9020 + (4 * (n))))
#define	rADPWBSTRD(n)			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9028 + (4 * (n))))
#define	rADPWBCNTL			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9030))
#define	rADPWBCHROMADOWN		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9034))
#define	rADPWBLINECNT(n)		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9038 + (4 * (n))))
#define	rADP_DITHER_SKEW0		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9040))
#define	rADP_DITHER_SKEW1		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9044))
#define	rADP_DITHER_SKEW2		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9048))
#define	rADP_DITHER_KERNEL		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x904c))

//SMMU Registers
#define	rADPSMMU_CONFIG			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x10000c))
#define	rADPSMMU_ERR_STATUS		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100010))
#define	rADPSMMU_ERR_AXI_REQ0		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100014))
#define	rADPSMMU_ERR_AXI_REQ1		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100018))
#define	rADPSMMU_ERR_ADDRESS		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x10001c))
#define	rADPSMMU_DIAG_CONFIG		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100020))
#define	rADPSMMU_DIAG_BOGUS_ACCESS	(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100024))
#define	rADPSMMU_BYPASS_ADDR		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x10002c))
#define	rADPSMMU_ERR_STTIDX		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100030))
#define	rADPSMMU_REQ_SCOREBOARD(n)	(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100080 + ((n) * 4))
#define	rADPSMMU_ACK_SCOREBOARD(n)	(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1000c0 + ((n) * 4))
#define	rADPSMMU_PERF_CONFIG		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x101000))
#define	rADPSMMU_CTR			(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x101004))
#define	rADPSMMU_STT_PA_DATA		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x102000))

//DART Registers
#define rADPDART_DIAG_CONFIG		(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104020))
#define rADPDART_DIAG_BOGUS_ACCESS	(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104024))
#define rADPDART_FETCH_REQ_CONFIG	(*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104030))

#endif /* ! __APPLE_DISPLAY_FRONTEND_REGS_H */
