/*! 
 *  Automatically generated by socgen. DO NOT EDIT!
 *  
 *  Copyright (c) 2014 Apple Inc. All rights reserved.
 *  
 *  This document is the property of Apple Inc.
 *  It is considered confidential and proprietary.
 *  
 *  This document may not be reproduced or transmitted in any form
 *  in whole or in part, without the express written permission of
 *  Apple inc.
 */

#ifndef SPDS_AES_H
#define SPDS_AES_H

/*       Chips             s5l8960x_a0, s5l8960x_b0, s5l8960x_b1, t7000_a0, t7000_b0, t7000_b1, t7001_a0, t7001_a1  */
/*       Reported Version  1.1.2                                                                                    */
#define  SPDS_AES_V1       1

/*       Chips             s7002_a1, s7002_a1                                                                       */
/*       Reported Version  1.1.0                                                                                    */
#define  SPDS_AES_V2       2

/*       Chips             s8000_a1, s8000_a1                                                                       */
/*       Reported Version  0.0.1                                                                                    */
#define  SPDS_AES_V3       3

/*       Chips             s8000_b0                                                                                 */
/*       Reported Version  0.0.1                                                                                    */
#define  SPDS_AES_V4       4

/*       Chips             s8001_a0                                                                                 */
/*       Reported Version  0.0.1                                                                                    */
#define  SPDS_AES_V5       5

/*       Chips             t8002_a0                                                                                 */
/*       Reported Version  0.0.1                                                                                    */
#define  SPDS_AES_V6       6

/*       Chips             t8010_a0                                                                                 */
/*       Reported Version  0.0.1                                                                                    */
#define  SPDS_AES_V7       7

#if     (defined(SPDS_AES_VERSION) && (SPDS_AES_VERSION < 1 || SPDS_AES_VERSION > 7))
#error  'SPDS_AES_VERSION': value is invalid.
#endif

/*! @ingroup group873046 */

/*! 
 *  @addtogroup group995868 aes
 *  @brief Address = 0x20a108000
 *  @details Version = 0.0.1 @n
 *  AES Registers
 *  @{
 */

/*! 
 *  @addtogroup group995869 blk (AES)
 *  @brief Offset = 0x0
 *  @details General Control registers
 *  @see @ref SAIAddressBlock
 *  @{
 */

#define  AES_BLK_OFFSET                                                     (0x0)

/*! 
 *  @addtogroup group995870 version
 *  @brief Offset = 0x0
 *  @details IP Implementation Version
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_VERSION_OFFSET_V3                                          (0x0 + 0x0)
#define  AES_BLK_VERSION_OFFSET_V4                                          (0x0 + 0x0)
#define  AES_BLK_VERSION_OFFSET_V5                                          (0x0 + 0x0)
#define  AES_BLK_VERSION_OFFSET_V6                                          (0x0 + 0x0)
#define  AES_BLK_VERSION_OFFSET_V7                                          (0x0 + 0x0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_OFFSET                                             AES_BLK_VERSION_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_OFFSET                                             AES_BLK_VERSION_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_OFFSET                                             AES_BLK_VERSION_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_OFFSET                                             AES_BLK_VERSION_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_OFFSET                                             AES_BLK_VERSION_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995871 minor_release
 *  @brief Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0
 *  @details Minor Release Number
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_VERSION_MINOR_RELEASE_SHIFT_V3                             (0)
#define  AES_BLK_VERSION_MINOR_RELEASE_SHIFT_V4                             (0)
#define  AES_BLK_VERSION_MINOR_RELEASE_SHIFT_V5                             (0)
#define  AES_BLK_VERSION_MINOR_RELEASE_SHIFT_V6                             (0)
#define  AES_BLK_VERSION_MINOR_RELEASE_SHIFT_V7                             (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MINOR_RELEASE_SHIFT                                AES_BLK_VERSION_MINOR_RELEASE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MINOR_RELEASE_SHIFT                                AES_BLK_VERSION_MINOR_RELEASE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MINOR_RELEASE_SHIFT                                AES_BLK_VERSION_MINOR_RELEASE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MINOR_RELEASE_SHIFT                                AES_BLK_VERSION_MINOR_RELEASE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MINOR_RELEASE_SHIFT                                AES_BLK_VERSION_MINOR_RELEASE_SHIFT_V7
#endif

#define  AES_BLK_VERSION_MINOR_RELEASE_WIDTH_V3                             (8)
#define  AES_BLK_VERSION_MINOR_RELEASE_WIDTH_V4                             (8)
#define  AES_BLK_VERSION_MINOR_RELEASE_WIDTH_V5                             (8)
#define  AES_BLK_VERSION_MINOR_RELEASE_WIDTH_V6                             (8)
#define  AES_BLK_VERSION_MINOR_RELEASE_WIDTH_V7                             (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MINOR_RELEASE_WIDTH                                AES_BLK_VERSION_MINOR_RELEASE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MINOR_RELEASE_WIDTH                                AES_BLK_VERSION_MINOR_RELEASE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MINOR_RELEASE_WIDTH                                AES_BLK_VERSION_MINOR_RELEASE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MINOR_RELEASE_WIDTH                                AES_BLK_VERSION_MINOR_RELEASE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MINOR_RELEASE_WIDTH                                AES_BLK_VERSION_MINOR_RELEASE_WIDTH_V7
#endif

#define  AES_BLK_VERSION_MINOR_RELEASE_UMASK_V3                             (0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_UMASK_V4                             (0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_UMASK_V5                             (0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_UMASK_V6                             (0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_UMASK_V7                             (0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MINOR_RELEASE_UMASK                                AES_BLK_VERSION_MINOR_RELEASE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MINOR_RELEASE_UMASK                                AES_BLK_VERSION_MINOR_RELEASE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MINOR_RELEASE_UMASK                                AES_BLK_VERSION_MINOR_RELEASE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MINOR_RELEASE_UMASK                                AES_BLK_VERSION_MINOR_RELEASE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MINOR_RELEASE_UMASK                                AES_BLK_VERSION_MINOR_RELEASE_UMASK_V7
#endif

#define  AES_BLK_VERSION_MINOR_RELEASE_SMASK_V3                             (0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_SMASK_V4                             (0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_SMASK_V5                             (0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_SMASK_V6                             (0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_SMASK_V7                             (0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MINOR_RELEASE_SMASK                                AES_BLK_VERSION_MINOR_RELEASE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MINOR_RELEASE_SMASK                                AES_BLK_VERSION_MINOR_RELEASE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MINOR_RELEASE_SMASK                                AES_BLK_VERSION_MINOR_RELEASE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MINOR_RELEASE_SMASK                                AES_BLK_VERSION_MINOR_RELEASE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MINOR_RELEASE_SMASK                                AES_BLK_VERSION_MINOR_RELEASE_SMASK_V7
#endif

#define  AES_BLK_VERSION_MINOR_RELEASE_XTRCT_V3(r)                          ((((uint32_t)r) >> 0) & 0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_XTRCT_V4(r)                          ((((uint32_t)r) >> 0) & 0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_XTRCT_V5(r)                          ((((uint32_t)r) >> 0) & 0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_XTRCT_V6(r)                          ((((uint32_t)r) >> 0) & 0xff)
#define  AES_BLK_VERSION_MINOR_RELEASE_XTRCT_V7(r)                          ((((uint32_t)r) >> 0) & 0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MINOR_RELEASE_XTRCT                                AES_BLK_VERSION_MINOR_RELEASE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MINOR_RELEASE_XTRCT                                AES_BLK_VERSION_MINOR_RELEASE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MINOR_RELEASE_XTRCT                                AES_BLK_VERSION_MINOR_RELEASE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MINOR_RELEASE_XTRCT                                AES_BLK_VERSION_MINOR_RELEASE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MINOR_RELEASE_XTRCT                                AES_BLK_VERSION_MINOR_RELEASE_XTRCT_V7
#endif

#define  AES_BLK_VERSION_MINOR_RELEASE_INSRT_V3(f)                          ((((uint32_t)f) & 0xff) << 0)
#define  AES_BLK_VERSION_MINOR_RELEASE_INSRT_V4(f)                          ((((uint32_t)f) & 0xff) << 0)
#define  AES_BLK_VERSION_MINOR_RELEASE_INSRT_V5(f)                          ((((uint32_t)f) & 0xff) << 0)
#define  AES_BLK_VERSION_MINOR_RELEASE_INSRT_V6(f)                          ((((uint32_t)f) & 0xff) << 0)
#define  AES_BLK_VERSION_MINOR_RELEASE_INSRT_V7(f)                          ((((uint32_t)f) & 0xff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MINOR_RELEASE_INSRT                                AES_BLK_VERSION_MINOR_RELEASE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MINOR_RELEASE_INSRT                                AES_BLK_VERSION_MINOR_RELEASE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MINOR_RELEASE_INSRT                                AES_BLK_VERSION_MINOR_RELEASE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MINOR_RELEASE_INSRT                                AES_BLK_VERSION_MINOR_RELEASE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MINOR_RELEASE_INSRT                                AES_BLK_VERSION_MINOR_RELEASE_INSRT_V7
#endif

/*! @} minor_release */

/*! 
 *  @addtogroup group995872 major_release
 *  @brief Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0
 *  @details Major Release Number
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_VERSION_MAJOR_RELEASE_SHIFT_V3                             (8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_SHIFT_V4                             (8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_SHIFT_V5                             (8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_SHIFT_V6                             (8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_SHIFT_V7                             (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MAJOR_RELEASE_SHIFT                                AES_BLK_VERSION_MAJOR_RELEASE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MAJOR_RELEASE_SHIFT                                AES_BLK_VERSION_MAJOR_RELEASE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MAJOR_RELEASE_SHIFT                                AES_BLK_VERSION_MAJOR_RELEASE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MAJOR_RELEASE_SHIFT                                AES_BLK_VERSION_MAJOR_RELEASE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MAJOR_RELEASE_SHIFT                                AES_BLK_VERSION_MAJOR_RELEASE_SHIFT_V7
#endif

#define  AES_BLK_VERSION_MAJOR_RELEASE_WIDTH_V3                             (8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_WIDTH_V4                             (8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_WIDTH_V5                             (8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_WIDTH_V6                             (8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_WIDTH_V7                             (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MAJOR_RELEASE_WIDTH                                AES_BLK_VERSION_MAJOR_RELEASE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MAJOR_RELEASE_WIDTH                                AES_BLK_VERSION_MAJOR_RELEASE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MAJOR_RELEASE_WIDTH                                AES_BLK_VERSION_MAJOR_RELEASE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MAJOR_RELEASE_WIDTH                                AES_BLK_VERSION_MAJOR_RELEASE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MAJOR_RELEASE_WIDTH                                AES_BLK_VERSION_MAJOR_RELEASE_WIDTH_V7
#endif

#define  AES_BLK_VERSION_MAJOR_RELEASE_UMASK_V3                             (0xff00)
#define  AES_BLK_VERSION_MAJOR_RELEASE_UMASK_V4                             (0xff00)
#define  AES_BLK_VERSION_MAJOR_RELEASE_UMASK_V5                             (0xff00)
#define  AES_BLK_VERSION_MAJOR_RELEASE_UMASK_V6                             (0xff00)
#define  AES_BLK_VERSION_MAJOR_RELEASE_UMASK_V7                             (0xff00)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MAJOR_RELEASE_UMASK                                AES_BLK_VERSION_MAJOR_RELEASE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MAJOR_RELEASE_UMASK                                AES_BLK_VERSION_MAJOR_RELEASE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MAJOR_RELEASE_UMASK                                AES_BLK_VERSION_MAJOR_RELEASE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MAJOR_RELEASE_UMASK                                AES_BLK_VERSION_MAJOR_RELEASE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MAJOR_RELEASE_UMASK                                AES_BLK_VERSION_MAJOR_RELEASE_UMASK_V7
#endif

#define  AES_BLK_VERSION_MAJOR_RELEASE_SMASK_V3                             (0xff)
#define  AES_BLK_VERSION_MAJOR_RELEASE_SMASK_V4                             (0xff)
#define  AES_BLK_VERSION_MAJOR_RELEASE_SMASK_V5                             (0xff)
#define  AES_BLK_VERSION_MAJOR_RELEASE_SMASK_V6                             (0xff)
#define  AES_BLK_VERSION_MAJOR_RELEASE_SMASK_V7                             (0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MAJOR_RELEASE_SMASK                                AES_BLK_VERSION_MAJOR_RELEASE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MAJOR_RELEASE_SMASK                                AES_BLK_VERSION_MAJOR_RELEASE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MAJOR_RELEASE_SMASK                                AES_BLK_VERSION_MAJOR_RELEASE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MAJOR_RELEASE_SMASK                                AES_BLK_VERSION_MAJOR_RELEASE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MAJOR_RELEASE_SMASK                                AES_BLK_VERSION_MAJOR_RELEASE_SMASK_V7
#endif

#define  AES_BLK_VERSION_MAJOR_RELEASE_XTRCT_V3(r)                          ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_VERSION_MAJOR_RELEASE_XTRCT_V4(r)                          ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_VERSION_MAJOR_RELEASE_XTRCT_V5(r)                          ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_VERSION_MAJOR_RELEASE_XTRCT_V6(r)                          ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_VERSION_MAJOR_RELEASE_XTRCT_V7(r)                          ((((uint32_t)r) >> 8) & 0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MAJOR_RELEASE_XTRCT                                AES_BLK_VERSION_MAJOR_RELEASE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MAJOR_RELEASE_XTRCT                                AES_BLK_VERSION_MAJOR_RELEASE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MAJOR_RELEASE_XTRCT                                AES_BLK_VERSION_MAJOR_RELEASE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MAJOR_RELEASE_XTRCT                                AES_BLK_VERSION_MAJOR_RELEASE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MAJOR_RELEASE_XTRCT                                AES_BLK_VERSION_MAJOR_RELEASE_XTRCT_V7
#endif

#define  AES_BLK_VERSION_MAJOR_RELEASE_INSRT_V3(f)                          ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_INSRT_V4(f)                          ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_INSRT_V5(f)                          ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_INSRT_V6(f)                          ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_VERSION_MAJOR_RELEASE_INSRT_V7(f)                          ((((uint32_t)f) & 0xff) << 8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_MAJOR_RELEASE_INSRT                                AES_BLK_VERSION_MAJOR_RELEASE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_MAJOR_RELEASE_INSRT                                AES_BLK_VERSION_MAJOR_RELEASE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_MAJOR_RELEASE_INSRT                                AES_BLK_VERSION_MAJOR_RELEASE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_MAJOR_RELEASE_INSRT                                AES_BLK_VERSION_MAJOR_RELEASE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_MAJOR_RELEASE_INSRT                                AES_BLK_VERSION_MAJOR_RELEASE_INSRT_V7
#endif

/*! @} major_release */

/*! 
 *  @addtogroup group995873 fld (VERSION)
 *  @brief Range = 23:16 | Width = 8 | Access = read-only | Default = 0x0
 *  @details Version Number
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_VERSION_FLD_SHIFT_V3                                       (16)
#define  AES_BLK_VERSION_FLD_SHIFT_V4                                       (16)
#define  AES_BLK_VERSION_FLD_SHIFT_V5                                       (16)
#define  AES_BLK_VERSION_FLD_SHIFT_V6                                       (16)
#define  AES_BLK_VERSION_FLD_SHIFT_V7                                       (16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_FLD_SHIFT                                          AES_BLK_VERSION_FLD_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_FLD_SHIFT                                          AES_BLK_VERSION_FLD_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_FLD_SHIFT                                          AES_BLK_VERSION_FLD_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_FLD_SHIFT                                          AES_BLK_VERSION_FLD_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_FLD_SHIFT                                          AES_BLK_VERSION_FLD_SHIFT_V7
#endif

#define  AES_BLK_VERSION_FLD_WIDTH_V3                                       (8)
#define  AES_BLK_VERSION_FLD_WIDTH_V4                                       (8)
#define  AES_BLK_VERSION_FLD_WIDTH_V5                                       (8)
#define  AES_BLK_VERSION_FLD_WIDTH_V6                                       (8)
#define  AES_BLK_VERSION_FLD_WIDTH_V7                                       (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_FLD_WIDTH                                          AES_BLK_VERSION_FLD_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_FLD_WIDTH                                          AES_BLK_VERSION_FLD_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_FLD_WIDTH                                          AES_BLK_VERSION_FLD_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_FLD_WIDTH                                          AES_BLK_VERSION_FLD_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_FLD_WIDTH                                          AES_BLK_VERSION_FLD_WIDTH_V7
#endif

#define  AES_BLK_VERSION_FLD_UMASK_V3                                       (0xff0000)
#define  AES_BLK_VERSION_FLD_UMASK_V4                                       (0xff0000)
#define  AES_BLK_VERSION_FLD_UMASK_V5                                       (0xff0000)
#define  AES_BLK_VERSION_FLD_UMASK_V6                                       (0xff0000)
#define  AES_BLK_VERSION_FLD_UMASK_V7                                       (0xff0000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_FLD_UMASK                                          AES_BLK_VERSION_FLD_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_FLD_UMASK                                          AES_BLK_VERSION_FLD_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_FLD_UMASK                                          AES_BLK_VERSION_FLD_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_FLD_UMASK                                          AES_BLK_VERSION_FLD_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_FLD_UMASK                                          AES_BLK_VERSION_FLD_UMASK_V7
#endif

#define  AES_BLK_VERSION_FLD_SMASK_V3                                       (0xff)
#define  AES_BLK_VERSION_FLD_SMASK_V4                                       (0xff)
#define  AES_BLK_VERSION_FLD_SMASK_V5                                       (0xff)
#define  AES_BLK_VERSION_FLD_SMASK_V6                                       (0xff)
#define  AES_BLK_VERSION_FLD_SMASK_V7                                       (0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_FLD_SMASK                                          AES_BLK_VERSION_FLD_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_FLD_SMASK                                          AES_BLK_VERSION_FLD_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_FLD_SMASK                                          AES_BLK_VERSION_FLD_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_FLD_SMASK                                          AES_BLK_VERSION_FLD_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_FLD_SMASK                                          AES_BLK_VERSION_FLD_SMASK_V7
#endif

#define  AES_BLK_VERSION_FLD_XTRCT_V3(r)                                    ((((uint32_t)r) >> 16) & 0xff)
#define  AES_BLK_VERSION_FLD_XTRCT_V4(r)                                    ((((uint32_t)r) >> 16) & 0xff)
#define  AES_BLK_VERSION_FLD_XTRCT_V5(r)                                    ((((uint32_t)r) >> 16) & 0xff)
#define  AES_BLK_VERSION_FLD_XTRCT_V6(r)                                    ((((uint32_t)r) >> 16) & 0xff)
#define  AES_BLK_VERSION_FLD_XTRCT_V7(r)                                    ((((uint32_t)r) >> 16) & 0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_FLD_XTRCT                                          AES_BLK_VERSION_FLD_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_FLD_XTRCT                                          AES_BLK_VERSION_FLD_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_FLD_XTRCT                                          AES_BLK_VERSION_FLD_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_FLD_XTRCT                                          AES_BLK_VERSION_FLD_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_FLD_XTRCT                                          AES_BLK_VERSION_FLD_XTRCT_V7
#endif

#define  AES_BLK_VERSION_FLD_INSRT_V3(f)                                    ((((uint32_t)f) & 0xff) << 16)
#define  AES_BLK_VERSION_FLD_INSRT_V4(f)                                    ((((uint32_t)f) & 0xff) << 16)
#define  AES_BLK_VERSION_FLD_INSRT_V5(f)                                    ((((uint32_t)f) & 0xff) << 16)
#define  AES_BLK_VERSION_FLD_INSRT_V6(f)                                    ((((uint32_t)f) & 0xff) << 16)
#define  AES_BLK_VERSION_FLD_INSRT_V7(f)                                    ((((uint32_t)f) & 0xff) << 16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_VERSION_FLD_INSRT                                          AES_BLK_VERSION_FLD_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_VERSION_FLD_INSRT                                          AES_BLK_VERSION_FLD_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_VERSION_FLD_INSRT                                          AES_BLK_VERSION_FLD_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_VERSION_FLD_INSRT                                          AES_BLK_VERSION_FLD_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_VERSION_FLD_INSRT                                          AES_BLK_VERSION_FLD_INSRT_V7
#endif

/*! @} fld (VERSION) */

/*! 
 *  @addtogroup group995875 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_VERSION_TNBLE_RESET_UMASK_S8000_A1                         (0xffffff)
#define  AES_BLK_VERSION_TNBLE_RESET_UMASK_S8000_B0                         (0xffffff)
#define  AES_BLK_VERSION_TNBLE_RESET_UMASK_S8001_A0                         (0xffffff)
#define  AES_BLK_VERSION_TNBLE_RESET_UMASK_T8002_A0                         (0xffffff)
#define  AES_BLK_VERSION_TNBLE_RESET_UMASK_T8010_A0                         (0xffffff)

#define  AES_BLK_VERSION_TNBLE_RESET_VALUE_S8000_A1                         (0x0)
#define  AES_BLK_VERSION_TNBLE_RESET_VALUE_S8000_B0                         (0x0)
#define  AES_BLK_VERSION_TNBLE_RESET_VALUE_S8001_A0                         (0x0)
#define  AES_BLK_VERSION_TNBLE_RESET_VALUE_T8002_A0                         (0x0)
#define  AES_BLK_VERSION_TNBLE_RESET_VALUE_T8010_A0                         (0x0)

/*! @} reset */

/*! @} version */

/*! 
 *  @addtogroup group995876 config
 *  @brief Offset = 0x4
 *  @details Configuration register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_CONFIG_OFFSET_V3                                           (0x0 + 0x4)
#define  AES_BLK_CONFIG_OFFSET_V4                                           (0x0 + 0x4)
#define  AES_BLK_CONFIG_OFFSET_V5                                           (0x0 + 0x4)
#define  AES_BLK_CONFIG_OFFSET_V6                                           (0x0 + 0x4)
#define  AES_BLK_CONFIG_OFFSET_V7                                           (0x0 + 0x4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_OFFSET                                              AES_BLK_CONFIG_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_OFFSET                                              AES_BLK_CONFIG_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_OFFSET                                              AES_BLK_CONFIG_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_OFFSET                                              AES_BLK_CONFIG_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_OFFSET                                              AES_BLK_CONFIG_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995877 axi_aruser
 *  @brief Range = 3:0 | Width = 4 | Access = read-write | Default = 0x0
 *  @details USER ID for AXI Address Read transactions
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CONFIG_AXI_ARUSER_SHIFT_V3                                 (0)
#define  AES_BLK_CONFIG_AXI_ARUSER_SHIFT_V4                                 (0)
#define  AES_BLK_CONFIG_AXI_ARUSER_SHIFT_V5                                 (0)
#define  AES_BLK_CONFIG_AXI_ARUSER_SHIFT_V6                                 (0)
#define  AES_BLK_CONFIG_AXI_ARUSER_SHIFT_V7                                 (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARUSER_SHIFT                                    AES_BLK_CONFIG_AXI_ARUSER_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARUSER_SHIFT                                    AES_BLK_CONFIG_AXI_ARUSER_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARUSER_SHIFT                                    AES_BLK_CONFIG_AXI_ARUSER_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARUSER_SHIFT                                    AES_BLK_CONFIG_AXI_ARUSER_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARUSER_SHIFT                                    AES_BLK_CONFIG_AXI_ARUSER_SHIFT_V7
#endif

#define  AES_BLK_CONFIG_AXI_ARUSER_WIDTH_V3                                 (4)
#define  AES_BLK_CONFIG_AXI_ARUSER_WIDTH_V4                                 (4)
#define  AES_BLK_CONFIG_AXI_ARUSER_WIDTH_V5                                 (4)
#define  AES_BLK_CONFIG_AXI_ARUSER_WIDTH_V6                                 (4)
#define  AES_BLK_CONFIG_AXI_ARUSER_WIDTH_V7                                 (4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARUSER_WIDTH                                    AES_BLK_CONFIG_AXI_ARUSER_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARUSER_WIDTH                                    AES_BLK_CONFIG_AXI_ARUSER_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARUSER_WIDTH                                    AES_BLK_CONFIG_AXI_ARUSER_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARUSER_WIDTH                                    AES_BLK_CONFIG_AXI_ARUSER_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARUSER_WIDTH                                    AES_BLK_CONFIG_AXI_ARUSER_WIDTH_V7
#endif

#define  AES_BLK_CONFIG_AXI_ARUSER_UMASK_V3                                 (0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_UMASK_V4                                 (0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_UMASK_V5                                 (0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_UMASK_V6                                 (0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_UMASK_V7                                 (0xf)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARUSER_UMASK                                    AES_BLK_CONFIG_AXI_ARUSER_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARUSER_UMASK                                    AES_BLK_CONFIG_AXI_ARUSER_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARUSER_UMASK                                    AES_BLK_CONFIG_AXI_ARUSER_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARUSER_UMASK                                    AES_BLK_CONFIG_AXI_ARUSER_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARUSER_UMASK                                    AES_BLK_CONFIG_AXI_ARUSER_UMASK_V7
#endif

#define  AES_BLK_CONFIG_AXI_ARUSER_SMASK_V3                                 (0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_SMASK_V4                                 (0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_SMASK_V5                                 (0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_SMASK_V6                                 (0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_SMASK_V7                                 (0xf)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARUSER_SMASK                                    AES_BLK_CONFIG_AXI_ARUSER_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARUSER_SMASK                                    AES_BLK_CONFIG_AXI_ARUSER_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARUSER_SMASK                                    AES_BLK_CONFIG_AXI_ARUSER_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARUSER_SMASK                                    AES_BLK_CONFIG_AXI_ARUSER_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARUSER_SMASK                                    AES_BLK_CONFIG_AXI_ARUSER_SMASK_V7
#endif

#define  AES_BLK_CONFIG_AXI_ARUSER_XTRCT_V3(r)                              ((((uint32_t)r) >> 0) & 0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_XTRCT_V4(r)                              ((((uint32_t)r) >> 0) & 0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_XTRCT_V5(r)                              ((((uint32_t)r) >> 0) & 0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_XTRCT_V6(r)                              ((((uint32_t)r) >> 0) & 0xf)
#define  AES_BLK_CONFIG_AXI_ARUSER_XTRCT_V7(r)                              ((((uint32_t)r) >> 0) & 0xf)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARUSER_XTRCT                                    AES_BLK_CONFIG_AXI_ARUSER_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARUSER_XTRCT                                    AES_BLK_CONFIG_AXI_ARUSER_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARUSER_XTRCT                                    AES_BLK_CONFIG_AXI_ARUSER_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARUSER_XTRCT                                    AES_BLK_CONFIG_AXI_ARUSER_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARUSER_XTRCT                                    AES_BLK_CONFIG_AXI_ARUSER_XTRCT_V7
#endif

#define  AES_BLK_CONFIG_AXI_ARUSER_INSRT_V3(f)                              ((((uint32_t)f) & 0xf) << 0)
#define  AES_BLK_CONFIG_AXI_ARUSER_INSRT_V4(f)                              ((((uint32_t)f) & 0xf) << 0)
#define  AES_BLK_CONFIG_AXI_ARUSER_INSRT_V5(f)                              ((((uint32_t)f) & 0xf) << 0)
#define  AES_BLK_CONFIG_AXI_ARUSER_INSRT_V6(f)                              ((((uint32_t)f) & 0xf) << 0)
#define  AES_BLK_CONFIG_AXI_ARUSER_INSRT_V7(f)                              ((((uint32_t)f) & 0xf) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARUSER_INSRT                                    AES_BLK_CONFIG_AXI_ARUSER_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARUSER_INSRT                                    AES_BLK_CONFIG_AXI_ARUSER_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARUSER_INSRT                                    AES_BLK_CONFIG_AXI_ARUSER_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARUSER_INSRT                                    AES_BLK_CONFIG_AXI_ARUSER_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARUSER_INSRT                                    AES_BLK_CONFIG_AXI_ARUSER_INSRT_V7
#endif

/*! @} axi_aruser */

/*! 
 *  @addtogroup group995878 axi_arcache
 *  @brief Range = 7:4 | Width = 4 | Access = read-write | Default = 0x0
 *  @details ARCACHE for AXI Address Read transactions
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CONFIG_AXI_ARCACHE_SHIFT_V3                                (4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_SHIFT_V4                                (4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_SHIFT_V5                                (4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_SHIFT_V6                                (4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_SHIFT_V7                                (4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARCACHE_SHIFT                                   AES_BLK_CONFIG_AXI_ARCACHE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARCACHE_SHIFT                                   AES_BLK_CONFIG_AXI_ARCACHE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARCACHE_SHIFT                                   AES_BLK_CONFIG_AXI_ARCACHE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARCACHE_SHIFT                                   AES_BLK_CONFIG_AXI_ARCACHE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARCACHE_SHIFT                                   AES_BLK_CONFIG_AXI_ARCACHE_SHIFT_V7
#endif

#define  AES_BLK_CONFIG_AXI_ARCACHE_WIDTH_V3                                (4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_WIDTH_V4                                (4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_WIDTH_V5                                (4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_WIDTH_V6                                (4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_WIDTH_V7                                (4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARCACHE_WIDTH                                   AES_BLK_CONFIG_AXI_ARCACHE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARCACHE_WIDTH                                   AES_BLK_CONFIG_AXI_ARCACHE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARCACHE_WIDTH                                   AES_BLK_CONFIG_AXI_ARCACHE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARCACHE_WIDTH                                   AES_BLK_CONFIG_AXI_ARCACHE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARCACHE_WIDTH                                   AES_BLK_CONFIG_AXI_ARCACHE_WIDTH_V7
#endif

#define  AES_BLK_CONFIG_AXI_ARCACHE_UMASK_V3                                (0xf0)
#define  AES_BLK_CONFIG_AXI_ARCACHE_UMASK_V4                                (0xf0)
#define  AES_BLK_CONFIG_AXI_ARCACHE_UMASK_V5                                (0xf0)
#define  AES_BLK_CONFIG_AXI_ARCACHE_UMASK_V6                                (0xf0)
#define  AES_BLK_CONFIG_AXI_ARCACHE_UMASK_V7                                (0xf0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARCACHE_UMASK                                   AES_BLK_CONFIG_AXI_ARCACHE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARCACHE_UMASK                                   AES_BLK_CONFIG_AXI_ARCACHE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARCACHE_UMASK                                   AES_BLK_CONFIG_AXI_ARCACHE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARCACHE_UMASK                                   AES_BLK_CONFIG_AXI_ARCACHE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARCACHE_UMASK                                   AES_BLK_CONFIG_AXI_ARCACHE_UMASK_V7
#endif

#define  AES_BLK_CONFIG_AXI_ARCACHE_SMASK_V3                                (0xf)
#define  AES_BLK_CONFIG_AXI_ARCACHE_SMASK_V4                                (0xf)
#define  AES_BLK_CONFIG_AXI_ARCACHE_SMASK_V5                                (0xf)
#define  AES_BLK_CONFIG_AXI_ARCACHE_SMASK_V6                                (0xf)
#define  AES_BLK_CONFIG_AXI_ARCACHE_SMASK_V7                                (0xf)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARCACHE_SMASK                                   AES_BLK_CONFIG_AXI_ARCACHE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARCACHE_SMASK                                   AES_BLK_CONFIG_AXI_ARCACHE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARCACHE_SMASK                                   AES_BLK_CONFIG_AXI_ARCACHE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARCACHE_SMASK                                   AES_BLK_CONFIG_AXI_ARCACHE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARCACHE_SMASK                                   AES_BLK_CONFIG_AXI_ARCACHE_SMASK_V7
#endif

#define  AES_BLK_CONFIG_AXI_ARCACHE_XTRCT_V3(r)                             ((((uint32_t)r) >> 4) & 0xf)
#define  AES_BLK_CONFIG_AXI_ARCACHE_XTRCT_V4(r)                             ((((uint32_t)r) >> 4) & 0xf)
#define  AES_BLK_CONFIG_AXI_ARCACHE_XTRCT_V5(r)                             ((((uint32_t)r) >> 4) & 0xf)
#define  AES_BLK_CONFIG_AXI_ARCACHE_XTRCT_V6(r)                             ((((uint32_t)r) >> 4) & 0xf)
#define  AES_BLK_CONFIG_AXI_ARCACHE_XTRCT_V7(r)                             ((((uint32_t)r) >> 4) & 0xf)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARCACHE_XTRCT                                   AES_BLK_CONFIG_AXI_ARCACHE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARCACHE_XTRCT                                   AES_BLK_CONFIG_AXI_ARCACHE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARCACHE_XTRCT                                   AES_BLK_CONFIG_AXI_ARCACHE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARCACHE_XTRCT                                   AES_BLK_CONFIG_AXI_ARCACHE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARCACHE_XTRCT                                   AES_BLK_CONFIG_AXI_ARCACHE_XTRCT_V7
#endif

#define  AES_BLK_CONFIG_AXI_ARCACHE_INSRT_V3(f)                             ((((uint32_t)f) & 0xf) << 4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_INSRT_V4(f)                             ((((uint32_t)f) & 0xf) << 4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_INSRT_V5(f)                             ((((uint32_t)f) & 0xf) << 4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_INSRT_V6(f)                             ((((uint32_t)f) & 0xf) << 4)
#define  AES_BLK_CONFIG_AXI_ARCACHE_INSRT_V7(f)                             ((((uint32_t)f) & 0xf) << 4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_ARCACHE_INSRT                                   AES_BLK_CONFIG_AXI_ARCACHE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_ARCACHE_INSRT                                   AES_BLK_CONFIG_AXI_ARCACHE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_ARCACHE_INSRT                                   AES_BLK_CONFIG_AXI_ARCACHE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_ARCACHE_INSRT                                   AES_BLK_CONFIG_AXI_ARCACHE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_ARCACHE_INSRT                                   AES_BLK_CONFIG_AXI_ARCACHE_INSRT_V7
#endif

/*! @} axi_arcache */

/*! 
 *  @addtogroup group995879 axi_awuser
 *  @brief Range = 11:8 | Width = 4 | Access = read-write | Default = 0x0
 *  @details USER ID for AXI Address Write transactions
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CONFIG_AXI_AWUSER_SHIFT_V3                                 (8)
#define  AES_BLK_CONFIG_AXI_AWUSER_SHIFT_V4                                 (8)
#define  AES_BLK_CONFIG_AXI_AWUSER_SHIFT_V5                                 (8)
#define  AES_BLK_CONFIG_AXI_AWUSER_SHIFT_V6                                 (8)
#define  AES_BLK_CONFIG_AXI_AWUSER_SHIFT_V7                                 (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWUSER_SHIFT                                    AES_BLK_CONFIG_AXI_AWUSER_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWUSER_SHIFT                                    AES_BLK_CONFIG_AXI_AWUSER_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWUSER_SHIFT                                    AES_BLK_CONFIG_AXI_AWUSER_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWUSER_SHIFT                                    AES_BLK_CONFIG_AXI_AWUSER_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWUSER_SHIFT                                    AES_BLK_CONFIG_AXI_AWUSER_SHIFT_V7
#endif

#define  AES_BLK_CONFIG_AXI_AWUSER_WIDTH_V3                                 (4)
#define  AES_BLK_CONFIG_AXI_AWUSER_WIDTH_V4                                 (4)
#define  AES_BLK_CONFIG_AXI_AWUSER_WIDTH_V5                                 (4)
#define  AES_BLK_CONFIG_AXI_AWUSER_WIDTH_V6                                 (4)
#define  AES_BLK_CONFIG_AXI_AWUSER_WIDTH_V7                                 (4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWUSER_WIDTH                                    AES_BLK_CONFIG_AXI_AWUSER_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWUSER_WIDTH                                    AES_BLK_CONFIG_AXI_AWUSER_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWUSER_WIDTH                                    AES_BLK_CONFIG_AXI_AWUSER_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWUSER_WIDTH                                    AES_BLK_CONFIG_AXI_AWUSER_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWUSER_WIDTH                                    AES_BLK_CONFIG_AXI_AWUSER_WIDTH_V7
#endif

#define  AES_BLK_CONFIG_AXI_AWUSER_UMASK_V3                                 (0xf00)
#define  AES_BLK_CONFIG_AXI_AWUSER_UMASK_V4                                 (0xf00)
#define  AES_BLK_CONFIG_AXI_AWUSER_UMASK_V5                                 (0xf00)
#define  AES_BLK_CONFIG_AXI_AWUSER_UMASK_V6                                 (0xf00)
#define  AES_BLK_CONFIG_AXI_AWUSER_UMASK_V7                                 (0xf00)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWUSER_UMASK                                    AES_BLK_CONFIG_AXI_AWUSER_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWUSER_UMASK                                    AES_BLK_CONFIG_AXI_AWUSER_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWUSER_UMASK                                    AES_BLK_CONFIG_AXI_AWUSER_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWUSER_UMASK                                    AES_BLK_CONFIG_AXI_AWUSER_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWUSER_UMASK                                    AES_BLK_CONFIG_AXI_AWUSER_UMASK_V7
#endif

#define  AES_BLK_CONFIG_AXI_AWUSER_SMASK_V3                                 (0xf)
#define  AES_BLK_CONFIG_AXI_AWUSER_SMASK_V4                                 (0xf)
#define  AES_BLK_CONFIG_AXI_AWUSER_SMASK_V5                                 (0xf)
#define  AES_BLK_CONFIG_AXI_AWUSER_SMASK_V6                                 (0xf)
#define  AES_BLK_CONFIG_AXI_AWUSER_SMASK_V7                                 (0xf)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWUSER_SMASK                                    AES_BLK_CONFIG_AXI_AWUSER_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWUSER_SMASK                                    AES_BLK_CONFIG_AXI_AWUSER_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWUSER_SMASK                                    AES_BLK_CONFIG_AXI_AWUSER_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWUSER_SMASK                                    AES_BLK_CONFIG_AXI_AWUSER_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWUSER_SMASK                                    AES_BLK_CONFIG_AXI_AWUSER_SMASK_V7
#endif

#define  AES_BLK_CONFIG_AXI_AWUSER_XTRCT_V3(r)                              ((((uint32_t)r) >> 8) & 0xf)
#define  AES_BLK_CONFIG_AXI_AWUSER_XTRCT_V4(r)                              ((((uint32_t)r) >> 8) & 0xf)
#define  AES_BLK_CONFIG_AXI_AWUSER_XTRCT_V5(r)                              ((((uint32_t)r) >> 8) & 0xf)
#define  AES_BLK_CONFIG_AXI_AWUSER_XTRCT_V6(r)                              ((((uint32_t)r) >> 8) & 0xf)
#define  AES_BLK_CONFIG_AXI_AWUSER_XTRCT_V7(r)                              ((((uint32_t)r) >> 8) & 0xf)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWUSER_XTRCT                                    AES_BLK_CONFIG_AXI_AWUSER_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWUSER_XTRCT                                    AES_BLK_CONFIG_AXI_AWUSER_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWUSER_XTRCT                                    AES_BLK_CONFIG_AXI_AWUSER_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWUSER_XTRCT                                    AES_BLK_CONFIG_AXI_AWUSER_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWUSER_XTRCT                                    AES_BLK_CONFIG_AXI_AWUSER_XTRCT_V7
#endif

#define  AES_BLK_CONFIG_AXI_AWUSER_INSRT_V3(f)                              ((((uint32_t)f) & 0xf) << 8)
#define  AES_BLK_CONFIG_AXI_AWUSER_INSRT_V4(f)                              ((((uint32_t)f) & 0xf) << 8)
#define  AES_BLK_CONFIG_AXI_AWUSER_INSRT_V5(f)                              ((((uint32_t)f) & 0xf) << 8)
#define  AES_BLK_CONFIG_AXI_AWUSER_INSRT_V6(f)                              ((((uint32_t)f) & 0xf) << 8)
#define  AES_BLK_CONFIG_AXI_AWUSER_INSRT_V7(f)                              ((((uint32_t)f) & 0xf) << 8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWUSER_INSRT                                    AES_BLK_CONFIG_AXI_AWUSER_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWUSER_INSRT                                    AES_BLK_CONFIG_AXI_AWUSER_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWUSER_INSRT                                    AES_BLK_CONFIG_AXI_AWUSER_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWUSER_INSRT                                    AES_BLK_CONFIG_AXI_AWUSER_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWUSER_INSRT                                    AES_BLK_CONFIG_AXI_AWUSER_INSRT_V7
#endif

/*! @} axi_awuser */

/*! 
 *  @addtogroup group995880 axi_awcache
 *  @brief Range = 15:12 | Width = 4 | Access = read-write | Default = 0x0
 *  @details AWCACHE for AXI Address Write transactions
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CONFIG_AXI_AWCACHE_SHIFT_V3                                (12)
#define  AES_BLK_CONFIG_AXI_AWCACHE_SHIFT_V4                                (12)
#define  AES_BLK_CONFIG_AXI_AWCACHE_SHIFT_V5                                (12)
#define  AES_BLK_CONFIG_AXI_AWCACHE_SHIFT_V6                                (12)
#define  AES_BLK_CONFIG_AXI_AWCACHE_SHIFT_V7                                (12)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWCACHE_SHIFT                                   AES_BLK_CONFIG_AXI_AWCACHE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWCACHE_SHIFT                                   AES_BLK_CONFIG_AXI_AWCACHE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWCACHE_SHIFT                                   AES_BLK_CONFIG_AXI_AWCACHE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWCACHE_SHIFT                                   AES_BLK_CONFIG_AXI_AWCACHE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWCACHE_SHIFT                                   AES_BLK_CONFIG_AXI_AWCACHE_SHIFT_V7
#endif

#define  AES_BLK_CONFIG_AXI_AWCACHE_WIDTH_V3                                (4)
#define  AES_BLK_CONFIG_AXI_AWCACHE_WIDTH_V4                                (4)
#define  AES_BLK_CONFIG_AXI_AWCACHE_WIDTH_V5                                (4)
#define  AES_BLK_CONFIG_AXI_AWCACHE_WIDTH_V6                                (4)
#define  AES_BLK_CONFIG_AXI_AWCACHE_WIDTH_V7                                (4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWCACHE_WIDTH                                   AES_BLK_CONFIG_AXI_AWCACHE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWCACHE_WIDTH                                   AES_BLK_CONFIG_AXI_AWCACHE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWCACHE_WIDTH                                   AES_BLK_CONFIG_AXI_AWCACHE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWCACHE_WIDTH                                   AES_BLK_CONFIG_AXI_AWCACHE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWCACHE_WIDTH                                   AES_BLK_CONFIG_AXI_AWCACHE_WIDTH_V7
#endif

#define  AES_BLK_CONFIG_AXI_AWCACHE_UMASK_V3                                (0xf000)
#define  AES_BLK_CONFIG_AXI_AWCACHE_UMASK_V4                                (0xf000)
#define  AES_BLK_CONFIG_AXI_AWCACHE_UMASK_V5                                (0xf000)
#define  AES_BLK_CONFIG_AXI_AWCACHE_UMASK_V6                                (0xf000)
#define  AES_BLK_CONFIG_AXI_AWCACHE_UMASK_V7                                (0xf000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWCACHE_UMASK                                   AES_BLK_CONFIG_AXI_AWCACHE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWCACHE_UMASK                                   AES_BLK_CONFIG_AXI_AWCACHE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWCACHE_UMASK                                   AES_BLK_CONFIG_AXI_AWCACHE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWCACHE_UMASK                                   AES_BLK_CONFIG_AXI_AWCACHE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWCACHE_UMASK                                   AES_BLK_CONFIG_AXI_AWCACHE_UMASK_V7
#endif

#define  AES_BLK_CONFIG_AXI_AWCACHE_SMASK_V3                                (0xf)
#define  AES_BLK_CONFIG_AXI_AWCACHE_SMASK_V4                                (0xf)
#define  AES_BLK_CONFIG_AXI_AWCACHE_SMASK_V5                                (0xf)
#define  AES_BLK_CONFIG_AXI_AWCACHE_SMASK_V6                                (0xf)
#define  AES_BLK_CONFIG_AXI_AWCACHE_SMASK_V7                                (0xf)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWCACHE_SMASK                                   AES_BLK_CONFIG_AXI_AWCACHE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWCACHE_SMASK                                   AES_BLK_CONFIG_AXI_AWCACHE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWCACHE_SMASK                                   AES_BLK_CONFIG_AXI_AWCACHE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWCACHE_SMASK                                   AES_BLK_CONFIG_AXI_AWCACHE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWCACHE_SMASK                                   AES_BLK_CONFIG_AXI_AWCACHE_SMASK_V7
#endif

#define  AES_BLK_CONFIG_AXI_AWCACHE_XTRCT_V3(r)                             ((((uint32_t)r) >> 12) & 0xf)
#define  AES_BLK_CONFIG_AXI_AWCACHE_XTRCT_V4(r)                             ((((uint32_t)r) >> 12) & 0xf)
#define  AES_BLK_CONFIG_AXI_AWCACHE_XTRCT_V5(r)                             ((((uint32_t)r) >> 12) & 0xf)
#define  AES_BLK_CONFIG_AXI_AWCACHE_XTRCT_V6(r)                             ((((uint32_t)r) >> 12) & 0xf)
#define  AES_BLK_CONFIG_AXI_AWCACHE_XTRCT_V7(r)                             ((((uint32_t)r) >> 12) & 0xf)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWCACHE_XTRCT                                   AES_BLK_CONFIG_AXI_AWCACHE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWCACHE_XTRCT                                   AES_BLK_CONFIG_AXI_AWCACHE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWCACHE_XTRCT                                   AES_BLK_CONFIG_AXI_AWCACHE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWCACHE_XTRCT                                   AES_BLK_CONFIG_AXI_AWCACHE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWCACHE_XTRCT                                   AES_BLK_CONFIG_AXI_AWCACHE_XTRCT_V7
#endif

#define  AES_BLK_CONFIG_AXI_AWCACHE_INSRT_V3(f)                             ((((uint32_t)f) & 0xf) << 12)
#define  AES_BLK_CONFIG_AXI_AWCACHE_INSRT_V4(f)                             ((((uint32_t)f) & 0xf) << 12)
#define  AES_BLK_CONFIG_AXI_AWCACHE_INSRT_V5(f)                             ((((uint32_t)f) & 0xf) << 12)
#define  AES_BLK_CONFIG_AXI_AWCACHE_INSRT_V6(f)                             ((((uint32_t)f) & 0xf) << 12)
#define  AES_BLK_CONFIG_AXI_AWCACHE_INSRT_V7(f)                             ((((uint32_t)f) & 0xf) << 12)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_AXI_AWCACHE_INSRT                                   AES_BLK_CONFIG_AXI_AWCACHE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_AXI_AWCACHE_INSRT                                   AES_BLK_CONFIG_AXI_AWCACHE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_AXI_AWCACHE_INSRT                                   AES_BLK_CONFIG_AXI_AWCACHE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_AXI_AWCACHE_INSRT                                   AES_BLK_CONFIG_AXI_AWCACHE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_AXI_AWCACHE_INSRT                                   AES_BLK_CONFIG_AXI_AWCACHE_INSRT_V7
#endif

/*! @} axi_awcache */

/*! 
 *  @addtogroup group995881 burst_size
 *  @brief Range = 17:16 | Width = 2 | Access = read-write | Default = 0x0
 *  @details 0 = Full Size (default) 64 bytes, 1 = Half Size 32 bytes, 2 =
 *  Quarter Size 16 bytes, 3 = N/A
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CONFIG_BURST_SIZE_SHIFT_V3                                 (16)
#define  AES_BLK_CONFIG_BURST_SIZE_SHIFT_V4                                 (16)
#define  AES_BLK_CONFIG_BURST_SIZE_SHIFT_V5                                 (16)
#define  AES_BLK_CONFIG_BURST_SIZE_SHIFT_V6                                 (16)
#define  AES_BLK_CONFIG_BURST_SIZE_SHIFT_V7                                 (16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_BURST_SIZE_SHIFT                                    AES_BLK_CONFIG_BURST_SIZE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_BURST_SIZE_SHIFT                                    AES_BLK_CONFIG_BURST_SIZE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_BURST_SIZE_SHIFT                                    AES_BLK_CONFIG_BURST_SIZE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_BURST_SIZE_SHIFT                                    AES_BLK_CONFIG_BURST_SIZE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_BURST_SIZE_SHIFT                                    AES_BLK_CONFIG_BURST_SIZE_SHIFT_V7
#endif

#define  AES_BLK_CONFIG_BURST_SIZE_WIDTH_V3                                 (2)
#define  AES_BLK_CONFIG_BURST_SIZE_WIDTH_V4                                 (2)
#define  AES_BLK_CONFIG_BURST_SIZE_WIDTH_V5                                 (2)
#define  AES_BLK_CONFIG_BURST_SIZE_WIDTH_V6                                 (2)
#define  AES_BLK_CONFIG_BURST_SIZE_WIDTH_V7                                 (2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_BURST_SIZE_WIDTH                                    AES_BLK_CONFIG_BURST_SIZE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_BURST_SIZE_WIDTH                                    AES_BLK_CONFIG_BURST_SIZE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_BURST_SIZE_WIDTH                                    AES_BLK_CONFIG_BURST_SIZE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_BURST_SIZE_WIDTH                                    AES_BLK_CONFIG_BURST_SIZE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_BURST_SIZE_WIDTH                                    AES_BLK_CONFIG_BURST_SIZE_WIDTH_V7
#endif

#define  AES_BLK_CONFIG_BURST_SIZE_UMASK_V3                                 (0x30000)
#define  AES_BLK_CONFIG_BURST_SIZE_UMASK_V4                                 (0x30000)
#define  AES_BLK_CONFIG_BURST_SIZE_UMASK_V5                                 (0x30000)
#define  AES_BLK_CONFIG_BURST_SIZE_UMASK_V6                                 (0x30000)
#define  AES_BLK_CONFIG_BURST_SIZE_UMASK_V7                                 (0x30000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_BURST_SIZE_UMASK                                    AES_BLK_CONFIG_BURST_SIZE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_BURST_SIZE_UMASK                                    AES_BLK_CONFIG_BURST_SIZE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_BURST_SIZE_UMASK                                    AES_BLK_CONFIG_BURST_SIZE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_BURST_SIZE_UMASK                                    AES_BLK_CONFIG_BURST_SIZE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_BURST_SIZE_UMASK                                    AES_BLK_CONFIG_BURST_SIZE_UMASK_V7
#endif

#define  AES_BLK_CONFIG_BURST_SIZE_SMASK_V3                                 (0x3)
#define  AES_BLK_CONFIG_BURST_SIZE_SMASK_V4                                 (0x3)
#define  AES_BLK_CONFIG_BURST_SIZE_SMASK_V5                                 (0x3)
#define  AES_BLK_CONFIG_BURST_SIZE_SMASK_V6                                 (0x3)
#define  AES_BLK_CONFIG_BURST_SIZE_SMASK_V7                                 (0x3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_BURST_SIZE_SMASK                                    AES_BLK_CONFIG_BURST_SIZE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_BURST_SIZE_SMASK                                    AES_BLK_CONFIG_BURST_SIZE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_BURST_SIZE_SMASK                                    AES_BLK_CONFIG_BURST_SIZE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_BURST_SIZE_SMASK                                    AES_BLK_CONFIG_BURST_SIZE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_BURST_SIZE_SMASK                                    AES_BLK_CONFIG_BURST_SIZE_SMASK_V7
#endif

#define  AES_BLK_CONFIG_BURST_SIZE_XTRCT_V3(r)                              ((((uint32_t)r) >> 16) & 0x3)
#define  AES_BLK_CONFIG_BURST_SIZE_XTRCT_V4(r)                              ((((uint32_t)r) >> 16) & 0x3)
#define  AES_BLK_CONFIG_BURST_SIZE_XTRCT_V5(r)                              ((((uint32_t)r) >> 16) & 0x3)
#define  AES_BLK_CONFIG_BURST_SIZE_XTRCT_V6(r)                              ((((uint32_t)r) >> 16) & 0x3)
#define  AES_BLK_CONFIG_BURST_SIZE_XTRCT_V7(r)                              ((((uint32_t)r) >> 16) & 0x3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_BURST_SIZE_XTRCT                                    AES_BLK_CONFIG_BURST_SIZE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_BURST_SIZE_XTRCT                                    AES_BLK_CONFIG_BURST_SIZE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_BURST_SIZE_XTRCT                                    AES_BLK_CONFIG_BURST_SIZE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_BURST_SIZE_XTRCT                                    AES_BLK_CONFIG_BURST_SIZE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_BURST_SIZE_XTRCT                                    AES_BLK_CONFIG_BURST_SIZE_XTRCT_V7
#endif

#define  AES_BLK_CONFIG_BURST_SIZE_INSRT_V3(f)                              ((((uint32_t)f) & 0x3) << 16)
#define  AES_BLK_CONFIG_BURST_SIZE_INSRT_V4(f)                              ((((uint32_t)f) & 0x3) << 16)
#define  AES_BLK_CONFIG_BURST_SIZE_INSRT_V5(f)                              ((((uint32_t)f) & 0x3) << 16)
#define  AES_BLK_CONFIG_BURST_SIZE_INSRT_V6(f)                              ((((uint32_t)f) & 0x3) << 16)
#define  AES_BLK_CONFIG_BURST_SIZE_INSRT_V7(f)                              ((((uint32_t)f) & 0x3) << 16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONFIG_BURST_SIZE_INSRT                                    AES_BLK_CONFIG_BURST_SIZE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONFIG_BURST_SIZE_INSRT                                    AES_BLK_CONFIG_BURST_SIZE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONFIG_BURST_SIZE_INSRT                                    AES_BLK_CONFIG_BURST_SIZE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONFIG_BURST_SIZE_INSRT                                    AES_BLK_CONFIG_BURST_SIZE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONFIG_BURST_SIZE_INSRT                                    AES_BLK_CONFIG_BURST_SIZE_INSRT_V7
#endif

/*! @} burst_size */

/*! 
 *  @addtogroup group995883 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_CONFIG_TNBLE_RESET_UMASK_S8000_A1                          (0x3ffff)
#define  AES_BLK_CONFIG_TNBLE_RESET_UMASK_S8000_B0                          (0x3ffff)
#define  AES_BLK_CONFIG_TNBLE_RESET_UMASK_S8001_A0                          (0x3ffff)
#define  AES_BLK_CONFIG_TNBLE_RESET_UMASK_T8002_A0                          (0x3ffff)
#define  AES_BLK_CONFIG_TNBLE_RESET_UMASK_T8010_A0                          (0x3ffff)

#define  AES_BLK_CONFIG_TNBLE_RESET_VALUE_S8000_A1                          (0x0)
#define  AES_BLK_CONFIG_TNBLE_RESET_VALUE_S8000_B0                          (0x0)
#define  AES_BLK_CONFIG_TNBLE_RESET_VALUE_S8001_A0                          (0x0)
#define  AES_BLK_CONFIG_TNBLE_RESET_VALUE_T8002_A0                          (0x0)
#define  AES_BLK_CONFIG_TNBLE_RESET_VALUE_T8010_A0                          (0x0)

/*! @} reset */

/*! 
 *  @addtogroup group995884 _default (default)
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_CONFIG_TNBLE_DEFAULT_UMASK_S8000_A1                        (0x30000)
#define  AES_BLK_CONFIG_TNBLE_DEFAULT_UMASK_S8000_B0                        (0x30000)
#define  AES_BLK_CONFIG_TNBLE_DEFAULT_UMASK_S8001_A0                        (0x30000)
#define  AES_BLK_CONFIG_TNBLE_DEFAULT_UMASK_T8002_A0                        (0x30000)
#define  AES_BLK_CONFIG_TNBLE_DEFAULT_UMASK_T8010_A0                        (0x30000)

#define  AES_BLK_CONFIG_TNBLE_DEFAULT_VALUE_S8000_A1                        (0x0)
#define  AES_BLK_CONFIG_TNBLE_DEFAULT_VALUE_S8000_B0                        (0x0)
#define  AES_BLK_CONFIG_TNBLE_DEFAULT_VALUE_S8001_A0                        (0x0)
#define  AES_BLK_CONFIG_TNBLE_DEFAULT_VALUE_T8002_A0                        (0x0)
#define  AES_BLK_CONFIG_TNBLE_DEFAULT_VALUE_T8010_A0                        (0x0)

/*! @} _default (default) */

/*! @} config */

/*! 
 *  @addtogroup group995885 control
 *  @brief Offset = 0x8
 *  @details Control Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_CONTROL_OFFSET_V3                                          (0x0 + 0x8)
#define  AES_BLK_CONTROL_OFFSET_V4                                          (0x0 + 0x8)
#define  AES_BLK_CONTROL_OFFSET_V5                                          (0x0 + 0x8)
#define  AES_BLK_CONTROL_OFFSET_V6                                          (0x0 + 0x8)
#define  AES_BLK_CONTROL_OFFSET_V7                                          (0x0 + 0x8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_OFFSET                                             AES_BLK_CONTROL_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_OFFSET                                             AES_BLK_CONTROL_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_OFFSET                                             AES_BLK_CONTROL_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_OFFSET                                             AES_BLK_CONTROL_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_OFFSET                                             AES_BLK_CONTROL_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995886 start
 *  @brief Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0
 *  @details Start executing commands in Command FIFO
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CONTROL_START_SHIFT_V3                                     (0)
#define  AES_BLK_CONTROL_START_SHIFT_V4                                     (0)
#define  AES_BLK_CONTROL_START_SHIFT_V5                                     (0)
#define  AES_BLK_CONTROL_START_SHIFT_V6                                     (0)
#define  AES_BLK_CONTROL_START_SHIFT_V7                                     (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_START_SHIFT                                        AES_BLK_CONTROL_START_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_START_SHIFT                                        AES_BLK_CONTROL_START_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_START_SHIFT                                        AES_BLK_CONTROL_START_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_START_SHIFT                                        AES_BLK_CONTROL_START_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_START_SHIFT                                        AES_BLK_CONTROL_START_SHIFT_V7
#endif

#define  AES_BLK_CONTROL_START_WIDTH_V3                                     (1)
#define  AES_BLK_CONTROL_START_WIDTH_V4                                     (1)
#define  AES_BLK_CONTROL_START_WIDTH_V5                                     (1)
#define  AES_BLK_CONTROL_START_WIDTH_V6                                     (1)
#define  AES_BLK_CONTROL_START_WIDTH_V7                                     (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_START_WIDTH                                        AES_BLK_CONTROL_START_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_START_WIDTH                                        AES_BLK_CONTROL_START_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_START_WIDTH                                        AES_BLK_CONTROL_START_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_START_WIDTH                                        AES_BLK_CONTROL_START_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_START_WIDTH                                        AES_BLK_CONTROL_START_WIDTH_V7
#endif

#define  AES_BLK_CONTROL_START_UMASK_V3                                     (0x1)
#define  AES_BLK_CONTROL_START_UMASK_V4                                     (0x1)
#define  AES_BLK_CONTROL_START_UMASK_V5                                     (0x1)
#define  AES_BLK_CONTROL_START_UMASK_V6                                     (0x1)
#define  AES_BLK_CONTROL_START_UMASK_V7                                     (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_START_UMASK                                        AES_BLK_CONTROL_START_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_START_UMASK                                        AES_BLK_CONTROL_START_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_START_UMASK                                        AES_BLK_CONTROL_START_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_START_UMASK                                        AES_BLK_CONTROL_START_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_START_UMASK                                        AES_BLK_CONTROL_START_UMASK_V7
#endif

#define  AES_BLK_CONTROL_START_SMASK_V3                                     (0x1)
#define  AES_BLK_CONTROL_START_SMASK_V4                                     (0x1)
#define  AES_BLK_CONTROL_START_SMASK_V5                                     (0x1)
#define  AES_BLK_CONTROL_START_SMASK_V6                                     (0x1)
#define  AES_BLK_CONTROL_START_SMASK_V7                                     (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_START_SMASK                                        AES_BLK_CONTROL_START_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_START_SMASK                                        AES_BLK_CONTROL_START_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_START_SMASK                                        AES_BLK_CONTROL_START_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_START_SMASK                                        AES_BLK_CONTROL_START_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_START_SMASK                                        AES_BLK_CONTROL_START_SMASK_V7
#endif

#define  AES_BLK_CONTROL_START_XTRCT_V3(r)                                  ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_CONTROL_START_XTRCT_V4(r)                                  ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_CONTROL_START_XTRCT_V5(r)                                  ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_CONTROL_START_XTRCT_V6(r)                                  ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_CONTROL_START_XTRCT_V7(r)                                  ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_START_XTRCT                                        AES_BLK_CONTROL_START_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_START_XTRCT                                        AES_BLK_CONTROL_START_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_START_XTRCT                                        AES_BLK_CONTROL_START_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_START_XTRCT                                        AES_BLK_CONTROL_START_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_START_XTRCT                                        AES_BLK_CONTROL_START_XTRCT_V7
#endif

#define  AES_BLK_CONTROL_START_INSRT_V3(f)                                  ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_CONTROL_START_INSRT_V4(f)                                  ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_CONTROL_START_INSRT_V5(f)                                  ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_CONTROL_START_INSRT_V6(f)                                  ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_CONTROL_START_INSRT_V7(f)                                  ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_START_INSRT                                        AES_BLK_CONTROL_START_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_START_INSRT                                        AES_BLK_CONTROL_START_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_START_INSRT                                        AES_BLK_CONTROL_START_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_START_INSRT                                        AES_BLK_CONTROL_START_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_START_INSRT                                        AES_BLK_CONTROL_START_INSRT_V7
#endif

/*! @} start */

/*! 
 *  @addtogroup group995887 stop
 *  @brief Range = 1 | Width = 1 | Access = write-auto-clear | Default = 0x0
 *  @details Stop executing commands in Command FIFO
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CONTROL_STOP_SHIFT_V3                                      (1)
#define  AES_BLK_CONTROL_STOP_SHIFT_V4                                      (1)
#define  AES_BLK_CONTROL_STOP_SHIFT_V5                                      (1)
#define  AES_BLK_CONTROL_STOP_SHIFT_V6                                      (1)
#define  AES_BLK_CONTROL_STOP_SHIFT_V7                                      (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_STOP_SHIFT                                         AES_BLK_CONTROL_STOP_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_STOP_SHIFT                                         AES_BLK_CONTROL_STOP_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_STOP_SHIFT                                         AES_BLK_CONTROL_STOP_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_STOP_SHIFT                                         AES_BLK_CONTROL_STOP_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_STOP_SHIFT                                         AES_BLK_CONTROL_STOP_SHIFT_V7
#endif

#define  AES_BLK_CONTROL_STOP_WIDTH_V3                                      (1)
#define  AES_BLK_CONTROL_STOP_WIDTH_V4                                      (1)
#define  AES_BLK_CONTROL_STOP_WIDTH_V5                                      (1)
#define  AES_BLK_CONTROL_STOP_WIDTH_V6                                      (1)
#define  AES_BLK_CONTROL_STOP_WIDTH_V7                                      (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_STOP_WIDTH                                         AES_BLK_CONTROL_STOP_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_STOP_WIDTH                                         AES_BLK_CONTROL_STOP_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_STOP_WIDTH                                         AES_BLK_CONTROL_STOP_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_STOP_WIDTH                                         AES_BLK_CONTROL_STOP_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_STOP_WIDTH                                         AES_BLK_CONTROL_STOP_WIDTH_V7
#endif

#define  AES_BLK_CONTROL_STOP_UMASK_V3                                      (0x2)
#define  AES_BLK_CONTROL_STOP_UMASK_V4                                      (0x2)
#define  AES_BLK_CONTROL_STOP_UMASK_V5                                      (0x2)
#define  AES_BLK_CONTROL_STOP_UMASK_V6                                      (0x2)
#define  AES_BLK_CONTROL_STOP_UMASK_V7                                      (0x2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_STOP_UMASK                                         AES_BLK_CONTROL_STOP_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_STOP_UMASK                                         AES_BLK_CONTROL_STOP_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_STOP_UMASK                                         AES_BLK_CONTROL_STOP_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_STOP_UMASK                                         AES_BLK_CONTROL_STOP_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_STOP_UMASK                                         AES_BLK_CONTROL_STOP_UMASK_V7
#endif

#define  AES_BLK_CONTROL_STOP_SMASK_V3                                      (0x1)
#define  AES_BLK_CONTROL_STOP_SMASK_V4                                      (0x1)
#define  AES_BLK_CONTROL_STOP_SMASK_V5                                      (0x1)
#define  AES_BLK_CONTROL_STOP_SMASK_V6                                      (0x1)
#define  AES_BLK_CONTROL_STOP_SMASK_V7                                      (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_STOP_SMASK                                         AES_BLK_CONTROL_STOP_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_STOP_SMASK                                         AES_BLK_CONTROL_STOP_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_STOP_SMASK                                         AES_BLK_CONTROL_STOP_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_STOP_SMASK                                         AES_BLK_CONTROL_STOP_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_STOP_SMASK                                         AES_BLK_CONTROL_STOP_SMASK_V7
#endif

#define  AES_BLK_CONTROL_STOP_XTRCT_V3(r)                                   ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_CONTROL_STOP_XTRCT_V4(r)                                   ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_CONTROL_STOP_XTRCT_V5(r)                                   ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_CONTROL_STOP_XTRCT_V6(r)                                   ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_CONTROL_STOP_XTRCT_V7(r)                                   ((((uint32_t)r) >> 1) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_STOP_XTRCT                                         AES_BLK_CONTROL_STOP_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_STOP_XTRCT                                         AES_BLK_CONTROL_STOP_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_STOP_XTRCT                                         AES_BLK_CONTROL_STOP_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_STOP_XTRCT                                         AES_BLK_CONTROL_STOP_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_STOP_XTRCT                                         AES_BLK_CONTROL_STOP_XTRCT_V7
#endif

#define  AES_BLK_CONTROL_STOP_INSRT_V3(f)                                   ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_CONTROL_STOP_INSRT_V4(f)                                   ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_CONTROL_STOP_INSRT_V5(f)                                   ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_CONTROL_STOP_INSRT_V6(f)                                   ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_CONTROL_STOP_INSRT_V7(f)                                   ((((uint32_t)f) & 0x1) << 1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_STOP_INSRT                                         AES_BLK_CONTROL_STOP_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_STOP_INSRT                                         AES_BLK_CONTROL_STOP_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_STOP_INSRT                                         AES_BLK_CONTROL_STOP_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_STOP_INSRT                                         AES_BLK_CONTROL_STOP_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_STOP_INSRT                                         AES_BLK_CONTROL_STOP_INSRT_V7
#endif

/*! @} stop */

/*! 
 *  @addtogroup group995888 reset
 *  @brief Range = 2 | Width = 1 | Access = write-auto-clear | Default = 0x0
 *  @details Empty Command FIFO
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CONTROL_RESET_SHIFT_V7                                     (2)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_SHIFT                                        AES_BLK_CONTROL_RESET_SHIFT_V7
#endif

#define  AES_BLK_CONTROL_RESET_WIDTH_V7                                     (1)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_WIDTH                                        AES_BLK_CONTROL_RESET_WIDTH_V7
#endif

#define  AES_BLK_CONTROL_RESET_UMASK_V7                                     (0x4)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_UMASK                                        AES_BLK_CONTROL_RESET_UMASK_V7
#endif

#define  AES_BLK_CONTROL_RESET_SMASK_V7                                     (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_SMASK                                        AES_BLK_CONTROL_RESET_SMASK_V7
#endif

#define  AES_BLK_CONTROL_RESET_XTRCT_V7(r)                                  ((((uint32_t)r) >> 2) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_XTRCT                                        AES_BLK_CONTROL_RESET_XTRCT_V7
#endif

#define  AES_BLK_CONTROL_RESET_INSRT_V7(f)                                  ((((uint32_t)f) & 0x1) << 2)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_INSRT                                        AES_BLK_CONTROL_RESET_INSRT_V7
#endif

/*! @} reset */

/*! 
 *  @addtogroup group995889 reset_aes
 *  @brief Range = 3 | Width = 1 | Access = write-auto-clear | Default = 0x0
 *  @details Reset the AES Engine
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CONTROL_RESET_AES_SHIFT_V3                                 (3)
#define  AES_BLK_CONTROL_RESET_AES_SHIFT_V4                                 (3)
#define  AES_BLK_CONTROL_RESET_AES_SHIFT_V5                                 (3)
#define  AES_BLK_CONTROL_RESET_AES_SHIFT_V6                                 (3)
#define  AES_BLK_CONTROL_RESET_AES_SHIFT_V7                                 (3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_AES_SHIFT                                    AES_BLK_CONTROL_RESET_AES_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_AES_SHIFT                                    AES_BLK_CONTROL_RESET_AES_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_AES_SHIFT                                    AES_BLK_CONTROL_RESET_AES_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_AES_SHIFT                                    AES_BLK_CONTROL_RESET_AES_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_AES_SHIFT                                    AES_BLK_CONTROL_RESET_AES_SHIFT_V7
#endif

#define  AES_BLK_CONTROL_RESET_AES_WIDTH_V3                                 (1)
#define  AES_BLK_CONTROL_RESET_AES_WIDTH_V4                                 (1)
#define  AES_BLK_CONTROL_RESET_AES_WIDTH_V5                                 (1)
#define  AES_BLK_CONTROL_RESET_AES_WIDTH_V6                                 (1)
#define  AES_BLK_CONTROL_RESET_AES_WIDTH_V7                                 (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_AES_WIDTH                                    AES_BLK_CONTROL_RESET_AES_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_AES_WIDTH                                    AES_BLK_CONTROL_RESET_AES_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_AES_WIDTH                                    AES_BLK_CONTROL_RESET_AES_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_AES_WIDTH                                    AES_BLK_CONTROL_RESET_AES_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_AES_WIDTH                                    AES_BLK_CONTROL_RESET_AES_WIDTH_V7
#endif

#define  AES_BLK_CONTROL_RESET_AES_UMASK_V3                                 (0x8)
#define  AES_BLK_CONTROL_RESET_AES_UMASK_V4                                 (0x8)
#define  AES_BLK_CONTROL_RESET_AES_UMASK_V5                                 (0x8)
#define  AES_BLK_CONTROL_RESET_AES_UMASK_V6                                 (0x8)
#define  AES_BLK_CONTROL_RESET_AES_UMASK_V7                                 (0x8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_AES_UMASK                                    AES_BLK_CONTROL_RESET_AES_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_AES_UMASK                                    AES_BLK_CONTROL_RESET_AES_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_AES_UMASK                                    AES_BLK_CONTROL_RESET_AES_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_AES_UMASK                                    AES_BLK_CONTROL_RESET_AES_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_AES_UMASK                                    AES_BLK_CONTROL_RESET_AES_UMASK_V7
#endif

#define  AES_BLK_CONTROL_RESET_AES_SMASK_V3                                 (0x1)
#define  AES_BLK_CONTROL_RESET_AES_SMASK_V4                                 (0x1)
#define  AES_BLK_CONTROL_RESET_AES_SMASK_V5                                 (0x1)
#define  AES_BLK_CONTROL_RESET_AES_SMASK_V6                                 (0x1)
#define  AES_BLK_CONTROL_RESET_AES_SMASK_V7                                 (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_AES_SMASK                                    AES_BLK_CONTROL_RESET_AES_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_AES_SMASK                                    AES_BLK_CONTROL_RESET_AES_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_AES_SMASK                                    AES_BLK_CONTROL_RESET_AES_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_AES_SMASK                                    AES_BLK_CONTROL_RESET_AES_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_AES_SMASK                                    AES_BLK_CONTROL_RESET_AES_SMASK_V7
#endif

#define  AES_BLK_CONTROL_RESET_AES_XTRCT_V3(r)                              ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_CONTROL_RESET_AES_XTRCT_V4(r)                              ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_CONTROL_RESET_AES_XTRCT_V5(r)                              ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_CONTROL_RESET_AES_XTRCT_V6(r)                              ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_CONTROL_RESET_AES_XTRCT_V7(r)                              ((((uint32_t)r) >> 3) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_AES_XTRCT                                    AES_BLK_CONTROL_RESET_AES_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_AES_XTRCT                                    AES_BLK_CONTROL_RESET_AES_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_AES_XTRCT                                    AES_BLK_CONTROL_RESET_AES_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_AES_XTRCT                                    AES_BLK_CONTROL_RESET_AES_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_AES_XTRCT                                    AES_BLK_CONTROL_RESET_AES_XTRCT_V7
#endif

#define  AES_BLK_CONTROL_RESET_AES_INSRT_V3(f)                              ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_CONTROL_RESET_AES_INSRT_V4(f)                              ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_CONTROL_RESET_AES_INSRT_V5(f)                              ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_CONTROL_RESET_AES_INSRT_V6(f)                              ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_CONTROL_RESET_AES_INSRT_V7(f)                              ((((uint32_t)f) & 0x1) << 3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_AES_INSRT                                    AES_BLK_CONTROL_RESET_AES_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_AES_INSRT                                    AES_BLK_CONTROL_RESET_AES_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_AES_INSRT                                    AES_BLK_CONTROL_RESET_AES_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_AES_INSRT                                    AES_BLK_CONTROL_RESET_AES_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_AES_INSRT                                    AES_BLK_CONTROL_RESET_AES_INSRT_V7
#endif

/*! @} reset_aes */

/*! 
 *  @addtogroup group995890 reset_read_channel
 *  @brief Range = 4 | Width = 1 | Access = write-auto-clear | Default = 0x0
 *  @details Unused. May be used in future chips.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT_V3                        (4)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT_V4                        (4)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT_V5                        (4)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT_V6                        (4)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT_V7                        (4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_SHIFT_V7
#endif

#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH_V3                        (1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH_V4                        (1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH_V5                        (1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH_V6                        (1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH_V7                        (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH                           AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH                           AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH                           AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH                           AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH                           AES_BLK_CONTROL_RESET_READ_CHANNEL_WIDTH_V7
#endif

#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK_V3                        (0x10)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK_V4                        (0x10)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK_V5                        (0x10)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK_V6                        (0x10)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK_V7                        (0x10)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK                           AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK                           AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK                           AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK                           AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK                           AES_BLK_CONTROL_RESET_READ_CHANNEL_UMASK_V7
#endif

#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK_V3                        (0x1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK_V4                        (0x1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK_V5                        (0x1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK_V6                        (0x1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK_V7                        (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK                           AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK                           AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK                           AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK                           AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK                           AES_BLK_CONTROL_RESET_READ_CHANNEL_SMASK_V7
#endif

#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT_V3(r)                     ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT_V4(r)                     ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT_V5(r)                     ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT_V6(r)                     ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT_V7(r)                     ((((uint32_t)r) >> 4) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_XTRCT_V7
#endif

#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT_V3(f)                     ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT_V4(f)                     ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT_V5(f)                     ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT_V6(f)                     ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT_V7(f)                     ((((uint32_t)f) & 0x1) << 4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT                           AES_BLK_CONTROL_RESET_READ_CHANNEL_INSRT_V7
#endif

/*! @} reset_read_channel */

/*! 
 *  @addtogroup group995891 reset_write_channel
 *  @brief Range = 5 | Width = 1 | Access = write-auto-clear | Default = 0x0
 *  @details Unused. May be used in future chips.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT_V3                       (5)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT_V4                       (5)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT_V5                       (5)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT_V6                       (5)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT_V7                       (5)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SHIFT_V7
#endif

#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH_V3                       (1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH_V4                       (1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH_V5                       (1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH_V6                       (1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH_V7                       (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_WIDTH_V7
#endif

#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK_V3                       (0x20)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK_V4                       (0x20)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK_V5                       (0x20)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK_V6                       (0x20)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK_V7                       (0x20)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_UMASK_V7
#endif

#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK_V3                       (0x1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK_V4                       (0x1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK_V5                       (0x1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK_V6                       (0x1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK_V7                       (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_SMASK_V7
#endif

#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT_V3(r)                    ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT_V4(r)                    ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT_V5(r)                    ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT_V6(r)                    ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT_V7(r)                    ((((uint32_t)r) >> 5) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_XTRCT_V7
#endif

#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT_V3(f)                    ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT_V4(f)                    ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT_V5(f)                    ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT_V6(f)                    ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT_V7(f)                    ((((uint32_t)f) & 0x1) << 5)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT                          AES_BLK_CONTROL_RESET_WRITE_CHANNEL_INSRT_V7
#endif

/*! @} reset_write_channel */

/*! 
 *  @addtogroup group995893 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_CONTROL_TNBLE_RESET_UMASK_T8010_A0                         (0x3f)

#define  AES_BLK_CONTROL_TNBLE_RESET_VALUE_T8010_A0                         (0x0)

/*! @} reset */

/*! @} control */

/*! 
 *  @addtogroup group995894 status
 *  @brief Offset = 0xc
 *  @details Channel status register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_STATUS_OFFSET_V1                                           (0x0 + 0x0)
#define  AES_BLK_STATUS_OFFSET_V2                                           (0x0 + 0x0)
#define  AES_BLK_STATUS_OFFSET_V3                                           (0x0 + 0xc)
#define  AES_BLK_STATUS_OFFSET_V4                                           (0x0 + 0xc)
#define  AES_BLK_STATUS_OFFSET_V5                                           (0x0 + 0xc)
#define  AES_BLK_STATUS_OFFSET_V6                                           (0x0 + 0xc)
#define  AES_BLK_STATUS_OFFSET_V7                                           (0x0 + 0xc)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_STATUS_OFFSET                                              AES_BLK_STATUS_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_STATUS_OFFSET                                              AES_BLK_STATUS_OFFSET_V2
#elif    SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_OFFSET                                              AES_BLK_STATUS_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_OFFSET                                              AES_BLK_STATUS_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_OFFSET                                              AES_BLK_STATUS_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_OFFSET                                              AES_BLK_STATUS_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_OFFSET                                              AES_BLK_STATUS_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995895 dma_read_active
 *  @brief Range = 0 | Width = 1 | Access = read-only | Default = 0x0
 *  @details The DMA is reading data from System Memory
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT_V3                            (0)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT_V4                            (0)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT_V5                            (0)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT_V6                            (0)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT_V7                            (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT                               AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT                               AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT                               AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT                               AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT                               AES_BLK_STATUS_DMA_READ_ACTIVE_SHIFT_V7
#endif

#define  AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH_V3                            (1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH_V4                            (1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH_V5                            (1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH_V6                            (1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH_V7                            (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH                               AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH                               AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH                               AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH                               AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH                               AES_BLK_STATUS_DMA_READ_ACTIVE_WIDTH_V7
#endif

#define  AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK_V3                            (0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK_V4                            (0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK_V5                            (0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK_V6                            (0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK_V7                            (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK                               AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK                               AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK                               AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK                               AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK                               AES_BLK_STATUS_DMA_READ_ACTIVE_UMASK_V7
#endif

#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK_V3                            (0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK_V4                            (0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK_V5                            (0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK_V6                            (0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK_V7                            (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK                               AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK                               AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK                               AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK                               AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK                               AES_BLK_STATUS_DMA_READ_ACTIVE_SMASK_V7
#endif

#define  AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT_V3(r)                         ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT_V4(r)                         ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT_V5(r)                         ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT_V6(r)                         ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT_V7(r)                         ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT                               AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT                               AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT                               AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT                               AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT                               AES_BLK_STATUS_DMA_READ_ACTIVE_XTRCT_V7
#endif

#define  AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT_V3(f)                         ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT_V4(f)                         ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT_V5(f)                         ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT_V6(f)                         ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT_V7(f)                         ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT                               AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT                               AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT                               AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT                               AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT                               AES_BLK_STATUS_DMA_READ_ACTIVE_INSRT_V7
#endif

/*! @} dma_read_active */

/*! 
 *  @addtogroup group995896 dma_read_incomplete
 *  @brief Range = 1 | Width = 1 | Access = read-only | Default = 0x0
 *  @details The DMA is done reading data from System Memory but not all data
 *  has been pushed into the AES engine
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT_V3                        (1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT_V4                        (1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT_V5                        (1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT_V6                        (1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT_V7                        (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_SHIFT_V7
#endif

#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH_V3                        (1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH_V4                        (1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH_V5                        (1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH_V6                        (1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH_V7                        (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_WIDTH_V7
#endif

#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK_V3                        (0x2)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK_V4                        (0x2)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK_V5                        (0x2)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK_V6                        (0x2)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK_V7                        (0x2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_UMASK_V7
#endif

#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK_V3                        (0x1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK_V4                        (0x1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK_V5                        (0x1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK_V6                        (0x1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK_V7                        (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_SMASK_V7
#endif

#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT_V3(r)                     ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT_V4(r)                     ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT_V5(r)                     ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT_V6(r)                     ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT_V7(r)                     ((((uint32_t)r) >> 1) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_XTRCT_V7
#endif

#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT_V3(f)                     ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT_V4(f)                     ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT_V5(f)                     ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT_V6(f)                     ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT_V7(f)                     ((((uint32_t)f) & 0x1) << 1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT                           AES_BLK_STATUS_DMA_READ_INCOMPLETE_INSRT_V7
#endif

/*! @} dma_read_incomplete */

/*! 
 *  @addtogroup group995897 dma_write_active
 *  @brief Range = 2 | Width = 1 | Access = read-only | Default = 0x0
 *  @details The DMA is writing data to System Memory
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT_V3                           (2)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT_V4                           (2)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT_V5                           (2)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT_V6                           (2)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT_V7                           (2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_SHIFT_V7
#endif

#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH_V3                           (1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH_V4                           (1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH_V5                           (1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH_V6                           (1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH_V7                           (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_WIDTH_V7
#endif

#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK_V3                           (0x4)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK_V4                           (0x4)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK_V5                           (0x4)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK_V6                           (0x4)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK_V7                           (0x4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_UMASK_V7
#endif

#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK_V3                           (0x1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK_V4                           (0x1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK_V5                           (0x1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK_V6                           (0x1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK_V7                           (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_SMASK_V7
#endif

#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT_V3(r)                        ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT_V4(r)                        ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT_V5(r)                        ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT_V6(r)                        ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT_V7(r)                        ((((uint32_t)r) >> 2) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_XTRCT_V7
#endif

#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT_V3(f)                        ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT_V4(f)                        ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT_V5(f)                        ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT_V6(f)                        ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT_V7(f)                        ((((uint32_t)f) & 0x1) << 2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT                              AES_BLK_STATUS_DMA_WRITE_ACTIVE_INSRT_V7
#endif

/*! @} dma_write_active */

/*! 
 *  @addtogroup group995898 dma_write_incomplete
 *  @brief Range = 3 | Width = 1 | Access = read-only | Default = 0x0
 *  @details The DMA is done writing data to System Memory but not all data has
 *  been written
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT_V3                       (3)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT_V4                       (3)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT_V5                       (3)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT_V6                       (3)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT_V7                       (3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SHIFT_V7
#endif

#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH_V3                       (1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH_V4                       (1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH_V5                       (1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH_V6                       (1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH_V7                       (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_WIDTH_V7
#endif

#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK_V3                       (0x8)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK_V4                       (0x8)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK_V5                       (0x8)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK_V6                       (0x8)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK_V7                       (0x8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_UMASK_V7
#endif

#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK_V3                       (0x1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK_V4                       (0x1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK_V5                       (0x1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK_V6                       (0x1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK_V7                       (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_SMASK_V7
#endif

#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT_V3(r)                    ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT_V4(r)                    ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT_V5(r)                    ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT_V6(r)                    ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT_V7(r)                    ((((uint32_t)r) >> 3) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_XTRCT_V7
#endif

#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT_V3(f)                    ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT_V4(f)                    ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT_V5(f)                    ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT_V6(f)                    ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT_V7(f)                    ((((uint32_t)f) & 0x1) << 3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT                          AES_BLK_STATUS_DMA_WRITE_INCOMPLETE_INSRT_V7
#endif

/*! @} dma_write_incomplete */

/*! 
 *  @addtogroup group995899 active (AES_ACTIVE)
 *  @brief Range = 4 | Width = 1 | Access = read-only | Default = 0x0
 *  @details AES module is busy
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_STATUS_ACTIVE_SHIFT_V3                                     (4)
#define  AES_BLK_STATUS_ACTIVE_SHIFT_V4                                     (4)
#define  AES_BLK_STATUS_ACTIVE_SHIFT_V5                                     (4)
#define  AES_BLK_STATUS_ACTIVE_SHIFT_V6                                     (4)
#define  AES_BLK_STATUS_ACTIVE_SHIFT_V7                                     (4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_ACTIVE_SHIFT                                        AES_BLK_STATUS_ACTIVE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_ACTIVE_SHIFT                                        AES_BLK_STATUS_ACTIVE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_ACTIVE_SHIFT                                        AES_BLK_STATUS_ACTIVE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_ACTIVE_SHIFT                                        AES_BLK_STATUS_ACTIVE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_ACTIVE_SHIFT                                        AES_BLK_STATUS_ACTIVE_SHIFT_V7
#endif

#define  AES_BLK_STATUS_ACTIVE_WIDTH_V3                                     (1)
#define  AES_BLK_STATUS_ACTIVE_WIDTH_V4                                     (1)
#define  AES_BLK_STATUS_ACTIVE_WIDTH_V5                                     (1)
#define  AES_BLK_STATUS_ACTIVE_WIDTH_V6                                     (1)
#define  AES_BLK_STATUS_ACTIVE_WIDTH_V7                                     (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_ACTIVE_WIDTH                                        AES_BLK_STATUS_ACTIVE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_ACTIVE_WIDTH                                        AES_BLK_STATUS_ACTIVE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_ACTIVE_WIDTH                                        AES_BLK_STATUS_ACTIVE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_ACTIVE_WIDTH                                        AES_BLK_STATUS_ACTIVE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_ACTIVE_WIDTH                                        AES_BLK_STATUS_ACTIVE_WIDTH_V7
#endif

#define  AES_BLK_STATUS_ACTIVE_UMASK_V3                                     (0x10)
#define  AES_BLK_STATUS_ACTIVE_UMASK_V4                                     (0x10)
#define  AES_BLK_STATUS_ACTIVE_UMASK_V5                                     (0x10)
#define  AES_BLK_STATUS_ACTIVE_UMASK_V6                                     (0x10)
#define  AES_BLK_STATUS_ACTIVE_UMASK_V7                                     (0x10)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_ACTIVE_UMASK                                        AES_BLK_STATUS_ACTIVE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_ACTIVE_UMASK                                        AES_BLK_STATUS_ACTIVE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_ACTIVE_UMASK                                        AES_BLK_STATUS_ACTIVE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_ACTIVE_UMASK                                        AES_BLK_STATUS_ACTIVE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_ACTIVE_UMASK                                        AES_BLK_STATUS_ACTIVE_UMASK_V7
#endif

#define  AES_BLK_STATUS_ACTIVE_SMASK_V3                                     (0x1)
#define  AES_BLK_STATUS_ACTIVE_SMASK_V4                                     (0x1)
#define  AES_BLK_STATUS_ACTIVE_SMASK_V5                                     (0x1)
#define  AES_BLK_STATUS_ACTIVE_SMASK_V6                                     (0x1)
#define  AES_BLK_STATUS_ACTIVE_SMASK_V7                                     (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_ACTIVE_SMASK                                        AES_BLK_STATUS_ACTIVE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_ACTIVE_SMASK                                        AES_BLK_STATUS_ACTIVE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_ACTIVE_SMASK                                        AES_BLK_STATUS_ACTIVE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_ACTIVE_SMASK                                        AES_BLK_STATUS_ACTIVE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_ACTIVE_SMASK                                        AES_BLK_STATUS_ACTIVE_SMASK_V7
#endif

#define  AES_BLK_STATUS_ACTIVE_XTRCT_V3(r)                                  ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_STATUS_ACTIVE_XTRCT_V4(r)                                  ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_STATUS_ACTIVE_XTRCT_V5(r)                                  ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_STATUS_ACTIVE_XTRCT_V6(r)                                  ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_STATUS_ACTIVE_XTRCT_V7(r)                                  ((((uint32_t)r) >> 4) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_ACTIVE_XTRCT                                        AES_BLK_STATUS_ACTIVE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_ACTIVE_XTRCT                                        AES_BLK_STATUS_ACTIVE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_ACTIVE_XTRCT                                        AES_BLK_STATUS_ACTIVE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_ACTIVE_XTRCT                                        AES_BLK_STATUS_ACTIVE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_ACTIVE_XTRCT                                        AES_BLK_STATUS_ACTIVE_XTRCT_V7
#endif

#define  AES_BLK_STATUS_ACTIVE_INSRT_V3(f)                                  ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_STATUS_ACTIVE_INSRT_V4(f)                                  ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_STATUS_ACTIVE_INSRT_V5(f)                                  ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_STATUS_ACTIVE_INSRT_V6(f)                                  ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_STATUS_ACTIVE_INSRT_V7(f)                                  ((((uint32_t)f) & 0x1) << 4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_ACTIVE_INSRT                                        AES_BLK_STATUS_ACTIVE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_ACTIVE_INSRT                                        AES_BLK_STATUS_ACTIVE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_ACTIVE_INSRT                                        AES_BLK_STATUS_ACTIVE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_ACTIVE_INSRT                                        AES_BLK_STATUS_ACTIVE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_ACTIVE_INSRT                                        AES_BLK_STATUS_ACTIVE_INSRT_V7
#endif

/*! @} active (AES_ACTIVE) */

/*! 
 *  @addtogroup group995900 command_fifo_active
 *  @brief Range = 5 | Width = 1 | Access = read-only | Default = 0x0
 *  @details A command is being executed from the Command FIFO
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT_V3                        (5)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT_V4                        (5)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT_V5                        (5)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT_V6                        (5)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT_V7                        (5)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SHIFT_V7
#endif

#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH_V3                        (1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH_V4                        (1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH_V5                        (1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH_V6                        (1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH_V7                        (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_WIDTH_V7
#endif

#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK_V3                        (0x20)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK_V4                        (0x20)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK_V5                        (0x20)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK_V6                        (0x20)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK_V7                        (0x20)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_UMASK_V7
#endif

#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK_V3                        (0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK_V4                        (0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK_V5                        (0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK_V6                        (0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK_V7                        (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_SMASK_V7
#endif

#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT_V3(r)                     ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT_V4(r)                     ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT_V5(r)                     ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT_V6(r)                     ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT_V7(r)                     ((((uint32_t)r) >> 5) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_XTRCT_V7
#endif

#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT_V3(f)                     ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT_V4(f)                     ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT_V5(f)                     ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT_V6(f)                     ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT_V7(f)                     ((((uint32_t)f) & 0x1) << 5)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT                           AES_BLK_STATUS_COMMAND_FIFO_ACTIVE_INSRT_V7
#endif

/*! @} command_fifo_active */

/*! 
 *  @addtogroup group995901 command_fifo_enabled
 *  @brief Range = 6 | Width = 1 | Access = read-only | Default = 0x0
 *  @details Indicates the Command FIFO has been enabled and ready to execute
 *  commands
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT_V3                       (6)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT_V4                       (6)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT_V5                       (6)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT_V6                       (6)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT_V7                       (6)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SHIFT_V7
#endif

#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH_V3                       (1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH_V4                       (1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH_V5                       (1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH_V6                       (1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH_V7                       (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_WIDTH_V7
#endif

#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK_V3                       (0x40)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK_V4                       (0x40)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK_V5                       (0x40)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK_V6                       (0x40)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK_V7                       (0x40)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_UMASK_V7
#endif

#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK_V3                       (0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK_V4                       (0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK_V5                       (0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK_V6                       (0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK_V7                       (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_SMASK_V7
#endif

#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT_V3(r)                    ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT_V4(r)                    ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT_V5(r)                    ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT_V6(r)                    ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT_V7(r)                    ((((uint32_t)r) >> 6) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_XTRCT_V7
#endif

#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT_V3(f)                    ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT_V4(f)                    ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT_V5(f)                    ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT_V6(f)                    ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT_V7(f)                    ((((uint32_t)f) & 0x1) << 6)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT                          AES_BLK_STATUS_COMMAND_FIFO_ENABLED_INSRT_V7
#endif

/*! @} command_fifo_enabled */

/*! 
 *  @addtogroup group995902 text_dpa_random_seeded
 *  @brief Range = 7 | Width = 1 | Access = read-only | Default = 0x0
 *  @details The random number generator for text DPA has been seeded
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SHIFT_V6                     (7)
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SHIFT_V7                     (7)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SHIFT                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SHIFT                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SHIFT_V7
#endif

#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_WIDTH_V6                     (1)
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_WIDTH_V7                     (1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_WIDTH                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_WIDTH                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_WIDTH_V7
#endif

#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_UMASK_V6                     (0x80)
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_UMASK_V7                     (0x80)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_UMASK                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_UMASK                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_UMASK_V7
#endif

#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SMASK_V6                     (0x1)
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SMASK_V7                     (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SMASK                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SMASK                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_SMASK_V7
#endif

#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_XTRCT_V6(r)                  ((((uint32_t)r) >> 7) & 0x1)
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_XTRCT_V7(r)                  ((((uint32_t)r) >> 7) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_XTRCT                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_XTRCT                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_XTRCT_V7
#endif

#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_INSRT_V6(f)                  ((((uint32_t)f) & 0x1) << 7)
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_INSRT_V7(f)                  ((((uint32_t)f) & 0x1) << 7)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_INSRT                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_INSRT                        AES_BLK_STATUS_TEXT_DPA_RANDOM_SEEDED_INSRT_V7
#endif

/*! @} text_dpa_random_seeded */

/*! 
 *  @addtogroup group995903 key_unwrap_dpa_random_seeded
 *  @brief Range = 8 | Width = 1 | Access = read-only | Default = 0x0
 *  @details The random number generator for key unwrap DPA has been seeded
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SHIFT_V6               (8)
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SHIFT_V7               (8)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SHIFT                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SHIFT                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SHIFT_V7
#endif

#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_WIDTH_V6               (1)
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_WIDTH_V7               (1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_WIDTH                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_WIDTH                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_WIDTH_V7
#endif

#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_UMASK_V6               (0x100)
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_UMASK_V7               (0x100)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_UMASK                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_UMASK                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_UMASK_V7
#endif

#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SMASK_V6               (0x1)
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SMASK_V7               (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SMASK                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SMASK                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_SMASK_V7
#endif

#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_XTRCT_V6(r)            ((((uint32_t)r) >> 8) & 0x1)
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_XTRCT_V7(r)            ((((uint32_t)r) >> 8) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_XTRCT                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_XTRCT                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_XTRCT_V7
#endif

#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_INSRT_V6(f)            ((((uint32_t)f) & 0x1) << 8)
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_INSRT_V7(f)            ((((uint32_t)f) & 0x1) << 8)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_INSRT                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_INSRT                  AES_BLK_STATUS_KEY_UNWRAP_DPA_RANDOM_SEEDED_INSRT_V7
#endif

/*! @} key_unwrap_dpa_random_seeded */

/*! 
 *  @addtogroup group995905 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_S5L8960X_A0                       (0x1)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_S5L8960X_B0                       (0x1)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_S5L8960X_B1                       (0x1)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_T7000_A0                          (0x1)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_T7000_B0                          (0x1)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_T7000_B1                          (0x1)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_T7001_A0                          (0x1)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_T7001_A1                          (0x1)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_S7002_A1                          (0x1)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_S8000_A1                          (0x7f)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_S8000_B0                          (0x7f)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_S8001_A0                          (0x7f)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_T8002_A0                          (0x1ff)
#define  AES_BLK_STATUS_TNBLE_RESET_UMASK_T8010_A0                          (0x1ff)

#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_S5L8960X_A0                       (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_S5L8960X_B0                       (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_S5L8960X_B1                       (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_T7000_A0                          (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_T7000_B0                          (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_T7000_B1                          (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_T7001_A0                          (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_T7001_A1                          (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_S7002_A1                          (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_S8000_A1                          (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_S8000_B0                          (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_S8001_A0                          (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_T8002_A0                          (0x0)
#define  AES_BLK_STATUS_TNBLE_RESET_VALUE_T8010_A0                          (0x0)

/*! @} reset */

/*! 
 *  @addtogroup group120223 busy (aes_busy)
 *  @brief Range = 0 | Width = 1 | Access = read-only | Default = 0x0
 *  @details Asserted when either the key configurator, IV setup, or AES cipher
 *  engines are busy
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_STATUS_BUSY_SHIFT_V1                                       (0)
#define  AES_BLK_STATUS_BUSY_SHIFT_V2                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_STATUS_BUSY_SHIFT                                          AES_BLK_STATUS_BUSY_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_STATUS_BUSY_SHIFT                                          AES_BLK_STATUS_BUSY_SHIFT_V2
#endif

#define  AES_BLK_STATUS_BUSY_WIDTH_V1                                       (1)
#define  AES_BLK_STATUS_BUSY_WIDTH_V2                                       (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_STATUS_BUSY_WIDTH                                          AES_BLK_STATUS_BUSY_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_STATUS_BUSY_WIDTH                                          AES_BLK_STATUS_BUSY_WIDTH_V2
#endif

#define  AES_BLK_STATUS_BUSY_UMASK_V1                                       (0x1)
#define  AES_BLK_STATUS_BUSY_UMASK_V2                                       (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_STATUS_BUSY_UMASK                                          AES_BLK_STATUS_BUSY_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_STATUS_BUSY_UMASK                                          AES_BLK_STATUS_BUSY_UMASK_V2
#endif

#define  AES_BLK_STATUS_BUSY_SMASK_V1                                       (0x1)
#define  AES_BLK_STATUS_BUSY_SMASK_V2                                       (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_STATUS_BUSY_SMASK                                          AES_BLK_STATUS_BUSY_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_STATUS_BUSY_SMASK                                          AES_BLK_STATUS_BUSY_SMASK_V2
#endif

#define  AES_BLK_STATUS_BUSY_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_STATUS_BUSY_XTRCT_V2(r)                                    ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_STATUS_BUSY_XTRCT                                          AES_BLK_STATUS_BUSY_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_STATUS_BUSY_XTRCT                                          AES_BLK_STATUS_BUSY_XTRCT_V2
#endif

#define  AES_BLK_STATUS_BUSY_INSRT_V1(f)                                    ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_STATUS_BUSY_INSRT_V2(f)                                    ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_STATUS_BUSY_INSRT                                          AES_BLK_STATUS_BUSY_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_STATUS_BUSY_INSRT                                          AES_BLK_STATUS_BUSY_INSRT_V2
#endif

/*! @} busy (aes_busy) */

/*! @} status */

/*! 
 *  @addtogroup group995906 key_id
 *  @brief Offset = 0x10
 *  @details Current Key IDs
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_KEY_ID_OFFSET_V3                                           (0x0 + 0x10)
#define  AES_BLK_KEY_ID_OFFSET_V4                                           (0x0 + 0x10)
#define  AES_BLK_KEY_ID_OFFSET_V5                                           (0x0 + 0x10)
#define  AES_BLK_KEY_ID_OFFSET_V6                                           (0x0 + 0x10)
#define  AES_BLK_KEY_ID_OFFSET_V7                                           (0x0 + 0x10)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_OFFSET                                              AES_BLK_KEY_ID_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_OFFSET                                              AES_BLK_KEY_ID_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_OFFSET                                              AES_BLK_KEY_ID_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_OFFSET                                              AES_BLK_KEY_ID_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_OFFSET                                              AES_BLK_KEY_ID_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995907 context_0
 *  @brief Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0
 *  @details ID for Key in context 0
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_ID_CONTEXT_0_SHIFT_V3                                  (0)
#define  AES_BLK_KEY_ID_CONTEXT_0_SHIFT_V4                                  (0)
#define  AES_BLK_KEY_ID_CONTEXT_0_SHIFT_V5                                  (0)
#define  AES_BLK_KEY_ID_CONTEXT_0_SHIFT_V6                                  (0)
#define  AES_BLK_KEY_ID_CONTEXT_0_SHIFT_V7                                  (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_0_SHIFT                                     AES_BLK_KEY_ID_CONTEXT_0_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_0_SHIFT                                     AES_BLK_KEY_ID_CONTEXT_0_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_0_SHIFT                                     AES_BLK_KEY_ID_CONTEXT_0_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_0_SHIFT                                     AES_BLK_KEY_ID_CONTEXT_0_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_0_SHIFT                                     AES_BLK_KEY_ID_CONTEXT_0_SHIFT_V7
#endif

#define  AES_BLK_KEY_ID_CONTEXT_0_WIDTH_V3                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_0_WIDTH_V4                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_0_WIDTH_V5                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_0_WIDTH_V6                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_0_WIDTH_V7                                  (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_0_WIDTH                                     AES_BLK_KEY_ID_CONTEXT_0_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_0_WIDTH                                     AES_BLK_KEY_ID_CONTEXT_0_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_0_WIDTH                                     AES_BLK_KEY_ID_CONTEXT_0_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_0_WIDTH                                     AES_BLK_KEY_ID_CONTEXT_0_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_0_WIDTH                                     AES_BLK_KEY_ID_CONTEXT_0_WIDTH_V7
#endif

#define  AES_BLK_KEY_ID_CONTEXT_0_UMASK_V3                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_UMASK_V4                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_UMASK_V5                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_UMASK_V6                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_UMASK_V7                                  (0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_0_UMASK                                     AES_BLK_KEY_ID_CONTEXT_0_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_0_UMASK                                     AES_BLK_KEY_ID_CONTEXT_0_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_0_UMASK                                     AES_BLK_KEY_ID_CONTEXT_0_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_0_UMASK                                     AES_BLK_KEY_ID_CONTEXT_0_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_0_UMASK                                     AES_BLK_KEY_ID_CONTEXT_0_UMASK_V7
#endif

#define  AES_BLK_KEY_ID_CONTEXT_0_SMASK_V3                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_SMASK_V4                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_SMASK_V5                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_SMASK_V6                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_SMASK_V7                                  (0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_0_SMASK                                     AES_BLK_KEY_ID_CONTEXT_0_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_0_SMASK                                     AES_BLK_KEY_ID_CONTEXT_0_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_0_SMASK                                     AES_BLK_KEY_ID_CONTEXT_0_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_0_SMASK                                     AES_BLK_KEY_ID_CONTEXT_0_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_0_SMASK                                     AES_BLK_KEY_ID_CONTEXT_0_SMASK_V7
#endif

#define  AES_BLK_KEY_ID_CONTEXT_0_XTRCT_V3(r)                               ((((uint32_t)r) >> 0) & 0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_XTRCT_V4(r)                               ((((uint32_t)r) >> 0) & 0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_XTRCT_V5(r)                               ((((uint32_t)r) >> 0) & 0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_XTRCT_V6(r)                               ((((uint32_t)r) >> 0) & 0xff)
#define  AES_BLK_KEY_ID_CONTEXT_0_XTRCT_V7(r)                               ((((uint32_t)r) >> 0) & 0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_0_XTRCT                                     AES_BLK_KEY_ID_CONTEXT_0_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_0_XTRCT                                     AES_BLK_KEY_ID_CONTEXT_0_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_0_XTRCT                                     AES_BLK_KEY_ID_CONTEXT_0_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_0_XTRCT                                     AES_BLK_KEY_ID_CONTEXT_0_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_0_XTRCT                                     AES_BLK_KEY_ID_CONTEXT_0_XTRCT_V7
#endif

#define  AES_BLK_KEY_ID_CONTEXT_0_INSRT_V3(f)                               ((((uint32_t)f) & 0xff) << 0)
#define  AES_BLK_KEY_ID_CONTEXT_0_INSRT_V4(f)                               ((((uint32_t)f) & 0xff) << 0)
#define  AES_BLK_KEY_ID_CONTEXT_0_INSRT_V5(f)                               ((((uint32_t)f) & 0xff) << 0)
#define  AES_BLK_KEY_ID_CONTEXT_0_INSRT_V6(f)                               ((((uint32_t)f) & 0xff) << 0)
#define  AES_BLK_KEY_ID_CONTEXT_0_INSRT_V7(f)                               ((((uint32_t)f) & 0xff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_0_INSRT                                     AES_BLK_KEY_ID_CONTEXT_0_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_0_INSRT                                     AES_BLK_KEY_ID_CONTEXT_0_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_0_INSRT                                     AES_BLK_KEY_ID_CONTEXT_0_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_0_INSRT                                     AES_BLK_KEY_ID_CONTEXT_0_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_0_INSRT                                     AES_BLK_KEY_ID_CONTEXT_0_INSRT_V7
#endif

/*! @} context_0 */

/*! 
 *  @addtogroup group995908 context_1
 *  @brief Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0
 *  @details ID for Key in context 1
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_ID_CONTEXT_1_SHIFT_V3                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_1_SHIFT_V4                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_1_SHIFT_V5                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_1_SHIFT_V6                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_1_SHIFT_V7                                  (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_1_SHIFT                                     AES_BLK_KEY_ID_CONTEXT_1_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_1_SHIFT                                     AES_BLK_KEY_ID_CONTEXT_1_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_1_SHIFT                                     AES_BLK_KEY_ID_CONTEXT_1_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_1_SHIFT                                     AES_BLK_KEY_ID_CONTEXT_1_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_1_SHIFT                                     AES_BLK_KEY_ID_CONTEXT_1_SHIFT_V7
#endif

#define  AES_BLK_KEY_ID_CONTEXT_1_WIDTH_V3                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_1_WIDTH_V4                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_1_WIDTH_V5                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_1_WIDTH_V6                                  (8)
#define  AES_BLK_KEY_ID_CONTEXT_1_WIDTH_V7                                  (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_1_WIDTH                                     AES_BLK_KEY_ID_CONTEXT_1_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_1_WIDTH                                     AES_BLK_KEY_ID_CONTEXT_1_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_1_WIDTH                                     AES_BLK_KEY_ID_CONTEXT_1_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_1_WIDTH                                     AES_BLK_KEY_ID_CONTEXT_1_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_1_WIDTH                                     AES_BLK_KEY_ID_CONTEXT_1_WIDTH_V7
#endif

#define  AES_BLK_KEY_ID_CONTEXT_1_UMASK_V3                                  (0xff00)
#define  AES_BLK_KEY_ID_CONTEXT_1_UMASK_V4                                  (0xff00)
#define  AES_BLK_KEY_ID_CONTEXT_1_UMASK_V5                                  (0xff00)
#define  AES_BLK_KEY_ID_CONTEXT_1_UMASK_V6                                  (0xff00)
#define  AES_BLK_KEY_ID_CONTEXT_1_UMASK_V7                                  (0xff00)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_1_UMASK                                     AES_BLK_KEY_ID_CONTEXT_1_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_1_UMASK                                     AES_BLK_KEY_ID_CONTEXT_1_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_1_UMASK                                     AES_BLK_KEY_ID_CONTEXT_1_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_1_UMASK                                     AES_BLK_KEY_ID_CONTEXT_1_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_1_UMASK                                     AES_BLK_KEY_ID_CONTEXT_1_UMASK_V7
#endif

#define  AES_BLK_KEY_ID_CONTEXT_1_SMASK_V3                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_1_SMASK_V4                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_1_SMASK_V5                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_1_SMASK_V6                                  (0xff)
#define  AES_BLK_KEY_ID_CONTEXT_1_SMASK_V7                                  (0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_1_SMASK                                     AES_BLK_KEY_ID_CONTEXT_1_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_1_SMASK                                     AES_BLK_KEY_ID_CONTEXT_1_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_1_SMASK                                     AES_BLK_KEY_ID_CONTEXT_1_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_1_SMASK                                     AES_BLK_KEY_ID_CONTEXT_1_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_1_SMASK                                     AES_BLK_KEY_ID_CONTEXT_1_SMASK_V7
#endif

#define  AES_BLK_KEY_ID_CONTEXT_1_XTRCT_V3(r)                               ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_KEY_ID_CONTEXT_1_XTRCT_V4(r)                               ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_KEY_ID_CONTEXT_1_XTRCT_V5(r)                               ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_KEY_ID_CONTEXT_1_XTRCT_V6(r)                               ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_KEY_ID_CONTEXT_1_XTRCT_V7(r)                               ((((uint32_t)r) >> 8) & 0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_1_XTRCT                                     AES_BLK_KEY_ID_CONTEXT_1_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_1_XTRCT                                     AES_BLK_KEY_ID_CONTEXT_1_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_1_XTRCT                                     AES_BLK_KEY_ID_CONTEXT_1_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_1_XTRCT                                     AES_BLK_KEY_ID_CONTEXT_1_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_1_XTRCT                                     AES_BLK_KEY_ID_CONTEXT_1_XTRCT_V7
#endif

#define  AES_BLK_KEY_ID_CONTEXT_1_INSRT_V3(f)                               ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_KEY_ID_CONTEXT_1_INSRT_V4(f)                               ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_KEY_ID_CONTEXT_1_INSRT_V5(f)                               ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_KEY_ID_CONTEXT_1_INSRT_V6(f)                               ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_KEY_ID_CONTEXT_1_INSRT_V7(f)                               ((((uint32_t)f) & 0xff) << 8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_KEY_ID_CONTEXT_1_INSRT                                     AES_BLK_KEY_ID_CONTEXT_1_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_KEY_ID_CONTEXT_1_INSRT                                     AES_BLK_KEY_ID_CONTEXT_1_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_KEY_ID_CONTEXT_1_INSRT                                     AES_BLK_KEY_ID_CONTEXT_1_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_KEY_ID_CONTEXT_1_INSRT                                     AES_BLK_KEY_ID_CONTEXT_1_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_KEY_ID_CONTEXT_1_INSRT                                     AES_BLK_KEY_ID_CONTEXT_1_INSRT_V7
#endif

/*! @} context_1 */

/*! 
 *  @addtogroup group995910 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_KEY_ID_TNBLE_RESET_UMASK_S8000_A1                          (0xffff)
#define  AES_BLK_KEY_ID_TNBLE_RESET_UMASK_S8000_B0                          (0xffff)
#define  AES_BLK_KEY_ID_TNBLE_RESET_UMASK_S8001_A0                          (0xffff)
#define  AES_BLK_KEY_ID_TNBLE_RESET_UMASK_T8002_A0                          (0xffff)
#define  AES_BLK_KEY_ID_TNBLE_RESET_UMASK_T8010_A0                          (0xffff)

#define  AES_BLK_KEY_ID_TNBLE_RESET_VALUE_S8000_A1                          (0x0)
#define  AES_BLK_KEY_ID_TNBLE_RESET_VALUE_S8000_B0                          (0x0)
#define  AES_BLK_KEY_ID_TNBLE_RESET_VALUE_S8001_A0                          (0x0)
#define  AES_BLK_KEY_ID_TNBLE_RESET_VALUE_T8002_A0                          (0x0)
#define  AES_BLK_KEY_ID_TNBLE_RESET_VALUE_T8010_A0                          (0x0)

/*! @} reset */

/*! @} key_id */

/*! 
 *  @addtogroup group995911 axi_status
 *  @brief Offset = 0x14
 *  @details AXI status register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_AXI_STATUS_OFFSET_V3                                       (0x0 + 0x14)
#define  AES_BLK_AXI_STATUS_OFFSET_V4                                       (0x0 + 0x14)
#define  AES_BLK_AXI_STATUS_OFFSET_V5                                       (0x0 + 0x14)
#define  AES_BLK_AXI_STATUS_OFFSET_V6                                       (0x0 + 0x14)
#define  AES_BLK_AXI_STATUS_OFFSET_V7                                       (0x0 + 0x14)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_OFFSET                                          AES_BLK_AXI_STATUS_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_OFFSET                                          AES_BLK_AXI_STATUS_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_OFFSET                                          AES_BLK_AXI_STATUS_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_OFFSET                                          AES_BLK_AXI_STATUS_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_OFFSET                                          AES_BLK_AXI_STATUS_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995912 read_response
 *  @brief Range = 1:0 | Width = 2 | Access = read-only | Default = 0x0
 *  @details AXI response to read request
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT_V3                          (0)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT_V4                          (0)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT_V5                          (0)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT_V6                          (0)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT_V7                          (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT                             AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT                             AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT                             AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT                             AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT                             AES_BLK_AXI_STATUS_READ_RESPONSE_SHIFT_V7
#endif

#define  AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH_V3                          (2)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH_V4                          (2)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH_V5                          (2)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH_V6                          (2)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH_V7                          (2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH                             AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH                             AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH                             AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH                             AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH                             AES_BLK_AXI_STATUS_READ_RESPONSE_WIDTH_V7
#endif

#define  AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK_V3                          (0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK_V4                          (0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK_V5                          (0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK_V6                          (0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK_V7                          (0x3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK                             AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK                             AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK                             AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK                             AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK                             AES_BLK_AXI_STATUS_READ_RESPONSE_UMASK_V7
#endif

#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK_V3                          (0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK_V4                          (0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK_V5                          (0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK_V6                          (0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK_V7                          (0x3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK                             AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK                             AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK                             AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK                             AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK                             AES_BLK_AXI_STATUS_READ_RESPONSE_SMASK_V7
#endif

#define  AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT_V3(r)                       ((((uint32_t)r) >> 0) & 0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT_V4(r)                       ((((uint32_t)r) >> 0) & 0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT_V5(r)                       ((((uint32_t)r) >> 0) & 0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT_V6(r)                       ((((uint32_t)r) >> 0) & 0x3)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT_V7(r)                       ((((uint32_t)r) >> 0) & 0x3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT                             AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT                             AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT                             AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT                             AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT                             AES_BLK_AXI_STATUS_READ_RESPONSE_XTRCT_V7
#endif

#define  AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT_V3(f)                       ((((uint32_t)f) & 0x3) << 0)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT_V4(f)                       ((((uint32_t)f) & 0x3) << 0)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT_V5(f)                       ((((uint32_t)f) & 0x3) << 0)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT_V6(f)                       ((((uint32_t)f) & 0x3) << 0)
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT_V7(f)                       ((((uint32_t)f) & 0x3) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT                             AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT                             AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT                             AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT                             AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT                             AES_BLK_AXI_STATUS_READ_RESPONSE_INSRT_V7
#endif

/*! @} read_response */

/*! 
 *  @addtogroup group995913 write_response
 *  @brief Range = 3:2 | Width = 2 | Access = read-only | Default = 0x0
 *  @details AXI response to write request
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT_V3                         (2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT_V4                         (2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT_V5                         (2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT_V6                         (2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT_V7                         (2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_SHIFT_V7
#endif

#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH_V3                         (2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH_V4                         (2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH_V5                         (2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH_V6                         (2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH_V7                         (2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_WIDTH_V7
#endif

#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK_V3                         (0xc)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK_V4                         (0xc)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK_V5                         (0xc)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK_V6                         (0xc)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK_V7                         (0xc)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_UMASK_V7
#endif

#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK_V3                         (0x3)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK_V4                         (0x3)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK_V5                         (0x3)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK_V6                         (0x3)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK_V7                         (0x3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_SMASK_V7
#endif

#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT_V3(r)                      ((((uint32_t)r) >> 2) & 0x3)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT_V4(r)                      ((((uint32_t)r) >> 2) & 0x3)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT_V5(r)                      ((((uint32_t)r) >> 2) & 0x3)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT_V6(r)                      ((((uint32_t)r) >> 2) & 0x3)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT_V7(r)                      ((((uint32_t)r) >> 2) & 0x3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_XTRCT_V7
#endif

#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT_V3(f)                      ((((uint32_t)f) & 0x3) << 2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT_V4(f)                      ((((uint32_t)f) & 0x3) << 2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT_V5(f)                      ((((uint32_t)f) & 0x3) << 2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT_V6(f)                      ((((uint32_t)f) & 0x3) << 2)
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT_V7(f)                      ((((uint32_t)f) & 0x3) << 2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT                            AES_BLK_AXI_STATUS_WRITE_RESPONSE_INSRT_V7
#endif

/*! @} write_response */

/*! 
 *  @addtogroup group995915 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_AXI_STATUS_TNBLE_RESET_UMASK_S8000_A1                      (0xf)
#define  AES_BLK_AXI_STATUS_TNBLE_RESET_UMASK_S8000_B0                      (0xf)
#define  AES_BLK_AXI_STATUS_TNBLE_RESET_UMASK_S8001_A0                      (0xf)
#define  AES_BLK_AXI_STATUS_TNBLE_RESET_UMASK_T8002_A0                      (0xf)
#define  AES_BLK_AXI_STATUS_TNBLE_RESET_UMASK_T8010_A0                      (0xf)

#define  AES_BLK_AXI_STATUS_TNBLE_RESET_VALUE_S8000_A1                      (0x0)
#define  AES_BLK_AXI_STATUS_TNBLE_RESET_VALUE_S8000_B0                      (0x0)
#define  AES_BLK_AXI_STATUS_TNBLE_RESET_VALUE_S8001_A0                      (0x0)
#define  AES_BLK_AXI_STATUS_TNBLE_RESET_VALUE_T8002_A0                      (0x0)
#define  AES_BLK_AXI_STATUS_TNBLE_RESET_VALUE_T8010_A0                      (0x0)

/*! @} reset */

/*! @} axi_status */

/*! 
 *  @addtogroup group995916 int_status
 *  @brief Offset = 0x18
 *  @details Channel interrupt status register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_INT_STATUS_OFFSET_V3                                       (0x0 + 0x18)
#define  AES_BLK_INT_STATUS_OFFSET_V4                                       (0x0 + 0x18)
#define  AES_BLK_INT_STATUS_OFFSET_V5                                       (0x0 + 0x18)
#define  AES_BLK_INT_STATUS_OFFSET_V6                                       (0x0 + 0x18)
#define  AES_BLK_INT_STATUS_OFFSET_V7                                       (0x0 + 0x18)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_OFFSET                                          AES_BLK_INT_STATUS_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_OFFSET                                          AES_BLK_INT_STATUS_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_OFFSET                                          AES_BLK_INT_STATUS_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_OFFSET                                          AES_BLK_INT_STATUS_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_OFFSET                                          AES_BLK_INT_STATUS_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995917 command_fifo_low
 *  @brief Range = 0 | Width = 1 | Access = read-only | Default = 0x0
 *  @details The number of entries in the Command FIFO has gone below
 *  CHAN.DMA_WATERMARKS.COMMAND_FIFO_LOW (not sticky)
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT_V3                       (0)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT_V4                       (0)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT_V5                       (0)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT_V6                       (0)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT_V7                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH_V3                       (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH_V4                       (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH_V5                       (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH_V6                       (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH_V7                       (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK_V3                       (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK_V4                       (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK_V5                       (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK_V6                       (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK_V7                       (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK_V3                       (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK_V4                       (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK_V5                       (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK_V6                       (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK_V7                       (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT_V3(r)                    ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT_V4(r)                    ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT_V5(r)                    ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT_V6(r)                    ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT_V7(r)                    ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT_V3(f)                    ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT_V4(f)                    ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT_V5(f)                    ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT_V6(f)                    ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT_V7(f)                    ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT                          AES_BLK_INT_STATUS_COMMAND_FIFO_LOW_INSRT_V7
#endif

/*! @} command_fifo_low */

/*! 
 *  @addtogroup group995918 command_fifo_overflow
 *  @brief Range = 1 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details SW pushed (wrote) too many entries into the Command FIFO
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT_V3                  (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT_V4                  (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT_V5                  (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT_V6                  (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT_V7                  (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH_V3                  (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH_V4                  (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH_V5                  (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH_V6                  (1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH_V7                  (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK_V3                  (0x2)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK_V4                  (0x2)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK_V5                  (0x2)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK_V6                  (0x2)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK_V7                  (0x2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK_V3                  (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK_V4                  (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK_V5                  (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK_V6                  (0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK_V7                  (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT_V3(r)               ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT_V4(r)               ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT_V5(r)               ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT_V6(r)               ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT_V7(r)               ((((uint32_t)r) >> 1) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT_V3(f)               ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT_V4(f)               ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT_V5(f)               ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT_V6(f)               ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT_V7(f)               ((((uint32_t)f) & 0x1) << 1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT                     AES_BLK_INT_STATUS_COMMAND_FIFO_OVERFLOW_INSRT_V7
#endif

/*! @} command_fifo_overflow */

/*! 
 *  @addtogroup group995919 invalid_command
 *  @brief Range = 2 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details An invalid opcode detected.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT_V3                        (2)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT_V4                        (2)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT_V5                        (2)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT_V6                        (2)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT_V7                        (2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT                           AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT                           AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT                           AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT                           AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT                           AES_BLK_INT_STATUS_INVALID_COMMAND_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH_V3                        (1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH_V4                        (1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH_V5                        (1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH_V6                        (1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH_V7                        (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH                           AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH                           AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH                           AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH                           AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH                           AES_BLK_INT_STATUS_INVALID_COMMAND_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK_V3                        (0x4)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK_V4                        (0x4)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK_V5                        (0x4)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK_V6                        (0x4)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK_V7                        (0x4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK                           AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK                           AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK                           AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK                           AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK                           AES_BLK_INT_STATUS_INVALID_COMMAND_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK_V3                        (0x1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK_V4                        (0x1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK_V5                        (0x1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK_V6                        (0x1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK_V7                        (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK                           AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK                           AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK                           AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK                           AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK                           AES_BLK_INT_STATUS_INVALID_COMMAND_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT_V3(r)                     ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT_V4(r)                     ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT_V5(r)                     ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT_V6(r)                     ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT_V7(r)                     ((((uint32_t)r) >> 2) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT                           AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT                           AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT                           AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT                           AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT                           AES_BLK_INT_STATUS_INVALID_COMMAND_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT_V3(f)                     ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT_V4(f)                     ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT_V5(f)                     ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT_V6(f)                     ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT_V7(f)                     ((((uint32_t)f) & 0x1) << 2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT                           AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT                           AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT                           AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT                           AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT                           AES_BLK_INT_STATUS_INVALID_COMMAND_INSRT_V7
#endif

/*! @} invalid_command */

/*! 
 *  @addtogroup group995920 axi_read_response_not_okay
 *  @brief Range = 3 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details AXI responded with an "error", "retry" or "split"
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V3             (3)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V4             (3)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V5             (3)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V6             (3)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V7             (3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V3             (1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V4             (1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V5             (1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V6             (1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V7             (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V3             (0x8)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V4             (0x8)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V5             (0x8)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V6             (0x8)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V7             (0x8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V3             (0x1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V4             (0x1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V5             (0x1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V6             (0x1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V7             (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V3(r)          ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V4(r)          ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V5(r)          ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V6(r)          ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V7(r)          ((((uint32_t)r) >> 3) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V3(f)          ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V4(f)          ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V5(f)          ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V6(f)          ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V7(f)          ((((uint32_t)f) & 0x1) << 3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT                AES_BLK_INT_STATUS_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V7
#endif

/*! @} axi_read_response_not_okay */

/*! 
 *  @addtogroup group995921 axi_write_response_not_okay
 *  @brief Range = 4 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details AXI responded with an "error", "retry" or "split"
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V3            (4)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V4            (4)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V5            (4)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V6            (4)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V7            (4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V3            (1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V4            (1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V5            (1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V6            (1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V7            (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V3            (0x10)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V4            (0x10)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V5            (0x10)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V6            (0x10)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V7            (0x10)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V3            (0x1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V4            (0x1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V5            (0x1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V6            (0x1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V7            (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V3(r)         ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V4(r)         ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V5(r)         ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V6(r)         ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V7(r)         ((((uint32_t)r) >> 4) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V3(f)         ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V4(f)         ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V5(f)         ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V6(f)         ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V7(f)         ((((uint32_t)f) & 0x1) << 4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT               AES_BLK_INT_STATUS_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V7
#endif

/*! @} axi_write_response_not_okay */

/*! 
 *  @addtogroup group995922 flag_command
 *  @brief Range = 5 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details A "flag" command has been executed.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT_V3                           (5)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT_V4                           (5)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT_V5                           (5)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT_V6                           (5)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT_V7                           (5)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT                              AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT                              AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT                              AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT                              AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT                              AES_BLK_INT_STATUS_FLAG_COMMAND_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH_V3                           (1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH_V4                           (1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH_V5                           (1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH_V6                           (1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH_V7                           (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH                              AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH                              AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH                              AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH                              AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH                              AES_BLK_INT_STATUS_FLAG_COMMAND_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK_V3                           (0x20)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK_V4                           (0x20)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK_V5                           (0x20)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK_V6                           (0x20)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK_V7                           (0x20)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK                              AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK                              AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK                              AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK                              AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK                              AES_BLK_INT_STATUS_FLAG_COMMAND_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK_V3                           (0x1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK_V4                           (0x1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK_V5                           (0x1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK_V6                           (0x1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK_V7                           (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK                              AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK                              AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK                              AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK                              AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK                              AES_BLK_INT_STATUS_FLAG_COMMAND_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT_V3(r)                        ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT_V4(r)                        ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT_V5(r)                        ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT_V6(r)                        ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT_V7(r)                        ((((uint32_t)r) >> 5) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT                              AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT                              AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT                              AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT                              AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT                              AES_BLK_INT_STATUS_FLAG_COMMAND_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT_V3(f)                        ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT_V4(f)                        ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT_V5(f)                        ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT_V6(f)                        ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT_V7(f)                        ((((uint32_t)f) & 0x1) << 5)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT                              AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT                              AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT                              AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT                              AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT                              AES_BLK_INT_STATUS_FLAG_COMMAND_INSRT_V7
#endif

/*! @} flag_command */

/*! 
 *  @addtogroup group995923 invalid_data_length
 *  @brief Range = 6 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details Non-multiple of 16B data length.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT_V3                    (6)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT_V4                    (6)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT_V5                    (6)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT_V6                    (6)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT_V7                    (6)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH_V3                    (1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH_V4                    (1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH_V5                    (1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH_V6                    (1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH_V7                    (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK_V3                    (0x40)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK_V4                    (0x40)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK_V5                    (0x40)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK_V6                    (0x40)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK_V7                    (0x40)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK_V3                    (0x1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK_V4                    (0x1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK_V5                    (0x1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK_V6                    (0x1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK_V7                    (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT_V3(r)                 ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT_V4(r)                 ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT_V5(r)                 ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT_V6(r)                 ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT_V7(r)                 ((((uint32_t)r) >> 6) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT_V3(f)                 ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT_V4(f)                 ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT_V5(f)                 ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT_V6(f)                 ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT_V7(f)                 ((((uint32_t)f) & 0x1) << 6)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT                       AES_BLK_INT_STATUS_INVALID_DATA_LENGTH_INSRT_V7
#endif

/*! @} invalid_data_length */

/*! 
 *  @addtogroup group995924 key_0_disabled
 *  @brief Range = 7 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details Keys are disabled
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT_V3                         (7)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT_V4                         (7)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT_V5                         (7)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT_V6                         (7)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT_V7                         (7)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH_V3                         (1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH_V4                         (1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH_V5                         (1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH_V6                         (1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH_V7                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH                            AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH                            AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH                            AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH                            AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH                            AES_BLK_INT_STATUS_KEY_0_DISABLED_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK_V3                         (0x80)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK_V4                         (0x80)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK_V5                         (0x80)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK_V6                         (0x80)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK_V7                         (0x80)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK                            AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK                            AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK                            AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK                            AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK                            AES_BLK_INT_STATUS_KEY_0_DISABLED_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK_V3                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK_V4                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK_V5                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK_V6                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK_V7                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK                            AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK                            AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK                            AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK                            AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK                            AES_BLK_INT_STATUS_KEY_0_DISABLED_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT_V3(r)                      ((((uint32_t)r) >> 7) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT_V4(r)                      ((((uint32_t)r) >> 7) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT_V5(r)                      ((((uint32_t)r) >> 7) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT_V6(r)                      ((((uint32_t)r) >> 7) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT_V7(r)                      ((((uint32_t)r) >> 7) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT_V3(f)                      ((((uint32_t)f) & 0x1) << 7)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT_V4(f)                      ((((uint32_t)f) & 0x1) << 7)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT_V5(f)                      ((((uint32_t)f) & 0x1) << 7)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT_V6(f)                      ((((uint32_t)f) & 0x1) << 7)
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT_V7(f)                      ((((uint32_t)f) & 0x1) << 7)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT                            AES_BLK_INT_STATUS_KEY_0_DISABLED_INSRT_V7
#endif

/*! @} key_0_disabled */

/*! 
 *  @addtogroup group995925 key_0_cmac_tag_mismatch
 *  @brief Range = 8 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details CMAC Tag mismatch detected
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V3                (8)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V4                (8)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V5                (8)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V6                (8)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V7                (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V3                (1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V4                (1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V5                (1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V6                (1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V7                (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK_V3                (0x100)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK_V4                (0x100)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK_V5                (0x100)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK_V6                (0x100)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK_V7                (0x100)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK_V3                (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK_V4                (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK_V5                (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK_V6                (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK_V7                (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V3(r)             ((((uint32_t)r) >> 8) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V4(r)             ((((uint32_t)r) >> 8) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V5(r)             ((((uint32_t)r) >> 8) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V6(r)             ((((uint32_t)r) >> 8) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V7(r)             ((((uint32_t)r) >> 8) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT_V3(f)             ((((uint32_t)f) & 0x1) << 8)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT_V4(f)             ((((uint32_t)f) & 0x1) << 8)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT_V5(f)             ((((uint32_t)f) & 0x1) << 8)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT_V6(f)             ((((uint32_t)f) & 0x1) << 8)
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT_V7(f)             ((((uint32_t)f) & 0x1) << 8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_STATUS_KEY_0_CMAC_TAG_MISMATCH_INSRT_V7
#endif

/*! @} key_0_cmac_tag_mismatch */

/*! 
 *  @addtogroup group995926 key_0_policy_mismatch
 *  @brief Range = 9 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details Key policy mismatch at load time
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT_V3                  (9)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT_V4                  (9)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT_V5                  (9)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT_V6                  (9)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT_V7                  (9)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH_V3                  (1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH_V4                  (1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH_V5                  (1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH_V6                  (1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH_V7                  (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK_V3                  (0x200)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK_V4                  (0x200)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK_V5                  (0x200)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK_V6                  (0x200)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK_V7                  (0x200)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK_V3                  (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK_V4                  (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK_V5                  (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK_V6                  (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK_V7                  (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT_V3(r)               ((((uint32_t)r) >> 9) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT_V4(r)               ((((uint32_t)r) >> 9) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT_V5(r)               ((((uint32_t)r) >> 9) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT_V6(r)               ((((uint32_t)r) >> 9) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT_V7(r)               ((((uint32_t)r) >> 9) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT_V3(f)               ((((uint32_t)f) & 0x1) << 9)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT_V4(f)               ((((uint32_t)f) & 0x1) << 9)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT_V5(f)               ((((uint32_t)f) & 0x1) << 9)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT_V6(f)               ((((uint32_t)f) & 0x1) << 9)
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT_V7(f)               ((((uint32_t)f) & 0x1) << 9)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT                     AES_BLK_INT_STATUS_KEY_0_POLICY_MISMATCH_INSRT_V7
#endif

/*! @} key_0_policy_mismatch */

/*! 
 *  @addtogroup group995927 key_0_invalid_at_use_time
 *  @brief Range = 10 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details Keys have expired
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT_V3              (10)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT_V4              (10)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT_V5              (10)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT_V6              (10)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT_V7              (10)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH_V3              (1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH_V4              (1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH_V5              (1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH_V6              (1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH_V7              (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK_V3              (0x400)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK_V4              (0x400)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK_V5              (0x400)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK_V6              (0x400)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK_V7              (0x400)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK_V3              (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK_V4              (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK_V5              (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK_V6              (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK_V7              (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT_V3(r)           ((((uint32_t)r) >> 10) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT_V4(r)           ((((uint32_t)r) >> 10) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT_V5(r)           ((((uint32_t)r) >> 10) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT_V6(r)           ((((uint32_t)r) >> 10) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT_V7(r)           ((((uint32_t)r) >> 10) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT_V3(f)           ((((uint32_t)f) & 0x1) << 10)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT_V4(f)           ((((uint32_t)f) & 0x1) << 10)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT_V5(f)           ((((uint32_t)f) & 0x1) << 10)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT_V6(f)           ((((uint32_t)f) & 0x1) << 10)
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT_V7(f)           ((((uint32_t)f) & 0x1) << 10)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_STATUS_KEY_0_INVALID_AT_USE_TIME_INSRT_V7
#endif

/*! @} key_0_invalid_at_use_time */

/*! 
 *  @addtogroup group995928 key_0_hdcp_err
 *  @brief Range = 11 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details HDCP error detected
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT_V3                         (11)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT_V4                         (11)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT_V5                         (11)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT_V6                         (11)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT_V7                         (11)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH_V3                         (1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH_V4                         (1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH_V5                         (1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH_V6                         (1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH_V7                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK_V3                         (0x800)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK_V4                         (0x800)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK_V5                         (0x800)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK_V6                         (0x800)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK_V7                         (0x800)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK_V3                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK_V4                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK_V5                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK_V6                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK_V7                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT_V3(r)                      ((((uint32_t)r) >> 11) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT_V4(r)                      ((((uint32_t)r) >> 11) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT_V5(r)                      ((((uint32_t)r) >> 11) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT_V6(r)                      ((((uint32_t)r) >> 11) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT_V7(r)                      ((((uint32_t)r) >> 11) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT_V3(f)                      ((((uint32_t)f) & 0x1) << 11)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT_V4(f)                      ((((uint32_t)f) & 0x1) << 11)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT_V5(f)                      ((((uint32_t)f) & 0x1) << 11)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT_V6(f)                      ((((uint32_t)f) & 0x1) << 11)
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT_V7(f)                      ((((uint32_t)f) & 0x1) << 11)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT                            AES_BLK_INT_STATUS_KEY_0_HDCP_ERR_INSRT_V7
#endif

/*! @} key_0_hdcp_err */

/*! 
 *  @addtogroup group995929 key_0_dpa_random_unseeded
 *  @brief Range = 12 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details DAP random number generator has not been seeded
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT_V6              (12)
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT_V7              (12)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH_V6              (1)
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH_V7              (1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_UMASK_V6              (0x1000)
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_UMASK_V7              (0x1000)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_UMASK                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_UMASK                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SMASK_V6              (0x1)
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SMASK_V7              (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SMASK                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SMASK                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT_V6(r)           ((((uint32_t)r) >> 12) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT_V7(r)           ((((uint32_t)r) >> 12) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_INSRT_V6(f)           ((((uint32_t)f) & 0x1) << 12)
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_INSRT_V7(f)           ((((uint32_t)f) & 0x1) << 12)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_INSRT                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_INSRT                 AES_BLK_INT_STATUS_KEY_0_DPA_RANDOM_UNSEEDED_INSRT_V7
#endif

/*! @} key_0_dpa_random_unseeded */

/*! 
 *  @addtogroup group995930 key_1_disabled
 *  @brief Range = 13 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details Keys are disabled
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT_V3                         (12)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT_V4                         (12)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT_V5                         (12)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT_V6                         (13)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT_V7                         (13)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH_V3                         (1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH_V4                         (1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH_V5                         (1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH_V6                         (1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH_V7                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH                            AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH                            AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH                            AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH                            AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH                            AES_BLK_INT_STATUS_KEY_1_DISABLED_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK_V3                         (0x1000)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK_V4                         (0x1000)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK_V5                         (0x1000)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK_V6                         (0x2000)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK_V7                         (0x2000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK                            AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK                            AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK                            AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK                            AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK                            AES_BLK_INT_STATUS_KEY_1_DISABLED_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK_V3                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK_V4                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK_V5                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK_V6                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK_V7                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK                            AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK                            AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK                            AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK                            AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK                            AES_BLK_INT_STATUS_KEY_1_DISABLED_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT_V3(r)                      ((((uint32_t)r) >> 12) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT_V4(r)                      ((((uint32_t)r) >> 12) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT_V5(r)                      ((((uint32_t)r) >> 12) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT_V6(r)                      ((((uint32_t)r) >> 13) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT_V7(r)                      ((((uint32_t)r) >> 13) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT_V3(f)                      ((((uint32_t)f) & 0x1) << 12)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT_V4(f)                      ((((uint32_t)f) & 0x1) << 12)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT_V5(f)                      ((((uint32_t)f) & 0x1) << 12)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT_V6(f)                      ((((uint32_t)f) & 0x1) << 13)
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT_V7(f)                      ((((uint32_t)f) & 0x1) << 13)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT                            AES_BLK_INT_STATUS_KEY_1_DISABLED_INSRT_V7
#endif

/*! @} key_1_disabled */

/*! 
 *  @addtogroup group995931 key_1_cmac_tag_mismatch
 *  @brief Range = 14 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details CMAC Tag mismatch detected
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V3                (13)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V4                (13)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V5                (13)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V6                (14)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V7                (14)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V3                (1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V4                (1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V5                (1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V6                (1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V7                (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK_V3                (0x2000)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK_V4                (0x2000)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK_V5                (0x2000)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK_V6                (0x4000)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK_V7                (0x4000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK_V3                (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK_V4                (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK_V5                (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK_V6                (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK_V7                (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V3(r)             ((((uint32_t)r) >> 13) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V4(r)             ((((uint32_t)r) >> 13) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V5(r)             ((((uint32_t)r) >> 13) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V6(r)             ((((uint32_t)r) >> 14) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V7(r)             ((((uint32_t)r) >> 14) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT_V3(f)             ((((uint32_t)f) & 0x1) << 13)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT_V4(f)             ((((uint32_t)f) & 0x1) << 13)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT_V5(f)             ((((uint32_t)f) & 0x1) << 13)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT_V6(f)             ((((uint32_t)f) & 0x1) << 14)
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT_V7(f)             ((((uint32_t)f) & 0x1) << 14)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_STATUS_KEY_1_CMAC_TAG_MISMATCH_INSRT_V7
#endif

/*! @} key_1_cmac_tag_mismatch */

/*! 
 *  @addtogroup group995932 key_1_policy_mismatch
 *  @brief Range = 15 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details Key policy mismatch at load time
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT_V3                  (14)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT_V4                  (14)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT_V5                  (14)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT_V6                  (15)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT_V7                  (15)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH_V3                  (1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH_V4                  (1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH_V5                  (1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH_V6                  (1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH_V7                  (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK_V3                  (0x4000)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK_V4                  (0x4000)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK_V5                  (0x4000)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK_V6                  (0x8000)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK_V7                  (0x8000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK_V3                  (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK_V4                  (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK_V5                  (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK_V6                  (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK_V7                  (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT_V3(r)               ((((uint32_t)r) >> 14) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT_V4(r)               ((((uint32_t)r) >> 14) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT_V5(r)               ((((uint32_t)r) >> 14) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT_V6(r)               ((((uint32_t)r) >> 15) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT_V7(r)               ((((uint32_t)r) >> 15) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT_V3(f)               ((((uint32_t)f) & 0x1) << 14)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT_V4(f)               ((((uint32_t)f) & 0x1) << 14)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT_V5(f)               ((((uint32_t)f) & 0x1) << 14)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT_V6(f)               ((((uint32_t)f) & 0x1) << 15)
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT_V7(f)               ((((uint32_t)f) & 0x1) << 15)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT                     AES_BLK_INT_STATUS_KEY_1_POLICY_MISMATCH_INSRT_V7
#endif

/*! @} key_1_policy_mismatch */

/*! 
 *  @addtogroup group995933 key_1_invalid_at_use_time
 *  @brief Range = 16 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details Keys have expired
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT_V3              (15)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT_V4              (15)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT_V5              (15)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT_V6              (16)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT_V7              (16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH_V3              (1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH_V4              (1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH_V5              (1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH_V6              (1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH_V7              (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK_V3              (0x8000)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK_V4              (0x8000)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK_V5              (0x8000)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK_V6              (0x10000)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK_V7              (0x10000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK_V3              (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK_V4              (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK_V5              (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK_V6              (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK_V7              (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT_V3(r)           ((((uint32_t)r) >> 15) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT_V4(r)           ((((uint32_t)r) >> 15) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT_V5(r)           ((((uint32_t)r) >> 15) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT_V6(r)           ((((uint32_t)r) >> 16) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT_V7(r)           ((((uint32_t)r) >> 16) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT_V3(f)           ((((uint32_t)f) & 0x1) << 15)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT_V4(f)           ((((uint32_t)f) & 0x1) << 15)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT_V5(f)           ((((uint32_t)f) & 0x1) << 15)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT_V6(f)           ((((uint32_t)f) & 0x1) << 16)
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT_V7(f)           ((((uint32_t)f) & 0x1) << 16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_STATUS_KEY_1_INVALID_AT_USE_TIME_INSRT_V7
#endif

/*! @} key_1_invalid_at_use_time */

/*! 
 *  @addtogroup group995934 key_1_hdcp_err
 *  @brief Range = 17 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details HDCP error detected
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT_V3                         (16)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT_V4                         (16)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT_V5                         (16)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT_V6                         (17)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT_V7                         (17)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH_V3                         (1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH_V4                         (1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH_V5                         (1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH_V6                         (1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH_V7                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK_V3                         (0x10000)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK_V4                         (0x10000)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK_V5                         (0x10000)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK_V6                         (0x20000)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK_V7                         (0x20000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK_V3                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK_V4                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK_V5                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK_V6                         (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK_V7                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT_V3(r)                      ((((uint32_t)r) >> 16) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT_V4(r)                      ((((uint32_t)r) >> 16) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT_V5(r)                      ((((uint32_t)r) >> 16) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT_V6(r)                      ((((uint32_t)r) >> 17) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT_V7(r)                      ((((uint32_t)r) >> 17) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT_V3(f)                      ((((uint32_t)f) & 0x1) << 16)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT_V4(f)                      ((((uint32_t)f) & 0x1) << 16)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT_V5(f)                      ((((uint32_t)f) & 0x1) << 16)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT_V6(f)                      ((((uint32_t)f) & 0x1) << 17)
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT_V7(f)                      ((((uint32_t)f) & 0x1) << 17)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT                            AES_BLK_INT_STATUS_KEY_1_HDCP_ERR_INSRT_V7
#endif

/*! @} key_1_hdcp_err */

/*! 
 *  @addtogroup group995935 key_1_dpa_random_unseeded
 *  @brief Range = 18 | Width = 1 | Access = write-once-clear | Default = 0x0
 *  @details DAP random number generator has not been seeded
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT_V6              (18)
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT_V7              (18)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH_V6              (1)
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH_V7              (1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_UMASK_V6              (0x40000)
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_UMASK_V7              (0x40000)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_UMASK                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_UMASK                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_UMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SMASK_V6              (0x1)
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SMASK_V7              (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SMASK                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SMASK                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_SMASK_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT_V6(r)           ((((uint32_t)r) >> 18) & 0x1)
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT_V7(r)           ((((uint32_t)r) >> 18) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT_V7
#endif

#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_INSRT_V6(f)           ((((uint32_t)f) & 0x1) << 18)
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_INSRT_V7(f)           ((((uint32_t)f) & 0x1) << 18)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_INSRT                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_INSRT                 AES_BLK_INT_STATUS_KEY_1_DPA_RANDOM_UNSEEDED_INSRT_V7
#endif

/*! @} key_1_dpa_random_unseeded */

/*! 
 *  @addtogroup group995937 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_INT_STATUS_TNBLE_RESET_UMASK_S8000_A1                      (0x1ffff)
#define  AES_BLK_INT_STATUS_TNBLE_RESET_UMASK_S8000_B0                      (0x1ffff)
#define  AES_BLK_INT_STATUS_TNBLE_RESET_UMASK_S8001_A0                      (0x1ffff)
#define  AES_BLK_INT_STATUS_TNBLE_RESET_UMASK_T8002_A0                      (0x7ffff)
#define  AES_BLK_INT_STATUS_TNBLE_RESET_UMASK_T8010_A0                      (0x7ffff)

#define  AES_BLK_INT_STATUS_TNBLE_RESET_VALUE_S8000_A1                      (0x0)
#define  AES_BLK_INT_STATUS_TNBLE_RESET_VALUE_S8000_B0                      (0x0)
#define  AES_BLK_INT_STATUS_TNBLE_RESET_VALUE_S8001_A0                      (0x0)
#define  AES_BLK_INT_STATUS_TNBLE_RESET_VALUE_T8002_A0                      (0x0)
#define  AES_BLK_INT_STATUS_TNBLE_RESET_VALUE_T8010_A0                      (0x0)

/*! @} reset */

/*! @} int_status */

/*! 
 *  @addtogroup group995938 int_enable
 *  @brief Offset = 0x1c
 *  @details Channel interrupt enable register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_INT_ENABLE_OFFSET_V3                                       (0x0 + 0x1c)
#define  AES_BLK_INT_ENABLE_OFFSET_V4                                       (0x0 + 0x1c)
#define  AES_BLK_INT_ENABLE_OFFSET_V5                                       (0x0 + 0x1c)
#define  AES_BLK_INT_ENABLE_OFFSET_V6                                       (0x0 + 0x1c)
#define  AES_BLK_INT_ENABLE_OFFSET_V7                                       (0x0 + 0x1c)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_OFFSET                                          AES_BLK_INT_ENABLE_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_OFFSET                                          AES_BLK_INT_ENABLE_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_OFFSET                                          AES_BLK_INT_ENABLE_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_OFFSET                                          AES_BLK_INT_ENABLE_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_OFFSET                                          AES_BLK_INT_ENABLE_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995939 command_fifo_low
 *  @brief Range = 0 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable COMMAND_FIFO_LOW Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT_V3                       (0)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT_V4                       (0)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT_V5                       (0)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT_V6                       (0)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT_V7                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH_V3                       (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH_V4                       (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH_V5                       (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH_V6                       (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH_V7                       (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK_V3                       (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK_V4                       (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK_V5                       (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK_V6                       (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK_V7                       (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK_V3                       (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK_V4                       (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK_V5                       (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK_V6                       (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK_V7                       (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT_V3(r)                    ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT_V4(r)                    ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT_V5(r)                    ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT_V6(r)                    ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT_V7(r)                    ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT_V3(f)                    ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT_V4(f)                    ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT_V5(f)                    ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT_V6(f)                    ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT_V7(f)                    ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT                          AES_BLK_INT_ENABLE_COMMAND_FIFO_LOW_INSRT_V7
#endif

/*! @} command_fifo_low */

/*! 
 *  @addtogroup group995940 command_fifo_overflow
 *  @brief Range = 1 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable COMMAND_FIFO_OVERFLOW Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT_V3                  (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT_V4                  (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT_V5                  (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT_V6                  (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT_V7                  (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH_V3                  (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH_V4                  (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH_V5                  (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH_V6                  (1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH_V7                  (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK_V3                  (0x2)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK_V4                  (0x2)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK_V5                  (0x2)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK_V6                  (0x2)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK_V7                  (0x2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK_V3                  (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK_V4                  (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK_V5                  (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK_V6                  (0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK_V7                  (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT_V3(r)               ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT_V4(r)               ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT_V5(r)               ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT_V6(r)               ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT_V7(r)               ((((uint32_t)r) >> 1) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT_V3(f)               ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT_V4(f)               ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT_V5(f)               ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT_V6(f)               ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT_V7(f)               ((((uint32_t)f) & 0x1) << 1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT                     AES_BLK_INT_ENABLE_COMMAND_FIFO_OVERFLOW_INSRT_V7
#endif

/*! @} command_fifo_overflow */

/*! 
 *  @addtogroup group995941 invalid_command
 *  @brief Range = 2 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable INVALID_COMMAND Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT_V3                        (2)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT_V4                        (2)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT_V5                        (2)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT_V6                        (2)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT_V7                        (2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH_V3                        (1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH_V4                        (1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH_V5                        (1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH_V6                        (1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH_V7                        (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH                           AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH                           AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH                           AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH                           AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH                           AES_BLK_INT_ENABLE_INVALID_COMMAND_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK_V3                        (0x4)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK_V4                        (0x4)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK_V5                        (0x4)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK_V6                        (0x4)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK_V7                        (0x4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK                           AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK                           AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK                           AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK                           AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK                           AES_BLK_INT_ENABLE_INVALID_COMMAND_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK_V3                        (0x1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK_V4                        (0x1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK_V5                        (0x1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK_V6                        (0x1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK_V7                        (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK                           AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK                           AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK                           AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK                           AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK                           AES_BLK_INT_ENABLE_INVALID_COMMAND_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT_V3(r)                     ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT_V4(r)                     ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT_V5(r)                     ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT_V6(r)                     ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT_V7(r)                     ((((uint32_t)r) >> 2) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT_V3(f)                     ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT_V4(f)                     ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT_V5(f)                     ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT_V6(f)                     ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT_V7(f)                     ((((uint32_t)f) & 0x1) << 2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT                           AES_BLK_INT_ENABLE_INVALID_COMMAND_INSRT_V7
#endif

/*! @} invalid_command */

/*! 
 *  @addtogroup group995942 axi_read_response_not_okay
 *  @brief Range = 3 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable AXI_READ_RESPONSE_NOT_OKAY Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V3             (3)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V4             (3)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V5             (3)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V6             (3)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V7             (3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V3             (1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V4             (1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V5             (1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V6             (1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V7             (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V3             (0x8)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V4             (0x8)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V5             (0x8)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V6             (0x8)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V7             (0x8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V3             (0x1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V4             (0x1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V5             (0x1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V6             (0x1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V7             (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V3(r)          ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V4(r)          ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V5(r)          ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V6(r)          ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V7(r)          ((((uint32_t)r) >> 3) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V3(f)          ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V4(f)          ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V5(f)          ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V6(f)          ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V7(f)          ((((uint32_t)f) & 0x1) << 3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT                AES_BLK_INT_ENABLE_AXI_READ_RESPONSE_NOT_OKAY_INSRT_V7
#endif

/*! @} axi_read_response_not_okay */

/*! 
 *  @addtogroup group995943 axi_write_response_not_okay
 *  @brief Range = 4 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable AXI_WRITE_RESPONSE_NOT_OKAY Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V3            (4)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V4            (4)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V5            (4)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V6            (4)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V7            (4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V3            (1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V4            (1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V5            (1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V6            (1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V7            (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V3            (0x10)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V4            (0x10)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V5            (0x10)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V6            (0x10)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V7            (0x10)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V3            (0x1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V4            (0x1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V5            (0x1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V6            (0x1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V7            (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V3(r)         ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V4(r)         ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V5(r)         ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V6(r)         ((((uint32_t)r) >> 4) & 0x1)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V7(r)         ((((uint32_t)r) >> 4) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V3(f)         ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V4(f)         ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V5(f)         ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V6(f)         ((((uint32_t)f) & 0x1) << 4)
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V7(f)         ((((uint32_t)f) & 0x1) << 4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT               AES_BLK_INT_ENABLE_AXI_WRITE_RESPONSE_NOT_OKAY_INSRT_V7
#endif

/*! @} axi_write_response_not_okay */

/*! 
 *  @addtogroup group995944 flag_command
 *  @brief Range = 5 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable FLAG_COMMAND Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT_V3                           (5)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT_V4                           (5)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT_V5                           (5)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT_V6                           (5)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT_V7                           (5)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH_V3                           (1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH_V4                           (1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH_V5                           (1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH_V6                           (1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH_V7                           (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH                              AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH                              AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH                              AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH                              AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH                              AES_BLK_INT_ENABLE_FLAG_COMMAND_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK_V3                           (0x20)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK_V4                           (0x20)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK_V5                           (0x20)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK_V6                           (0x20)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK_V7                           (0x20)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK                              AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK                              AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK                              AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK                              AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK                              AES_BLK_INT_ENABLE_FLAG_COMMAND_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK_V3                           (0x1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK_V4                           (0x1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK_V5                           (0x1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK_V6                           (0x1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK_V7                           (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK                              AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK                              AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK                              AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK                              AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK                              AES_BLK_INT_ENABLE_FLAG_COMMAND_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT_V3(r)                        ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT_V4(r)                        ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT_V5(r)                        ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT_V6(r)                        ((((uint32_t)r) >> 5) & 0x1)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT_V7(r)                        ((((uint32_t)r) >> 5) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT_V3(f)                        ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT_V4(f)                        ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT_V5(f)                        ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT_V6(f)                        ((((uint32_t)f) & 0x1) << 5)
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT_V7(f)                        ((((uint32_t)f) & 0x1) << 5)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT                              AES_BLK_INT_ENABLE_FLAG_COMMAND_INSRT_V7
#endif

/*! @} flag_command */

/*! 
 *  @addtogroup group995945 invalid_data_length
 *  @brief Range = 6 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable INVALID_DATA_LENGTH Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT_V3                    (6)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT_V4                    (6)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT_V5                    (6)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT_V6                    (6)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT_V7                    (6)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH_V3                    (1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH_V4                    (1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH_V5                    (1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH_V6                    (1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH_V7                    (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK_V3                    (0x40)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK_V4                    (0x40)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK_V5                    (0x40)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK_V6                    (0x40)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK_V7                    (0x40)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK_V3                    (0x1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK_V4                    (0x1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK_V5                    (0x1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK_V6                    (0x1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK_V7                    (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT_V3(r)                 ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT_V4(r)                 ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT_V5(r)                 ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT_V6(r)                 ((((uint32_t)r) >> 6) & 0x1)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT_V7(r)                 ((((uint32_t)r) >> 6) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT_V3(f)                 ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT_V4(f)                 ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT_V5(f)                 ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT_V6(f)                 ((((uint32_t)f) & 0x1) << 6)
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT_V7(f)                 ((((uint32_t)f) & 0x1) << 6)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT                       AES_BLK_INT_ENABLE_INVALID_DATA_LENGTH_INSRT_V7
#endif

/*! @} invalid_data_length */

/*! 
 *  @addtogroup group995946 key_0_disabled
 *  @brief Range = 7 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_0_DISABLED Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT_V3                         (7)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT_V4                         (7)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT_V5                         (7)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT_V6                         (7)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT_V7                         (7)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH_V3                         (1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH_V4                         (1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH_V5                         (1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH_V6                         (1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH_V7                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK_V3                         (0x80)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK_V4                         (0x80)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK_V5                         (0x80)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK_V6                         (0x80)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK_V7                         (0x80)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK_V3                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK_V4                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK_V5                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK_V6                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK_V7                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT_V3(r)                      ((((uint32_t)r) >> 7) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT_V4(r)                      ((((uint32_t)r) >> 7) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT_V5(r)                      ((((uint32_t)r) >> 7) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT_V6(r)                      ((((uint32_t)r) >> 7) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT_V7(r)                      ((((uint32_t)r) >> 7) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT_V3(f)                      ((((uint32_t)f) & 0x1) << 7)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT_V4(f)                      ((((uint32_t)f) & 0x1) << 7)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT_V5(f)                      ((((uint32_t)f) & 0x1) << 7)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT_V6(f)                      ((((uint32_t)f) & 0x1) << 7)
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT_V7(f)                      ((((uint32_t)f) & 0x1) << 7)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT                            AES_BLK_INT_ENABLE_KEY_0_DISABLED_INSRT_V7
#endif

/*! @} key_0_disabled */

/*! 
 *  @addtogroup group995947 key_0_cmac_tag_mismatch
 *  @brief Range = 8 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_0_CMAC_TAG_MISMATCH Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V3                (8)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V4                (8)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V5                (8)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V6                (8)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V7                (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V3                (1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V4                (1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V5                (1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V6                (1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V7                (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK_V3                (0x100)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK_V4                (0x100)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK_V5                (0x100)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK_V6                (0x100)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK_V7                (0x100)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK_V3                (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK_V4                (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK_V5                (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK_V6                (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK_V7                (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V3(r)             ((((uint32_t)r) >> 8) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V4(r)             ((((uint32_t)r) >> 8) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V5(r)             ((((uint32_t)r) >> 8) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V6(r)             ((((uint32_t)r) >> 8) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V7(r)             ((((uint32_t)r) >> 8) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT_V3(f)             ((((uint32_t)f) & 0x1) << 8)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT_V4(f)             ((((uint32_t)f) & 0x1) << 8)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT_V5(f)             ((((uint32_t)f) & 0x1) << 8)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT_V6(f)             ((((uint32_t)f) & 0x1) << 8)
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT_V7(f)             ((((uint32_t)f) & 0x1) << 8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_ENABLE_KEY_0_CMAC_TAG_MISMATCH_INSRT_V7
#endif

/*! @} key_0_cmac_tag_mismatch */

/*! 
 *  @addtogroup group995948 key_0_policy_mismatch
 *  @brief Range = 9 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_0_POLICY_MISMATCH Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT_V3                  (9)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT_V4                  (9)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT_V5                  (9)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT_V6                  (9)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT_V7                  (9)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH_V3                  (1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH_V4                  (1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH_V5                  (1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH_V6                  (1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH_V7                  (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK_V3                  (0x200)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK_V4                  (0x200)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK_V5                  (0x200)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK_V6                  (0x200)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK_V7                  (0x200)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK_V3                  (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK_V4                  (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK_V5                  (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK_V6                  (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK_V7                  (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT_V3(r)               ((((uint32_t)r) >> 9) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT_V4(r)               ((((uint32_t)r) >> 9) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT_V5(r)               ((((uint32_t)r) >> 9) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT_V6(r)               ((((uint32_t)r) >> 9) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT_V7(r)               ((((uint32_t)r) >> 9) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT_V3(f)               ((((uint32_t)f) & 0x1) << 9)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT_V4(f)               ((((uint32_t)f) & 0x1) << 9)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT_V5(f)               ((((uint32_t)f) & 0x1) << 9)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT_V6(f)               ((((uint32_t)f) & 0x1) << 9)
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT_V7(f)               ((((uint32_t)f) & 0x1) << 9)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT                     AES_BLK_INT_ENABLE_KEY_0_POLICY_MISMATCH_INSRT_V7
#endif

/*! @} key_0_policy_mismatch */

/*! 
 *  @addtogroup group995949 key_0_invalid_at_use_time
 *  @brief Range = 10 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_0_INVALID_AT_USE_TIME Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT_V3              (10)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT_V4              (10)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT_V5              (10)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT_V6              (10)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT_V7              (10)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH_V3              (1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH_V4              (1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH_V5              (1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH_V6              (1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH_V7              (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK_V3              (0x400)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK_V4              (0x400)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK_V5              (0x400)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK_V6              (0x400)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK_V7              (0x400)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK_V3              (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK_V4              (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK_V5              (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK_V6              (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK_V7              (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT_V3(r)           ((((uint32_t)r) >> 10) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT_V4(r)           ((((uint32_t)r) >> 10) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT_V5(r)           ((((uint32_t)r) >> 10) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT_V6(r)           ((((uint32_t)r) >> 10) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT_V7(r)           ((((uint32_t)r) >> 10) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT_V3(f)           ((((uint32_t)f) & 0x1) << 10)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT_V4(f)           ((((uint32_t)f) & 0x1) << 10)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT_V5(f)           ((((uint32_t)f) & 0x1) << 10)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT_V6(f)           ((((uint32_t)f) & 0x1) << 10)
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT_V7(f)           ((((uint32_t)f) & 0x1) << 10)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_ENABLE_KEY_0_INVALID_AT_USE_TIME_INSRT_V7
#endif

/*! @} key_0_invalid_at_use_time */

/*! 
 *  @addtogroup group995950 key_0_hdcp_err
 *  @brief Range = 11 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_0_HDCP_ERR Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT_V3                         (11)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT_V4                         (11)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT_V5                         (11)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT_V6                         (11)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT_V7                         (11)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH_V3                         (1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH_V4                         (1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH_V5                         (1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH_V6                         (1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH_V7                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK_V3                         (0x800)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK_V4                         (0x800)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK_V5                         (0x800)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK_V6                         (0x800)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK_V7                         (0x800)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK_V3                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK_V4                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK_V5                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK_V6                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK_V7                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT_V3(r)                      ((((uint32_t)r) >> 11) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT_V4(r)                      ((((uint32_t)r) >> 11) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT_V5(r)                      ((((uint32_t)r) >> 11) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT_V6(r)                      ((((uint32_t)r) >> 11) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT_V7(r)                      ((((uint32_t)r) >> 11) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT_V3(f)                      ((((uint32_t)f) & 0x1) << 11)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT_V4(f)                      ((((uint32_t)f) & 0x1) << 11)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT_V5(f)                      ((((uint32_t)f) & 0x1) << 11)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT_V6(f)                      ((((uint32_t)f) & 0x1) << 11)
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT_V7(f)                      ((((uint32_t)f) & 0x1) << 11)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT                            AES_BLK_INT_ENABLE_KEY_0_HDCP_ERR_INSRT_V7
#endif

/*! @} key_0_hdcp_err */

/*! 
 *  @addtogroup group995951 key_0_dpa_random_unseeded
 *  @brief Range = 12 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_0_DPA_RANDOM_UNSEEDED Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT_V6              (12)
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT_V7              (12)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH_V6              (1)
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH_V7              (1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_UMASK_V6              (0x1000)
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_UMASK_V7              (0x1000)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_UMASK                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_UMASK                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SMASK_V6              (0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SMASK_V7              (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SMASK                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SMASK                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT_V6(r)           ((((uint32_t)r) >> 12) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT_V7(r)           ((((uint32_t)r) >> 12) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_INSRT_V6(f)           ((((uint32_t)f) & 0x1) << 12)
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_INSRT_V7(f)           ((((uint32_t)f) & 0x1) << 12)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_INSRT                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_INSRT                 AES_BLK_INT_ENABLE_KEY_0_DPA_RANDOM_UNSEEDED_INSRT_V7
#endif

/*! @} key_0_dpa_random_unseeded */

/*! 
 *  @addtogroup group995952 key_1_disabled
 *  @brief Range = 13 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_1_DISABLED Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT_V3                         (12)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT_V4                         (12)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT_V5                         (12)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT_V6                         (13)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT_V7                         (13)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH_V3                         (1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH_V4                         (1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH_V5                         (1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH_V6                         (1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH_V7                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK_V3                         (0x1000)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK_V4                         (0x1000)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK_V5                         (0x1000)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK_V6                         (0x2000)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK_V7                         (0x2000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK_V3                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK_V4                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK_V5                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK_V6                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK_V7                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT_V3(r)                      ((((uint32_t)r) >> 12) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT_V4(r)                      ((((uint32_t)r) >> 12) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT_V5(r)                      ((((uint32_t)r) >> 12) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT_V6(r)                      ((((uint32_t)r) >> 13) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT_V7(r)                      ((((uint32_t)r) >> 13) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT_V3(f)                      ((((uint32_t)f) & 0x1) << 12)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT_V4(f)                      ((((uint32_t)f) & 0x1) << 12)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT_V5(f)                      ((((uint32_t)f) & 0x1) << 12)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT_V6(f)                      ((((uint32_t)f) & 0x1) << 13)
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT_V7(f)                      ((((uint32_t)f) & 0x1) << 13)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT                            AES_BLK_INT_ENABLE_KEY_1_DISABLED_INSRT_V7
#endif

/*! @} key_1_disabled */

/*! 
 *  @addtogroup group995953 key_1_cmac_tag_mismatch
 *  @brief Range = 14 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_1_CMAC_TAG_MISMATCH Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V3                (13)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V4                (13)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V5                (13)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V6                (14)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V7                (14)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V3                (1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V4                (1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V5                (1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V6                (1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V7                (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK_V3                (0x2000)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK_V4                (0x2000)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK_V5                (0x2000)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK_V6                (0x4000)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK_V7                (0x4000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK_V3                (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK_V4                (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK_V5                (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK_V6                (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK_V7                (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V3(r)             ((((uint32_t)r) >> 13) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V4(r)             ((((uint32_t)r) >> 13) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V5(r)             ((((uint32_t)r) >> 13) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V6(r)             ((((uint32_t)r) >> 14) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V7(r)             ((((uint32_t)r) >> 14) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT_V3(f)             ((((uint32_t)f) & 0x1) << 13)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT_V4(f)             ((((uint32_t)f) & 0x1) << 13)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT_V5(f)             ((((uint32_t)f) & 0x1) << 13)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT_V6(f)             ((((uint32_t)f) & 0x1) << 14)
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT_V7(f)             ((((uint32_t)f) & 0x1) << 14)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT                   AES_BLK_INT_ENABLE_KEY_1_CMAC_TAG_MISMATCH_INSRT_V7
#endif

/*! @} key_1_cmac_tag_mismatch */

/*! 
 *  @addtogroup group995954 key_1_policy_mismatch
 *  @brief Range = 15 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_1_POLICY_MISMATCH Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT_V3                  (14)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT_V4                  (14)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT_V5                  (14)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT_V6                  (15)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT_V7                  (15)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH_V3                  (1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH_V4                  (1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH_V5                  (1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH_V6                  (1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH_V7                  (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK_V3                  (0x4000)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK_V4                  (0x4000)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK_V5                  (0x4000)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK_V6                  (0x8000)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK_V7                  (0x8000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK_V3                  (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK_V4                  (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK_V5                  (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK_V6                  (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK_V7                  (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT_V3(r)               ((((uint32_t)r) >> 14) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT_V4(r)               ((((uint32_t)r) >> 14) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT_V5(r)               ((((uint32_t)r) >> 14) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT_V6(r)               ((((uint32_t)r) >> 15) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT_V7(r)               ((((uint32_t)r) >> 15) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT_V3(f)               ((((uint32_t)f) & 0x1) << 14)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT_V4(f)               ((((uint32_t)f) & 0x1) << 14)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT_V5(f)               ((((uint32_t)f) & 0x1) << 14)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT_V6(f)               ((((uint32_t)f) & 0x1) << 15)
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT_V7(f)               ((((uint32_t)f) & 0x1) << 15)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT                     AES_BLK_INT_ENABLE_KEY_1_POLICY_MISMATCH_INSRT_V7
#endif

/*! @} key_1_policy_mismatch */

/*! 
 *  @addtogroup group995955 key_1_invalid_at_use_time
 *  @brief Range = 16 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_1_INVALID_AT_USE_TIME Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT_V3              (15)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT_V4              (15)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT_V5              (15)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT_V6              (16)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT_V7              (16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH_V3              (1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH_V4              (1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH_V5              (1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH_V6              (1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH_V7              (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK_V3              (0x8000)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK_V4              (0x8000)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK_V5              (0x8000)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK_V6              (0x10000)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK_V7              (0x10000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK_V3              (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK_V4              (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK_V5              (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK_V6              (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK_V7              (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT_V3(r)           ((((uint32_t)r) >> 15) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT_V4(r)           ((((uint32_t)r) >> 15) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT_V5(r)           ((((uint32_t)r) >> 15) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT_V6(r)           ((((uint32_t)r) >> 16) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT_V7(r)           ((((uint32_t)r) >> 16) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT_V3(f)           ((((uint32_t)f) & 0x1) << 15)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT_V4(f)           ((((uint32_t)f) & 0x1) << 15)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT_V5(f)           ((((uint32_t)f) & 0x1) << 15)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT_V6(f)           ((((uint32_t)f) & 0x1) << 16)
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT_V7(f)           ((((uint32_t)f) & 0x1) << 16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT                 AES_BLK_INT_ENABLE_KEY_1_INVALID_AT_USE_TIME_INSRT_V7
#endif

/*! @} key_1_invalid_at_use_time */

/*! 
 *  @addtogroup group995956 key_1_hdcp_err
 *  @brief Range = 17 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_1_HDCP_ERR Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT_V3                         (16)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT_V4                         (16)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT_V5                         (16)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT_V6                         (17)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT_V7                         (17)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH_V3                         (1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH_V4                         (1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH_V5                         (1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH_V6                         (1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH_V7                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK_V3                         (0x10000)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK_V4                         (0x10000)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK_V5                         (0x10000)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK_V6                         (0x20000)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK_V7                         (0x20000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK_V3                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK_V4                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK_V5                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK_V6                         (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK_V7                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT_V3(r)                      ((((uint32_t)r) >> 16) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT_V4(r)                      ((((uint32_t)r) >> 16) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT_V5(r)                      ((((uint32_t)r) >> 16) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT_V6(r)                      ((((uint32_t)r) >> 17) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT_V7(r)                      ((((uint32_t)r) >> 17) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT_V3(f)                      ((((uint32_t)f) & 0x1) << 16)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT_V4(f)                      ((((uint32_t)f) & 0x1) << 16)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT_V5(f)                      ((((uint32_t)f) & 0x1) << 16)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT_V6(f)                      ((((uint32_t)f) & 0x1) << 17)
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT_V7(f)                      ((((uint32_t)f) & 0x1) << 17)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT                            AES_BLK_INT_ENABLE_KEY_1_HDCP_ERR_INSRT_V7
#endif

/*! @} key_1_hdcp_err */

/*! 
 *  @addtogroup group995957 key_1_dpa_random_unseeded
 *  @brief Range = 18 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Enable KEY_1_DPA_RANDOM_UNSEEDED Interrupt.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT_V6              (18)
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT_V7              (18)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SHIFT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH_V6              (1)
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH_V7              (1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_WIDTH_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_UMASK_V6              (0x40000)
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_UMASK_V7              (0x40000)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_UMASK                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_UMASK                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_UMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SMASK_V6              (0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SMASK_V7              (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SMASK                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SMASK                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_SMASK_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT_V6(r)           ((((uint32_t)r) >> 18) & 0x1)
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT_V7(r)           ((((uint32_t)r) >> 18) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_XTRCT_V7
#endif

#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_INSRT_V6(f)           ((((uint32_t)f) & 0x1) << 18)
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_INSRT_V7(f)           ((((uint32_t)f) & 0x1) << 18)
#if      SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_INSRT                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_INSRT                 AES_BLK_INT_ENABLE_KEY_1_DPA_RANDOM_UNSEEDED_INSRT_V7
#endif

/*! @} key_1_dpa_random_unseeded */

/*! 
 *  @addtogroup group995959 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_INT_ENABLE_TNBLE_RESET_UMASK_S8000_A1                      (0x1ffff)
#define  AES_BLK_INT_ENABLE_TNBLE_RESET_UMASK_S8000_B0                      (0x1ffff)
#define  AES_BLK_INT_ENABLE_TNBLE_RESET_UMASK_S8001_A0                      (0x1ffff)
#define  AES_BLK_INT_ENABLE_TNBLE_RESET_UMASK_T8002_A0                      (0x7ffff)
#define  AES_BLK_INT_ENABLE_TNBLE_RESET_UMASK_T8010_A0                      (0x7ffff)

#define  AES_BLK_INT_ENABLE_TNBLE_RESET_VALUE_S8000_A1                      (0x0)
#define  AES_BLK_INT_ENABLE_TNBLE_RESET_VALUE_S8000_B0                      (0x0)
#define  AES_BLK_INT_ENABLE_TNBLE_RESET_VALUE_S8001_A0                      (0x0)
#define  AES_BLK_INT_ENABLE_TNBLE_RESET_VALUE_T8002_A0                      (0x0)
#define  AES_BLK_INT_ENABLE_TNBLE_RESET_VALUE_T8010_A0                      (0x0)

/*! @} reset */

/*! @} int_enable */

/*! 
 *  @addtogroup group995960 watermarks
 *  @brief Offset = 0x20
 *  @details Watermarks for FIFO interrupts.
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_WATERMARKS_OFFSET_V3                                       (0x0 + 0x20)
#define  AES_BLK_WATERMARKS_OFFSET_V4                                       (0x0 + 0x20)
#define  AES_BLK_WATERMARKS_OFFSET_V5                                       (0x0 + 0x20)
#define  AES_BLK_WATERMARKS_OFFSET_V6                                       (0x0 + 0x20)
#define  AES_BLK_WATERMARKS_OFFSET_V7                                       (0x0 + 0x20)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_WATERMARKS_OFFSET                                          AES_BLK_WATERMARKS_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_WATERMARKS_OFFSET                                          AES_BLK_WATERMARKS_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_WATERMARKS_OFFSET                                          AES_BLK_WATERMARKS_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_WATERMARKS_OFFSET                                          AES_BLK_WATERMARKS_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_WATERMARKS_OFFSET                                          AES_BLK_WATERMARKS_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995961 command_fifo_low
 *  @brief Range = 6:0 | Width = 7 | Access = read-write | Default = 0x0
 *  @details Command FIFO Level below which the COMMAND_FIFO_LOW interrupt will
 *  be asserted
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT_V3                       (0)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT_V4                       (0)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT_V5                       (0)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT_V6                       (0)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT_V7                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SHIFT_V7
#endif

#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH_V3                       (7)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH_V4                       (7)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH_V5                       (7)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH_V6                       (7)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH_V7                       (7)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_WIDTH_V7
#endif

#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK_V3                       (0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK_V4                       (0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK_V5                       (0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK_V6                       (0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK_V7                       (0x7f)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_UMASK_V7
#endif

#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK_V3                       (0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK_V4                       (0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK_V5                       (0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK_V6                       (0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK_V7                       (0x7f)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_SMASK_V7
#endif

#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT_V3(r)                    ((((uint32_t)r) >> 0) & 0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT_V4(r)                    ((((uint32_t)r) >> 0) & 0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT_V5(r)                    ((((uint32_t)r) >> 0) & 0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT_V6(r)                    ((((uint32_t)r) >> 0) & 0x7f)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT_V7(r)                    ((((uint32_t)r) >> 0) & 0x7f)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_XTRCT_V7
#endif

#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT_V3(f)                    ((((uint32_t)f) & 0x7f) << 0)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT_V4(f)                    ((((uint32_t)f) & 0x7f) << 0)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT_V5(f)                    ((((uint32_t)f) & 0x7f) << 0)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT_V6(f)                    ((((uint32_t)f) & 0x7f) << 0)
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT_V7(f)                    ((((uint32_t)f) & 0x7f) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT                          AES_BLK_WATERMARKS_COMMAND_FIFO_LOW_INSRT_V7
#endif

/*! @} command_fifo_low */

/*! 
 *  @addtogroup group995963 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_WATERMARKS_TNBLE_RESET_UMASK_S8000_A1                      (0x7f)
#define  AES_BLK_WATERMARKS_TNBLE_RESET_UMASK_S8000_B0                      (0x7f)
#define  AES_BLK_WATERMARKS_TNBLE_RESET_UMASK_S8001_A0                      (0x7f)
#define  AES_BLK_WATERMARKS_TNBLE_RESET_UMASK_T8002_A0                      (0x7f)
#define  AES_BLK_WATERMARKS_TNBLE_RESET_UMASK_T8010_A0                      (0x7f)

#define  AES_BLK_WATERMARKS_TNBLE_RESET_VALUE_S8000_A1                      (0x0)
#define  AES_BLK_WATERMARKS_TNBLE_RESET_VALUE_S8000_B0                      (0x0)
#define  AES_BLK_WATERMARKS_TNBLE_RESET_VALUE_S8001_A0                      (0x0)
#define  AES_BLK_WATERMARKS_TNBLE_RESET_VALUE_T8002_A0                      (0x0)
#define  AES_BLK_WATERMARKS_TNBLE_RESET_VALUE_T8010_A0                      (0x0)

/*! @} reset */

/*! @} watermarks */

/*! 
 *  @addtogroup group995964 command_fifo_status
 *  @brief Offset = 0x24
 *  @details Status information for the Command Queue
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_STATUS_OFFSET_V3                              (0x0 + 0x24)
#define  AES_BLK_COMMAND_FIFO_STATUS_OFFSET_V4                              (0x0 + 0x24)
#define  AES_BLK_COMMAND_FIFO_STATUS_OFFSET_V5                              (0x0 + 0x24)
#define  AES_BLK_COMMAND_FIFO_STATUS_OFFSET_V6                              (0x0 + 0x24)
#define  AES_BLK_COMMAND_FIFO_STATUS_OFFSET_V7                              (0x0 + 0x24)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_OFFSET                                 AES_BLK_COMMAND_FIFO_STATUS_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_OFFSET                                 AES_BLK_COMMAND_FIFO_STATUS_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_OFFSET                                 AES_BLK_COMMAND_FIFO_STATUS_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_OFFSET                                 AES_BLK_COMMAND_FIFO_STATUS_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_OFFSET                                 AES_BLK_COMMAND_FIFO_STATUS_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995965 low
 *  @brief Range = 0 | Width = 1 | Access = read-only | Default = 0x0
 *  @details Command FIFO has gone below Low Watermark
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT_V3                           (0)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT_V4                           (0)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT_V5                           (0)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT_V6                           (0)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT_V7                           (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_SHIFT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH_V3                           (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH_V4                           (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH_V5                           (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH_V6                           (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH_V7                           (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH                              AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH                              AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH                              AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH                              AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH                              AES_BLK_COMMAND_FIFO_STATUS_LOW_WIDTH_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK_V3                           (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK_V4                           (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK_V5                           (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK_V6                           (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK_V7                           (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK                              AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK                              AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK                              AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK                              AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK                              AES_BLK_COMMAND_FIFO_STATUS_LOW_UMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK_V3                           (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK_V4                           (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK_V5                           (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK_V6                           (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK_V7                           (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK                              AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK                              AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK                              AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK                              AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK                              AES_BLK_COMMAND_FIFO_STATUS_LOW_SMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT_V3(r)                        ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT_V4(r)                        ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT_V5(r)                        ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT_V6(r)                        ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT_V7(r)                        ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_XTRCT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT_V3(f)                        ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT_V4(f)                        ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT_V5(f)                        ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT_V6(f)                        ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT_V7(f)                        ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT                              AES_BLK_COMMAND_FIFO_STATUS_LOW_INSRT_V7
#endif

/*! @} low */

/*! 
 *  @addtogroup group995966 empty
 *  @brief Range = 1 | Width = 1 | Access = read-only | Default = 0x1
 *  @details Command FIFO is empty
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT_V3                         (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT_V4                         (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT_V5                         (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT_V6                         (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT_V7                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SHIFT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH_V3                         (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH_V4                         (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH_V5                         (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH_V6                         (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH_V7                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_WIDTH_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK_V3                         (0x2)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK_V4                         (0x2)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK_V5                         (0x2)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK_V6                         (0x2)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK_V7                         (0x2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_UMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK_V3                         (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK_V4                         (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK_V5                         (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK_V6                         (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK_V7                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_SMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT_V3(r)                      ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT_V4(r)                      ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT_V5(r)                      ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT_V6(r)                      ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT_V7(r)                      ((((uint32_t)r) >> 1) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_XTRCT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT_V3(f)                      ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT_V4(f)                      ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT_V5(f)                      ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT_V6(f)                      ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT_V7(f)                      ((((uint32_t)f) & 0x1) << 1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT                            AES_BLK_COMMAND_FIFO_STATUS_EMPTY_INSRT_V7
#endif

/*! @} empty */

/*! 
 *  @addtogroup group995967 full
 *  @brief Range = 2 | Width = 1 | Access = read-only | Default = 0x0
 *  @details Command FIFO is full
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT_V3                          (2)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT_V4                          (2)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT_V5                          (2)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT_V6                          (2)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT_V7                          (2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_SHIFT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH_V3                          (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH_V4                          (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH_V5                          (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH_V6                          (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH_V7                          (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH                             AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH                             AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH                             AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH                             AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH                             AES_BLK_COMMAND_FIFO_STATUS_FULL_WIDTH_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK_V3                          (0x4)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK_V4                          (0x4)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK_V5                          (0x4)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK_V6                          (0x4)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK_V7                          (0x4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK                             AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK                             AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK                             AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK                             AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK                             AES_BLK_COMMAND_FIFO_STATUS_FULL_UMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK_V3                          (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK_V4                          (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK_V5                          (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK_V6                          (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK_V7                          (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK                             AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK                             AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK                             AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK                             AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK                             AES_BLK_COMMAND_FIFO_STATUS_FULL_SMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT_V3(r)                       ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT_V4(r)                       ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT_V5(r)                       ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT_V6(r)                       ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT_V7(r)                       ((((uint32_t)r) >> 2) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_XTRCT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT_V3(f)                       ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT_V4(f)                       ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT_V5(f)                       ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT_V6(f)                       ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT_V7(f)                       ((((uint32_t)f) & 0x1) << 2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT                             AES_BLK_COMMAND_FIFO_STATUS_FULL_INSRT_V7
#endif

/*! @} full */

/*! 
 *  @addtogroup group995968 overflow
 *  @brief Range = 3 | Width = 1 | Access = read-only | Default = 0x0
 *  @details Software overflowed Command FIFO. This bit is not sticky
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT_V3                      (3)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT_V4                      (3)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT_V5                      (3)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT_V6                      (3)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT_V7                      (3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SHIFT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH_V3                      (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH_V4                      (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH_V5                      (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH_V6                      (1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH_V7                      (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_WIDTH_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK_V3                      (0x8)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK_V4                      (0x8)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK_V5                      (0x8)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK_V6                      (0x8)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK_V7                      (0x8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_UMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK_V3                      (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK_V4                      (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK_V5                      (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK_V6                      (0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK_V7                      (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_SMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT_V3(r)                   ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT_V4(r)                   ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT_V5(r)                   ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT_V6(r)                   ((((uint32_t)r) >> 3) & 0x1)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT_V7(r)                   ((((uint32_t)r) >> 3) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_XTRCT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT_V3(f)                   ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT_V4(f)                   ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT_V5(f)                   ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT_V6(f)                   ((((uint32_t)f) & 0x1) << 3)
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT_V7(f)                   ((((uint32_t)f) & 0x1) << 3)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT                         AES_BLK_COMMAND_FIFO_STATUS_OVERFLOW_INSRT_V7
#endif

/*! @} overflow */

/*! 
 *  @addtogroup group995970 level
 *  @brief Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0
 *  @details Number of 4 byte words in the Command FIFO
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT_V3                         (8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT_V4                         (8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT_V5                         (8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT_V6                         (8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT_V7                         (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SHIFT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH_V3                         (8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH_V4                         (8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH_V5                         (8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH_V6                         (8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH_V7                         (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_WIDTH_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK_V3                         (0xff00)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK_V4                         (0xff00)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK_V5                         (0xff00)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK_V6                         (0xff00)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK_V7                         (0xff00)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_UMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK_V3                         (0xff)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK_V4                         (0xff)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK_V5                         (0xff)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK_V6                         (0xff)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK_V7                         (0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_SMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT_V3(r)                      ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT_V4(r)                      ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT_V5(r)                      ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT_V6(r)                      ((((uint32_t)r) >> 8) & 0xff)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT_V7(r)                      ((((uint32_t)r) >> 8) & 0xff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_XTRCT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT_V3(f)                      ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT_V4(f)                      ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT_V5(f)                      ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT_V6(f)                      ((((uint32_t)f) & 0xff) << 8)
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT_V7(f)                      ((((uint32_t)f) & 0xff) << 8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT                            AES_BLK_COMMAND_FIFO_STATUS_LEVEL_INSRT_V7
#endif

/*! @} level */

/*! 
 *  @addtogroup group995971 read_pointer
 *  @brief Range = 22:16 | Width = 7 | Access = read-only | Default = 0x0
 *  @details Pointer to next command
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT_V3                  (16)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT_V4                  (16)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT_V5                  (16)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT_V6                  (16)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT_V7                  (16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SHIFT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH_V3                  (7)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH_V4                  (7)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH_V5                  (7)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH_V6                  (7)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH_V7                  (7)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_WIDTH_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK_V3                  (0x7f0000)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK_V4                  (0x7f0000)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK_V5                  (0x7f0000)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK_V6                  (0x7f0000)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK_V7                  (0x7f0000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_UMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK_V3                  (0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK_V4                  (0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK_V5                  (0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK_V6                  (0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK_V7                  (0x7f)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_SMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT_V3(r)               ((((uint32_t)r) >> 16) & 0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT_V4(r)               ((((uint32_t)r) >> 16) & 0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT_V5(r)               ((((uint32_t)r) >> 16) & 0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT_V6(r)               ((((uint32_t)r) >> 16) & 0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT_V7(r)               ((((uint32_t)r) >> 16) & 0x7f)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_XTRCT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT_V3(f)               ((((uint32_t)f) & 0x7f) << 16)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT_V4(f)               ((((uint32_t)f) & 0x7f) << 16)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT_V5(f)               ((((uint32_t)f) & 0x7f) << 16)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT_V6(f)               ((((uint32_t)f) & 0x7f) << 16)
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT_V7(f)               ((((uint32_t)f) & 0x7f) << 16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT                     AES_BLK_COMMAND_FIFO_STATUS_READ_POINTER_INSRT_V7
#endif

/*! @} read_pointer */

/*! 
 *  @addtogroup group995973 write_pointer
 *  @brief Range = 30:24 | Width = 7 | Access = read-only | Default = 0x0
 *  @details Pointer to next empty location
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT_V3                 (24)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT_V4                 (24)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT_V5                 (24)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT_V6                 (24)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT_V7                 (24)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SHIFT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH_V3                 (7)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH_V4                 (7)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH_V5                 (7)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH_V6                 (7)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH_V7                 (7)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_WIDTH_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK_V3                 (0x7f000000)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK_V4                 (0x7f000000)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK_V5                 (0x7f000000)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK_V6                 (0x7f000000)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK_V7                 (0x7f000000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_UMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK_V3                 (0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK_V4                 (0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK_V5                 (0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK_V6                 (0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK_V7                 (0x7f)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_SMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT_V3(r)              ((((uint32_t)r) >> 24) & 0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT_V4(r)              ((((uint32_t)r) >> 24) & 0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT_V5(r)              ((((uint32_t)r) >> 24) & 0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT_V6(r)              ((((uint32_t)r) >> 24) & 0x7f)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT_V7(r)              ((((uint32_t)r) >> 24) & 0x7f)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_XTRCT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT_V3(f)              ((((uint32_t)f) & 0x7f) << 24)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT_V4(f)              ((((uint32_t)f) & 0x7f) << 24)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT_V5(f)              ((((uint32_t)f) & 0x7f) << 24)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT_V6(f)              ((((uint32_t)f) & 0x7f) << 24)
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT_V7(f)              ((((uint32_t)f) & 0x7f) << 24)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT                    AES_BLK_COMMAND_FIFO_STATUS_WRITE_POINTER_INSRT_V7
#endif

/*! @} write_pointer */

/*! 
 *  @addtogroup group995975 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_STATUS_TNBLE_RESET_UMASK_S8000_A1             (0x7f7fff0f)
#define  AES_BLK_COMMAND_FIFO_STATUS_TNBLE_RESET_UMASK_S8000_B0             (0x7f7fff0f)
#define  AES_BLK_COMMAND_FIFO_STATUS_TNBLE_RESET_UMASK_S8001_A0             (0x7f7fff0f)
#define  AES_BLK_COMMAND_FIFO_STATUS_TNBLE_RESET_UMASK_T8002_A0             (0x7f7fff0f)
#define  AES_BLK_COMMAND_FIFO_STATUS_TNBLE_RESET_UMASK_T8010_A0             (0x7f7fff0f)

#define  AES_BLK_COMMAND_FIFO_STATUS_TNBLE_RESET_VALUE_S8000_A1             (0x2)
#define  AES_BLK_COMMAND_FIFO_STATUS_TNBLE_RESET_VALUE_S8000_B0             (0x2)
#define  AES_BLK_COMMAND_FIFO_STATUS_TNBLE_RESET_VALUE_S8001_A0             (0x2)
#define  AES_BLK_COMMAND_FIFO_STATUS_TNBLE_RESET_VALUE_T8002_A0             (0x2)
#define  AES_BLK_COMMAND_FIFO_STATUS_TNBLE_RESET_VALUE_T8010_A0             (0x2)

/*! @} reset */

/*! @} command_fifo_status */

/*! 
 *  @addtogroup group995976 history_fifo_status
 *  @brief Offset = 0x28
 *  @details Status information for the DMA Debug FIFO
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_HISTORY_FIFO_STATUS_OFFSET_V3                              (0x0 + 0x28)
#define  AES_BLK_HISTORY_FIFO_STATUS_OFFSET_V4                              (0x0 + 0x28)
#define  AES_BLK_HISTORY_FIFO_STATUS_OFFSET_V5                              (0x0 + 0x28)
#define  AES_BLK_HISTORY_FIFO_STATUS_OFFSET_V6                              (0x0 + 0x28)
#define  AES_BLK_HISTORY_FIFO_STATUS_OFFSET_V7                              (0x0 + 0x28)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_OFFSET                                 AES_BLK_HISTORY_FIFO_STATUS_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_OFFSET                                 AES_BLK_HISTORY_FIFO_STATUS_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_OFFSET                                 AES_BLK_HISTORY_FIFO_STATUS_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_OFFSET                                 AES_BLK_HISTORY_FIFO_STATUS_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_OFFSET                                 AES_BLK_HISTORY_FIFO_STATUS_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995977 empty
 *  @brief Range = 0 | Width = 1 | Access = read-only | Default = 0x1
 *  @details History FIFO is empty
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT_V3                         (0)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT_V4                         (0)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT_V5                         (0)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT_V6                         (0)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT_V7                         (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SHIFT_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH_V3                         (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH_V4                         (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH_V5                         (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH_V6                         (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH_V7                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_WIDTH_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK_V3                         (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK_V4                         (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK_V5                         (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK_V6                         (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK_V7                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_UMASK_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK_V3                         (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK_V4                         (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK_V5                         (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK_V6                         (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK_V7                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_SMASK_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT_V3(r)                      ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT_V4(r)                      ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT_V5(r)                      ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT_V6(r)                      ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT_V7(r)                      ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_XTRCT_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT_V3(f)                      ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT_V4(f)                      ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT_V5(f)                      ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT_V6(f)                      ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT_V7(f)                      ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT                            AES_BLK_HISTORY_FIFO_STATUS_EMPTY_INSRT_V7
#endif

/*! @} empty */

/*! 
 *  @addtogroup group995978 full
 *  @brief Range = 1 | Width = 1 | Access = read-only | Default = 0x0
 *  @details History FIFO is full
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT_V3                          (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT_V4                          (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT_V5                          (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT_V6                          (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT_V7                          (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_SHIFT_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH_V3                          (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH_V4                          (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH_V5                          (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH_V6                          (1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH_V7                          (1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH                             AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH                             AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH                             AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH                             AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH                             AES_BLK_HISTORY_FIFO_STATUS_FULL_WIDTH_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK_V3                          (0x2)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK_V4                          (0x2)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK_V5                          (0x2)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK_V6                          (0x2)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK_V7                          (0x2)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK                             AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK                             AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK                             AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK                             AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK                             AES_BLK_HISTORY_FIFO_STATUS_FULL_UMASK_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK_V3                          (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK_V4                          (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK_V5                          (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK_V6                          (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK_V7                          (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK                             AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK                             AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK                             AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK                             AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK                             AES_BLK_HISTORY_FIFO_STATUS_FULL_SMASK_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT_V3(r)                       ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT_V4(r)                       ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT_V5(r)                       ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT_V6(r)                       ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT_V7(r)                       ((((uint32_t)r) >> 1) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_XTRCT_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT_V3(f)                       ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT_V4(f)                       ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT_V5(f)                       ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT_V6(f)                       ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT_V7(f)                       ((((uint32_t)f) & 0x1) << 1)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT                             AES_BLK_HISTORY_FIFO_STATUS_FULL_INSRT_V7
#endif

/*! @} full */

/*! 
 *  @addtogroup group995980 level
 *  @brief Range = 13:8 | Width = 6 | Access = read-only | Default = 0x0
 *  @details Number of 4 byte words in the History FIFO
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT_V3                         (8)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT_V4                         (8)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT_V5                         (8)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT_V6                         (8)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT_V7                         (8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SHIFT_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH_V3                         (6)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH_V4                         (6)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH_V5                         (6)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH_V6                         (6)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH_V7                         (6)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_WIDTH_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK_V3                         (0x3f00)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK_V4                         (0x3f00)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK_V5                         (0x3f00)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK_V6                         (0x3f00)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK_V7                         (0x3f00)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_UMASK_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK_V3                         (0x3f)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK_V4                         (0x3f)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK_V5                         (0x3f)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK_V6                         (0x3f)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK_V7                         (0x3f)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_SMASK_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT_V3(r)                      ((((uint32_t)r) >> 8) & 0x3f)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT_V4(r)                      ((((uint32_t)r) >> 8) & 0x3f)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT_V5(r)                      ((((uint32_t)r) >> 8) & 0x3f)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT_V6(r)                      ((((uint32_t)r) >> 8) & 0x3f)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT_V7(r)                      ((((uint32_t)r) >> 8) & 0x3f)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_XTRCT_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT_V3(f)                      ((((uint32_t)f) & 0x3f) << 8)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT_V4(f)                      ((((uint32_t)f) & 0x3f) << 8)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT_V5(f)                      ((((uint32_t)f) & 0x3f) << 8)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT_V6(f)                      ((((uint32_t)f) & 0x3f) << 8)
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT_V7(f)                      ((((uint32_t)f) & 0x3f) << 8)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT                            AES_BLK_HISTORY_FIFO_STATUS_LEVEL_INSRT_V7
#endif

/*! @} level */

/*! 
 *  @addtogroup group995982 write_pointer
 *  @brief Range = 20:16 | Width = 5 | Access = read-only | Default = 0x0
 *  @details Pointer to next write location
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT_V3                 (16)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT_V4                 (16)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT_V5                 (16)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT_V6                 (16)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT_V7                 (16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SHIFT_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH_V3                 (5)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH_V4                 (5)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH_V5                 (5)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH_V6                 (5)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH_V7                 (5)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_WIDTH_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK_V3                 (0x1f0000)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK_V4                 (0x1f0000)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK_V5                 (0x1f0000)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK_V6                 (0x1f0000)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK_V7                 (0x1f0000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_UMASK_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK_V3                 (0x1f)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK_V4                 (0x1f)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK_V5                 (0x1f)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK_V6                 (0x1f)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK_V7                 (0x1f)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_SMASK_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT_V3(r)              ((((uint32_t)r) >> 16) & 0x1f)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT_V4(r)              ((((uint32_t)r) >> 16) & 0x1f)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT_V5(r)              ((((uint32_t)r) >> 16) & 0x1f)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT_V6(r)              ((((uint32_t)r) >> 16) & 0x1f)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT_V7(r)              ((((uint32_t)r) >> 16) & 0x1f)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_XTRCT_V7
#endif

#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT_V3(f)              ((((uint32_t)f) & 0x1f) << 16)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT_V4(f)              ((((uint32_t)f) & 0x1f) << 16)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT_V5(f)              ((((uint32_t)f) & 0x1f) << 16)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT_V6(f)              ((((uint32_t)f) & 0x1f) << 16)
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT_V7(f)              ((((uint32_t)f) & 0x1f) << 16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT                    AES_BLK_HISTORY_FIFO_STATUS_WRITE_POINTER_INSRT_V7
#endif

/*! @} write_pointer */

/*! 
 *  @addtogroup group995984 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_HISTORY_FIFO_STATUS_TNBLE_RESET_UMASK_S8000_A1             (0x1f3f03)
#define  AES_BLK_HISTORY_FIFO_STATUS_TNBLE_RESET_UMASK_S8000_B0             (0x1f3f03)
#define  AES_BLK_HISTORY_FIFO_STATUS_TNBLE_RESET_UMASK_S8001_A0             (0x1f3f03)
#define  AES_BLK_HISTORY_FIFO_STATUS_TNBLE_RESET_UMASK_T8002_A0             (0x1f3f03)
#define  AES_BLK_HISTORY_FIFO_STATUS_TNBLE_RESET_UMASK_T8010_A0             (0x1f3f03)

#define  AES_BLK_HISTORY_FIFO_STATUS_TNBLE_RESET_VALUE_S8000_A1             (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_TNBLE_RESET_VALUE_S8000_B0             (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_TNBLE_RESET_VALUE_S8001_A0             (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_TNBLE_RESET_VALUE_T8002_A0             (0x1)
#define  AES_BLK_HISTORY_FIFO_STATUS_TNBLE_RESET_VALUE_T8010_A0             (0x1)

/*! @} reset */

/*! @} history_fifo_status */

/*! 
 *  @addtogroup group995985 command_fifo_count
 *  @brief Offset = 0x2c
 *  @details Total count of commands since the Command FIFO was last enabled
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_COUNT_OFFSET_V3                               (0x0 + 0x2c)
#define  AES_BLK_COMMAND_FIFO_COUNT_OFFSET_V4                               (0x0 + 0x2c)
#define  AES_BLK_COMMAND_FIFO_COUNT_OFFSET_V5                               (0x0 + 0x2c)
#define  AES_BLK_COMMAND_FIFO_COUNT_OFFSET_V6                               (0x0 + 0x2c)
#define  AES_BLK_COMMAND_FIFO_COUNT_OFFSET_V7                               (0x0 + 0x2c)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_COUNT_OFFSET                                  AES_BLK_COMMAND_FIFO_COUNT_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_COUNT_OFFSET                                  AES_BLK_COMMAND_FIFO_COUNT_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_COUNT_OFFSET                                  AES_BLK_COMMAND_FIFO_COUNT_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_COUNT_OFFSET                                  AES_BLK_COMMAND_FIFO_COUNT_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_COUNT_OFFSET                                  AES_BLK_COMMAND_FIFO_COUNT_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995986 total
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details Number of commands popped from the Command FIFO since it was last
 *  turned on. (saturates at max)
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT_V3                          (0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT_V4                          (0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT_V5                          (0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT_V6                          (0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT_V7                          (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SHIFT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH_V3                          (32)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH_V4                          (32)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH_V5                          (32)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH_V6                          (32)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH_V7                          (32)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_WIDTH_V7
#endif

#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK_V3                          (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK_V4                          (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK_V5                          (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK_V6                          (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK_V7                          (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_UMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK_V3                          (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK_V4                          (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK_V5                          (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK_V6                          (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK_V7                          (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_SMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT_V3(r)                       ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT_V4(r)                       ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT_V5(r)                       ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT_V6(r)                       ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT_V7(r)                       ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_XTRCT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT_V3(f)                       ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT_V4(f)                       ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT_V5(f)                       ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT_V6(f)                       ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT_V7(f)                       ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT                             AES_BLK_COMMAND_FIFO_COUNT_TOTAL_INSRT_V7
#endif

/*! @} total */

/*! 
 *  @addtogroup group995987 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_COUNT_TNBLE_RESET_UMASK_S8000_A1              (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TNBLE_RESET_UMASK_S8000_B0              (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TNBLE_RESET_UMASK_S8001_A0              (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TNBLE_RESET_UMASK_T8002_A0              (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_COUNT_TNBLE_RESET_UMASK_T8010_A0              (0xffffffff)

#define  AES_BLK_COMMAND_FIFO_COUNT_TNBLE_RESET_VALUE_S8000_A1              (0x0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TNBLE_RESET_VALUE_S8000_B0              (0x0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TNBLE_RESET_VALUE_S8001_A0              (0x0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TNBLE_RESET_VALUE_T8002_A0              (0x0)
#define  AES_BLK_COMMAND_FIFO_COUNT_TNBLE_RESET_VALUE_T8010_A0              (0x0)

/*! @} reset */

/*! @} command_fifo_count */

/*! 
 *  @addtogroup group995988 flag_command
 *  @brief Offset = 0x30
 *  @details Interrupt code that provides information about the flag interrupt
 *  that occurred.
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_FLAG_COMMAND_OFFSET_V3                                     (0x0 + 0x30)
#define  AES_BLK_FLAG_COMMAND_OFFSET_V4                                     (0x0 + 0x30)
#define  AES_BLK_FLAG_COMMAND_OFFSET_V5                                     (0x0 + 0x30)
#define  AES_BLK_FLAG_COMMAND_OFFSET_V6                                     (0x0 + 0x30)
#define  AES_BLK_FLAG_COMMAND_OFFSET_V7                                     (0x0 + 0x30)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_FLAG_COMMAND_OFFSET                                        AES_BLK_FLAG_COMMAND_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_FLAG_COMMAND_OFFSET                                        AES_BLK_FLAG_COMMAND_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_FLAG_COMMAND_OFFSET                                        AES_BLK_FLAG_COMMAND_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_FLAG_COMMAND_OFFSET                                        AES_BLK_FLAG_COMMAND_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_FLAG_COMMAND_OFFSET                                        AES_BLK_FLAG_COMMAND_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995989 code
 *  @brief Range = 15:0 | Width = 16 | Access = read-only | Default = 0x0
 *  @details Interrupt code from the last flag command executed in the Command
 *  FIFO
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_FLAG_COMMAND_CODE_SHIFT_V3                                 (0)
#define  AES_BLK_FLAG_COMMAND_CODE_SHIFT_V4                                 (0)
#define  AES_BLK_FLAG_COMMAND_CODE_SHIFT_V5                                 (0)
#define  AES_BLK_FLAG_COMMAND_CODE_SHIFT_V6                                 (0)
#define  AES_BLK_FLAG_COMMAND_CODE_SHIFT_V7                                 (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_FLAG_COMMAND_CODE_SHIFT                                    AES_BLK_FLAG_COMMAND_CODE_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_FLAG_COMMAND_CODE_SHIFT                                    AES_BLK_FLAG_COMMAND_CODE_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_FLAG_COMMAND_CODE_SHIFT                                    AES_BLK_FLAG_COMMAND_CODE_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_FLAG_COMMAND_CODE_SHIFT                                    AES_BLK_FLAG_COMMAND_CODE_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_FLAG_COMMAND_CODE_SHIFT                                    AES_BLK_FLAG_COMMAND_CODE_SHIFT_V7
#endif

#define  AES_BLK_FLAG_COMMAND_CODE_WIDTH_V3                                 (16)
#define  AES_BLK_FLAG_COMMAND_CODE_WIDTH_V4                                 (16)
#define  AES_BLK_FLAG_COMMAND_CODE_WIDTH_V5                                 (16)
#define  AES_BLK_FLAG_COMMAND_CODE_WIDTH_V6                                 (16)
#define  AES_BLK_FLAG_COMMAND_CODE_WIDTH_V7                                 (16)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_FLAG_COMMAND_CODE_WIDTH                                    AES_BLK_FLAG_COMMAND_CODE_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_FLAG_COMMAND_CODE_WIDTH                                    AES_BLK_FLAG_COMMAND_CODE_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_FLAG_COMMAND_CODE_WIDTH                                    AES_BLK_FLAG_COMMAND_CODE_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_FLAG_COMMAND_CODE_WIDTH                                    AES_BLK_FLAG_COMMAND_CODE_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_FLAG_COMMAND_CODE_WIDTH                                    AES_BLK_FLAG_COMMAND_CODE_WIDTH_V7
#endif

#define  AES_BLK_FLAG_COMMAND_CODE_UMASK_V3                                 (0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_UMASK_V4                                 (0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_UMASK_V5                                 (0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_UMASK_V6                                 (0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_UMASK_V7                                 (0xffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_FLAG_COMMAND_CODE_UMASK                                    AES_BLK_FLAG_COMMAND_CODE_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_FLAG_COMMAND_CODE_UMASK                                    AES_BLK_FLAG_COMMAND_CODE_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_FLAG_COMMAND_CODE_UMASK                                    AES_BLK_FLAG_COMMAND_CODE_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_FLAG_COMMAND_CODE_UMASK                                    AES_BLK_FLAG_COMMAND_CODE_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_FLAG_COMMAND_CODE_UMASK                                    AES_BLK_FLAG_COMMAND_CODE_UMASK_V7
#endif

#define  AES_BLK_FLAG_COMMAND_CODE_SMASK_V3                                 (0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_SMASK_V4                                 (0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_SMASK_V5                                 (0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_SMASK_V6                                 (0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_SMASK_V7                                 (0xffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_FLAG_COMMAND_CODE_SMASK                                    AES_BLK_FLAG_COMMAND_CODE_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_FLAG_COMMAND_CODE_SMASK                                    AES_BLK_FLAG_COMMAND_CODE_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_FLAG_COMMAND_CODE_SMASK                                    AES_BLK_FLAG_COMMAND_CODE_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_FLAG_COMMAND_CODE_SMASK                                    AES_BLK_FLAG_COMMAND_CODE_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_FLAG_COMMAND_CODE_SMASK                                    AES_BLK_FLAG_COMMAND_CODE_SMASK_V7
#endif

#define  AES_BLK_FLAG_COMMAND_CODE_XTRCT_V3(r)                              ((((uint32_t)r) >> 0) & 0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_XTRCT_V4(r)                              ((((uint32_t)r) >> 0) & 0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_XTRCT_V5(r)                              ((((uint32_t)r) >> 0) & 0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_XTRCT_V6(r)                              ((((uint32_t)r) >> 0) & 0xffff)
#define  AES_BLK_FLAG_COMMAND_CODE_XTRCT_V7(r)                              ((((uint32_t)r) >> 0) & 0xffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_FLAG_COMMAND_CODE_XTRCT                                    AES_BLK_FLAG_COMMAND_CODE_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_FLAG_COMMAND_CODE_XTRCT                                    AES_BLK_FLAG_COMMAND_CODE_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_FLAG_COMMAND_CODE_XTRCT                                    AES_BLK_FLAG_COMMAND_CODE_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_FLAG_COMMAND_CODE_XTRCT                                    AES_BLK_FLAG_COMMAND_CODE_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_FLAG_COMMAND_CODE_XTRCT                                    AES_BLK_FLAG_COMMAND_CODE_XTRCT_V7
#endif

#define  AES_BLK_FLAG_COMMAND_CODE_INSRT_V3(f)                              ((((uint32_t)f) & 0xffff) << 0)
#define  AES_BLK_FLAG_COMMAND_CODE_INSRT_V4(f)                              ((((uint32_t)f) & 0xffff) << 0)
#define  AES_BLK_FLAG_COMMAND_CODE_INSRT_V5(f)                              ((((uint32_t)f) & 0xffff) << 0)
#define  AES_BLK_FLAG_COMMAND_CODE_INSRT_V6(f)                              ((((uint32_t)f) & 0xffff) << 0)
#define  AES_BLK_FLAG_COMMAND_CODE_INSRT_V7(f)                              ((((uint32_t)f) & 0xffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_FLAG_COMMAND_CODE_INSRT                                    AES_BLK_FLAG_COMMAND_CODE_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_FLAG_COMMAND_CODE_INSRT                                    AES_BLK_FLAG_COMMAND_CODE_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_FLAG_COMMAND_CODE_INSRT                                    AES_BLK_FLAG_COMMAND_CODE_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_FLAG_COMMAND_CODE_INSRT                                    AES_BLK_FLAG_COMMAND_CODE_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_FLAG_COMMAND_CODE_INSRT                                    AES_BLK_FLAG_COMMAND_CODE_INSRT_V7
#endif

/*! @} code */

/*! 
 *  @addtogroup group995991 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_FLAG_COMMAND_TNBLE_RESET_UMASK_S8000_A1                    (0xffff)
#define  AES_BLK_FLAG_COMMAND_TNBLE_RESET_UMASK_S8000_B0                    (0xffff)
#define  AES_BLK_FLAG_COMMAND_TNBLE_RESET_UMASK_S8001_A0                    (0xffff)
#define  AES_BLK_FLAG_COMMAND_TNBLE_RESET_UMASK_T8002_A0                    (0xffff)
#define  AES_BLK_FLAG_COMMAND_TNBLE_RESET_UMASK_T8010_A0                    (0xffff)

#define  AES_BLK_FLAG_COMMAND_TNBLE_RESET_VALUE_S8000_A1                    (0x0)
#define  AES_BLK_FLAG_COMMAND_TNBLE_RESET_VALUE_S8000_B0                    (0x0)
#define  AES_BLK_FLAG_COMMAND_TNBLE_RESET_VALUE_S8001_A0                    (0x0)
#define  AES_BLK_FLAG_COMMAND_TNBLE_RESET_VALUE_T8002_A0                    (0x0)
#define  AES_BLK_FLAG_COMMAND_TNBLE_RESET_VALUE_T8010_A0                    (0x0)

/*! @} reset */

/*! @} flag_command */

/*! 
 *  @addtogroup group995992 skg_key
 *  @brief Offset = 0x34
 *  @details Secure Key Generation Key
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_SKG_KEY_OFFSET_V3                                          (0x0 + 0x34)
#define  AES_BLK_SKG_KEY_OFFSET_V4                                          (0x0 + 0x34)
#define  AES_BLK_SKG_KEY_OFFSET_V5                                          (0x0 + 0x34)
#define  AES_BLK_SKG_KEY_OFFSET_V6                                          (0x0 + 0x34)
#define  AES_BLK_SKG_KEY_OFFSET_V7                                          (0x0 + 0x34)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_SKG_KEY_OFFSET                                             AES_BLK_SKG_KEY_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_SKG_KEY_OFFSET                                             AES_BLK_SKG_KEY_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_SKG_KEY_OFFSET                                             AES_BLK_SKG_KEY_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_SKG_KEY_OFFSET                                             AES_BLK_SKG_KEY_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_SKG_KEY_OFFSET                                             AES_BLK_SKG_KEY_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995993 count
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details Count
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_SKG_KEY_COUNT_SHIFT_V3                                     (0)
#define  AES_BLK_SKG_KEY_COUNT_SHIFT_V4                                     (0)
#define  AES_BLK_SKG_KEY_COUNT_SHIFT_V5                                     (0)
#define  AES_BLK_SKG_KEY_COUNT_SHIFT_V6                                     (0)
#define  AES_BLK_SKG_KEY_COUNT_SHIFT_V7                                     (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_SKG_KEY_COUNT_SHIFT                                        AES_BLK_SKG_KEY_COUNT_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_SKG_KEY_COUNT_SHIFT                                        AES_BLK_SKG_KEY_COUNT_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_SKG_KEY_COUNT_SHIFT                                        AES_BLK_SKG_KEY_COUNT_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_SKG_KEY_COUNT_SHIFT                                        AES_BLK_SKG_KEY_COUNT_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_SKG_KEY_COUNT_SHIFT                                        AES_BLK_SKG_KEY_COUNT_SHIFT_V7
#endif

#define  AES_BLK_SKG_KEY_COUNT_WIDTH_V3                                     (32)
#define  AES_BLK_SKG_KEY_COUNT_WIDTH_V4                                     (32)
#define  AES_BLK_SKG_KEY_COUNT_WIDTH_V5                                     (32)
#define  AES_BLK_SKG_KEY_COUNT_WIDTH_V6                                     (32)
#define  AES_BLK_SKG_KEY_COUNT_WIDTH_V7                                     (32)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_SKG_KEY_COUNT_WIDTH                                        AES_BLK_SKG_KEY_COUNT_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_SKG_KEY_COUNT_WIDTH                                        AES_BLK_SKG_KEY_COUNT_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_SKG_KEY_COUNT_WIDTH                                        AES_BLK_SKG_KEY_COUNT_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_SKG_KEY_COUNT_WIDTH                                        AES_BLK_SKG_KEY_COUNT_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_SKG_KEY_COUNT_WIDTH                                        AES_BLK_SKG_KEY_COUNT_WIDTH_V7
#endif

#define  AES_BLK_SKG_KEY_COUNT_UMASK_V3                                     (0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_UMASK_V4                                     (0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_UMASK_V5                                     (0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_UMASK_V6                                     (0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_UMASK_V7                                     (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_SKG_KEY_COUNT_UMASK                                        AES_BLK_SKG_KEY_COUNT_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_SKG_KEY_COUNT_UMASK                                        AES_BLK_SKG_KEY_COUNT_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_SKG_KEY_COUNT_UMASK                                        AES_BLK_SKG_KEY_COUNT_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_SKG_KEY_COUNT_UMASK                                        AES_BLK_SKG_KEY_COUNT_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_SKG_KEY_COUNT_UMASK                                        AES_BLK_SKG_KEY_COUNT_UMASK_V7
#endif

#define  AES_BLK_SKG_KEY_COUNT_SMASK_V3                                     (0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_SMASK_V4                                     (0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_SMASK_V5                                     (0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_SMASK_V6                                     (0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_SMASK_V7                                     (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_SKG_KEY_COUNT_SMASK                                        AES_BLK_SKG_KEY_COUNT_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_SKG_KEY_COUNT_SMASK                                        AES_BLK_SKG_KEY_COUNT_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_SKG_KEY_COUNT_SMASK                                        AES_BLK_SKG_KEY_COUNT_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_SKG_KEY_COUNT_SMASK                                        AES_BLK_SKG_KEY_COUNT_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_SKG_KEY_COUNT_SMASK                                        AES_BLK_SKG_KEY_COUNT_SMASK_V7
#endif

#define  AES_BLK_SKG_KEY_COUNT_XTRCT_V3(r)                                  ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_XTRCT_V4(r)                                  ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_XTRCT_V5(r)                                  ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_XTRCT_V6(r)                                  ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_SKG_KEY_COUNT_XTRCT_V7(r)                                  ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_SKG_KEY_COUNT_XTRCT                                        AES_BLK_SKG_KEY_COUNT_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_SKG_KEY_COUNT_XTRCT                                        AES_BLK_SKG_KEY_COUNT_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_SKG_KEY_COUNT_XTRCT                                        AES_BLK_SKG_KEY_COUNT_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_SKG_KEY_COUNT_XTRCT                                        AES_BLK_SKG_KEY_COUNT_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_SKG_KEY_COUNT_XTRCT                                        AES_BLK_SKG_KEY_COUNT_XTRCT_V7
#endif

#define  AES_BLK_SKG_KEY_COUNT_INSRT_V3(f)                                  ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_SKG_KEY_COUNT_INSRT_V4(f)                                  ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_SKG_KEY_COUNT_INSRT_V5(f)                                  ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_SKG_KEY_COUNT_INSRT_V6(f)                                  ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_SKG_KEY_COUNT_INSRT_V7(f)                                  ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_SKG_KEY_COUNT_INSRT                                        AES_BLK_SKG_KEY_COUNT_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_SKG_KEY_COUNT_INSRT                                        AES_BLK_SKG_KEY_COUNT_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_SKG_KEY_COUNT_INSRT                                        AES_BLK_SKG_KEY_COUNT_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_SKG_KEY_COUNT_INSRT                                        AES_BLK_SKG_KEY_COUNT_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_SKG_KEY_COUNT_INSRT                                        AES_BLK_SKG_KEY_COUNT_INSRT_V7
#endif

/*! @} count */

/*! 
 *  @addtogroup group995994 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_SKG_KEY_TNBLE_RESET_UMASK_S8000_A1                         (0xffffffff)
#define  AES_BLK_SKG_KEY_TNBLE_RESET_UMASK_S8000_B0                         (0xffffffff)
#define  AES_BLK_SKG_KEY_TNBLE_RESET_UMASK_S8001_A0                         (0xffffffff)
#define  AES_BLK_SKG_KEY_TNBLE_RESET_UMASK_T8002_A0                         (0xffffffff)
#define  AES_BLK_SKG_KEY_TNBLE_RESET_UMASK_T8010_A0                         (0xffffffff)

#define  AES_BLK_SKG_KEY_TNBLE_RESET_VALUE_S8000_A1                         (0x0)
#define  AES_BLK_SKG_KEY_TNBLE_RESET_VALUE_S8000_B0                         (0x0)
#define  AES_BLK_SKG_KEY_TNBLE_RESET_VALUE_S8001_A0                         (0x0)
#define  AES_BLK_SKG_KEY_TNBLE_RESET_VALUE_T8002_A0                         (0x0)
#define  AES_BLK_SKG_KEY_TNBLE_RESET_VALUE_T8010_A0                         (0x0)

/*! @} reset */

/*! @} skg_key */

/*! 
 *  @addtogroup group995995 clear_fifos
 *  @brief Offset = 0x38
 *  @details Clear COMMAND and HISTORY FIFOs
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_CLEAR_FIFOS_OFFSET_V5                                      (0x0 + 0x38)
#define  AES_BLK_CLEAR_FIFOS_OFFSET_V6                                      (0x0 + 0x38)
#define  AES_BLK_CLEAR_FIFOS_OFFSET_V7                                      (0x0 + 0x38)
#if      SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_CLEAR_FIFOS_OFFSET                                         AES_BLK_CLEAR_FIFOS_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_CLEAR_FIFOS_OFFSET                                         AES_BLK_CLEAR_FIFOS_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CLEAR_FIFOS_OFFSET                                         AES_BLK_CLEAR_FIFOS_OFFSET_V7
#endif

/*! 
 *  @addtogroup group995996 reset
 *  @brief Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0
 *  @details Write 1 to this field to reset the contents of the Command and
 *  History FIFOs to zero.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_CLEAR_FIFOS_RESET_SHIFT_V7                                 (0)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CLEAR_FIFOS_RESET_SHIFT                                    AES_BLK_CLEAR_FIFOS_RESET_SHIFT_V7
#endif

#define  AES_BLK_CLEAR_FIFOS_RESET_WIDTH_V7                                 (1)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CLEAR_FIFOS_RESET_WIDTH                                    AES_BLK_CLEAR_FIFOS_RESET_WIDTH_V7
#endif

#define  AES_BLK_CLEAR_FIFOS_RESET_UMASK_V7                                 (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CLEAR_FIFOS_RESET_UMASK                                    AES_BLK_CLEAR_FIFOS_RESET_UMASK_V7
#endif

#define  AES_BLK_CLEAR_FIFOS_RESET_SMASK_V7                                 (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CLEAR_FIFOS_RESET_SMASK                                    AES_BLK_CLEAR_FIFOS_RESET_SMASK_V7
#endif

#define  AES_BLK_CLEAR_FIFOS_RESET_XTRCT_V7(r)                              ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CLEAR_FIFOS_RESET_XTRCT                                    AES_BLK_CLEAR_FIFOS_RESET_XTRCT_V7
#endif

#define  AES_BLK_CLEAR_FIFOS_RESET_INSRT_V7(f)                              ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_CLEAR_FIFOS_RESET_INSRT                                    AES_BLK_CLEAR_FIFOS_RESET_INSRT_V7
#endif

/*! @} reset */

/*! 
 *  @addtogroup group995998 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_CLEAR_FIFOS_TNBLE_RESET_UMASK_T8010_A0                     (0x1)

#define  AES_BLK_CLEAR_FIFOS_TNBLE_RESET_VALUE_T8010_A0                     (0x0)

/*! @} reset */

/*! @} clear_fifos */

/*! 
 *  @addtogroup group995999 command_fifo
 *  @brief Offset = 0x200
 *  @details Command FIFO. FIFO Depth is (128) Words
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_OFFSET_V3                                     (0x0 + 0x100)
#define  AES_BLK_COMMAND_FIFO_OFFSET_V4                                     (0x0 + 0x100)
#define  AES_BLK_COMMAND_FIFO_OFFSET_V5                                     (0x0 + 0x200)
#define  AES_BLK_COMMAND_FIFO_OFFSET_V6                                     (0x0 + 0x200)
#define  AES_BLK_COMMAND_FIFO_OFFSET_V7                                     (0x0 + 0x200)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_OFFSET                                        AES_BLK_COMMAND_FIFO_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_OFFSET                                        AES_BLK_COMMAND_FIFO_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_OFFSET                                        AES_BLK_COMMAND_FIFO_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_OFFSET                                        AES_BLK_COMMAND_FIFO_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_OFFSET                                        AES_BLK_COMMAND_FIFO_OFFSET_V7
#endif

/*! 
 *  @addtogroup group996000 push_word
 *  @brief Range = 31:0 | Width = 32 | Access = write-only | Default = 0x0
 *  @details Command Word
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT_V3                            (0)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT_V4                            (0)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT_V5                            (0)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT_V6                            (0)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT_V7                            (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_SHIFT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH_V3                            (32)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH_V4                            (32)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH_V5                            (32)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH_V6                            (32)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH_V7                            (32)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH                               AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH                               AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH                               AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH                               AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH                               AES_BLK_COMMAND_FIFO_PUSH_WORD_WIDTH_V7
#endif

#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK_V3                            (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK_V4                            (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK_V5                            (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK_V6                            (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK_V7                            (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK                               AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK                               AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK                               AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK                               AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK                               AES_BLK_COMMAND_FIFO_PUSH_WORD_UMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK_V3                            (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK_V4                            (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK_V5                            (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK_V6                            (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK_V7                            (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK                               AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK                               AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK                               AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK                               AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK                               AES_BLK_COMMAND_FIFO_PUSH_WORD_SMASK_V7
#endif

#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT_V3(r)                         ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT_V4(r)                         ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT_V5(r)                         ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT_V6(r)                         ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT_V7(r)                         ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_XTRCT_V7
#endif

#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT_V3(f)                         ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT_V4(f)                         ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT_V5(f)                         ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT_V6(f)                         ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT_V7(f)                         ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT                               AES_BLK_COMMAND_FIFO_PUSH_WORD_INSRT_V7
#endif

/*! @} push_word */

/*! 
 *  @addtogroup group996001 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_COMMAND_FIFO_TNBLE_RESET_UMASK_S8000_A1                    (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_TNBLE_RESET_UMASK_S8000_B0                    (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_TNBLE_RESET_UMASK_S8001_A0                    (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_TNBLE_RESET_UMASK_T8002_A0                    (0xffffffff)
#define  AES_BLK_COMMAND_FIFO_TNBLE_RESET_UMASK_T8010_A0                    (0xffffffff)

#define  AES_BLK_COMMAND_FIFO_TNBLE_RESET_VALUE_S8000_A1                    (0x0)
#define  AES_BLK_COMMAND_FIFO_TNBLE_RESET_VALUE_S8000_B0                    (0x0)
#define  AES_BLK_COMMAND_FIFO_TNBLE_RESET_VALUE_S8001_A0                    (0x0)
#define  AES_BLK_COMMAND_FIFO_TNBLE_RESET_VALUE_T8002_A0                    (0x0)
#define  AES_BLK_COMMAND_FIFO_TNBLE_RESET_VALUE_T8010_A0                    (0x0)

/*! @} reset */

/*! @} command_fifo */

/*! 
 *  @addtogroup group996003 history_fifo
 *  @brief Offset = 0x400
 *  @details Last (32) Commands words
 *  @see @ref SAIRegister
 *  @{
 */

/*! 
 *  Compute the offset for an element in array 'history_fifo'. The base offset
 *  of 'history_fifo' is 0x400. The size of each element in 'history_fifo' is 4
 *  bytes.
 *  @param i Index for an element in 'history_fifo'. Legal values include [0...31].
 */
#define  AES_BLK_HISTORY_FIFO_OFFSET_V3                                     (0x0 + 0x200)
#define  AES_BLK_HISTORY_FIFO_OFFSET_V4                                     (0x0 + 0x200)
#define  AES_BLK_HISTORY_FIFO_OFFSET_V5(i)                                  (0x0 + 0x400 + (i) * 4)
#define  AES_BLK_HISTORY_FIFO_OFFSET_V6                                     (0x0 + 0x400)
#define  AES_BLK_HISTORY_FIFO_OFFSET_V7(i)                                  (0x0 + 0x400 + (i) * 4)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_OFFSET                                        AES_BLK_HISTORY_FIFO_OFFSET_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_OFFSET                                        AES_BLK_HISTORY_FIFO_OFFSET_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_OFFSET                                        AES_BLK_HISTORY_FIFO_OFFSET_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_OFFSET                                        AES_BLK_HISTORY_FIFO_OFFSET_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_OFFSET                                        AES_BLK_HISTORY_FIFO_OFFSET_V7
#endif

#define  AES_BLK_HISTORY_FIFO_COUNT_V3                                      (1)
#define  AES_BLK_HISTORY_FIFO_COUNT_V4                                      (1)
#define  AES_BLK_HISTORY_FIFO_COUNT_V5                                      (32)
#define  AES_BLK_HISTORY_FIFO_COUNT_V6                                      (1)
#define  AES_BLK_HISTORY_FIFO_COUNT_V7                                      (32)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_COUNT                                         AES_BLK_HISTORY_FIFO_COUNT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_COUNT                                         AES_BLK_HISTORY_FIFO_COUNT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_COUNT                                         AES_BLK_HISTORY_FIFO_COUNT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_COUNT                                         AES_BLK_HISTORY_FIFO_COUNT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_COUNT                                         AES_BLK_HISTORY_FIFO_COUNT_V7
#endif

/*! 
 *  @addtogroup group996004 pop_word
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details Unconnected FIFO output. Command words should be read from
 *  HISTORY_FIFO - 0x3600
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT_V3                             (0)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT_V4                             (0)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT_V5                             (0)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT_V6                             (0)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT_V7                             (0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT                                AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT                                AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT                                AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT                                AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT                                AES_BLK_HISTORY_FIFO_POP_WORD_SHIFT_V7
#endif

#define  AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH_V3                             (32)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH_V4                             (32)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH_V5                             (32)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH_V6                             (32)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH_V7                             (32)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH                                AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH                                AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH                                AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH                                AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH                                AES_BLK_HISTORY_FIFO_POP_WORD_WIDTH_V7
#endif

#define  AES_BLK_HISTORY_FIFO_POP_WORD_UMASK_V3                             (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_UMASK_V4                             (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_UMASK_V5                             (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_UMASK_V6                             (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_UMASK_V7                             (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_POP_WORD_UMASK                                AES_BLK_HISTORY_FIFO_POP_WORD_UMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_POP_WORD_UMASK                                AES_BLK_HISTORY_FIFO_POP_WORD_UMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_POP_WORD_UMASK                                AES_BLK_HISTORY_FIFO_POP_WORD_UMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_POP_WORD_UMASK                                AES_BLK_HISTORY_FIFO_POP_WORD_UMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_POP_WORD_UMASK                                AES_BLK_HISTORY_FIFO_POP_WORD_UMASK_V7
#endif

#define  AES_BLK_HISTORY_FIFO_POP_WORD_SMASK_V3                             (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SMASK_V4                             (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SMASK_V5                             (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SMASK_V6                             (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SMASK_V7                             (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SMASK                                AES_BLK_HISTORY_FIFO_POP_WORD_SMASK_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SMASK                                AES_BLK_HISTORY_FIFO_POP_WORD_SMASK_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SMASK                                AES_BLK_HISTORY_FIFO_POP_WORD_SMASK_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SMASK                                AES_BLK_HISTORY_FIFO_POP_WORD_SMASK_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_POP_WORD_SMASK                                AES_BLK_HISTORY_FIFO_POP_WORD_SMASK_V7
#endif

#define  AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT_V3(r)                          ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT_V4(r)                          ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT_V5(r)                          ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT_V6(r)                          ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT_V7(r)                          ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT                                AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT                                AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT                                AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT                                AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT                                AES_BLK_HISTORY_FIFO_POP_WORD_XTRCT_V7
#endif

#define  AES_BLK_HISTORY_FIFO_POP_WORD_INSRT_V3(f)                          ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_INSRT_V4(f)                          ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_INSRT_V5(f)                          ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_INSRT_V6(f)                          ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_HISTORY_FIFO_POP_WORD_INSRT_V7(f)                          ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_BLK_HISTORY_FIFO_POP_WORD_INSRT                                AES_BLK_HISTORY_FIFO_POP_WORD_INSRT_V3
#elif    SPDS_AES_VERSION == SPDS_AES_V4
#define  AES_BLK_HISTORY_FIFO_POP_WORD_INSRT                                AES_BLK_HISTORY_FIFO_POP_WORD_INSRT_V4
#elif    SPDS_AES_VERSION == SPDS_AES_V5
#define  AES_BLK_HISTORY_FIFO_POP_WORD_INSRT                                AES_BLK_HISTORY_FIFO_POP_WORD_INSRT_V5
#elif    SPDS_AES_VERSION == SPDS_AES_V6
#define  AES_BLK_HISTORY_FIFO_POP_WORD_INSRT                                AES_BLK_HISTORY_FIFO_POP_WORD_INSRT_V6
#elif    SPDS_AES_VERSION == SPDS_AES_V7
#define  AES_BLK_HISTORY_FIFO_POP_WORD_INSRT                                AES_BLK_HISTORY_FIFO_POP_WORD_INSRT_V7
#endif

/*! @} pop_word */

/*! 
 *  @addtogroup group996005 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_HISTORY_FIFO_TNBLE_RESET_UMASK_S8000_A1                    (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_TNBLE_RESET_UMASK_S8000_B0                    (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_TNBLE_RESET_UMASK_S8001_A0                    (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_TNBLE_RESET_UMASK_T8002_A0                    (0xffffffff)
#define  AES_BLK_HISTORY_FIFO_TNBLE_RESET_UMASK_T8010_A0                    (0xffffffff)

#define  AES_BLK_HISTORY_FIFO_TNBLE_RESET_VALUE_S8000_A1                    (0x0)
#define  AES_BLK_HISTORY_FIFO_TNBLE_RESET_VALUE_S8000_B0                    (0x0)
#define  AES_BLK_HISTORY_FIFO_TNBLE_RESET_VALUE_S8001_A0                    (0x0)
#define  AES_BLK_HISTORY_FIFO_TNBLE_RESET_VALUE_T8002_A0                    (0x0)
#define  AES_BLK_HISTORY_FIFO_TNBLE_RESET_VALUE_T8010_A0                    (0x0)

/*! @} reset */

/*! @} history_fifo */

/*! 
 *  @addtogroup group570682 disable (AES_DISABLE)
 *  @brief Offset = 0x4
 *  @details AES GID0, GID1, UID1 and Fairplay Descrambler Disable register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_DISABLE_OFFSET_V1                                          (0x0 + 0x4)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_OFFSET                                             AES_BLK_DISABLE_OFFSET_V1
#endif

/*! 
 *  @addtogroup group570683 id (disable_id)
 *  @brief Range = 2:0 | Width = 3 | Access = write-only | Default = 0x0
 *  @details Write to the disable_id field to disable use of GID0, GID1, and
 *  UID1 keys until the next chip reset.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DISABLE_ID_SHIFT_V1                                        (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_SHIFT                                           AES_BLK_DISABLE_ID_SHIFT_V1
#endif

#define  AES_BLK_DISABLE_ID_WIDTH_V1                                        (3)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_WIDTH                                           AES_BLK_DISABLE_ID_WIDTH_V1
#endif

#define  AES_BLK_DISABLE_ID_UMASK_V1                                        (0x7)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_UMASK                                           AES_BLK_DISABLE_ID_UMASK_V1
#endif

#define  AES_BLK_DISABLE_ID_SMASK_V1                                        (0x7)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_SMASK                                           AES_BLK_DISABLE_ID_SMASK_V1
#endif

#define  AES_BLK_DISABLE_ID_XTRCT_V1(r)                                     ((((uint32_t)r) >> 0) & 0x7)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_XTRCT                                           AES_BLK_DISABLE_ID_XTRCT_V1
#endif

#define  AES_BLK_DISABLE_ID_INSRT_V1(f)                                     ((((uint32_t)f) & 0x7) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_INSRT                                           AES_BLK_DISABLE_ID_INSRT_V1
#endif

/*! @} id (disable_id) */

/*! 
 *  @addtogroup group570687 dsb (disable_dsb)
 *  @brief Range = 3 | Width = 1 | Access = write-only | Default = 0x0
 *  @details Write to the disable_dsb field to disable use of the Fairplay
 *  descrambler until the next chip reset.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DISABLE_DSB_SHIFT_V1                                       (3)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_SHIFT                                          AES_BLK_DISABLE_DSB_SHIFT_V1
#endif

#define  AES_BLK_DISABLE_DSB_WIDTH_V1                                       (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_WIDTH                                          AES_BLK_DISABLE_DSB_WIDTH_V1
#endif

#define  AES_BLK_DISABLE_DSB_UMASK_V1                                       (0x8)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_UMASK                                          AES_BLK_DISABLE_DSB_UMASK_V1
#endif

#define  AES_BLK_DISABLE_DSB_SMASK_V1                                       (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_SMASK                                          AES_BLK_DISABLE_DSB_SMASK_V1
#endif

#define  AES_BLK_DISABLE_DSB_XTRCT_V1(r)                                    ((((uint32_t)r) >> 3) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_XTRCT                                          AES_BLK_DISABLE_DSB_XTRCT_V1
#endif

#define  AES_BLK_DISABLE_DSB_INSRT_V1(f)                                    ((((uint32_t)f) & 0x1) << 3)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_INSRT                                          AES_BLK_DISABLE_DSB_INSRT_V1
#endif

/*! @} dsb (disable_dsb) */

/*! 
 *  @addtogroup group570689 id_disabled
 *  @brief Range = 10:8 | Width = 3 | Access = read-only | Default = 0x0
 *  @details The id_disabled field indicates which keys are disabled.  If the
 *  GID0, GID1, or UID1 keys are selected for use when disabled, then the key
 *  used in the AES operation is zero and an error interrupt is generated.
 *  This field is only cleared on a chip reset.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DISABLE_ID_DISABLED_SHIFT_V1                               (8)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_DISABLED_SHIFT                                  AES_BLK_DISABLE_ID_DISABLED_SHIFT_V1
#endif

#define  AES_BLK_DISABLE_ID_DISABLED_WIDTH_V1                               (3)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_DISABLED_WIDTH                                  AES_BLK_DISABLE_ID_DISABLED_WIDTH_V1
#endif

#define  AES_BLK_DISABLE_ID_DISABLED_UMASK_V1                               (0x700)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_DISABLED_UMASK                                  AES_BLK_DISABLE_ID_DISABLED_UMASK_V1
#endif

#define  AES_BLK_DISABLE_ID_DISABLED_SMASK_V1                               (0x7)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_DISABLED_SMASK                                  AES_BLK_DISABLE_ID_DISABLED_SMASK_V1
#endif

#define  AES_BLK_DISABLE_ID_DISABLED_XTRCT_V1(r)                            ((((uint32_t)r) >> 8) & 0x7)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_DISABLED_XTRCT                                  AES_BLK_DISABLE_ID_DISABLED_XTRCT_V1
#endif

#define  AES_BLK_DISABLE_ID_DISABLED_INSRT_V1(f)                            ((((uint32_t)f) & 0x7) << 8)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_ID_DISABLED_INSRT                                  AES_BLK_DISABLE_ID_DISABLED_INSRT_V1
#endif

/*! @} id_disabled */

/*! 
 *  @addtogroup group570693 dsb_disabled
 *  @brief Range = 11 | Width = 1 | Access = read-only | Default = 0x0
 *  @details When set, the dsb_disabled field indicates that the Fairplay key
 *  descrambler is disabled.  If the Fairplay key descrambler is selected for
 *  use when disabled, then the scrambling operation is bypassed and an error
 *  interrupt is generated.  This field is only cleared on a chip reset.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DISABLE_DSB_DISABLED_SHIFT_V1                              (11)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_DISABLED_SHIFT                                 AES_BLK_DISABLE_DSB_DISABLED_SHIFT_V1
#endif

#define  AES_BLK_DISABLE_DSB_DISABLED_WIDTH_V1                              (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_DISABLED_WIDTH                                 AES_BLK_DISABLE_DSB_DISABLED_WIDTH_V1
#endif

#define  AES_BLK_DISABLE_DSB_DISABLED_UMASK_V1                              (0x800)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_DISABLED_UMASK                                 AES_BLK_DISABLE_DSB_DISABLED_UMASK_V1
#endif

#define  AES_BLK_DISABLE_DSB_DISABLED_SMASK_V1                              (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_DISABLED_SMASK                                 AES_BLK_DISABLE_DSB_DISABLED_SMASK_V1
#endif

#define  AES_BLK_DISABLE_DSB_DISABLED_XTRCT_V1(r)                           ((((uint32_t)r) >> 11) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_DISABLED_XTRCT                                 AES_BLK_DISABLE_DSB_DISABLED_XTRCT_V1
#endif

#define  AES_BLK_DISABLE_DSB_DISABLED_INSRT_V1(f)                           ((((uint32_t)f) & 0x1) << 11)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DISABLE_DSB_DISABLED_INSRT                                 AES_BLK_DISABLE_DSB_DISABLED_INSRT_V1
#endif

/*! @} dsb_disabled */

/*! 
 *  @addtogroup group570695 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_DISABLE_TNBLE_RESET_UMASK_S5L8960X_A0                      (0xf0f)
#define  AES_BLK_DISABLE_TNBLE_RESET_UMASK_S5L8960X_B0                      (0xf0f)
#define  AES_BLK_DISABLE_TNBLE_RESET_UMASK_S5L8960X_B1                      (0xf0f)
#define  AES_BLK_DISABLE_TNBLE_RESET_UMASK_T7000_A0                         (0xf0f)
#define  AES_BLK_DISABLE_TNBLE_RESET_UMASK_T7000_B0                         (0xf0f)
#define  AES_BLK_DISABLE_TNBLE_RESET_UMASK_T7000_B1                         (0xf0f)
#define  AES_BLK_DISABLE_TNBLE_RESET_UMASK_T7001_A0                         (0xf0f)
#define  AES_BLK_DISABLE_TNBLE_RESET_UMASK_T7001_A1                         (0xf0f)

#define  AES_BLK_DISABLE_TNBLE_RESET_VALUE_S5L8960X_A0                      (0x0)
#define  AES_BLK_DISABLE_TNBLE_RESET_VALUE_S5L8960X_B0                      (0x0)
#define  AES_BLK_DISABLE_TNBLE_RESET_VALUE_S5L8960X_B1                      (0x0)
#define  AES_BLK_DISABLE_TNBLE_RESET_VALUE_T7000_A0                         (0x0)
#define  AES_BLK_DISABLE_TNBLE_RESET_VALUE_T7000_B0                         (0x0)
#define  AES_BLK_DISABLE_TNBLE_RESET_VALUE_T7000_B1                         (0x0)
#define  AES_BLK_DISABLE_TNBLE_RESET_VALUE_T7001_A0                         (0x0)
#define  AES_BLK_DISABLE_TNBLE_RESET_VALUE_T7001_A1                         (0x0)

/*! @} reset */

/*! @} disable (AES_DISABLE) */

/*! 
 *  @addtogroup group120226 txt_in_control (AES_TXT_IN_CONTROL)
 *  @brief Offset = 0x8
 *  @details AES Cipher TXT_IN Control Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_IN_CONTROL_OFFSET_V1                                   (0x0 + 0x8)
#define  AES_BLK_TXT_IN_CONTROL_OFFSET_V2                                   (0x0 + 0x8)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_OFFSET                                      AES_BLK_TXT_IN_CONTROL_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_OFFSET                                      AES_BLK_TXT_IN_CONTROL_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120228 txt_in_key_ctx
 *  @brief Range = 1 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Select the key to use for the AES cipher operation.  Software is
 *  responsible for ensuring that the keys are configured and ready for use
 *  through the AES_KEY_IN registers.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SHIFT_V1                     (1)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SHIFT_V2                     (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SHIFT                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SHIFT                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SHIFT_V2
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_WIDTH_V1                     (1)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_WIDTH_V2                     (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_WIDTH                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_WIDTH                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_WIDTH_V2
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_UMASK_V1                     (0x2)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_UMASK_V2                     (0x2)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_UMASK                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_UMASK                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_UMASK_V2
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SMASK_V1                     (0x1)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SMASK_V2                     (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SMASK                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SMASK                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_SMASK_V2
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_XTRCT_V1(r)                  ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_XTRCT_V2(r)                  ((((uint32_t)r) >> 1) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_XTRCT                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_XTRCT                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_XTRCT_V2
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_INSRT_V1(f)                  ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_INSRT_V2(f)                  ((((uint32_t)f) & 0x1) << 1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_INSRT                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_INSRT                        AES_BLK_TXT_IN_CONTROL_TXT_IN_KEY_CTX_INSRT_V2
#endif

/*! @} txt_in_key_ctx */

/*! 
 *  @addtogroup group120229 txt_in_iv_ctx
 *  @brief Range = 2 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Select the IV to use for the AES CBC cipher operation.  Software
 *  is responsible for specifying the IV through the AES_IV_IN registers when
 *  starting a new operation.  When continuing an AES CBC cipher operation from
 *  the previous block, hardware updates the IV.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SHIFT_V1                      (2)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SHIFT_V2                      (2)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SHIFT                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SHIFT                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SHIFT_V2
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_WIDTH_V1                      (1)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_WIDTH_V2                      (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_WIDTH                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_WIDTH                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_WIDTH_V2
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_UMASK_V1                      (0x4)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_UMASK_V2                      (0x4)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_UMASK                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_UMASK                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_UMASK_V2
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SMASK_V1                      (0x1)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SMASK_V2                      (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SMASK                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SMASK                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_SMASK_V2
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_XTRCT_V1(r)                   ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_XTRCT_V2(r)                   ((((uint32_t)r) >> 2) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_XTRCT                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_XTRCT                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_XTRCT_V2
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_INSRT_V1(f)                   ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_INSRT_V2(f)                   ((((uint32_t)f) & 0x1) << 2)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_INSRT                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_INSRT                         AES_BLK_TXT_IN_CONTROL_TXT_IN_IV_CTX_INSRT_V2
#endif

/*! @} txt_in_iv_ctx */

/*! 
 *  @addtogroup group120231 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_IN_CONTROL_TNBLE_RESET_UMASK_T7001_A1                  (0x7)
#define  AES_BLK_TXT_IN_CONTROL_TNBLE_RESET_UMASK_S7002_A1                  (0x6)

#define  AES_BLK_TXT_IN_CONTROL_TNBLE_RESET_VALUE_T7001_A1                  (0x0)
#define  AES_BLK_TXT_IN_CONTROL_TNBLE_RESET_VALUE_S7002_A1                  (0x0)

/*! @} reset */

/*! 
 *  @addtogroup group570697 txt_in_val
 *  @brief Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0
 *  @details Set this field to start an AES cipher operation on the 16B block
 *  stored in the AES_TXT_IN0/1/2/3 registers.  Before starting an AES cipher
 *  operation, software must check that the AES cipher engine is ready by
 *  checking the AES_TXT_IN_STATUS register.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_SHIFT_V1                         (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_SHIFT                            AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_SHIFT_V1
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_WIDTH_V1                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_WIDTH                            AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_WIDTH_V1
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_UMASK_V1                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_UMASK                            AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_UMASK_V1
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_SMASK_V1                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_SMASK                            AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_SMASK_V1
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_XTRCT_V1(r)                      ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_XTRCT                            AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_XTRCT_V1
#endif

#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_INSRT_V1(f)                      ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_INSRT                            AES_BLK_TXT_IN_CONTROL_TXT_IN_VAL_INSRT_V1
#endif

/*! @} txt_in_val */

/*! @} txt_in_control (AES_TXT_IN_CONTROL) */

/*! 
 *  @addtogroup group120232 txt_in_status (AES_TXT_IN_STATUS)
 *  @brief Offset = 0xc
 *  @details AES Cipher TXT_IN Status register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_IN_STATUS_OFFSET_V1                                    (0x0 + 0xc)
#define  AES_BLK_TXT_IN_STATUS_OFFSET_V2                                    (0x0 + 0xc)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_STATUS_OFFSET                                       AES_BLK_TXT_IN_STATUS_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_STATUS_OFFSET                                       AES_BLK_TXT_IN_STATUS_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120233 tx_fifo_space_available
 *  @brief Range = 0 | Width = 1 | Access = read-only | Default = 0x1
 *  @details There are at least 16 bytes of space in the Tx fifo which can be
 *  written into.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_SHIFT_V2             (0)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_SHIFT                AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_SHIFT_V2
#endif

#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_WIDTH_V2             (1)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_WIDTH                AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_WIDTH_V2
#endif

#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_UMASK_V2             (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_UMASK                AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_UMASK_V2
#endif

#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_SMASK_V2             (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_SMASK                AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_SMASK_V2
#endif

#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_XTRCT_V2(r)          ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_XTRCT                AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_XTRCT_V2
#endif

#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_INSRT_V2(f)          ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_INSRT                AES_BLK_TXT_IN_STATUS_TX_FIFO_SPACE_AVAILABLE_INSRT_V2
#endif

/*! @} tx_fifo_space_available */

/*! 
 *  @addtogroup group120235 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_IN_STATUS_TNBLE_RESET_UMASK_T7001_A1                   (0x1)
#define  AES_BLK_TXT_IN_STATUS_TNBLE_RESET_UMASK_S7002_A1                   (0x1)

#define  AES_BLK_TXT_IN_STATUS_TNBLE_RESET_VALUE_T7001_A1                   (0x1)
#define  AES_BLK_TXT_IN_STATUS_TNBLE_RESET_VALUE_S7002_A1                   (0x1)

/*! @} reset */

/*! 
 *  @addtogroup group570703 txt_in_rdy
 *  @brief Range = 0 | Width = 1 | Access = read-only | Default = 0x1
 *  @details Check that the txt_in_rdy bit is set before writing to the
 *  AES_TXT_IN_CONTROL register to start an AES operation.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_SHIFT_V1                          (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_SHIFT                             AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_SHIFT_V1
#endif

#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_WIDTH_V1                          (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_WIDTH                             AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_WIDTH_V1
#endif

#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_UMASK_V1                          (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_UMASK                             AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_UMASK_V1
#endif

#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_SMASK_V1                          (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_SMASK                             AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_SMASK_V1
#endif

#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_XTRCT_V1(r)                       ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_XTRCT                             AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_XTRCT_V1
#endif

#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_INSRT_V1(f)                       ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_INSRT                             AES_BLK_TXT_IN_STATUS_TXT_IN_RDY_INSRT_V1
#endif

/*! @} txt_in_rdy */

/*! @} txt_in_status (AES_TXT_IN_STATUS) */

/*! 
 *  @addtogroup group570706 txt_in0 (AES_TXT_IN0)
 *  @brief Offset = 0x40
 *  @details AES Cipher TXT_IN[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_IN0_OFFSET_V1                                          (0x0 + 0x40)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN0_OFFSET                                             AES_BLK_TXT_IN0_OFFSET_V1
#endif

/*! 
 *  @addtogroup group570707 fld (txt_in0)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details txt_in[31:0]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_IN0_FLD_SHIFT_V1                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN0_FLD_SHIFT                                          AES_BLK_TXT_IN0_FLD_SHIFT_V1
#endif

#define  AES_BLK_TXT_IN0_FLD_WIDTH_V1                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN0_FLD_WIDTH                                          AES_BLK_TXT_IN0_FLD_WIDTH_V1
#endif

#define  AES_BLK_TXT_IN0_FLD_UMASK_V1                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN0_FLD_UMASK                                          AES_BLK_TXT_IN0_FLD_UMASK_V1
#endif

#define  AES_BLK_TXT_IN0_FLD_SMASK_V1                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN0_FLD_SMASK                                          AES_BLK_TXT_IN0_FLD_SMASK_V1
#endif

#define  AES_BLK_TXT_IN0_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN0_FLD_XTRCT                                          AES_BLK_TXT_IN0_FLD_XTRCT_V1
#endif

#define  AES_BLK_TXT_IN0_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN0_FLD_INSRT                                          AES_BLK_TXT_IN0_FLD_INSRT_V1
#endif

/*! @} fld (txt_in0) */

/*! 
 *  @addtogroup group570708 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_IN0_TNBLE_RESET_UMASK_S5L8960X_A0                      (0xffffffff)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_UMASK_S5L8960X_B0                      (0xffffffff)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_UMASK_S5L8960X_B1                      (0xffffffff)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_UMASK_T7000_A0                         (0xffffffff)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_UMASK_T7000_B0                         (0xffffffff)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_UMASK_T7000_B1                         (0xffffffff)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_UMASK_T7001_A0                         (0xffffffff)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)

#define  AES_BLK_TXT_IN0_TNBLE_RESET_VALUE_S5L8960X_A0                      (0x0)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_VALUE_S5L8960X_B0                      (0x0)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_VALUE_S5L8960X_B1                      (0x0)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_VALUE_T7000_A0                         (0x0)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_VALUE_T7000_B0                         (0x0)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_VALUE_T7000_B1                         (0x0)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_VALUE_T7001_A0                         (0x0)
#define  AES_BLK_TXT_IN0_TNBLE_RESET_VALUE_T7001_A1                         (0x0)

/*! @} reset */

/*! @} txt_in0 (AES_TXT_IN0) */

/*! 
 *  @addtogroup group570709 txt_in1 (AES_TXT_IN1)
 *  @brief Offset = 0x44
 *  @details AES Cipher TXT_IN[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_IN1_OFFSET_V1                                          (0x0 + 0x44)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN1_OFFSET                                             AES_BLK_TXT_IN1_OFFSET_V1
#endif

/*! 
 *  @addtogroup group570710 fld (txt_in1)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details txt_in[63:32]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_IN1_FLD_SHIFT_V1                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN1_FLD_SHIFT                                          AES_BLK_TXT_IN1_FLD_SHIFT_V1
#endif

#define  AES_BLK_TXT_IN1_FLD_WIDTH_V1                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN1_FLD_WIDTH                                          AES_BLK_TXT_IN1_FLD_WIDTH_V1
#endif

#define  AES_BLK_TXT_IN1_FLD_UMASK_V1                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN1_FLD_UMASK                                          AES_BLK_TXT_IN1_FLD_UMASK_V1
#endif

#define  AES_BLK_TXT_IN1_FLD_SMASK_V1                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN1_FLD_SMASK                                          AES_BLK_TXT_IN1_FLD_SMASK_V1
#endif

#define  AES_BLK_TXT_IN1_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN1_FLD_XTRCT                                          AES_BLK_TXT_IN1_FLD_XTRCT_V1
#endif

#define  AES_BLK_TXT_IN1_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN1_FLD_INSRT                                          AES_BLK_TXT_IN1_FLD_INSRT_V1
#endif

/*! @} fld (txt_in1) */

/*! 
 *  @addtogroup group570711 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_IN1_TNBLE_RESET_UMASK_S5L8960X_A0                      (0xffffffff)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_UMASK_S5L8960X_B0                      (0xffffffff)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_UMASK_S5L8960X_B1                      (0xffffffff)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_UMASK_T7000_A0                         (0xffffffff)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_UMASK_T7000_B0                         (0xffffffff)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_UMASK_T7000_B1                         (0xffffffff)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_UMASK_T7001_A0                         (0xffffffff)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)

#define  AES_BLK_TXT_IN1_TNBLE_RESET_VALUE_S5L8960X_A0                      (0x0)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_VALUE_S5L8960X_B0                      (0x0)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_VALUE_S5L8960X_B1                      (0x0)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_VALUE_T7000_A0                         (0x0)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_VALUE_T7000_B0                         (0x0)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_VALUE_T7000_B1                         (0x0)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_VALUE_T7001_A0                         (0x0)
#define  AES_BLK_TXT_IN1_TNBLE_RESET_VALUE_T7001_A1                         (0x0)

/*! @} reset */

/*! @} txt_in1 (AES_TXT_IN1) */

/*! 
 *  @addtogroup group570712 txt_in2 (AES_TXT_IN2)
 *  @brief Offset = 0x48
 *  @details AES Cipher TXT_IN[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_IN2_OFFSET_V1                                          (0x0 + 0x48)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN2_OFFSET                                             AES_BLK_TXT_IN2_OFFSET_V1
#endif

/*! 
 *  @addtogroup group570713 fld (txt_in2)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details txt_in[95:64]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_IN2_FLD_SHIFT_V1                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN2_FLD_SHIFT                                          AES_BLK_TXT_IN2_FLD_SHIFT_V1
#endif

#define  AES_BLK_TXT_IN2_FLD_WIDTH_V1                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN2_FLD_WIDTH                                          AES_BLK_TXT_IN2_FLD_WIDTH_V1
#endif

#define  AES_BLK_TXT_IN2_FLD_UMASK_V1                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN2_FLD_UMASK                                          AES_BLK_TXT_IN2_FLD_UMASK_V1
#endif

#define  AES_BLK_TXT_IN2_FLD_SMASK_V1                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN2_FLD_SMASK                                          AES_BLK_TXT_IN2_FLD_SMASK_V1
#endif

#define  AES_BLK_TXT_IN2_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN2_FLD_XTRCT                                          AES_BLK_TXT_IN2_FLD_XTRCT_V1
#endif

#define  AES_BLK_TXT_IN2_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN2_FLD_INSRT                                          AES_BLK_TXT_IN2_FLD_INSRT_V1
#endif

/*! @} fld (txt_in2) */

/*! 
 *  @addtogroup group570714 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_IN2_TNBLE_RESET_UMASK_S5L8960X_A0                      (0xffffffff)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_UMASK_S5L8960X_B0                      (0xffffffff)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_UMASK_S5L8960X_B1                      (0xffffffff)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_UMASK_T7000_A0                         (0xffffffff)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_UMASK_T7000_B0                         (0xffffffff)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_UMASK_T7000_B1                         (0xffffffff)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_UMASK_T7001_A0                         (0xffffffff)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)

#define  AES_BLK_TXT_IN2_TNBLE_RESET_VALUE_S5L8960X_A0                      (0x0)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_VALUE_S5L8960X_B0                      (0x0)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_VALUE_S5L8960X_B1                      (0x0)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_VALUE_T7000_A0                         (0x0)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_VALUE_T7000_B0                         (0x0)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_VALUE_T7000_B1                         (0x0)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_VALUE_T7001_A0                         (0x0)
#define  AES_BLK_TXT_IN2_TNBLE_RESET_VALUE_T7001_A1                         (0x0)

/*! @} reset */

/*! @} txt_in2 (AES_TXT_IN2) */

/*! 
 *  @addtogroup group570715 txt_in3 (AES_TXT_IN3)
 *  @brief Offset = 0x4c
 *  @details AES Cipher TXT_IN[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_IN3_OFFSET_V1                                          (0x0 + 0x4c)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN3_OFFSET                                             AES_BLK_TXT_IN3_OFFSET_V1
#endif

/*! 
 *  @addtogroup group570716 fld (txt_in3)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details txt_in[127:96]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_IN3_FLD_SHIFT_V1                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN3_FLD_SHIFT                                          AES_BLK_TXT_IN3_FLD_SHIFT_V1
#endif

#define  AES_BLK_TXT_IN3_FLD_WIDTH_V1                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN3_FLD_WIDTH                                          AES_BLK_TXT_IN3_FLD_WIDTH_V1
#endif

#define  AES_BLK_TXT_IN3_FLD_UMASK_V1                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN3_FLD_UMASK                                          AES_BLK_TXT_IN3_FLD_UMASK_V1
#endif

#define  AES_BLK_TXT_IN3_FLD_SMASK_V1                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN3_FLD_SMASK                                          AES_BLK_TXT_IN3_FLD_SMASK_V1
#endif

#define  AES_BLK_TXT_IN3_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN3_FLD_XTRCT                                          AES_BLK_TXT_IN3_FLD_XTRCT_V1
#endif

#define  AES_BLK_TXT_IN3_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_IN3_FLD_INSRT                                          AES_BLK_TXT_IN3_FLD_INSRT_V1
#endif

/*! @} fld (txt_in3) */

/*! 
 *  @addtogroup group570717 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_IN3_TNBLE_RESET_UMASK_S5L8960X_A0                      (0xffffffff)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_UMASK_S5L8960X_B0                      (0xffffffff)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_UMASK_S5L8960X_B1                      (0xffffffff)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_UMASK_T7000_A0                         (0xffffffff)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_UMASK_T7000_B0                         (0xffffffff)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_UMASK_T7000_B1                         (0xffffffff)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_UMASK_T7001_A0                         (0xffffffff)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)

#define  AES_BLK_TXT_IN3_TNBLE_RESET_VALUE_S5L8960X_A0                      (0x0)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_VALUE_S5L8960X_B0                      (0x0)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_VALUE_S5L8960X_B1                      (0x0)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_VALUE_T7000_A0                         (0x0)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_VALUE_T7000_B0                         (0x0)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_VALUE_T7000_B1                         (0x0)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_VALUE_T7001_A0                         (0x0)
#define  AES_BLK_TXT_IN3_TNBLE_RESET_VALUE_T7001_A1                         (0x0)

/*! @} reset */

/*! @} txt_in3 (AES_TXT_IN3) */

/*! 
 *  @addtogroup group120239 txt_out_status (AES_TXT_OUT_STATUS)
 *  @brief Offset = 0x50
 *  @details AES Cipher TXT_OUT Status Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_OUT_STATUS_OFFSET_V1                                   (0x0 + 0x50)
#define  AES_BLK_TXT_OUT_STATUS_OFFSET_V2                                   (0x0 + 0x50)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_OFFSET                                      AES_BLK_TXT_OUT_STATUS_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_OFFSET                                      AES_BLK_TXT_OUT_STATUS_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120240 rx_fifo_data_available
 *  @brief Range = 0 | Width = 1 | Access = read-only | Default = 0x0
 *  @details There are at least 16 bytes in the Rx fifo available for reading.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_SHIFT_V2             (0)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_SHIFT                AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_SHIFT_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_WIDTH_V2             (1)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_WIDTH                AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_WIDTH_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_UMASK_V2             (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_UMASK                AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_UMASK_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_SMASK_V2             (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_SMASK                AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_SMASK_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_XTRCT_V2(r)          ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_XTRCT                AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_XTRCT_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_INSRT_V2(f)          ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_INSRT                AES_BLK_TXT_OUT_STATUS_RX_FIFO_DATA_AVAILABLE_INSRT_V2
#endif

/*! @} rx_fifo_data_available */

/*! 
 *  @addtogroup group120241 txt_out_key_ctx
 *  @brief Range = 1 | Width = 1 | Access = read-only | Default = 0x0
 *  @details Identifies which key was used for the AES cipher operation.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SHIFT_V1                    (1)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SHIFT_V2                    (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SHIFT                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SHIFT                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SHIFT_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_WIDTH_V1                    (1)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_WIDTH_V2                    (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_WIDTH                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_WIDTH                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_WIDTH_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_UMASK_V1                    (0x2)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_UMASK_V2                    (0x2)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_UMASK                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_UMASK                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_UMASK_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SMASK_V1                    (0x1)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SMASK_V2                    (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SMASK                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SMASK                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_SMASK_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_XTRCT_V1(r)                 ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_XTRCT_V2(r)                 ((((uint32_t)r) >> 1) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_XTRCT                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_XTRCT                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_XTRCT_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_INSRT_V1(f)                 ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_INSRT_V2(f)                 ((((uint32_t)f) & 0x1) << 1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_INSRT                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_INSRT                       AES_BLK_TXT_OUT_STATUS_TXT_OUT_KEY_CTX_INSRT_V2
#endif

/*! @} txt_out_key_ctx */

/*! 
 *  @addtogroup group120242 txt_out_iv_ctx
 *  @brief Range = 2 | Width = 1 | Access = read-only | Default = 0x0
 *  @details Identifies which IV was used for the AES cipher operation.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SHIFT_V1                     (2)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SHIFT_V2                     (2)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SHIFT                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SHIFT                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SHIFT_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_WIDTH_V1                     (1)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_WIDTH_V2                     (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_WIDTH                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_WIDTH                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_WIDTH_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_UMASK_V1                     (0x4)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_UMASK_V2                     (0x4)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_UMASK                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_UMASK                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_UMASK_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SMASK_V1                     (0x1)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SMASK_V2                     (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SMASK                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SMASK                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_SMASK_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_XTRCT_V1(r)                  ((((uint32_t)r) >> 2) & 0x1)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_XTRCT_V2(r)                  ((((uint32_t)r) >> 2) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_XTRCT                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_XTRCT                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_XTRCT_V2
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_INSRT_V1(f)                  ((((uint32_t)f) & 0x1) << 2)
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_INSRT_V2(f)                  ((((uint32_t)f) & 0x1) << 2)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_INSRT                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_INSRT                        AES_BLK_TXT_OUT_STATUS_TXT_OUT_IV_CTX_INSRT_V2
#endif

/*! @} txt_out_iv_ctx */

/*! 
 *  @addtogroup group120244 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_OUT_STATUS_TNBLE_RESET_UMASK_T7001_A1                  (0x7)
#define  AES_BLK_TXT_OUT_STATUS_TNBLE_RESET_UMASK_S7002_A1                  (0x7)

#define  AES_BLK_TXT_OUT_STATUS_TNBLE_RESET_VALUE_T7001_A1                  (0x0)
#define  AES_BLK_TXT_OUT_STATUS_TNBLE_RESET_VALUE_S7002_A1                  (0x0)

/*! @} reset */

/*! 
 *  @addtogroup group570719 txt_out_val
 *  @brief Range = 0 | Width = 1 | Access = read-only | Default = 0x0
 *  @details When set, AES Cipher data may be read from the TXT_OUT and IV_OUT
 *  registers.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_SHIFT_V1                        (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_SHIFT                           AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_SHIFT_V1
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_WIDTH_V1                        (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_WIDTH                           AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_WIDTH_V1
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_UMASK_V1                        (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_UMASK                           AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_UMASK_V1
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_SMASK_V1                        (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_SMASK                           AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_SMASK_V1
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_XTRCT_V1(r)                     ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_XTRCT                           AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_XTRCT_V1
#endif

#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_INSRT_V1(f)                     ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_INSRT                           AES_BLK_TXT_OUT_STATUS_TXT_OUT_VAL_INSRT_V1
#endif

/*! @} txt_out_val */

/*! @} txt_out_status (AES_TXT_OUT_STATUS) */

/*! 
 *  @addtogroup group570724 txt_out0 (AES_TXT_OUT0)
 *  @brief Offset = 0x80
 *  @details AES Cipher TXT_OUT[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_OUT0_OFFSET_V1                                         (0x0 + 0x80)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT0_OFFSET                                            AES_BLK_TXT_OUT0_OFFSET_V1
#endif

/*! 
 *  @addtogroup group570725 fld (txt_out0)
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details txt_out[31:0]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_OUT0_FLD_SHIFT_V1                                      (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT0_FLD_SHIFT                                         AES_BLK_TXT_OUT0_FLD_SHIFT_V1
#endif

#define  AES_BLK_TXT_OUT0_FLD_WIDTH_V1                                      (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT0_FLD_WIDTH                                         AES_BLK_TXT_OUT0_FLD_WIDTH_V1
#endif

#define  AES_BLK_TXT_OUT0_FLD_UMASK_V1                                      (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT0_FLD_UMASK                                         AES_BLK_TXT_OUT0_FLD_UMASK_V1
#endif

#define  AES_BLK_TXT_OUT0_FLD_SMASK_V1                                      (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT0_FLD_SMASK                                         AES_BLK_TXT_OUT0_FLD_SMASK_V1
#endif

#define  AES_BLK_TXT_OUT0_FLD_XTRCT_V1(r)                                   ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT0_FLD_XTRCT                                         AES_BLK_TXT_OUT0_FLD_XTRCT_V1
#endif

#define  AES_BLK_TXT_OUT0_FLD_INSRT_V1(f)                                   ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT0_FLD_INSRT                                         AES_BLK_TXT_OUT0_FLD_INSRT_V1
#endif

/*! @} fld (txt_out0) */

/*! 
 *  @addtogroup group570726 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_OUT0_TNBLE_RESET_UMASK_S5L8960X_A0                     (0xffffffff)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_UMASK_S5L8960X_B0                     (0xffffffff)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_UMASK_S5L8960X_B1                     (0xffffffff)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_UMASK_T7000_A0                        (0xffffffff)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_UMASK_T7000_B0                        (0xffffffff)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_UMASK_T7000_B1                        (0xffffffff)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_UMASK_T7001_A0                        (0xffffffff)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)

#define  AES_BLK_TXT_OUT0_TNBLE_RESET_VALUE_S5L8960X_A0                     (0x0)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_VALUE_S5L8960X_B0                     (0x0)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_VALUE_S5L8960X_B1                     (0x0)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_VALUE_T7000_A0                        (0x0)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_VALUE_T7000_B0                        (0x0)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_VALUE_T7000_B1                        (0x0)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_VALUE_T7001_A0                        (0x0)
#define  AES_BLK_TXT_OUT0_TNBLE_RESET_VALUE_T7001_A1                        (0x0)

/*! @} reset */

/*! @} txt_out0 (AES_TXT_OUT0) */

/*! 
 *  @addtogroup group570727 txt_out1 (AES_TXT_OUT1)
 *  @brief Offset = 0x84
 *  @details AES Cipher TXT_OUT[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_OUT1_OFFSET_V1                                         (0x0 + 0x84)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT1_OFFSET                                            AES_BLK_TXT_OUT1_OFFSET_V1
#endif

/*! 
 *  @addtogroup group570728 fld (txt_out1)
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details txt_out[63:32]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_OUT1_FLD_SHIFT_V1                                      (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT1_FLD_SHIFT                                         AES_BLK_TXT_OUT1_FLD_SHIFT_V1
#endif

#define  AES_BLK_TXT_OUT1_FLD_WIDTH_V1                                      (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT1_FLD_WIDTH                                         AES_BLK_TXT_OUT1_FLD_WIDTH_V1
#endif

#define  AES_BLK_TXT_OUT1_FLD_UMASK_V1                                      (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT1_FLD_UMASK                                         AES_BLK_TXT_OUT1_FLD_UMASK_V1
#endif

#define  AES_BLK_TXT_OUT1_FLD_SMASK_V1                                      (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT1_FLD_SMASK                                         AES_BLK_TXT_OUT1_FLD_SMASK_V1
#endif

#define  AES_BLK_TXT_OUT1_FLD_XTRCT_V1(r)                                   ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT1_FLD_XTRCT                                         AES_BLK_TXT_OUT1_FLD_XTRCT_V1
#endif

#define  AES_BLK_TXT_OUT1_FLD_INSRT_V1(f)                                   ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT1_FLD_INSRT                                         AES_BLK_TXT_OUT1_FLD_INSRT_V1
#endif

/*! @} fld (txt_out1) */

/*! 
 *  @addtogroup group570729 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_OUT1_TNBLE_RESET_UMASK_S5L8960X_A0                     (0xffffffff)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_UMASK_S5L8960X_B0                     (0xffffffff)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_UMASK_S5L8960X_B1                     (0xffffffff)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_UMASK_T7000_A0                        (0xffffffff)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_UMASK_T7000_B0                        (0xffffffff)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_UMASK_T7000_B1                        (0xffffffff)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_UMASK_T7001_A0                        (0xffffffff)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)

#define  AES_BLK_TXT_OUT1_TNBLE_RESET_VALUE_S5L8960X_A0                     (0x0)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_VALUE_S5L8960X_B0                     (0x0)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_VALUE_S5L8960X_B1                     (0x0)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_VALUE_T7000_A0                        (0x0)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_VALUE_T7000_B0                        (0x0)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_VALUE_T7000_B1                        (0x0)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_VALUE_T7001_A0                        (0x0)
#define  AES_BLK_TXT_OUT1_TNBLE_RESET_VALUE_T7001_A1                        (0x0)

/*! @} reset */

/*! @} txt_out1 (AES_TXT_OUT1) */

/*! 
 *  @addtogroup group570730 txt_out2 (AES_TXT_OUT2)
 *  @brief Offset = 0x88
 *  @details AES Cipher TXT_OUT[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_OUT2_OFFSET_V1                                         (0x0 + 0x88)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT2_OFFSET                                            AES_BLK_TXT_OUT2_OFFSET_V1
#endif

/*! 
 *  @addtogroup group570731 fld (txt_out2)
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details txt_out[95:64]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_OUT2_FLD_SHIFT_V1                                      (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT2_FLD_SHIFT                                         AES_BLK_TXT_OUT2_FLD_SHIFT_V1
#endif

#define  AES_BLK_TXT_OUT2_FLD_WIDTH_V1                                      (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT2_FLD_WIDTH                                         AES_BLK_TXT_OUT2_FLD_WIDTH_V1
#endif

#define  AES_BLK_TXT_OUT2_FLD_UMASK_V1                                      (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT2_FLD_UMASK                                         AES_BLK_TXT_OUT2_FLD_UMASK_V1
#endif

#define  AES_BLK_TXT_OUT2_FLD_SMASK_V1                                      (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT2_FLD_SMASK                                         AES_BLK_TXT_OUT2_FLD_SMASK_V1
#endif

#define  AES_BLK_TXT_OUT2_FLD_XTRCT_V1(r)                                   ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT2_FLD_XTRCT                                         AES_BLK_TXT_OUT2_FLD_XTRCT_V1
#endif

#define  AES_BLK_TXT_OUT2_FLD_INSRT_V1(f)                                   ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT2_FLD_INSRT                                         AES_BLK_TXT_OUT2_FLD_INSRT_V1
#endif

/*! @} fld (txt_out2) */

/*! 
 *  @addtogroup group570732 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_OUT2_TNBLE_RESET_UMASK_S5L8960X_A0                     (0xffffffff)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_UMASK_S5L8960X_B0                     (0xffffffff)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_UMASK_S5L8960X_B1                     (0xffffffff)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_UMASK_T7000_A0                        (0xffffffff)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_UMASK_T7000_B0                        (0xffffffff)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_UMASK_T7000_B1                        (0xffffffff)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_UMASK_T7001_A0                        (0xffffffff)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)

#define  AES_BLK_TXT_OUT2_TNBLE_RESET_VALUE_S5L8960X_A0                     (0x0)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_VALUE_S5L8960X_B0                     (0x0)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_VALUE_S5L8960X_B1                     (0x0)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_VALUE_T7000_A0                        (0x0)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_VALUE_T7000_B0                        (0x0)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_VALUE_T7000_B1                        (0x0)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_VALUE_T7001_A0                        (0x0)
#define  AES_BLK_TXT_OUT2_TNBLE_RESET_VALUE_T7001_A1                        (0x0)

/*! @} reset */

/*! @} txt_out2 (AES_TXT_OUT2) */

/*! 
 *  @addtogroup group570733 txt_out3 (AES_TXT_OUT3)
 *  @brief Offset = 0x8c
 *  @details AES Cipher TXT_OUT[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_OUT3_OFFSET_V1                                         (0x0 + 0x8c)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT3_OFFSET                                            AES_BLK_TXT_OUT3_OFFSET_V1
#endif

/*! 
 *  @addtogroup group570734 fld (txt_out3)
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details txt_out[127:96]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_OUT3_FLD_SHIFT_V1                                      (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT3_FLD_SHIFT                                         AES_BLK_TXT_OUT3_FLD_SHIFT_V1
#endif

#define  AES_BLK_TXT_OUT3_FLD_WIDTH_V1                                      (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT3_FLD_WIDTH                                         AES_BLK_TXT_OUT3_FLD_WIDTH_V1
#endif

#define  AES_BLK_TXT_OUT3_FLD_UMASK_V1                                      (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT3_FLD_UMASK                                         AES_BLK_TXT_OUT3_FLD_UMASK_V1
#endif

#define  AES_BLK_TXT_OUT3_FLD_SMASK_V1                                      (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT3_FLD_SMASK                                         AES_BLK_TXT_OUT3_FLD_SMASK_V1
#endif

#define  AES_BLK_TXT_OUT3_FLD_XTRCT_V1(r)                                   ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT3_FLD_XTRCT                                         AES_BLK_TXT_OUT3_FLD_XTRCT_V1
#endif

#define  AES_BLK_TXT_OUT3_FLD_INSRT_V1(f)                                   ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_TXT_OUT3_FLD_INSRT                                         AES_BLK_TXT_OUT3_FLD_INSRT_V1
#endif

/*! @} fld (txt_out3) */

/*! 
 *  @addtogroup group570735 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_OUT3_TNBLE_RESET_UMASK_S5L8960X_A0                     (0xffffffff)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_UMASK_S5L8960X_B0                     (0xffffffff)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_UMASK_S5L8960X_B1                     (0xffffffff)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_UMASK_T7000_A0                        (0xffffffff)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_UMASK_T7000_B0                        (0xffffffff)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_UMASK_T7000_B1                        (0xffffffff)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_UMASK_T7001_A0                        (0xffffffff)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)

#define  AES_BLK_TXT_OUT3_TNBLE_RESET_VALUE_S5L8960X_A0                     (0x0)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_VALUE_S5L8960X_B0                     (0x0)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_VALUE_S5L8960X_B1                     (0x0)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_VALUE_T7000_A0                        (0x0)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_VALUE_T7000_B0                        (0x0)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_VALUE_T7000_B1                        (0x0)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_VALUE_T7001_A0                        (0x0)
#define  AES_BLK_TXT_OUT3_TNBLE_RESET_VALUE_T7001_A1                        (0x0)

/*! @} reset */

/*! @} txt_out3 (AES_TXT_OUT3) */

/*! 
 *  @addtogroup group120248 key_in_control (AES_KEY_IN_CONTROL)
 *  @brief Offset = 0x90
 *  @details AES KEY_IN Control Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_KEY_IN_CONTROL_OFFSET_V1                                   (0x0 + 0x90)
#define  AES_BLK_KEY_IN_CONTROL_OFFSET_V2                                   (0x0 + 0x90)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_OFFSET                                      AES_BLK_KEY_IN_CONTROL_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_OFFSET                                      AES_BLK_KEY_IN_CONTROL_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120249 key_in_val
 *  @brief Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0
 *  @details Set this field to start an AES key configurator operation.  Before
 *  starting an AES key configurator operation, software must check that the
 *  AES key configurator engine is ready by checking the AES_KEY_IN_STATUS
 *  register.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SHIFT_V1                         (0)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SHIFT_V2                         (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_WIDTH_V1                         (1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_WIDTH_V2                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_UMASK_V1                         (0x1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_UMASK_V2                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_UMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SMASK_V1                         (0x1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SMASK_V2                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_SMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_XTRCT_V1(r)                      ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_XTRCT_V2(r)                      ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_INSRT_V1(f)                      ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_INSRT_V2(f)                      ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_VAL_INSRT_V2
#endif

/*! @} key_in_val */

/*! 
 *  @addtogroup group120250 key_in_ctx
 *  @brief Range = 1 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Selects the key context that will be updated with the results of
 *  the AES key configurator operation.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SHIFT_V1                         (1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SHIFT_V2                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_WIDTH_V1                         (1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_WIDTH_V2                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_UMASK_V1                         (0x2)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_UMASK_V2                         (0x2)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_UMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SMASK_V1                         (0x1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SMASK_V2                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_SMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_XTRCT_V1(r)                      ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_XTRCT_V2(r)                      ((((uint32_t)r) >> 1) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_INSRT_V1(f)                      ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_INSRT_V2(f)                      ((((uint32_t)f) & 0x1) << 1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_CTX_INSRT_V2
#endif

/*! @} key_in_ctx */

/*! 
 *  @addtogroup group120252 key_in_sel
 *  @brief Range = 5:4 | Width = 2 | Access = read-write | Default = 0x0
 *  @details Selects which key to use as an input to the AES key configurator.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SHIFT_V1                         (4)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SHIFT_V2                         (4)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_WIDTH_V1                         (2)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_WIDTH_V2                         (2)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_UMASK_V1                         (0x30)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_UMASK_V2                         (0x30)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_UMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SMASK_V1                         (0x3)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SMASK_V2                         (0x3)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_SMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_XTRCT_V1(r)                      ((((uint32_t)r) >> 4) & 0x3)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_XTRCT_V2(r)                      ((((uint32_t)r) >> 4) & 0x3)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_INSRT_V1(f)                      ((((uint32_t)f) & 0x3) << 4)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_INSRT_V2(f)                      ((((uint32_t)f) & 0x3) << 4)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_SEL_INSRT_V2
#endif

/*! @} key_in_sel */

/*! 
 *  @addtogroup group120257 key_in_len
 *  @brief Range = 7:6 | Width = 2 | Access = read-write | Default = 0x0
 *  @details Key context length
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SHIFT_V1                         (6)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SHIFT_V2                         (6)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_WIDTH_V1                         (2)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_WIDTH_V2                         (2)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_UMASK_V1                         (0xc0)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_UMASK_V2                         (0xc0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_UMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SMASK_V1                         (0x3)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SMASK_V2                         (0x3)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_SMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_XTRCT_V1(r)                      ((((uint32_t)r) >> 6) & 0x3)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_XTRCT_V2(r)                      ((((uint32_t)r) >> 6) & 0x3)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_INSRT_V1(f)                      ((((uint32_t)f) & 0x3) << 6)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_INSRT_V2(f)                      ((((uint32_t)f) & 0x3) << 6)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_LEN_INSRT_V2
#endif

/*! @} key_in_len */

/*! 
 *  @addtogroup group120261 key_in_fun
 *  @brief Range = 10:8 | Width = 3 | Access = read-write | Default = 0x0
 *  @details Key function
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SHIFT_V1                         (8)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SHIFT_V2                         (8)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_WIDTH_V1                         (3)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_WIDTH_V2                         (3)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_UMASK_V1                         (0x700)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_UMASK_V2                         (0x700)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_UMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SMASK_V1                         (0x7)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SMASK_V2                         (0x7)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_SMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_XTRCT_V1(r)                      ((((uint32_t)r) >> 8) & 0x7)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_XTRCT_V2(r)                      ((((uint32_t)r) >> 8) & 0x7)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_INSRT_V1(f)                      ((((uint32_t)f) & 0x7) << 8)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_INSRT_V2(f)                      ((((uint32_t)f) & 0x7) << 8)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_FUN_INSRT_V2
#endif

/*! @} key_in_fun */

/*! 
 *  @addtogroup group120266 key_in_enc
 *  @brief Range = 12 | Width = 1 | Access = read-write | Default = 0x0
 *  @details When set, the key will be used for encryption.  When cleared, the
 *  key will be used for decryption.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SHIFT_V1                         (12)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SHIFT_V2                         (12)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_WIDTH_V1                         (1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_WIDTH_V2                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_UMASK_V1                         (0x1000)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_UMASK_V2                         (0x1000)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_UMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SMASK_V1                         (0x1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SMASK_V2                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_SMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_XTRCT_V1(r)                      ((((uint32_t)r) >> 12) & 0x1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_XTRCT_V2(r)                      ((((uint32_t)r) >> 12) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_INSRT_V1(f)                      ((((uint32_t)f) & 0x1) << 12)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_INSRT_V2(f)                      ((((uint32_t)f) & 0x1) << 12)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_ENC_INSRT_V2
#endif

/*! @} key_in_enc */

/*! 
 *  @addtogroup group120267 key_in_mod
 *  @brief Range = 13 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Block Cipher Mode:  When set, the AES cipher is configured to
 *  support CBC mode.  When cleared, the AES Cipher supports ECB mode.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SHIFT_V1                         (13)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SHIFT_V2                         (13)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SHIFT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_WIDTH_V1                         (1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_WIDTH_V2                         (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_WIDTH                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_UMASK_V1                         (0x2000)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_UMASK_V2                         (0x2000)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_UMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_UMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SMASK_V1                         (0x1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SMASK_V2                         (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SMASK                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_SMASK_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_XTRCT_V1(r)                      ((((uint32_t)r) >> 13) & 0x1)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_XTRCT_V2(r)                      ((((uint32_t)r) >> 13) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_XTRCT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_INSRT_V1(f)                      ((((uint32_t)f) & 0x1) << 13)
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_INSRT_V2(f)                      ((((uint32_t)f) & 0x1) << 13)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_INSRT                            AES_BLK_KEY_IN_CONTROL_KEY_IN_MOD_INSRT_V2
#endif

/*! @} key_in_mod */

/*! 
 *  @addtogroup group120269 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_KEY_IN_CONTROL_TNBLE_RESET_UMASK_T7001_A1                  (0x37f3)
#define  AES_BLK_KEY_IN_CONTROL_TNBLE_RESET_UMASK_S7002_A1                  (0x37f3)

#define  AES_BLK_KEY_IN_CONTROL_TNBLE_RESET_VALUE_T7001_A1                  (0x0)
#define  AES_BLK_KEY_IN_CONTROL_TNBLE_RESET_VALUE_S7002_A1                  (0x0)

/*! @} reset */

/*! @} key_in_control (AES_KEY_IN_CONTROL) */

/*! 
 *  @addtogroup group120270 key_in_status (AES_KEY_IN_STATUS)
 *  @brief Offset = 0x94
 *  @details AES KEY_IN Status Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_KEY_IN_STATUS_OFFSET_V1                                    (0x0 + 0x94)
#define  AES_BLK_KEY_IN_STATUS_OFFSET_V2                                    (0x0 + 0x94)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_STATUS_OFFSET                                       AES_BLK_KEY_IN_STATUS_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_STATUS_OFFSET                                       AES_BLK_KEY_IN_STATUS_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120271 key_in_rdy
 *  @brief Range = 0 | Width = 1 | Access = read-only | Default = 0x1
 *  @details When set, the AES Key configurator operation is complete and the
 *  key may be used by the AES Cipher engine.  After starting a key
 *  configurator operation, software checks this register to determine that the
 *  key context is ready for use.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SHIFT_V1                          (0)
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SHIFT_V2                          (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SHIFT                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SHIFT                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_WIDTH_V1                          (1)
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_WIDTH_V2                          (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_WIDTH                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_WIDTH                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_UMASK_V1                          (0x1)
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_UMASK_V2                          (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_UMASK                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_UMASK                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_UMASK_V2
#endif

#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SMASK_V1                          (0x1)
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SMASK_V2                          (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SMASK                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SMASK                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_SMASK_V2
#endif

#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_XTRCT_V1(r)                       ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_XTRCT_V2(r)                       ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_XTRCT                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_XTRCT                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_INSRT_V1(f)                       ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_INSRT_V2(f)                       ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_INSRT                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_INSRT                             AES_BLK_KEY_IN_STATUS_KEY_IN_RDY_INSRT_V2
#endif

/*! @} key_in_rdy */

/*! 
 *  @addtogroup group120273 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_KEY_IN_STATUS_TNBLE_RESET_UMASK_T7001_A1                   (0x1)
#define  AES_BLK_KEY_IN_STATUS_TNBLE_RESET_UMASK_S7002_A1                   (0x1)

#define  AES_BLK_KEY_IN_STATUS_TNBLE_RESET_VALUE_T7001_A1                   (0x1)
#define  AES_BLK_KEY_IN_STATUS_TNBLE_RESET_VALUE_S7002_A1                   (0x1)

/*! @} reset */

/*! @} key_in_status (AES_KEY_IN_STATUS) */

/*! 
 *  @addtogroup group120274 key_in0 (AES_KEY_IN0)
 *  @brief Offset = 0xc0
 *  @details AES KEY_IN[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_KEY_IN0_OFFSET_V1                                          (0x0 + 0xc0)
#define  AES_BLK_KEY_IN0_OFFSET_V2                                          (0x0 + 0xc0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN0_OFFSET                                             AES_BLK_KEY_IN0_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN0_OFFSET                                             AES_BLK_KEY_IN0_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120275 fld (key_in0)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details key_in[31:0]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN0_FLD_SHIFT_V1                                       (0)
#define  AES_BLK_KEY_IN0_FLD_SHIFT_V2                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN0_FLD_SHIFT                                          AES_BLK_KEY_IN0_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN0_FLD_SHIFT                                          AES_BLK_KEY_IN0_FLD_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN0_FLD_WIDTH_V1                                       (32)
#define  AES_BLK_KEY_IN0_FLD_WIDTH_V2                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN0_FLD_WIDTH                                          AES_BLK_KEY_IN0_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN0_FLD_WIDTH                                          AES_BLK_KEY_IN0_FLD_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN0_FLD_UMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN0_FLD_UMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN0_FLD_UMASK                                          AES_BLK_KEY_IN0_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN0_FLD_UMASK                                          AES_BLK_KEY_IN0_FLD_UMASK_V2
#endif

#define  AES_BLK_KEY_IN0_FLD_SMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN0_FLD_SMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN0_FLD_SMASK                                          AES_BLK_KEY_IN0_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN0_FLD_SMASK                                          AES_BLK_KEY_IN0_FLD_SMASK_V2
#endif

#define  AES_BLK_KEY_IN0_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_KEY_IN0_FLD_XTRCT_V2(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN0_FLD_XTRCT                                          AES_BLK_KEY_IN0_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN0_FLD_XTRCT                                          AES_BLK_KEY_IN0_FLD_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN0_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_KEY_IN0_FLD_INSRT_V2(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN0_FLD_INSRT                                          AES_BLK_KEY_IN0_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN0_FLD_INSRT                                          AES_BLK_KEY_IN0_FLD_INSRT_V2
#endif

/*! @} fld (key_in0) */

/*! 
 *  @addtogroup group120276 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_KEY_IN0_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)
#define  AES_BLK_KEY_IN0_TNBLE_RESET_UMASK_S7002_A1                         (0xffffffff)

#define  AES_BLK_KEY_IN0_TNBLE_RESET_VALUE_T7001_A1                         (0x0)
#define  AES_BLK_KEY_IN0_TNBLE_RESET_VALUE_S7002_A1                         (0x0)

/*! @} reset */

/*! @} key_in0 (AES_KEY_IN0) */

/*! 
 *  @addtogroup group120277 key_in1 (AES_KEY_IN1)
 *  @brief Offset = 0xc4
 *  @details AES KEY_IN[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_KEY_IN1_OFFSET_V1                                          (0x0 + 0xc4)
#define  AES_BLK_KEY_IN1_OFFSET_V2                                          (0x0 + 0xc4)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN1_OFFSET                                             AES_BLK_KEY_IN1_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN1_OFFSET                                             AES_BLK_KEY_IN1_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120278 fld (key_in1)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details key_in[63:32]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN1_FLD_SHIFT_V1                                       (0)
#define  AES_BLK_KEY_IN1_FLD_SHIFT_V2                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN1_FLD_SHIFT                                          AES_BLK_KEY_IN1_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN1_FLD_SHIFT                                          AES_BLK_KEY_IN1_FLD_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN1_FLD_WIDTH_V1                                       (32)
#define  AES_BLK_KEY_IN1_FLD_WIDTH_V2                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN1_FLD_WIDTH                                          AES_BLK_KEY_IN1_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN1_FLD_WIDTH                                          AES_BLK_KEY_IN1_FLD_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN1_FLD_UMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN1_FLD_UMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN1_FLD_UMASK                                          AES_BLK_KEY_IN1_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN1_FLD_UMASK                                          AES_BLK_KEY_IN1_FLD_UMASK_V2
#endif

#define  AES_BLK_KEY_IN1_FLD_SMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN1_FLD_SMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN1_FLD_SMASK                                          AES_BLK_KEY_IN1_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN1_FLD_SMASK                                          AES_BLK_KEY_IN1_FLD_SMASK_V2
#endif

#define  AES_BLK_KEY_IN1_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_KEY_IN1_FLD_XTRCT_V2(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN1_FLD_XTRCT                                          AES_BLK_KEY_IN1_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN1_FLD_XTRCT                                          AES_BLK_KEY_IN1_FLD_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN1_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_KEY_IN1_FLD_INSRT_V2(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN1_FLD_INSRT                                          AES_BLK_KEY_IN1_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN1_FLD_INSRT                                          AES_BLK_KEY_IN1_FLD_INSRT_V2
#endif

/*! @} fld (key_in1) */

/*! 
 *  @addtogroup group120279 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_KEY_IN1_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)
#define  AES_BLK_KEY_IN1_TNBLE_RESET_UMASK_S7002_A1                         (0xffffffff)

#define  AES_BLK_KEY_IN1_TNBLE_RESET_VALUE_T7001_A1                         (0x0)
#define  AES_BLK_KEY_IN1_TNBLE_RESET_VALUE_S7002_A1                         (0x0)

/*! @} reset */

/*! @} key_in1 (AES_KEY_IN1) */

/*! 
 *  @addtogroup group120280 key_in2 (AES_KEY_IN2)
 *  @brief Offset = 0xc8
 *  @details AES KEY_IN[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_KEY_IN2_OFFSET_V1                                          (0x0 + 0xc8)
#define  AES_BLK_KEY_IN2_OFFSET_V2                                          (0x0 + 0xc8)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN2_OFFSET                                             AES_BLK_KEY_IN2_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN2_OFFSET                                             AES_BLK_KEY_IN2_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120281 fld (key_in2)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details key_in[95:64]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN2_FLD_SHIFT_V1                                       (0)
#define  AES_BLK_KEY_IN2_FLD_SHIFT_V2                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN2_FLD_SHIFT                                          AES_BLK_KEY_IN2_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN2_FLD_SHIFT                                          AES_BLK_KEY_IN2_FLD_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN2_FLD_WIDTH_V1                                       (32)
#define  AES_BLK_KEY_IN2_FLD_WIDTH_V2                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN2_FLD_WIDTH                                          AES_BLK_KEY_IN2_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN2_FLD_WIDTH                                          AES_BLK_KEY_IN2_FLD_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN2_FLD_UMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN2_FLD_UMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN2_FLD_UMASK                                          AES_BLK_KEY_IN2_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN2_FLD_UMASK                                          AES_BLK_KEY_IN2_FLD_UMASK_V2
#endif

#define  AES_BLK_KEY_IN2_FLD_SMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN2_FLD_SMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN2_FLD_SMASK                                          AES_BLK_KEY_IN2_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN2_FLD_SMASK                                          AES_BLK_KEY_IN2_FLD_SMASK_V2
#endif

#define  AES_BLK_KEY_IN2_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_KEY_IN2_FLD_XTRCT_V2(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN2_FLD_XTRCT                                          AES_BLK_KEY_IN2_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN2_FLD_XTRCT                                          AES_BLK_KEY_IN2_FLD_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN2_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_KEY_IN2_FLD_INSRT_V2(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN2_FLD_INSRT                                          AES_BLK_KEY_IN2_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN2_FLD_INSRT                                          AES_BLK_KEY_IN2_FLD_INSRT_V2
#endif

/*! @} fld (key_in2) */

/*! 
 *  @addtogroup group120282 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_KEY_IN2_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)
#define  AES_BLK_KEY_IN2_TNBLE_RESET_UMASK_S7002_A1                         (0xffffffff)

#define  AES_BLK_KEY_IN2_TNBLE_RESET_VALUE_T7001_A1                         (0x0)
#define  AES_BLK_KEY_IN2_TNBLE_RESET_VALUE_S7002_A1                         (0x0)

/*! @} reset */

/*! @} key_in2 (AES_KEY_IN2) */

/*! 
 *  @addtogroup group120283 key_in3 (AES_KEY_IN3)
 *  @brief Offset = 0xcc
 *  @details AES KEY_IN[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_KEY_IN3_OFFSET_V1                                          (0x0 + 0xcc)
#define  AES_BLK_KEY_IN3_OFFSET_V2                                          (0x0 + 0xcc)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN3_OFFSET                                             AES_BLK_KEY_IN3_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN3_OFFSET                                             AES_BLK_KEY_IN3_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120284 fld (key_in3)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details key_in[127:96]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN3_FLD_SHIFT_V1                                       (0)
#define  AES_BLK_KEY_IN3_FLD_SHIFT_V2                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN3_FLD_SHIFT                                          AES_BLK_KEY_IN3_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN3_FLD_SHIFT                                          AES_BLK_KEY_IN3_FLD_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN3_FLD_WIDTH_V1                                       (32)
#define  AES_BLK_KEY_IN3_FLD_WIDTH_V2                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN3_FLD_WIDTH                                          AES_BLK_KEY_IN3_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN3_FLD_WIDTH                                          AES_BLK_KEY_IN3_FLD_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN3_FLD_UMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN3_FLD_UMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN3_FLD_UMASK                                          AES_BLK_KEY_IN3_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN3_FLD_UMASK                                          AES_BLK_KEY_IN3_FLD_UMASK_V2
#endif

#define  AES_BLK_KEY_IN3_FLD_SMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN3_FLD_SMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN3_FLD_SMASK                                          AES_BLK_KEY_IN3_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN3_FLD_SMASK                                          AES_BLK_KEY_IN3_FLD_SMASK_V2
#endif

#define  AES_BLK_KEY_IN3_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_KEY_IN3_FLD_XTRCT_V2(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN3_FLD_XTRCT                                          AES_BLK_KEY_IN3_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN3_FLD_XTRCT                                          AES_BLK_KEY_IN3_FLD_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN3_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_KEY_IN3_FLD_INSRT_V2(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN3_FLD_INSRT                                          AES_BLK_KEY_IN3_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN3_FLD_INSRT                                          AES_BLK_KEY_IN3_FLD_INSRT_V2
#endif

/*! @} fld (key_in3) */

/*! 
 *  @addtogroup group120285 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_KEY_IN3_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)
#define  AES_BLK_KEY_IN3_TNBLE_RESET_UMASK_S7002_A1                         (0xffffffff)

#define  AES_BLK_KEY_IN3_TNBLE_RESET_VALUE_T7001_A1                         (0x0)
#define  AES_BLK_KEY_IN3_TNBLE_RESET_VALUE_S7002_A1                         (0x0)

/*! @} reset */

/*! @} key_in3 (AES_KEY_IN3) */

/*! 
 *  @addtogroup group120286 key_in4 (AES_KEY_IN4)
 *  @brief Offset = 0xd0
 *  @details AES KEY_IN[159:128] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_KEY_IN4_OFFSET_V1                                          (0x0 + 0xd0)
#define  AES_BLK_KEY_IN4_OFFSET_V2                                          (0x0 + 0xd0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN4_OFFSET                                             AES_BLK_KEY_IN4_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN4_OFFSET                                             AES_BLK_KEY_IN4_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120287 fld (key_in4)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details key_in[159:128]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN4_FLD_SHIFT_V1                                       (0)
#define  AES_BLK_KEY_IN4_FLD_SHIFT_V2                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN4_FLD_SHIFT                                          AES_BLK_KEY_IN4_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN4_FLD_SHIFT                                          AES_BLK_KEY_IN4_FLD_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN4_FLD_WIDTH_V1                                       (32)
#define  AES_BLK_KEY_IN4_FLD_WIDTH_V2                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN4_FLD_WIDTH                                          AES_BLK_KEY_IN4_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN4_FLD_WIDTH                                          AES_BLK_KEY_IN4_FLD_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN4_FLD_UMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN4_FLD_UMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN4_FLD_UMASK                                          AES_BLK_KEY_IN4_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN4_FLD_UMASK                                          AES_BLK_KEY_IN4_FLD_UMASK_V2
#endif

#define  AES_BLK_KEY_IN4_FLD_SMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN4_FLD_SMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN4_FLD_SMASK                                          AES_BLK_KEY_IN4_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN4_FLD_SMASK                                          AES_BLK_KEY_IN4_FLD_SMASK_V2
#endif

#define  AES_BLK_KEY_IN4_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_KEY_IN4_FLD_XTRCT_V2(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN4_FLD_XTRCT                                          AES_BLK_KEY_IN4_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN4_FLD_XTRCT                                          AES_BLK_KEY_IN4_FLD_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN4_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_KEY_IN4_FLD_INSRT_V2(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN4_FLD_INSRT                                          AES_BLK_KEY_IN4_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN4_FLD_INSRT                                          AES_BLK_KEY_IN4_FLD_INSRT_V2
#endif

/*! @} fld (key_in4) */

/*! 
 *  @addtogroup group120288 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_KEY_IN4_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)
#define  AES_BLK_KEY_IN4_TNBLE_RESET_UMASK_S7002_A1                         (0xffffffff)

#define  AES_BLK_KEY_IN4_TNBLE_RESET_VALUE_T7001_A1                         (0x0)
#define  AES_BLK_KEY_IN4_TNBLE_RESET_VALUE_S7002_A1                         (0x0)

/*! @} reset */

/*! @} key_in4 (AES_KEY_IN4) */

/*! 
 *  @addtogroup group120289 key_in5 (AES_KEY_IN5)
 *  @brief Offset = 0xd4
 *  @details AES KEY_IN[191:160] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_KEY_IN5_OFFSET_V1                                          (0x0 + 0xd4)
#define  AES_BLK_KEY_IN5_OFFSET_V2                                          (0x0 + 0xd4)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN5_OFFSET                                             AES_BLK_KEY_IN5_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN5_OFFSET                                             AES_BLK_KEY_IN5_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120290 fld (key_in5)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details key_in[191:160]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN5_FLD_SHIFT_V1                                       (0)
#define  AES_BLK_KEY_IN5_FLD_SHIFT_V2                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN5_FLD_SHIFT                                          AES_BLK_KEY_IN5_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN5_FLD_SHIFT                                          AES_BLK_KEY_IN5_FLD_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN5_FLD_WIDTH_V1                                       (32)
#define  AES_BLK_KEY_IN5_FLD_WIDTH_V2                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN5_FLD_WIDTH                                          AES_BLK_KEY_IN5_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN5_FLD_WIDTH                                          AES_BLK_KEY_IN5_FLD_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN5_FLD_UMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN5_FLD_UMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN5_FLD_UMASK                                          AES_BLK_KEY_IN5_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN5_FLD_UMASK                                          AES_BLK_KEY_IN5_FLD_UMASK_V2
#endif

#define  AES_BLK_KEY_IN5_FLD_SMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN5_FLD_SMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN5_FLD_SMASK                                          AES_BLK_KEY_IN5_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN5_FLD_SMASK                                          AES_BLK_KEY_IN5_FLD_SMASK_V2
#endif

#define  AES_BLK_KEY_IN5_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_KEY_IN5_FLD_XTRCT_V2(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN5_FLD_XTRCT                                          AES_BLK_KEY_IN5_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN5_FLD_XTRCT                                          AES_BLK_KEY_IN5_FLD_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN5_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_KEY_IN5_FLD_INSRT_V2(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN5_FLD_INSRT                                          AES_BLK_KEY_IN5_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN5_FLD_INSRT                                          AES_BLK_KEY_IN5_FLD_INSRT_V2
#endif

/*! @} fld (key_in5) */

/*! 
 *  @addtogroup group120291 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_KEY_IN5_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)
#define  AES_BLK_KEY_IN5_TNBLE_RESET_UMASK_S7002_A1                         (0xffffffff)

#define  AES_BLK_KEY_IN5_TNBLE_RESET_VALUE_T7001_A1                         (0x0)
#define  AES_BLK_KEY_IN5_TNBLE_RESET_VALUE_S7002_A1                         (0x0)

/*! @} reset */

/*! @} key_in5 (AES_KEY_IN5) */

/*! 
 *  @addtogroup group120292 key_in6 (AES_KEY_IN6)
 *  @brief Offset = 0xd8
 *  @details AES KEY_IN[223:192] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_KEY_IN6_OFFSET_V1                                          (0x0 + 0xd8)
#define  AES_BLK_KEY_IN6_OFFSET_V2                                          (0x0 + 0xd8)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN6_OFFSET                                             AES_BLK_KEY_IN6_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN6_OFFSET                                             AES_BLK_KEY_IN6_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120293 fld (key_in6)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details key_in[223:192]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN6_FLD_SHIFT_V1                                       (0)
#define  AES_BLK_KEY_IN6_FLD_SHIFT_V2                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN6_FLD_SHIFT                                          AES_BLK_KEY_IN6_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN6_FLD_SHIFT                                          AES_BLK_KEY_IN6_FLD_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN6_FLD_WIDTH_V1                                       (32)
#define  AES_BLK_KEY_IN6_FLD_WIDTH_V2                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN6_FLD_WIDTH                                          AES_BLK_KEY_IN6_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN6_FLD_WIDTH                                          AES_BLK_KEY_IN6_FLD_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN6_FLD_UMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN6_FLD_UMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN6_FLD_UMASK                                          AES_BLK_KEY_IN6_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN6_FLD_UMASK                                          AES_BLK_KEY_IN6_FLD_UMASK_V2
#endif

#define  AES_BLK_KEY_IN6_FLD_SMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN6_FLD_SMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN6_FLD_SMASK                                          AES_BLK_KEY_IN6_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN6_FLD_SMASK                                          AES_BLK_KEY_IN6_FLD_SMASK_V2
#endif

#define  AES_BLK_KEY_IN6_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_KEY_IN6_FLD_XTRCT_V2(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN6_FLD_XTRCT                                          AES_BLK_KEY_IN6_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN6_FLD_XTRCT                                          AES_BLK_KEY_IN6_FLD_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN6_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_KEY_IN6_FLD_INSRT_V2(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN6_FLD_INSRT                                          AES_BLK_KEY_IN6_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN6_FLD_INSRT                                          AES_BLK_KEY_IN6_FLD_INSRT_V2
#endif

/*! @} fld (key_in6) */

/*! 
 *  @addtogroup group120294 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_KEY_IN6_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)
#define  AES_BLK_KEY_IN6_TNBLE_RESET_UMASK_S7002_A1                         (0xffffffff)

#define  AES_BLK_KEY_IN6_TNBLE_RESET_VALUE_T7001_A1                         (0x0)
#define  AES_BLK_KEY_IN6_TNBLE_RESET_VALUE_S7002_A1                         (0x0)

/*! @} reset */

/*! @} key_in6 (AES_KEY_IN6) */

/*! 
 *  @addtogroup group120295 key_in7 (AES_KEY_IN7)
 *  @brief Offset = 0xdc
 *  @details AES KEY_IN[255:224] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_KEY_IN7_OFFSET_V1                                          (0x0 + 0xdc)
#define  AES_BLK_KEY_IN7_OFFSET_V2                                          (0x0 + 0xdc)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN7_OFFSET                                             AES_BLK_KEY_IN7_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN7_OFFSET                                             AES_BLK_KEY_IN7_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120296 fld (key_in7)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details key_in[255:224]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_KEY_IN7_FLD_SHIFT_V1                                       (0)
#define  AES_BLK_KEY_IN7_FLD_SHIFT_V2                                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN7_FLD_SHIFT                                          AES_BLK_KEY_IN7_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN7_FLD_SHIFT                                          AES_BLK_KEY_IN7_FLD_SHIFT_V2
#endif

#define  AES_BLK_KEY_IN7_FLD_WIDTH_V1                                       (32)
#define  AES_BLK_KEY_IN7_FLD_WIDTH_V2                                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN7_FLD_WIDTH                                          AES_BLK_KEY_IN7_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN7_FLD_WIDTH                                          AES_BLK_KEY_IN7_FLD_WIDTH_V2
#endif

#define  AES_BLK_KEY_IN7_FLD_UMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN7_FLD_UMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN7_FLD_UMASK                                          AES_BLK_KEY_IN7_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN7_FLD_UMASK                                          AES_BLK_KEY_IN7_FLD_UMASK_V2
#endif

#define  AES_BLK_KEY_IN7_FLD_SMASK_V1                                       (0xffffffff)
#define  AES_BLK_KEY_IN7_FLD_SMASK_V2                                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN7_FLD_SMASK                                          AES_BLK_KEY_IN7_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN7_FLD_SMASK                                          AES_BLK_KEY_IN7_FLD_SMASK_V2
#endif

#define  AES_BLK_KEY_IN7_FLD_XTRCT_V1(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_KEY_IN7_FLD_XTRCT_V2(r)                                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN7_FLD_XTRCT                                          AES_BLK_KEY_IN7_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN7_FLD_XTRCT                                          AES_BLK_KEY_IN7_FLD_XTRCT_V2
#endif

#define  AES_BLK_KEY_IN7_FLD_INSRT_V1(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_KEY_IN7_FLD_INSRT_V2(f)                                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_KEY_IN7_FLD_INSRT                                          AES_BLK_KEY_IN7_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_KEY_IN7_FLD_INSRT                                          AES_BLK_KEY_IN7_FLD_INSRT_V2
#endif

/*! @} fld (key_in7) */

/*! 
 *  @addtogroup group120297 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_KEY_IN7_TNBLE_RESET_UMASK_T7001_A1                         (0xffffffff)
#define  AES_BLK_KEY_IN7_TNBLE_RESET_UMASK_S7002_A1                         (0xffffffff)

#define  AES_BLK_KEY_IN7_TNBLE_RESET_VALUE_T7001_A1                         (0x0)
#define  AES_BLK_KEY_IN7_TNBLE_RESET_VALUE_S7002_A1                         (0x0)

/*! @} reset */

/*! @} key_in7 (AES_KEY_IN7) */

/*! 
 *  @addtogroup group120298 iv_in_control (AES_IV_IN_CONTROL)
 *  @brief Offset = 0xe0
 *  @details AES IV_IN Control Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV_IN_CONTROL_OFFSET_V1                                    (0x0 + 0xe0)
#define  AES_BLK_IV_IN_CONTROL_OFFSET_V2                                    (0x0 + 0xe0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_OFFSET                                       AES_BLK_IV_IN_CONTROL_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_OFFSET                                       AES_BLK_IV_IN_CONTROL_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120299 iv_in_val
 *  @brief Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0
 *  @details Set this field to load the IV stored in the AES_IV_IN registers to
 *  the IV context specified by the iv_in_ctx field.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SHIFT_V1                           (0)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SHIFT_V2                           (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SHIFT                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SHIFT                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SHIFT_V2
#endif

#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_WIDTH_V1                           (1)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_WIDTH_V2                           (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_WIDTH                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_WIDTH                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_WIDTH_V2
#endif

#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_UMASK_V1                           (0x1)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_UMASK_V2                           (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_UMASK                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_UMASK                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_UMASK_V2
#endif

#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SMASK_V1                           (0x1)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SMASK_V2                           (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SMASK                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SMASK                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_SMASK_V2
#endif

#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_XTRCT_V1(r)                        ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_XTRCT_V2(r)                        ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_XTRCT                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_XTRCT                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_XTRCT_V2
#endif

#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_INSRT_V1(f)                        ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_INSRT_V2(f)                        ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_INSRT                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_VAL_INSRT                              AES_BLK_IV_IN_CONTROL_IV_IN_VAL_INSRT_V2
#endif

/*! @} iv_in_val */

/*! 
 *  @addtogroup group120300 iv_in_ctx
 *  @brief Range = 1 | Width = 1 | Access = read-write | Default = 0x0
 *  @details Selects which IV context is updated
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SHIFT_V1                           (1)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SHIFT_V2                           (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SHIFT                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SHIFT                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SHIFT_V2
#endif

#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_WIDTH_V1                           (1)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_WIDTH_V2                           (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_WIDTH                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_WIDTH                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_WIDTH_V2
#endif

#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_UMASK_V1                           (0x2)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_UMASK_V2                           (0x2)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_UMASK                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_UMASK                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_UMASK_V2
#endif

#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SMASK_V1                           (0x1)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SMASK_V2                           (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SMASK                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SMASK                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_SMASK_V2
#endif

#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_XTRCT_V1(r)                        ((((uint32_t)r) >> 1) & 0x1)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_XTRCT_V2(r)                        ((((uint32_t)r) >> 1) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_XTRCT                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_XTRCT                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_XTRCT_V2
#endif

#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_INSRT_V1(f)                        ((((uint32_t)f) & 0x1) << 1)
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_INSRT_V2(f)                        ((((uint32_t)f) & 0x1) << 1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_INSRT                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN_CONTROL_IV_IN_CTX_INSRT                              AES_BLK_IV_IN_CONTROL_IV_IN_CTX_INSRT_V2
#endif

/*! @} iv_in_ctx */

/*! 
 *  @addtogroup group120302 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV_IN_CONTROL_TNBLE_RESET_UMASK_T7001_A1                   (0x3)
#define  AES_BLK_IV_IN_CONTROL_TNBLE_RESET_UMASK_S7002_A1                   (0x3)

#define  AES_BLK_IV_IN_CONTROL_TNBLE_RESET_VALUE_T7001_A1                   (0x0)
#define  AES_BLK_IV_IN_CONTROL_TNBLE_RESET_VALUE_S7002_A1                   (0x0)

/*! @} reset */

/*! @} iv_in_control (AES_IV_IN_CONTROL) */

/*! 
 *  @addtogroup group120303 iv_in0 (AES_IV_IN0)
 *  @brief Offset = 0x100
 *  @details AES IV_IN[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV_IN0_OFFSET_V1                                           (0x0 + 0x100)
#define  AES_BLK_IV_IN0_OFFSET_V2                                           (0x0 + 0x100)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN0_OFFSET                                              AES_BLK_IV_IN0_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN0_OFFSET                                              AES_BLK_IV_IN0_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120304 fld (iv_in0)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details iv_in[31:0]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV_IN0_FLD_SHIFT_V1                                        (0)
#define  AES_BLK_IV_IN0_FLD_SHIFT_V2                                        (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN0_FLD_SHIFT                                           AES_BLK_IV_IN0_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN0_FLD_SHIFT                                           AES_BLK_IV_IN0_FLD_SHIFT_V2
#endif

#define  AES_BLK_IV_IN0_FLD_WIDTH_V1                                        (32)
#define  AES_BLK_IV_IN0_FLD_WIDTH_V2                                        (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN0_FLD_WIDTH                                           AES_BLK_IV_IN0_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN0_FLD_WIDTH                                           AES_BLK_IV_IN0_FLD_WIDTH_V2
#endif

#define  AES_BLK_IV_IN0_FLD_UMASK_V1                                        (0xffffffff)
#define  AES_BLK_IV_IN0_FLD_UMASK_V2                                        (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN0_FLD_UMASK                                           AES_BLK_IV_IN0_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN0_FLD_UMASK                                           AES_BLK_IV_IN0_FLD_UMASK_V2
#endif

#define  AES_BLK_IV_IN0_FLD_SMASK_V1                                        (0xffffffff)
#define  AES_BLK_IV_IN0_FLD_SMASK_V2                                        (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN0_FLD_SMASK                                           AES_BLK_IV_IN0_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN0_FLD_SMASK                                           AES_BLK_IV_IN0_FLD_SMASK_V2
#endif

#define  AES_BLK_IV_IN0_FLD_XTRCT_V1(r)                                     ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV_IN0_FLD_XTRCT_V2(r)                                     ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN0_FLD_XTRCT                                           AES_BLK_IV_IN0_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN0_FLD_XTRCT                                           AES_BLK_IV_IN0_FLD_XTRCT_V2
#endif

#define  AES_BLK_IV_IN0_FLD_INSRT_V1(f)                                     ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV_IN0_FLD_INSRT_V2(f)                                     ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN0_FLD_INSRT                                           AES_BLK_IV_IN0_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN0_FLD_INSRT                                           AES_BLK_IV_IN0_FLD_INSRT_V2
#endif

/*! @} fld (iv_in0) */

/*! 
 *  @addtogroup group120305 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV_IN0_TNBLE_RESET_UMASK_T7001_A1                          (0xffffffff)
#define  AES_BLK_IV_IN0_TNBLE_RESET_UMASK_S7002_A1                          (0xffffffff)

#define  AES_BLK_IV_IN0_TNBLE_RESET_VALUE_T7001_A1                          (0x0)
#define  AES_BLK_IV_IN0_TNBLE_RESET_VALUE_S7002_A1                          (0x0)

/*! @} reset */

/*! @} iv_in0 (AES_IV_IN0) */

/*! 
 *  @addtogroup group120306 iv_in1 (AES_IV_IN1)
 *  @brief Offset = 0x104
 *  @details AES IV_IN[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV_IN1_OFFSET_V1                                           (0x0 + 0x104)
#define  AES_BLK_IV_IN1_OFFSET_V2                                           (0x0 + 0x104)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN1_OFFSET                                              AES_BLK_IV_IN1_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN1_OFFSET                                              AES_BLK_IV_IN1_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120307 fld (iv_in1)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details iv_in[63:32]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV_IN1_FLD_SHIFT_V1                                        (0)
#define  AES_BLK_IV_IN1_FLD_SHIFT_V2                                        (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN1_FLD_SHIFT                                           AES_BLK_IV_IN1_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN1_FLD_SHIFT                                           AES_BLK_IV_IN1_FLD_SHIFT_V2
#endif

#define  AES_BLK_IV_IN1_FLD_WIDTH_V1                                        (32)
#define  AES_BLK_IV_IN1_FLD_WIDTH_V2                                        (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN1_FLD_WIDTH                                           AES_BLK_IV_IN1_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN1_FLD_WIDTH                                           AES_BLK_IV_IN1_FLD_WIDTH_V2
#endif

#define  AES_BLK_IV_IN1_FLD_UMASK_V1                                        (0xffffffff)
#define  AES_BLK_IV_IN1_FLD_UMASK_V2                                        (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN1_FLD_UMASK                                           AES_BLK_IV_IN1_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN1_FLD_UMASK                                           AES_BLK_IV_IN1_FLD_UMASK_V2
#endif

#define  AES_BLK_IV_IN1_FLD_SMASK_V1                                        (0xffffffff)
#define  AES_BLK_IV_IN1_FLD_SMASK_V2                                        (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN1_FLD_SMASK                                           AES_BLK_IV_IN1_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN1_FLD_SMASK                                           AES_BLK_IV_IN1_FLD_SMASK_V2
#endif

#define  AES_BLK_IV_IN1_FLD_XTRCT_V1(r)                                     ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV_IN1_FLD_XTRCT_V2(r)                                     ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN1_FLD_XTRCT                                           AES_BLK_IV_IN1_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN1_FLD_XTRCT                                           AES_BLK_IV_IN1_FLD_XTRCT_V2
#endif

#define  AES_BLK_IV_IN1_FLD_INSRT_V1(f)                                     ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV_IN1_FLD_INSRT_V2(f)                                     ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN1_FLD_INSRT                                           AES_BLK_IV_IN1_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN1_FLD_INSRT                                           AES_BLK_IV_IN1_FLD_INSRT_V2
#endif

/*! @} fld (iv_in1) */

/*! 
 *  @addtogroup group120308 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV_IN1_TNBLE_RESET_UMASK_T7001_A1                          (0xffffffff)
#define  AES_BLK_IV_IN1_TNBLE_RESET_UMASK_S7002_A1                          (0xffffffff)

#define  AES_BLK_IV_IN1_TNBLE_RESET_VALUE_T7001_A1                          (0x0)
#define  AES_BLK_IV_IN1_TNBLE_RESET_VALUE_S7002_A1                          (0x0)

/*! @} reset */

/*! @} iv_in1 (AES_IV_IN1) */

/*! 
 *  @addtogroup group120309 iv_in2 (AES_IV_IN2)
 *  @brief Offset = 0x108
 *  @details AES IV_IN[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV_IN2_OFFSET_V1                                           (0x0 + 0x108)
#define  AES_BLK_IV_IN2_OFFSET_V2                                           (0x0 + 0x108)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN2_OFFSET                                              AES_BLK_IV_IN2_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN2_OFFSET                                              AES_BLK_IV_IN2_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120310 fld (iv_in2)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details iv_in[95:64]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV_IN2_FLD_SHIFT_V1                                        (0)
#define  AES_BLK_IV_IN2_FLD_SHIFT_V2                                        (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN2_FLD_SHIFT                                           AES_BLK_IV_IN2_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN2_FLD_SHIFT                                           AES_BLK_IV_IN2_FLD_SHIFT_V2
#endif

#define  AES_BLK_IV_IN2_FLD_WIDTH_V1                                        (32)
#define  AES_BLK_IV_IN2_FLD_WIDTH_V2                                        (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN2_FLD_WIDTH                                           AES_BLK_IV_IN2_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN2_FLD_WIDTH                                           AES_BLK_IV_IN2_FLD_WIDTH_V2
#endif

#define  AES_BLK_IV_IN2_FLD_UMASK_V1                                        (0xffffffff)
#define  AES_BLK_IV_IN2_FLD_UMASK_V2                                        (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN2_FLD_UMASK                                           AES_BLK_IV_IN2_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN2_FLD_UMASK                                           AES_BLK_IV_IN2_FLD_UMASK_V2
#endif

#define  AES_BLK_IV_IN2_FLD_SMASK_V1                                        (0xffffffff)
#define  AES_BLK_IV_IN2_FLD_SMASK_V2                                        (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN2_FLD_SMASK                                           AES_BLK_IV_IN2_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN2_FLD_SMASK                                           AES_BLK_IV_IN2_FLD_SMASK_V2
#endif

#define  AES_BLK_IV_IN2_FLD_XTRCT_V1(r)                                     ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV_IN2_FLD_XTRCT_V2(r)                                     ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN2_FLD_XTRCT                                           AES_BLK_IV_IN2_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN2_FLD_XTRCT                                           AES_BLK_IV_IN2_FLD_XTRCT_V2
#endif

#define  AES_BLK_IV_IN2_FLD_INSRT_V1(f)                                     ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV_IN2_FLD_INSRT_V2(f)                                     ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN2_FLD_INSRT                                           AES_BLK_IV_IN2_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN2_FLD_INSRT                                           AES_BLK_IV_IN2_FLD_INSRT_V2
#endif

/*! @} fld (iv_in2) */

/*! 
 *  @addtogroup group120311 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV_IN2_TNBLE_RESET_UMASK_T7001_A1                          (0xffffffff)
#define  AES_BLK_IV_IN2_TNBLE_RESET_UMASK_S7002_A1                          (0xffffffff)

#define  AES_BLK_IV_IN2_TNBLE_RESET_VALUE_T7001_A1                          (0x0)
#define  AES_BLK_IV_IN2_TNBLE_RESET_VALUE_S7002_A1                          (0x0)

/*! @} reset */

/*! @} iv_in2 (AES_IV_IN2) */

/*! 
 *  @addtogroup group120312 iv_in3 (AES_IV_IN3)
 *  @brief Offset = 0x10c
 *  @details AES IV_IN[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV_IN3_OFFSET_V1                                           (0x0 + 0x10c)
#define  AES_BLK_IV_IN3_OFFSET_V2                                           (0x0 + 0x10c)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN3_OFFSET                                              AES_BLK_IV_IN3_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN3_OFFSET                                              AES_BLK_IV_IN3_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120313 fld (iv_in3)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details iv_in[127:96]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV_IN3_FLD_SHIFT_V1                                        (0)
#define  AES_BLK_IV_IN3_FLD_SHIFT_V2                                        (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN3_FLD_SHIFT                                           AES_BLK_IV_IN3_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN3_FLD_SHIFT                                           AES_BLK_IV_IN3_FLD_SHIFT_V2
#endif

#define  AES_BLK_IV_IN3_FLD_WIDTH_V1                                        (32)
#define  AES_BLK_IV_IN3_FLD_WIDTH_V2                                        (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN3_FLD_WIDTH                                           AES_BLK_IV_IN3_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN3_FLD_WIDTH                                           AES_BLK_IV_IN3_FLD_WIDTH_V2
#endif

#define  AES_BLK_IV_IN3_FLD_UMASK_V1                                        (0xffffffff)
#define  AES_BLK_IV_IN3_FLD_UMASK_V2                                        (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN3_FLD_UMASK                                           AES_BLK_IV_IN3_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN3_FLD_UMASK                                           AES_BLK_IV_IN3_FLD_UMASK_V2
#endif

#define  AES_BLK_IV_IN3_FLD_SMASK_V1                                        (0xffffffff)
#define  AES_BLK_IV_IN3_FLD_SMASK_V2                                        (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN3_FLD_SMASK                                           AES_BLK_IV_IN3_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN3_FLD_SMASK                                           AES_BLK_IV_IN3_FLD_SMASK_V2
#endif

#define  AES_BLK_IV_IN3_FLD_XTRCT_V1(r)                                     ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV_IN3_FLD_XTRCT_V2(r)                                     ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN3_FLD_XTRCT                                           AES_BLK_IV_IN3_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN3_FLD_XTRCT                                           AES_BLK_IV_IN3_FLD_XTRCT_V2
#endif

#define  AES_BLK_IV_IN3_FLD_INSRT_V1(f)                                     ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV_IN3_FLD_INSRT_V2(f)                                     ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV_IN3_FLD_INSRT                                           AES_BLK_IV_IN3_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV_IN3_FLD_INSRT                                           AES_BLK_IV_IN3_FLD_INSRT_V2
#endif

/*! @} fld (iv_in3) */

/*! 
 *  @addtogroup group120314 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV_IN3_TNBLE_RESET_UMASK_T7001_A1                          (0xffffffff)
#define  AES_BLK_IV_IN3_TNBLE_RESET_UMASK_S7002_A1                          (0xffffffff)

#define  AES_BLK_IV_IN3_TNBLE_RESET_VALUE_T7001_A1                          (0x0)
#define  AES_BLK_IV_IN3_TNBLE_RESET_VALUE_S7002_A1                          (0x0)

/*! @} reset */

/*! @} iv_in3 (AES_IV_IN3) */

/*! 
 *  @addtogroup group120315 iv0_out0 (AES_IV0_OUT0)
 *  @brief Offset = 0x140
 *  @details AES IV0_OUT[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV0_OUT0_OFFSET_V1                                         (0x0 + 0x140)
#define  AES_BLK_IV0_OUT0_OFFSET_V2                                         (0x0 + 0x140)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT0_OFFSET                                            AES_BLK_IV0_OUT0_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT0_OFFSET                                            AES_BLK_IV0_OUT0_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120316 iv_out0
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details IV0_OUT[31:0]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV0_OUT0_IV_OUT0_SHIFT_V1                                  (0)
#define  AES_BLK_IV0_OUT0_IV_OUT0_SHIFT_V2                                  (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT0_IV_OUT0_SHIFT                                     AES_BLK_IV0_OUT0_IV_OUT0_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT0_IV_OUT0_SHIFT                                     AES_BLK_IV0_OUT0_IV_OUT0_SHIFT_V2
#endif

#define  AES_BLK_IV0_OUT0_IV_OUT0_WIDTH_V1                                  (32)
#define  AES_BLK_IV0_OUT0_IV_OUT0_WIDTH_V2                                  (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT0_IV_OUT0_WIDTH                                     AES_BLK_IV0_OUT0_IV_OUT0_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT0_IV_OUT0_WIDTH                                     AES_BLK_IV0_OUT0_IV_OUT0_WIDTH_V2
#endif

#define  AES_BLK_IV0_OUT0_IV_OUT0_UMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV0_OUT0_IV_OUT0_UMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT0_IV_OUT0_UMASK                                     AES_BLK_IV0_OUT0_IV_OUT0_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT0_IV_OUT0_UMASK                                     AES_BLK_IV0_OUT0_IV_OUT0_UMASK_V2
#endif

#define  AES_BLK_IV0_OUT0_IV_OUT0_SMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV0_OUT0_IV_OUT0_SMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT0_IV_OUT0_SMASK                                     AES_BLK_IV0_OUT0_IV_OUT0_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT0_IV_OUT0_SMASK                                     AES_BLK_IV0_OUT0_IV_OUT0_SMASK_V2
#endif

#define  AES_BLK_IV0_OUT0_IV_OUT0_XTRCT_V1(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV0_OUT0_IV_OUT0_XTRCT_V2(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT0_IV_OUT0_XTRCT                                     AES_BLK_IV0_OUT0_IV_OUT0_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT0_IV_OUT0_XTRCT                                     AES_BLK_IV0_OUT0_IV_OUT0_XTRCT_V2
#endif

#define  AES_BLK_IV0_OUT0_IV_OUT0_INSRT_V1(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV0_OUT0_IV_OUT0_INSRT_V2(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT0_IV_OUT0_INSRT                                     AES_BLK_IV0_OUT0_IV_OUT0_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT0_IV_OUT0_INSRT                                     AES_BLK_IV0_OUT0_IV_OUT0_INSRT_V2
#endif

/*! @} iv_out0 */

/*! 
 *  @addtogroup group120317 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV0_OUT0_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)
#define  AES_BLK_IV0_OUT0_TNBLE_RESET_UMASK_S7002_A1                        (0xffffffff)

#define  AES_BLK_IV0_OUT0_TNBLE_RESET_VALUE_T7001_A1                        (0x0)
#define  AES_BLK_IV0_OUT0_TNBLE_RESET_VALUE_S7002_A1                        (0x0)

/*! @} reset */

/*! @} iv0_out0 (AES_IV0_OUT0) */

/*! 
 *  @addtogroup group120318 iv0_out1 (AES_IV0_OUT1)
 *  @brief Offset = 0x144
 *  @details AES IV0_OUT[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV0_OUT1_OFFSET_V1                                         (0x0 + 0x144)
#define  AES_BLK_IV0_OUT1_OFFSET_V2                                         (0x0 + 0x144)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT1_OFFSET                                            AES_BLK_IV0_OUT1_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT1_OFFSET                                            AES_BLK_IV0_OUT1_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120319 iv_out1
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details IV0_OUT[63:32]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV0_OUT1_IV_OUT1_SHIFT_V1                                  (0)
#define  AES_BLK_IV0_OUT1_IV_OUT1_SHIFT_V2                                  (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT1_IV_OUT1_SHIFT                                     AES_BLK_IV0_OUT1_IV_OUT1_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT1_IV_OUT1_SHIFT                                     AES_BLK_IV0_OUT1_IV_OUT1_SHIFT_V2
#endif

#define  AES_BLK_IV0_OUT1_IV_OUT1_WIDTH_V1                                  (32)
#define  AES_BLK_IV0_OUT1_IV_OUT1_WIDTH_V2                                  (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT1_IV_OUT1_WIDTH                                     AES_BLK_IV0_OUT1_IV_OUT1_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT1_IV_OUT1_WIDTH                                     AES_BLK_IV0_OUT1_IV_OUT1_WIDTH_V2
#endif

#define  AES_BLK_IV0_OUT1_IV_OUT1_UMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV0_OUT1_IV_OUT1_UMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT1_IV_OUT1_UMASK                                     AES_BLK_IV0_OUT1_IV_OUT1_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT1_IV_OUT1_UMASK                                     AES_BLK_IV0_OUT1_IV_OUT1_UMASK_V2
#endif

#define  AES_BLK_IV0_OUT1_IV_OUT1_SMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV0_OUT1_IV_OUT1_SMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT1_IV_OUT1_SMASK                                     AES_BLK_IV0_OUT1_IV_OUT1_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT1_IV_OUT1_SMASK                                     AES_BLK_IV0_OUT1_IV_OUT1_SMASK_V2
#endif

#define  AES_BLK_IV0_OUT1_IV_OUT1_XTRCT_V1(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV0_OUT1_IV_OUT1_XTRCT_V2(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT1_IV_OUT1_XTRCT                                     AES_BLK_IV0_OUT1_IV_OUT1_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT1_IV_OUT1_XTRCT                                     AES_BLK_IV0_OUT1_IV_OUT1_XTRCT_V2
#endif

#define  AES_BLK_IV0_OUT1_IV_OUT1_INSRT_V1(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV0_OUT1_IV_OUT1_INSRT_V2(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT1_IV_OUT1_INSRT                                     AES_BLK_IV0_OUT1_IV_OUT1_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT1_IV_OUT1_INSRT                                     AES_BLK_IV0_OUT1_IV_OUT1_INSRT_V2
#endif

/*! @} iv_out1 */

/*! 
 *  @addtogroup group120320 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV0_OUT1_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)
#define  AES_BLK_IV0_OUT1_TNBLE_RESET_UMASK_S7002_A1                        (0xffffffff)

#define  AES_BLK_IV0_OUT1_TNBLE_RESET_VALUE_T7001_A1                        (0x0)
#define  AES_BLK_IV0_OUT1_TNBLE_RESET_VALUE_S7002_A1                        (0x0)

/*! @} reset */

/*! @} iv0_out1 (AES_IV0_OUT1) */

/*! 
 *  @addtogroup group120321 iv0_out2 (AES_IV0_OUT2)
 *  @brief Offset = 0x148
 *  @details AES IV0_OUT[96:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV0_OUT2_OFFSET_V1                                         (0x0 + 0x148)
#define  AES_BLK_IV0_OUT2_OFFSET_V2                                         (0x0 + 0x148)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT2_OFFSET                                            AES_BLK_IV0_OUT2_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT2_OFFSET                                            AES_BLK_IV0_OUT2_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120322 iv_out2
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details IV0_OUT[95:64]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV0_OUT2_IV_OUT2_SHIFT_V1                                  (0)
#define  AES_BLK_IV0_OUT2_IV_OUT2_SHIFT_V2                                  (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT2_IV_OUT2_SHIFT                                     AES_BLK_IV0_OUT2_IV_OUT2_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT2_IV_OUT2_SHIFT                                     AES_BLK_IV0_OUT2_IV_OUT2_SHIFT_V2
#endif

#define  AES_BLK_IV0_OUT2_IV_OUT2_WIDTH_V1                                  (32)
#define  AES_BLK_IV0_OUT2_IV_OUT2_WIDTH_V2                                  (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT2_IV_OUT2_WIDTH                                     AES_BLK_IV0_OUT2_IV_OUT2_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT2_IV_OUT2_WIDTH                                     AES_BLK_IV0_OUT2_IV_OUT2_WIDTH_V2
#endif

#define  AES_BLK_IV0_OUT2_IV_OUT2_UMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV0_OUT2_IV_OUT2_UMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT2_IV_OUT2_UMASK                                     AES_BLK_IV0_OUT2_IV_OUT2_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT2_IV_OUT2_UMASK                                     AES_BLK_IV0_OUT2_IV_OUT2_UMASK_V2
#endif

#define  AES_BLK_IV0_OUT2_IV_OUT2_SMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV0_OUT2_IV_OUT2_SMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT2_IV_OUT2_SMASK                                     AES_BLK_IV0_OUT2_IV_OUT2_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT2_IV_OUT2_SMASK                                     AES_BLK_IV0_OUT2_IV_OUT2_SMASK_V2
#endif

#define  AES_BLK_IV0_OUT2_IV_OUT2_XTRCT_V1(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV0_OUT2_IV_OUT2_XTRCT_V2(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT2_IV_OUT2_XTRCT                                     AES_BLK_IV0_OUT2_IV_OUT2_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT2_IV_OUT2_XTRCT                                     AES_BLK_IV0_OUT2_IV_OUT2_XTRCT_V2
#endif

#define  AES_BLK_IV0_OUT2_IV_OUT2_INSRT_V1(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV0_OUT2_IV_OUT2_INSRT_V2(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT2_IV_OUT2_INSRT                                     AES_BLK_IV0_OUT2_IV_OUT2_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT2_IV_OUT2_INSRT                                     AES_BLK_IV0_OUT2_IV_OUT2_INSRT_V2
#endif

/*! @} iv_out2 */

/*! 
 *  @addtogroup group120323 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV0_OUT2_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)
#define  AES_BLK_IV0_OUT2_TNBLE_RESET_UMASK_S7002_A1                        (0xffffffff)

#define  AES_BLK_IV0_OUT2_TNBLE_RESET_VALUE_T7001_A1                        (0x0)
#define  AES_BLK_IV0_OUT2_TNBLE_RESET_VALUE_S7002_A1                        (0x0)

/*! @} reset */

/*! @} iv0_out2 (AES_IV0_OUT2) */

/*! 
 *  @addtogroup group120324 iv0_out3 (AES_IV0_OUT3)
 *  @brief Offset = 0x14c
 *  @details AES IV0_OUT[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV0_OUT3_OFFSET_V1                                         (0x0 + 0x14c)
#define  AES_BLK_IV0_OUT3_OFFSET_V2                                         (0x0 + 0x14c)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT3_OFFSET                                            AES_BLK_IV0_OUT3_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT3_OFFSET                                            AES_BLK_IV0_OUT3_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120325 iv_out3
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details IV0_OUT[127:96]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV0_OUT3_IV_OUT3_SHIFT_V1                                  (0)
#define  AES_BLK_IV0_OUT3_IV_OUT3_SHIFT_V2                                  (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT3_IV_OUT3_SHIFT                                     AES_BLK_IV0_OUT3_IV_OUT3_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT3_IV_OUT3_SHIFT                                     AES_BLK_IV0_OUT3_IV_OUT3_SHIFT_V2
#endif

#define  AES_BLK_IV0_OUT3_IV_OUT3_WIDTH_V1                                  (32)
#define  AES_BLK_IV0_OUT3_IV_OUT3_WIDTH_V2                                  (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT3_IV_OUT3_WIDTH                                     AES_BLK_IV0_OUT3_IV_OUT3_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT3_IV_OUT3_WIDTH                                     AES_BLK_IV0_OUT3_IV_OUT3_WIDTH_V2
#endif

#define  AES_BLK_IV0_OUT3_IV_OUT3_UMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV0_OUT3_IV_OUT3_UMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT3_IV_OUT3_UMASK                                     AES_BLK_IV0_OUT3_IV_OUT3_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT3_IV_OUT3_UMASK                                     AES_BLK_IV0_OUT3_IV_OUT3_UMASK_V2
#endif

#define  AES_BLK_IV0_OUT3_IV_OUT3_SMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV0_OUT3_IV_OUT3_SMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT3_IV_OUT3_SMASK                                     AES_BLK_IV0_OUT3_IV_OUT3_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT3_IV_OUT3_SMASK                                     AES_BLK_IV0_OUT3_IV_OUT3_SMASK_V2
#endif

#define  AES_BLK_IV0_OUT3_IV_OUT3_XTRCT_V1(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV0_OUT3_IV_OUT3_XTRCT_V2(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT3_IV_OUT3_XTRCT                                     AES_BLK_IV0_OUT3_IV_OUT3_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT3_IV_OUT3_XTRCT                                     AES_BLK_IV0_OUT3_IV_OUT3_XTRCT_V2
#endif

#define  AES_BLK_IV0_OUT3_IV_OUT3_INSRT_V1(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV0_OUT3_IV_OUT3_INSRT_V2(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV0_OUT3_IV_OUT3_INSRT                                     AES_BLK_IV0_OUT3_IV_OUT3_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV0_OUT3_IV_OUT3_INSRT                                     AES_BLK_IV0_OUT3_IV_OUT3_INSRT_V2
#endif

/*! @} iv_out3 */

/*! 
 *  @addtogroup group120326 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV0_OUT3_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)
#define  AES_BLK_IV0_OUT3_TNBLE_RESET_UMASK_S7002_A1                        (0xffffffff)

#define  AES_BLK_IV0_OUT3_TNBLE_RESET_VALUE_T7001_A1                        (0x0)
#define  AES_BLK_IV0_OUT3_TNBLE_RESET_VALUE_S7002_A1                        (0x0)

/*! @} reset */

/*! @} iv0_out3 (AES_IV0_OUT3) */

/*! 
 *  @addtogroup group120327 iv1_out0 (AES_IV1_OUT0)
 *  @brief Offset = 0x150
 *  @details AES IV1_OUT[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV1_OUT0_OFFSET_V1                                         (0x0 + 0x150)
#define  AES_BLK_IV1_OUT0_OFFSET_V2                                         (0x0 + 0x150)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT0_OFFSET                                            AES_BLK_IV1_OUT0_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT0_OFFSET                                            AES_BLK_IV1_OUT0_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120328 iv_out0
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details IV1_OUT[31:0]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV1_OUT0_IV_OUT0_SHIFT_V1                                  (0)
#define  AES_BLK_IV1_OUT0_IV_OUT0_SHIFT_V2                                  (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT0_IV_OUT0_SHIFT                                     AES_BLK_IV1_OUT0_IV_OUT0_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT0_IV_OUT0_SHIFT                                     AES_BLK_IV1_OUT0_IV_OUT0_SHIFT_V2
#endif

#define  AES_BLK_IV1_OUT0_IV_OUT0_WIDTH_V1                                  (32)
#define  AES_BLK_IV1_OUT0_IV_OUT0_WIDTH_V2                                  (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT0_IV_OUT0_WIDTH                                     AES_BLK_IV1_OUT0_IV_OUT0_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT0_IV_OUT0_WIDTH                                     AES_BLK_IV1_OUT0_IV_OUT0_WIDTH_V2
#endif

#define  AES_BLK_IV1_OUT0_IV_OUT0_UMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV1_OUT0_IV_OUT0_UMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT0_IV_OUT0_UMASK                                     AES_BLK_IV1_OUT0_IV_OUT0_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT0_IV_OUT0_UMASK                                     AES_BLK_IV1_OUT0_IV_OUT0_UMASK_V2
#endif

#define  AES_BLK_IV1_OUT0_IV_OUT0_SMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV1_OUT0_IV_OUT0_SMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT0_IV_OUT0_SMASK                                     AES_BLK_IV1_OUT0_IV_OUT0_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT0_IV_OUT0_SMASK                                     AES_BLK_IV1_OUT0_IV_OUT0_SMASK_V2
#endif

#define  AES_BLK_IV1_OUT0_IV_OUT0_XTRCT_V1(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV1_OUT0_IV_OUT0_XTRCT_V2(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT0_IV_OUT0_XTRCT                                     AES_BLK_IV1_OUT0_IV_OUT0_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT0_IV_OUT0_XTRCT                                     AES_BLK_IV1_OUT0_IV_OUT0_XTRCT_V2
#endif

#define  AES_BLK_IV1_OUT0_IV_OUT0_INSRT_V1(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV1_OUT0_IV_OUT0_INSRT_V2(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT0_IV_OUT0_INSRT                                     AES_BLK_IV1_OUT0_IV_OUT0_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT0_IV_OUT0_INSRT                                     AES_BLK_IV1_OUT0_IV_OUT0_INSRT_V2
#endif

/*! @} iv_out0 */

/*! 
 *  @addtogroup group120329 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV1_OUT0_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)
#define  AES_BLK_IV1_OUT0_TNBLE_RESET_UMASK_S7002_A1                        (0xffffffff)

#define  AES_BLK_IV1_OUT0_TNBLE_RESET_VALUE_T7001_A1                        (0x0)
#define  AES_BLK_IV1_OUT0_TNBLE_RESET_VALUE_S7002_A1                        (0x0)

/*! @} reset */

/*! @} iv1_out0 (AES_IV1_OUT0) */

/*! 
 *  @addtogroup group120330 iv1_out1 (AES_IV1_OUT1)
 *  @brief Offset = 0x154
 *  @details AES IV1_OUT[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV1_OUT1_OFFSET_V1                                         (0x0 + 0x154)
#define  AES_BLK_IV1_OUT1_OFFSET_V2                                         (0x0 + 0x154)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT1_OFFSET                                            AES_BLK_IV1_OUT1_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT1_OFFSET                                            AES_BLK_IV1_OUT1_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120331 iv_out1
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details IV1_OUT[63:32]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV1_OUT1_IV_OUT1_SHIFT_V1                                  (0)
#define  AES_BLK_IV1_OUT1_IV_OUT1_SHIFT_V2                                  (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT1_IV_OUT1_SHIFT                                     AES_BLK_IV1_OUT1_IV_OUT1_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT1_IV_OUT1_SHIFT                                     AES_BLK_IV1_OUT1_IV_OUT1_SHIFT_V2
#endif

#define  AES_BLK_IV1_OUT1_IV_OUT1_WIDTH_V1                                  (32)
#define  AES_BLK_IV1_OUT1_IV_OUT1_WIDTH_V2                                  (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT1_IV_OUT1_WIDTH                                     AES_BLK_IV1_OUT1_IV_OUT1_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT1_IV_OUT1_WIDTH                                     AES_BLK_IV1_OUT1_IV_OUT1_WIDTH_V2
#endif

#define  AES_BLK_IV1_OUT1_IV_OUT1_UMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV1_OUT1_IV_OUT1_UMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT1_IV_OUT1_UMASK                                     AES_BLK_IV1_OUT1_IV_OUT1_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT1_IV_OUT1_UMASK                                     AES_BLK_IV1_OUT1_IV_OUT1_UMASK_V2
#endif

#define  AES_BLK_IV1_OUT1_IV_OUT1_SMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV1_OUT1_IV_OUT1_SMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT1_IV_OUT1_SMASK                                     AES_BLK_IV1_OUT1_IV_OUT1_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT1_IV_OUT1_SMASK                                     AES_BLK_IV1_OUT1_IV_OUT1_SMASK_V2
#endif

#define  AES_BLK_IV1_OUT1_IV_OUT1_XTRCT_V1(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV1_OUT1_IV_OUT1_XTRCT_V2(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT1_IV_OUT1_XTRCT                                     AES_BLK_IV1_OUT1_IV_OUT1_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT1_IV_OUT1_XTRCT                                     AES_BLK_IV1_OUT1_IV_OUT1_XTRCT_V2
#endif

#define  AES_BLK_IV1_OUT1_IV_OUT1_INSRT_V1(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV1_OUT1_IV_OUT1_INSRT_V2(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT1_IV_OUT1_INSRT                                     AES_BLK_IV1_OUT1_IV_OUT1_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT1_IV_OUT1_INSRT                                     AES_BLK_IV1_OUT1_IV_OUT1_INSRT_V2
#endif

/*! @} iv_out1 */

/*! 
 *  @addtogroup group120332 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV1_OUT1_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)
#define  AES_BLK_IV1_OUT1_TNBLE_RESET_UMASK_S7002_A1                        (0xffffffff)

#define  AES_BLK_IV1_OUT1_TNBLE_RESET_VALUE_T7001_A1                        (0x0)
#define  AES_BLK_IV1_OUT1_TNBLE_RESET_VALUE_S7002_A1                        (0x0)

/*! @} reset */

/*! @} iv1_out1 (AES_IV1_OUT1) */

/*! 
 *  @addtogroup group120333 iv1_out2 (AES_IV1_OUT2)
 *  @brief Offset = 0x158
 *  @details AES IV1_OUT[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV1_OUT2_OFFSET_V1                                         (0x0 + 0x158)
#define  AES_BLK_IV1_OUT2_OFFSET_V2                                         (0x0 + 0x158)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT2_OFFSET                                            AES_BLK_IV1_OUT2_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT2_OFFSET                                            AES_BLK_IV1_OUT2_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120334 iv_out2
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details IV1_OUT[95:64]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV1_OUT2_IV_OUT2_SHIFT_V1                                  (0)
#define  AES_BLK_IV1_OUT2_IV_OUT2_SHIFT_V2                                  (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT2_IV_OUT2_SHIFT                                     AES_BLK_IV1_OUT2_IV_OUT2_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT2_IV_OUT2_SHIFT                                     AES_BLK_IV1_OUT2_IV_OUT2_SHIFT_V2
#endif

#define  AES_BLK_IV1_OUT2_IV_OUT2_WIDTH_V1                                  (32)
#define  AES_BLK_IV1_OUT2_IV_OUT2_WIDTH_V2                                  (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT2_IV_OUT2_WIDTH                                     AES_BLK_IV1_OUT2_IV_OUT2_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT2_IV_OUT2_WIDTH                                     AES_BLK_IV1_OUT2_IV_OUT2_WIDTH_V2
#endif

#define  AES_BLK_IV1_OUT2_IV_OUT2_UMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV1_OUT2_IV_OUT2_UMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT2_IV_OUT2_UMASK                                     AES_BLK_IV1_OUT2_IV_OUT2_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT2_IV_OUT2_UMASK                                     AES_BLK_IV1_OUT2_IV_OUT2_UMASK_V2
#endif

#define  AES_BLK_IV1_OUT2_IV_OUT2_SMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV1_OUT2_IV_OUT2_SMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT2_IV_OUT2_SMASK                                     AES_BLK_IV1_OUT2_IV_OUT2_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT2_IV_OUT2_SMASK                                     AES_BLK_IV1_OUT2_IV_OUT2_SMASK_V2
#endif

#define  AES_BLK_IV1_OUT2_IV_OUT2_XTRCT_V1(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV1_OUT2_IV_OUT2_XTRCT_V2(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT2_IV_OUT2_XTRCT                                     AES_BLK_IV1_OUT2_IV_OUT2_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT2_IV_OUT2_XTRCT                                     AES_BLK_IV1_OUT2_IV_OUT2_XTRCT_V2
#endif

#define  AES_BLK_IV1_OUT2_IV_OUT2_INSRT_V1(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV1_OUT2_IV_OUT2_INSRT_V2(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT2_IV_OUT2_INSRT                                     AES_BLK_IV1_OUT2_IV_OUT2_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT2_IV_OUT2_INSRT                                     AES_BLK_IV1_OUT2_IV_OUT2_INSRT_V2
#endif

/*! @} iv_out2 */

/*! 
 *  @addtogroup group120335 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV1_OUT2_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)
#define  AES_BLK_IV1_OUT2_TNBLE_RESET_UMASK_S7002_A1                        (0xffffffff)

#define  AES_BLK_IV1_OUT2_TNBLE_RESET_VALUE_T7001_A1                        (0x0)
#define  AES_BLK_IV1_OUT2_TNBLE_RESET_VALUE_S7002_A1                        (0x0)

/*! @} reset */

/*! @} iv1_out2 (AES_IV1_OUT2) */

/*! 
 *  @addtogroup group120336 iv1_out3 (AES_IV1_OUT3)
 *  @brief Offset = 0x15c
 *  @details AES IV1_OUT[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_IV1_OUT3_OFFSET_V1                                         (0x0 + 0x15c)
#define  AES_BLK_IV1_OUT3_OFFSET_V2                                         (0x0 + 0x15c)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT3_OFFSET                                            AES_BLK_IV1_OUT3_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT3_OFFSET                                            AES_BLK_IV1_OUT3_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120337 iv_out3
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details IV1_OUT[127:96]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_IV1_OUT3_IV_OUT3_SHIFT_V1                                  (0)
#define  AES_BLK_IV1_OUT3_IV_OUT3_SHIFT_V2                                  (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT3_IV_OUT3_SHIFT                                     AES_BLK_IV1_OUT3_IV_OUT3_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT3_IV_OUT3_SHIFT                                     AES_BLK_IV1_OUT3_IV_OUT3_SHIFT_V2
#endif

#define  AES_BLK_IV1_OUT3_IV_OUT3_WIDTH_V1                                  (32)
#define  AES_BLK_IV1_OUT3_IV_OUT3_WIDTH_V2                                  (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT3_IV_OUT3_WIDTH                                     AES_BLK_IV1_OUT3_IV_OUT3_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT3_IV_OUT3_WIDTH                                     AES_BLK_IV1_OUT3_IV_OUT3_WIDTH_V2
#endif

#define  AES_BLK_IV1_OUT3_IV_OUT3_UMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV1_OUT3_IV_OUT3_UMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT3_IV_OUT3_UMASK                                     AES_BLK_IV1_OUT3_IV_OUT3_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT3_IV_OUT3_UMASK                                     AES_BLK_IV1_OUT3_IV_OUT3_UMASK_V2
#endif

#define  AES_BLK_IV1_OUT3_IV_OUT3_SMASK_V1                                  (0xffffffff)
#define  AES_BLK_IV1_OUT3_IV_OUT3_SMASK_V2                                  (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT3_IV_OUT3_SMASK                                     AES_BLK_IV1_OUT3_IV_OUT3_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT3_IV_OUT3_SMASK                                     AES_BLK_IV1_OUT3_IV_OUT3_SMASK_V2
#endif

#define  AES_BLK_IV1_OUT3_IV_OUT3_XTRCT_V1(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_IV1_OUT3_IV_OUT3_XTRCT_V2(r)                               ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT3_IV_OUT3_XTRCT                                     AES_BLK_IV1_OUT3_IV_OUT3_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT3_IV_OUT3_XTRCT                                     AES_BLK_IV1_OUT3_IV_OUT3_XTRCT_V2
#endif

#define  AES_BLK_IV1_OUT3_IV_OUT3_INSRT_V1(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_IV1_OUT3_IV_OUT3_INSRT_V2(f)                               ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_IV1_OUT3_IV_OUT3_INSRT                                     AES_BLK_IV1_OUT3_IV_OUT3_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_IV1_OUT3_IV_OUT3_INSRT                                     AES_BLK_IV1_OUT3_IV_OUT3_INSRT_V2
#endif

/*! @} iv_out3 */

/*! 
 *  @addtogroup group120338 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_IV1_OUT3_TNBLE_RESET_UMASK_T7001_A1                        (0xffffffff)
#define  AES_BLK_IV1_OUT3_TNBLE_RESET_UMASK_S7002_A1                        (0xffffffff)

#define  AES_BLK_IV1_OUT3_TNBLE_RESET_VALUE_T7001_A1                        (0x0)
#define  AES_BLK_IV1_OUT3_TNBLE_RESET_VALUE_S7002_A1                        (0x0)

/*! @} reset */

/*! @} iv1_out3 (AES_IV1_OUT3) */

/*! 
 *  @addtogroup group120339 skg_key_cnt_in (AES_SKG_KEY_CNT_IN)
 *  @brief Offset = 0x160
 *  @details AES SKG_KEY_CNT_IN Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_SKG_KEY_CNT_IN_OFFSET_V1                                   (0x0 + 0x160)
#define  AES_BLK_SKG_KEY_CNT_IN_OFFSET_V2                                   (0x0 + 0x160)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_IN_OFFSET                                      AES_BLK_SKG_KEY_CNT_IN_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_IN_OFFSET                                      AES_BLK_SKG_KEY_CNT_IN_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120340 fld (skg_key_cnt_in)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details This register specifies the number of AES operations
 *  (skg_key_cnt_in+1) that are performed by legacy SKG unwrap logic.  This
 *  field can also be used to abort SKG operations by writing 0 to this register
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_SKG_KEY_CNT_IN_FLD_SHIFT_V1                                (0)
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_SHIFT_V2                                (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_SHIFT                                   AES_BLK_SKG_KEY_CNT_IN_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_SHIFT                                   AES_BLK_SKG_KEY_CNT_IN_FLD_SHIFT_V2
#endif

#define  AES_BLK_SKG_KEY_CNT_IN_FLD_WIDTH_V1                                (32)
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_WIDTH_V2                                (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_WIDTH                                   AES_BLK_SKG_KEY_CNT_IN_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_WIDTH                                   AES_BLK_SKG_KEY_CNT_IN_FLD_WIDTH_V2
#endif

#define  AES_BLK_SKG_KEY_CNT_IN_FLD_UMASK_V1                                (0xffffffff)
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_UMASK_V2                                (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_UMASK                                   AES_BLK_SKG_KEY_CNT_IN_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_UMASK                                   AES_BLK_SKG_KEY_CNT_IN_FLD_UMASK_V2
#endif

#define  AES_BLK_SKG_KEY_CNT_IN_FLD_SMASK_V1                                (0xffffffff)
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_SMASK_V2                                (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_SMASK                                   AES_BLK_SKG_KEY_CNT_IN_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_SMASK                                   AES_BLK_SKG_KEY_CNT_IN_FLD_SMASK_V2
#endif

#define  AES_BLK_SKG_KEY_CNT_IN_FLD_XTRCT_V1(r)                             ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_XTRCT_V2(r)                             ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_XTRCT                                   AES_BLK_SKG_KEY_CNT_IN_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_XTRCT                                   AES_BLK_SKG_KEY_CNT_IN_FLD_XTRCT_V2
#endif

#define  AES_BLK_SKG_KEY_CNT_IN_FLD_INSRT_V1(f)                             ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_INSRT_V2(f)                             ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_INSRT                                   AES_BLK_SKG_KEY_CNT_IN_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_IN_FLD_INSRT                                   AES_BLK_SKG_KEY_CNT_IN_FLD_INSRT_V2
#endif

/*! @} fld (skg_key_cnt_in) */

/*! 
 *  @addtogroup group120341 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_SKG_KEY_CNT_IN_TNBLE_RESET_UMASK_T7001_A1                  (0xffffffff)
#define  AES_BLK_SKG_KEY_CNT_IN_TNBLE_RESET_UMASK_S7002_A1                  (0xffffffff)

#define  AES_BLK_SKG_KEY_CNT_IN_TNBLE_RESET_VALUE_T7001_A1                  (0x0)
#define  AES_BLK_SKG_KEY_CNT_IN_TNBLE_RESET_VALUE_S7002_A1                  (0x0)

/*! @} reset */

/*! @} skg_key_cnt_in (AES_SKG_KEY_CNT_IN) */

/*! 
 *  @addtogroup group120342 skg_key_cnt_out (AES_SKG_KEY_CNT_OUT)
 *  @brief Offset = 0x164
 *  @details AES SKG_KEY_CNT_OUT Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_SKG_KEY_CNT_OUT_OFFSET_V1                                  (0x0 + 0x164)
#define  AES_BLK_SKG_KEY_CNT_OUT_OFFSET_V2                                  (0x0 + 0x164)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_OUT_OFFSET                                     AES_BLK_SKG_KEY_CNT_OUT_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_OUT_OFFSET                                     AES_BLK_SKG_KEY_CNT_OUT_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120343 skg_key_cnt
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details This register specifies the number of AES operations that have
 *  been performed during legacy SKG unwrap.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SHIFT_V1                       (0)
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SHIFT_V2                       (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SHIFT                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SHIFT                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SHIFT_V2
#endif

#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_WIDTH_V1                       (32)
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_WIDTH_V2                       (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_WIDTH                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_WIDTH                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_WIDTH_V2
#endif

#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_UMASK_V1                       (0xffffffff)
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_UMASK_V2                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_UMASK                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_UMASK                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_UMASK_V2
#endif

#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SMASK_V1                       (0xffffffff)
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SMASK_V2                       (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SMASK                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SMASK                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_SMASK_V2
#endif

#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_XTRCT_V1(r)                    ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_XTRCT_V2(r)                    ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_XTRCT                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_XTRCT                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_XTRCT_V2
#endif

#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_INSRT_V1(f)                    ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_INSRT_V2(f)                    ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_INSRT                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_INSRT                          AES_BLK_SKG_KEY_CNT_OUT_SKG_KEY_CNT_INSRT_V2
#endif

/*! @} skg_key_cnt */

/*! 
 *  @addtogroup group120344 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_SKG_KEY_CNT_OUT_TNBLE_RESET_UMASK_T7001_A1                 (0xffffffff)
#define  AES_BLK_SKG_KEY_CNT_OUT_TNBLE_RESET_UMASK_S7002_A1                 (0xffffffff)

#define  AES_BLK_SKG_KEY_CNT_OUT_TNBLE_RESET_VALUE_T7001_A1                 (0x0)
#define  AES_BLK_SKG_KEY_CNT_OUT_TNBLE_RESET_VALUE_S7002_A1                 (0x0)

/*! @} reset */

/*! @} skg_key_cnt_out (AES_SKG_KEY_CNT_OUT) */

/*! 
 *  @addtogroup group120345 dsb_r1_in0 (AES_DSB_R1_IN0)
 *  @brief Offset = 0x180
 *  @details AES DSB_R1_IN[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_DSB_R1_IN0_OFFSET_V1                                       (0x0 + 0x180)
#define  AES_BLK_DSB_R1_IN0_OFFSET_V2                                       (0x0 + 0x180)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN0_OFFSET                                          AES_BLK_DSB_R1_IN0_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN0_OFFSET                                          AES_BLK_DSB_R1_IN0_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120346 fld (dsb_r1_in0)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details DSB_R1_IN[31:0]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DSB_R1_IN0_FLD_SHIFT_V1                                    (0)
#define  AES_BLK_DSB_R1_IN0_FLD_SHIFT_V2                                    (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN0_FLD_SHIFT                                       AES_BLK_DSB_R1_IN0_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN0_FLD_SHIFT                                       AES_BLK_DSB_R1_IN0_FLD_SHIFT_V2
#endif

#define  AES_BLK_DSB_R1_IN0_FLD_WIDTH_V1                                    (32)
#define  AES_BLK_DSB_R1_IN0_FLD_WIDTH_V2                                    (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN0_FLD_WIDTH                                       AES_BLK_DSB_R1_IN0_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN0_FLD_WIDTH                                       AES_BLK_DSB_R1_IN0_FLD_WIDTH_V2
#endif

#define  AES_BLK_DSB_R1_IN0_FLD_UMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R1_IN0_FLD_UMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN0_FLD_UMASK                                       AES_BLK_DSB_R1_IN0_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN0_FLD_UMASK                                       AES_BLK_DSB_R1_IN0_FLD_UMASK_V2
#endif

#define  AES_BLK_DSB_R1_IN0_FLD_SMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R1_IN0_FLD_SMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN0_FLD_SMASK                                       AES_BLK_DSB_R1_IN0_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN0_FLD_SMASK                                       AES_BLK_DSB_R1_IN0_FLD_SMASK_V2
#endif

#define  AES_BLK_DSB_R1_IN0_FLD_XTRCT_V1(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_DSB_R1_IN0_FLD_XTRCT_V2(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN0_FLD_XTRCT                                       AES_BLK_DSB_R1_IN0_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN0_FLD_XTRCT                                       AES_BLK_DSB_R1_IN0_FLD_XTRCT_V2
#endif

#define  AES_BLK_DSB_R1_IN0_FLD_INSRT_V1(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_DSB_R1_IN0_FLD_INSRT_V2(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN0_FLD_INSRT                                       AES_BLK_DSB_R1_IN0_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN0_FLD_INSRT                                       AES_BLK_DSB_R1_IN0_FLD_INSRT_V2
#endif

/*! @} fld (dsb_r1_in0) */

/*! 
 *  @addtogroup group120347 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_DSB_R1_IN0_TNBLE_RESET_UMASK_T7001_A1                      (0xffffffff)
#define  AES_BLK_DSB_R1_IN0_TNBLE_RESET_UMASK_S7002_A1                      (0xffffffff)

#define  AES_BLK_DSB_R1_IN0_TNBLE_RESET_VALUE_T7001_A1                      (0x0)
#define  AES_BLK_DSB_R1_IN0_TNBLE_RESET_VALUE_S7002_A1                      (0x0)

/*! @} reset */

/*! @} dsb_r1_in0 (AES_DSB_R1_IN0) */

/*! 
 *  @addtogroup group120348 dsb_r1_in1 (AES_DSB_R1_IN1)
 *  @brief Offset = 0x184
 *  @details AES DSB_R1_IN[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_DSB_R1_IN1_OFFSET_V1                                       (0x0 + 0x184)
#define  AES_BLK_DSB_R1_IN1_OFFSET_V2                                       (0x0 + 0x184)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN1_OFFSET                                          AES_BLK_DSB_R1_IN1_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN1_OFFSET                                          AES_BLK_DSB_R1_IN1_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120349 fld (dsb_r1_in1)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details DSB_R1_IN[63:32]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DSB_R1_IN1_FLD_SHIFT_V1                                    (0)
#define  AES_BLK_DSB_R1_IN1_FLD_SHIFT_V2                                    (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN1_FLD_SHIFT                                       AES_BLK_DSB_R1_IN1_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN1_FLD_SHIFT                                       AES_BLK_DSB_R1_IN1_FLD_SHIFT_V2
#endif

#define  AES_BLK_DSB_R1_IN1_FLD_WIDTH_V1                                    (32)
#define  AES_BLK_DSB_R1_IN1_FLD_WIDTH_V2                                    (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN1_FLD_WIDTH                                       AES_BLK_DSB_R1_IN1_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN1_FLD_WIDTH                                       AES_BLK_DSB_R1_IN1_FLD_WIDTH_V2
#endif

#define  AES_BLK_DSB_R1_IN1_FLD_UMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R1_IN1_FLD_UMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN1_FLD_UMASK                                       AES_BLK_DSB_R1_IN1_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN1_FLD_UMASK                                       AES_BLK_DSB_R1_IN1_FLD_UMASK_V2
#endif

#define  AES_BLK_DSB_R1_IN1_FLD_SMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R1_IN1_FLD_SMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN1_FLD_SMASK                                       AES_BLK_DSB_R1_IN1_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN1_FLD_SMASK                                       AES_BLK_DSB_R1_IN1_FLD_SMASK_V2
#endif

#define  AES_BLK_DSB_R1_IN1_FLD_XTRCT_V1(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_DSB_R1_IN1_FLD_XTRCT_V2(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN1_FLD_XTRCT                                       AES_BLK_DSB_R1_IN1_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN1_FLD_XTRCT                                       AES_BLK_DSB_R1_IN1_FLD_XTRCT_V2
#endif

#define  AES_BLK_DSB_R1_IN1_FLD_INSRT_V1(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_DSB_R1_IN1_FLD_INSRT_V2(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN1_FLD_INSRT                                       AES_BLK_DSB_R1_IN1_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN1_FLD_INSRT                                       AES_BLK_DSB_R1_IN1_FLD_INSRT_V2
#endif

/*! @} fld (dsb_r1_in1) */

/*! 
 *  @addtogroup group120350 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_DSB_R1_IN1_TNBLE_RESET_UMASK_T7001_A1                      (0xffffffff)
#define  AES_BLK_DSB_R1_IN1_TNBLE_RESET_UMASK_S7002_A1                      (0xffffffff)

#define  AES_BLK_DSB_R1_IN1_TNBLE_RESET_VALUE_T7001_A1                      (0x0)
#define  AES_BLK_DSB_R1_IN1_TNBLE_RESET_VALUE_S7002_A1                      (0x0)

/*! @} reset */

/*! @} dsb_r1_in1 (AES_DSB_R1_IN1) */

/*! 
 *  @addtogroup group120351 dsb_r1_in2 (AES_DSB_R1_IN2)
 *  @brief Offset = 0x188
 *  @details AES DSB_R1_IN[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_DSB_R1_IN2_OFFSET_V1                                       (0x0 + 0x188)
#define  AES_BLK_DSB_R1_IN2_OFFSET_V2                                       (0x0 + 0x188)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN2_OFFSET                                          AES_BLK_DSB_R1_IN2_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN2_OFFSET                                          AES_BLK_DSB_R1_IN2_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120352 fld (dsb_r1_in2)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details DSB_R1_IN[95:64]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DSB_R1_IN2_FLD_SHIFT_V1                                    (0)
#define  AES_BLK_DSB_R1_IN2_FLD_SHIFT_V2                                    (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN2_FLD_SHIFT                                       AES_BLK_DSB_R1_IN2_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN2_FLD_SHIFT                                       AES_BLK_DSB_R1_IN2_FLD_SHIFT_V2
#endif

#define  AES_BLK_DSB_R1_IN2_FLD_WIDTH_V1                                    (32)
#define  AES_BLK_DSB_R1_IN2_FLD_WIDTH_V2                                    (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN2_FLD_WIDTH                                       AES_BLK_DSB_R1_IN2_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN2_FLD_WIDTH                                       AES_BLK_DSB_R1_IN2_FLD_WIDTH_V2
#endif

#define  AES_BLK_DSB_R1_IN2_FLD_UMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R1_IN2_FLD_UMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN2_FLD_UMASK                                       AES_BLK_DSB_R1_IN2_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN2_FLD_UMASK                                       AES_BLK_DSB_R1_IN2_FLD_UMASK_V2
#endif

#define  AES_BLK_DSB_R1_IN2_FLD_SMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R1_IN2_FLD_SMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN2_FLD_SMASK                                       AES_BLK_DSB_R1_IN2_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN2_FLD_SMASK                                       AES_BLK_DSB_R1_IN2_FLD_SMASK_V2
#endif

#define  AES_BLK_DSB_R1_IN2_FLD_XTRCT_V1(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_DSB_R1_IN2_FLD_XTRCT_V2(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN2_FLD_XTRCT                                       AES_BLK_DSB_R1_IN2_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN2_FLD_XTRCT                                       AES_BLK_DSB_R1_IN2_FLD_XTRCT_V2
#endif

#define  AES_BLK_DSB_R1_IN2_FLD_INSRT_V1(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_DSB_R1_IN2_FLD_INSRT_V2(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN2_FLD_INSRT                                       AES_BLK_DSB_R1_IN2_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN2_FLD_INSRT                                       AES_BLK_DSB_R1_IN2_FLD_INSRT_V2
#endif

/*! @} fld (dsb_r1_in2) */

/*! 
 *  @addtogroup group120353 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_DSB_R1_IN2_TNBLE_RESET_UMASK_T7001_A1                      (0xffffffff)
#define  AES_BLK_DSB_R1_IN2_TNBLE_RESET_UMASK_S7002_A1                      (0xffffffff)

#define  AES_BLK_DSB_R1_IN2_TNBLE_RESET_VALUE_T7001_A1                      (0x0)
#define  AES_BLK_DSB_R1_IN2_TNBLE_RESET_VALUE_S7002_A1                      (0x0)

/*! @} reset */

/*! @} dsb_r1_in2 (AES_DSB_R1_IN2) */

/*! 
 *  @addtogroup group120354 dsb_r1_in3 (AES_DSB_R1_IN3)
 *  @brief Offset = 0x18c
 *  @details AES DSB_R1_IN[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_DSB_R1_IN3_OFFSET_V1                                       (0x0 + 0x18c)
#define  AES_BLK_DSB_R1_IN3_OFFSET_V2                                       (0x0 + 0x18c)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN3_OFFSET                                          AES_BLK_DSB_R1_IN3_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN3_OFFSET                                          AES_BLK_DSB_R1_IN3_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120355 fld (dsb_r1_in3)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details DSB_R1_IN[127:96]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DSB_R1_IN3_FLD_SHIFT_V1                                    (0)
#define  AES_BLK_DSB_R1_IN3_FLD_SHIFT_V2                                    (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN3_FLD_SHIFT                                       AES_BLK_DSB_R1_IN3_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN3_FLD_SHIFT                                       AES_BLK_DSB_R1_IN3_FLD_SHIFT_V2
#endif

#define  AES_BLK_DSB_R1_IN3_FLD_WIDTH_V1                                    (32)
#define  AES_BLK_DSB_R1_IN3_FLD_WIDTH_V2                                    (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN3_FLD_WIDTH                                       AES_BLK_DSB_R1_IN3_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN3_FLD_WIDTH                                       AES_BLK_DSB_R1_IN3_FLD_WIDTH_V2
#endif

#define  AES_BLK_DSB_R1_IN3_FLD_UMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R1_IN3_FLD_UMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN3_FLD_UMASK                                       AES_BLK_DSB_R1_IN3_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN3_FLD_UMASK                                       AES_BLK_DSB_R1_IN3_FLD_UMASK_V2
#endif

#define  AES_BLK_DSB_R1_IN3_FLD_SMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R1_IN3_FLD_SMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN3_FLD_SMASK                                       AES_BLK_DSB_R1_IN3_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN3_FLD_SMASK                                       AES_BLK_DSB_R1_IN3_FLD_SMASK_V2
#endif

#define  AES_BLK_DSB_R1_IN3_FLD_XTRCT_V1(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_DSB_R1_IN3_FLD_XTRCT_V2(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN3_FLD_XTRCT                                       AES_BLK_DSB_R1_IN3_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN3_FLD_XTRCT                                       AES_BLK_DSB_R1_IN3_FLD_XTRCT_V2
#endif

#define  AES_BLK_DSB_R1_IN3_FLD_INSRT_V1(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_DSB_R1_IN3_FLD_INSRT_V2(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R1_IN3_FLD_INSRT                                       AES_BLK_DSB_R1_IN3_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R1_IN3_FLD_INSRT                                       AES_BLK_DSB_R1_IN3_FLD_INSRT_V2
#endif

/*! @} fld (dsb_r1_in3) */

/*! 
 *  @addtogroup group120356 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_DSB_R1_IN3_TNBLE_RESET_UMASK_T7001_A1                      (0xffffffff)
#define  AES_BLK_DSB_R1_IN3_TNBLE_RESET_UMASK_S7002_A1                      (0xffffffff)

#define  AES_BLK_DSB_R1_IN3_TNBLE_RESET_VALUE_T7001_A1                      (0x0)
#define  AES_BLK_DSB_R1_IN3_TNBLE_RESET_VALUE_S7002_A1                      (0x0)

/*! @} reset */

/*! @} dsb_r1_in3 (AES_DSB_R1_IN3) */

/*! 
 *  @addtogroup group120357 dsb_r2_in0 (AES_DSB_R2_IN0)
 *  @brief Offset = 0x1c0
 *  @details AES DSB_R2_IN[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_DSB_R2_IN0_OFFSET_V1                                       (0x0 + 0x1c0)
#define  AES_BLK_DSB_R2_IN0_OFFSET_V2                                       (0x0 + 0x1c0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN0_OFFSET                                          AES_BLK_DSB_R2_IN0_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN0_OFFSET                                          AES_BLK_DSB_R2_IN0_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120358 fld (dsb_r2_in0)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details DSB_R2_IN[31:0]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DSB_R2_IN0_FLD_SHIFT_V1                                    (0)
#define  AES_BLK_DSB_R2_IN0_FLD_SHIFT_V2                                    (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN0_FLD_SHIFT                                       AES_BLK_DSB_R2_IN0_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN0_FLD_SHIFT                                       AES_BLK_DSB_R2_IN0_FLD_SHIFT_V2
#endif

#define  AES_BLK_DSB_R2_IN0_FLD_WIDTH_V1                                    (32)
#define  AES_BLK_DSB_R2_IN0_FLD_WIDTH_V2                                    (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN0_FLD_WIDTH                                       AES_BLK_DSB_R2_IN0_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN0_FLD_WIDTH                                       AES_BLK_DSB_R2_IN0_FLD_WIDTH_V2
#endif

#define  AES_BLK_DSB_R2_IN0_FLD_UMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R2_IN0_FLD_UMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN0_FLD_UMASK                                       AES_BLK_DSB_R2_IN0_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN0_FLD_UMASK                                       AES_BLK_DSB_R2_IN0_FLD_UMASK_V2
#endif

#define  AES_BLK_DSB_R2_IN0_FLD_SMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R2_IN0_FLD_SMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN0_FLD_SMASK                                       AES_BLK_DSB_R2_IN0_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN0_FLD_SMASK                                       AES_BLK_DSB_R2_IN0_FLD_SMASK_V2
#endif

#define  AES_BLK_DSB_R2_IN0_FLD_XTRCT_V1(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_DSB_R2_IN0_FLD_XTRCT_V2(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN0_FLD_XTRCT                                       AES_BLK_DSB_R2_IN0_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN0_FLD_XTRCT                                       AES_BLK_DSB_R2_IN0_FLD_XTRCT_V2
#endif

#define  AES_BLK_DSB_R2_IN0_FLD_INSRT_V1(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_DSB_R2_IN0_FLD_INSRT_V2(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN0_FLD_INSRT                                       AES_BLK_DSB_R2_IN0_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN0_FLD_INSRT                                       AES_BLK_DSB_R2_IN0_FLD_INSRT_V2
#endif

/*! @} fld (dsb_r2_in0) */

/*! 
 *  @addtogroup group120359 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_DSB_R2_IN0_TNBLE_RESET_UMASK_T7001_A1                      (0xffffffff)
#define  AES_BLK_DSB_R2_IN0_TNBLE_RESET_UMASK_S7002_A1                      (0xffffffff)

#define  AES_BLK_DSB_R2_IN0_TNBLE_RESET_VALUE_T7001_A1                      (0x0)
#define  AES_BLK_DSB_R2_IN0_TNBLE_RESET_VALUE_S7002_A1                      (0x0)

/*! @} reset */

/*! @} dsb_r2_in0 (AES_DSB_R2_IN0) */

/*! 
 *  @addtogroup group120360 dsb_r2_in1 (AES_DSB_R2_IN1)
 *  @brief Offset = 0x1c4
 *  @details AES DSB_R2_IN[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_DSB_R2_IN1_OFFSET_V1                                       (0x0 + 0x1c4)
#define  AES_BLK_DSB_R2_IN1_OFFSET_V2                                       (0x0 + 0x1c4)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN1_OFFSET                                          AES_BLK_DSB_R2_IN1_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN1_OFFSET                                          AES_BLK_DSB_R2_IN1_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120361 fld (dsb_r2_in1)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details DSB_R2_IN[63:32]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DSB_R2_IN1_FLD_SHIFT_V1                                    (0)
#define  AES_BLK_DSB_R2_IN1_FLD_SHIFT_V2                                    (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN1_FLD_SHIFT                                       AES_BLK_DSB_R2_IN1_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN1_FLD_SHIFT                                       AES_BLK_DSB_R2_IN1_FLD_SHIFT_V2
#endif

#define  AES_BLK_DSB_R2_IN1_FLD_WIDTH_V1                                    (32)
#define  AES_BLK_DSB_R2_IN1_FLD_WIDTH_V2                                    (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN1_FLD_WIDTH                                       AES_BLK_DSB_R2_IN1_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN1_FLD_WIDTH                                       AES_BLK_DSB_R2_IN1_FLD_WIDTH_V2
#endif

#define  AES_BLK_DSB_R2_IN1_FLD_UMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R2_IN1_FLD_UMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN1_FLD_UMASK                                       AES_BLK_DSB_R2_IN1_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN1_FLD_UMASK                                       AES_BLK_DSB_R2_IN1_FLD_UMASK_V2
#endif

#define  AES_BLK_DSB_R2_IN1_FLD_SMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R2_IN1_FLD_SMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN1_FLD_SMASK                                       AES_BLK_DSB_R2_IN1_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN1_FLD_SMASK                                       AES_BLK_DSB_R2_IN1_FLD_SMASK_V2
#endif

#define  AES_BLK_DSB_R2_IN1_FLD_XTRCT_V1(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_DSB_R2_IN1_FLD_XTRCT_V2(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN1_FLD_XTRCT                                       AES_BLK_DSB_R2_IN1_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN1_FLD_XTRCT                                       AES_BLK_DSB_R2_IN1_FLD_XTRCT_V2
#endif

#define  AES_BLK_DSB_R2_IN1_FLD_INSRT_V1(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_DSB_R2_IN1_FLD_INSRT_V2(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN1_FLD_INSRT                                       AES_BLK_DSB_R2_IN1_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN1_FLD_INSRT                                       AES_BLK_DSB_R2_IN1_FLD_INSRT_V2
#endif

/*! @} fld (dsb_r2_in1) */

/*! 
 *  @addtogroup group120362 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_DSB_R2_IN1_TNBLE_RESET_UMASK_T7001_A1                      (0xffffffff)
#define  AES_BLK_DSB_R2_IN1_TNBLE_RESET_UMASK_S7002_A1                      (0xffffffff)

#define  AES_BLK_DSB_R2_IN1_TNBLE_RESET_VALUE_T7001_A1                      (0x0)
#define  AES_BLK_DSB_R2_IN1_TNBLE_RESET_VALUE_S7002_A1                      (0x0)

/*! @} reset */

/*! @} dsb_r2_in1 (AES_DSB_R2_IN1) */

/*! 
 *  @addtogroup group120363 dsb_r2_in2 (AES_DSB_R2_IN2)
 *  @brief Offset = 0x1c8
 *  @details AES DSB_R2_IN[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_DSB_R2_IN2_OFFSET_V1                                       (0x0 + 0x1c8)
#define  AES_BLK_DSB_R2_IN2_OFFSET_V2                                       (0x0 + 0x1c8)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN2_OFFSET                                          AES_BLK_DSB_R2_IN2_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN2_OFFSET                                          AES_BLK_DSB_R2_IN2_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120364 fld (dsb_r2_in2)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details DSB_R2_IN[95:64]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DSB_R2_IN2_FLD_SHIFT_V1                                    (0)
#define  AES_BLK_DSB_R2_IN2_FLD_SHIFT_V2                                    (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN2_FLD_SHIFT                                       AES_BLK_DSB_R2_IN2_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN2_FLD_SHIFT                                       AES_BLK_DSB_R2_IN2_FLD_SHIFT_V2
#endif

#define  AES_BLK_DSB_R2_IN2_FLD_WIDTH_V1                                    (32)
#define  AES_BLK_DSB_R2_IN2_FLD_WIDTH_V2                                    (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN2_FLD_WIDTH                                       AES_BLK_DSB_R2_IN2_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN2_FLD_WIDTH                                       AES_BLK_DSB_R2_IN2_FLD_WIDTH_V2
#endif

#define  AES_BLK_DSB_R2_IN2_FLD_UMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R2_IN2_FLD_UMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN2_FLD_UMASK                                       AES_BLK_DSB_R2_IN2_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN2_FLD_UMASK                                       AES_BLK_DSB_R2_IN2_FLD_UMASK_V2
#endif

#define  AES_BLK_DSB_R2_IN2_FLD_SMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R2_IN2_FLD_SMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN2_FLD_SMASK                                       AES_BLK_DSB_R2_IN2_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN2_FLD_SMASK                                       AES_BLK_DSB_R2_IN2_FLD_SMASK_V2
#endif

#define  AES_BLK_DSB_R2_IN2_FLD_XTRCT_V1(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_DSB_R2_IN2_FLD_XTRCT_V2(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN2_FLD_XTRCT                                       AES_BLK_DSB_R2_IN2_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN2_FLD_XTRCT                                       AES_BLK_DSB_R2_IN2_FLD_XTRCT_V2
#endif

#define  AES_BLK_DSB_R2_IN2_FLD_INSRT_V1(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_DSB_R2_IN2_FLD_INSRT_V2(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN2_FLD_INSRT                                       AES_BLK_DSB_R2_IN2_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN2_FLD_INSRT                                       AES_BLK_DSB_R2_IN2_FLD_INSRT_V2
#endif

/*! @} fld (dsb_r2_in2) */

/*! 
 *  @addtogroup group120365 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_DSB_R2_IN2_TNBLE_RESET_UMASK_T7001_A1                      (0xffffffff)
#define  AES_BLK_DSB_R2_IN2_TNBLE_RESET_UMASK_S7002_A1                      (0xffffffff)

#define  AES_BLK_DSB_R2_IN2_TNBLE_RESET_VALUE_T7001_A1                      (0x0)
#define  AES_BLK_DSB_R2_IN2_TNBLE_RESET_VALUE_S7002_A1                      (0x0)

/*! @} reset */

/*! @} dsb_r2_in2 (AES_DSB_R2_IN2) */

/*! 
 *  @addtogroup group120366 dsb_r2_in3 (AES_DSB_R2_IN3)
 *  @brief Offset = 0x1cc
 *  @details AES DSB_R2_IN[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_DSB_R2_IN3_OFFSET_V1                                       (0x0 + 0x1cc)
#define  AES_BLK_DSB_R2_IN3_OFFSET_V2                                       (0x0 + 0x1cc)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN3_OFFSET                                          AES_BLK_DSB_R2_IN3_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN3_OFFSET                                          AES_BLK_DSB_R2_IN3_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120367 fld (dsb_r2_in3)
 *  @brief Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0
 *  @details DSB_R2_IN[127:96]
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_DSB_R2_IN3_FLD_SHIFT_V1                                    (0)
#define  AES_BLK_DSB_R2_IN3_FLD_SHIFT_V2                                    (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN3_FLD_SHIFT                                       AES_BLK_DSB_R2_IN3_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN3_FLD_SHIFT                                       AES_BLK_DSB_R2_IN3_FLD_SHIFT_V2
#endif

#define  AES_BLK_DSB_R2_IN3_FLD_WIDTH_V1                                    (32)
#define  AES_BLK_DSB_R2_IN3_FLD_WIDTH_V2                                    (32)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN3_FLD_WIDTH                                       AES_BLK_DSB_R2_IN3_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN3_FLD_WIDTH                                       AES_BLK_DSB_R2_IN3_FLD_WIDTH_V2
#endif

#define  AES_BLK_DSB_R2_IN3_FLD_UMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R2_IN3_FLD_UMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN3_FLD_UMASK                                       AES_BLK_DSB_R2_IN3_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN3_FLD_UMASK                                       AES_BLK_DSB_R2_IN3_FLD_UMASK_V2
#endif

#define  AES_BLK_DSB_R2_IN3_FLD_SMASK_V1                                    (0xffffffff)
#define  AES_BLK_DSB_R2_IN3_FLD_SMASK_V2                                    (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN3_FLD_SMASK                                       AES_BLK_DSB_R2_IN3_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN3_FLD_SMASK                                       AES_BLK_DSB_R2_IN3_FLD_SMASK_V2
#endif

#define  AES_BLK_DSB_R2_IN3_FLD_XTRCT_V1(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#define  AES_BLK_DSB_R2_IN3_FLD_XTRCT_V2(r)                                 ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN3_FLD_XTRCT                                       AES_BLK_DSB_R2_IN3_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN3_FLD_XTRCT                                       AES_BLK_DSB_R2_IN3_FLD_XTRCT_V2
#endif

#define  AES_BLK_DSB_R2_IN3_FLD_INSRT_V1(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#define  AES_BLK_DSB_R2_IN3_FLD_INSRT_V2(f)                                 ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_DSB_R2_IN3_FLD_INSRT                                       AES_BLK_DSB_R2_IN3_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_DSB_R2_IN3_FLD_INSRT                                       AES_BLK_DSB_R2_IN3_FLD_INSRT_V2
#endif

/*! @} fld (dsb_r2_in3) */

/*! 
 *  @addtogroup group120368 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_DSB_R2_IN3_TNBLE_RESET_UMASK_T7001_A1                      (0xffffffff)
#define  AES_BLK_DSB_R2_IN3_TNBLE_RESET_UMASK_S7002_A1                      (0xffffffff)

#define  AES_BLK_DSB_R2_IN3_TNBLE_RESET_VALUE_T7001_A1                      (0x0)
#define  AES_BLK_DSB_R2_IN3_TNBLE_RESET_VALUE_S7002_A1                      (0x0)

/*! @} reset */

/*! @} dsb_r2_in3 (AES_DSB_R2_IN3) */

/*! 
 *  @addtogroup group120369 err (AES_ERR)
 *  @brief Offset = 0x1d0
 *  @details AES Error Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_ERR_OFFSET_V1                                              (0x0 + 0x1d0)
#define  AES_BLK_ERR_OFFSET_V2                                              (0x0 + 0x1d0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_ERR_OFFSET                                                 AES_BLK_ERR_OFFSET_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_ERR_OFFSET                                                 AES_BLK_ERR_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120370 fld (aes_err)
 *  @brief Range = 0 | Width = 1 | Access = read-only | Default = 0x0
 *  @details If the GID0, GID1, UID1, UID2, or Fairplay key descrambler is
 *  selected for use when disabled, then the error bit is set.  The error bit
 *  is sticky and is only cleared on a reset.
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_ERR_FLD_SHIFT_V1                                           (0)
#define  AES_BLK_ERR_FLD_SHIFT_V2                                           (0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_ERR_FLD_SHIFT                                              AES_BLK_ERR_FLD_SHIFT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_ERR_FLD_SHIFT                                              AES_BLK_ERR_FLD_SHIFT_V2
#endif

#define  AES_BLK_ERR_FLD_WIDTH_V1                                           (1)
#define  AES_BLK_ERR_FLD_WIDTH_V2                                           (1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_ERR_FLD_WIDTH                                              AES_BLK_ERR_FLD_WIDTH_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_ERR_FLD_WIDTH                                              AES_BLK_ERR_FLD_WIDTH_V2
#endif

#define  AES_BLK_ERR_FLD_UMASK_V1                                           (0x1)
#define  AES_BLK_ERR_FLD_UMASK_V2                                           (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_ERR_FLD_UMASK                                              AES_BLK_ERR_FLD_UMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_ERR_FLD_UMASK                                              AES_BLK_ERR_FLD_UMASK_V2
#endif

#define  AES_BLK_ERR_FLD_SMASK_V1                                           (0x1)
#define  AES_BLK_ERR_FLD_SMASK_V2                                           (0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_ERR_FLD_SMASK                                              AES_BLK_ERR_FLD_SMASK_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_ERR_FLD_SMASK                                              AES_BLK_ERR_FLD_SMASK_V2
#endif

#define  AES_BLK_ERR_FLD_XTRCT_V1(r)                                        ((((uint32_t)r) >> 0) & 0x1)
#define  AES_BLK_ERR_FLD_XTRCT_V2(r)                                        ((((uint32_t)r) >> 0) & 0x1)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_ERR_FLD_XTRCT                                              AES_BLK_ERR_FLD_XTRCT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_ERR_FLD_XTRCT                                              AES_BLK_ERR_FLD_XTRCT_V2
#endif

#define  AES_BLK_ERR_FLD_INSRT_V1(f)                                        ((((uint32_t)f) & 0x1) << 0)
#define  AES_BLK_ERR_FLD_INSRT_V2(f)                                        ((((uint32_t)f) & 0x1) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V1
#define  AES_BLK_ERR_FLD_INSRT                                              AES_BLK_ERR_FLD_INSRT_V1
#elif    SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_ERR_FLD_INSRT                                              AES_BLK_ERR_FLD_INSRT_V2
#endif

/*! @} fld (aes_err) */

/*! 
 *  @addtogroup group120372 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_ERR_TNBLE_RESET_UMASK_T7001_A1                             (0x1)
#define  AES_BLK_ERR_TNBLE_RESET_UMASK_S7002_A1                             (0x1)

#define  AES_BLK_ERR_TNBLE_RESET_VALUE_T7001_A1                             (0x0)
#define  AES_BLK_ERR_TNBLE_RESET_VALUE_S7002_A1                             (0x0)

/*! @} reset */

/*! @} err (AES_ERR) */

/*! 
 *  @addtogroup group120236 txt_in_data (AES_TXT_IN_DATA)
 *  @brief Offset = 0x40
 *  @details AES Cipher TXT_IN Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_IN_DATA_OFFSET_V2                                      (0x0 + 0x40)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_DATA_OFFSET                                         AES_BLK_TXT_IN_DATA_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120237 txt_in
 *  @brief Range = 31:0 | Width = 32 | Access = write_only | Default = 0x0
 *  @details txt_in to fifo
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_IN_DATA_TXT_IN_SHIFT_V2                                (0)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_DATA_TXT_IN_SHIFT                                   AES_BLK_TXT_IN_DATA_TXT_IN_SHIFT_V2
#endif

#define  AES_BLK_TXT_IN_DATA_TXT_IN_WIDTH_V2                                (32)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_DATA_TXT_IN_WIDTH                                   AES_BLK_TXT_IN_DATA_TXT_IN_WIDTH_V2
#endif

#define  AES_BLK_TXT_IN_DATA_TXT_IN_UMASK_V2                                (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_DATA_TXT_IN_UMASK                                   AES_BLK_TXT_IN_DATA_TXT_IN_UMASK_V2
#endif

#define  AES_BLK_TXT_IN_DATA_TXT_IN_SMASK_V2                                (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_DATA_TXT_IN_SMASK                                   AES_BLK_TXT_IN_DATA_TXT_IN_SMASK_V2
#endif

#define  AES_BLK_TXT_IN_DATA_TXT_IN_XTRCT_V2(r)                             ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_DATA_TXT_IN_XTRCT                                   AES_BLK_TXT_IN_DATA_TXT_IN_XTRCT_V2
#endif

#define  AES_BLK_TXT_IN_DATA_TXT_IN_INSRT_V2(f)                             ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_IN_DATA_TXT_IN_INSRT                                   AES_BLK_TXT_IN_DATA_TXT_IN_INSRT_V2
#endif

/*! @} txt_in */

/*! 
 *  @addtogroup group120238 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_IN_DATA_TNBLE_RESET_UMASK_S7002_A1                     (0xffffffff)

#define  AES_BLK_TXT_IN_DATA_TNBLE_RESET_VALUE_S7002_A1                     (0x0)

/*! @} reset */

/*! @} txt_in_data (AES_TXT_IN_DATA) */

/*! 
 *  @addtogroup group120245 txt_out_data (AES_TXT_OUT_DATA)
 *  @brief Offset = 0x80
 *  @details AES Cipher TXT_OUT Register
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_BLK_TXT_OUT_DATA_OFFSET_V2                                     (0x0 + 0x80)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_DATA_OFFSET                                        AES_BLK_TXT_OUT_DATA_OFFSET_V2
#endif

/*! 
 *  @addtogroup group120246 txt_out
 *  @brief Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0
 *  @details txt_out from fifo
 *  @see @ref SAIField
 *  @{
 */

#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_SHIFT_V2                              (0)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_SHIFT                                 AES_BLK_TXT_OUT_DATA_TXT_OUT_SHIFT_V2
#endif

#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_WIDTH_V2                              (32)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_WIDTH                                 AES_BLK_TXT_OUT_DATA_TXT_OUT_WIDTH_V2
#endif

#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_UMASK_V2                              (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_UMASK                                 AES_BLK_TXT_OUT_DATA_TXT_OUT_UMASK_V2
#endif

#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_SMASK_V2                              (0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_SMASK                                 AES_BLK_TXT_OUT_DATA_TXT_OUT_SMASK_V2
#endif

#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_XTRCT_V2(r)                           ((((uint32_t)r) >> 0) & 0xffffffff)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_XTRCT                                 AES_BLK_TXT_OUT_DATA_TXT_OUT_XTRCT_V2
#endif

#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_INSRT_V2(f)                           ((((uint32_t)f) & 0xffffffff) << 0)
#if      SPDS_AES_VERSION == SPDS_AES_V2
#define  AES_BLK_TXT_OUT_DATA_TXT_OUT_INSRT                                 AES_BLK_TXT_OUT_DATA_TXT_OUT_INSRT_V2
#endif

/*! @} txt_out */

/*! 
 *  @addtogroup group120247 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_BLK_TXT_OUT_DATA_TNBLE_RESET_UMASK_S7002_A1                    (0xffffffff)

#define  AES_BLK_TXT_OUT_DATA_TNBLE_RESET_VALUE_S7002_A1                    (0x0)

/*! @} reset */

/*! @} txt_out_data (AES_TXT_OUT_DATA) */

/*! @} blk (AES) */

/*! 
 *  @addtogroup group581457 command_fifo_direct_access
 *  @brief Offset = 0x4000
 *  @details Direct read access to 128 X 32 Command FIFO
 *  @see @ref SAIAddressBlock
 *  @{
 */

#define  AES_COMMAND_FIFO_DIRECT_ACCESS_OFFSET_V3                           (0x4000)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_COMMAND_FIFO_DIRECT_ACCESS_OFFSET                              AES_COMMAND_FIFO_DIRECT_ACCESS_OFFSET_V3
#endif

/*! 
 *  @addtogroup group581458 word
 *  @brief Offset = 0x0
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_COMMAND_FIFO_DIRECT_ACCESS_WORD_OFFSET_V3                      (0x4000 + 0x0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_COMMAND_FIFO_DIRECT_ACCESS_WORD_OFFSET                         AES_COMMAND_FIFO_DIRECT_ACCESS_WORD_OFFSET_V3
#endif

/*! 
 *  @addtogroup group581459 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_COMMAND_FIFO_DIRECT_ACCESS_WORD_TNBLE_RESET_UMASK_S8000_A1     (0x0)

#define  AES_COMMAND_FIFO_DIRECT_ACCESS_WORD_TNBLE_RESET_VALUE_S8000_A1     (0x0)

/*! @} reset */

/*! @} word */

/*! @} command_fifo_direct_access */

/*! 
 *  @addtogroup group581460 history_fifo_direct_access
 *  @brief Offset = 0x4600
 *  @details Direct read access to 32 word History FIFO
 *  @see @ref SAIAddressBlock
 *  @{
 */

#define  AES_HISTORY_FIFO_DIRECT_ACCESS_OFFSET_V3                           (0x4600)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_HISTORY_FIFO_DIRECT_ACCESS_OFFSET                              AES_HISTORY_FIFO_DIRECT_ACCESS_OFFSET_V3
#endif

/*! 
 *  @addtogroup group581461 command
 *  @brief Offset = 0x0
 *  @details Command Word Data
 *  @see @ref SAIRegister
 *  @{
 */

#define  AES_HISTORY_FIFO_DIRECT_ACCESS_COMMAND_OFFSET_V3                   (0x4600 + 0x0)
#if      SPDS_AES_VERSION == SPDS_AES_V3
#define  AES_HISTORY_FIFO_DIRECT_ACCESS_COMMAND_OFFSET                      AES_HISTORY_FIFO_DIRECT_ACCESS_COMMAND_OFFSET_V3
#endif

/*! 
 *  @addtogroup group581462 reset
 *  @see @ref SAITunable
 *  @{
 */

#define  AES_HISTORY_FIFO_DIRECT_ACCESS_COMMAND_TNBLE_RESET_UMASK_S8000_A1  (0x0)

#define  AES_HISTORY_FIFO_DIRECT_ACCESS_COMMAND_TNBLE_RESET_VALUE_S8000_A1  (0x0)

/*! @} reset */

/*! @} command */

/*! @} history_fifo_direct_access */

#define AES_TNBLES_DEFAULT_S8000_A1 \
/*  Key = spds_tunable_default                                                */ \
/*  Register Macro Identifier   Register Offset  Tunable Mask  Tunable Value  */ \
{   /*! AES_BLK_CONFIG */       0x4,             0x30000,      0x0            }, \
{                               -1,              -1,           -1             }

#define AES_TNBLES_DEFAULT_S8000_B0 \
/*  Key = spds_tunable_default                                                */ \
/*  Register Macro Identifier   Register Offset  Tunable Mask  Tunable Value  */ \
{   /*! AES_BLK_CONFIG */       0x4,             0x30000,      0x0            }, \
{                               -1,              -1,           -1             }

#define AES_TNBLES_DEFAULT_S8001_A0 \
/*  Key = spds_tunable_default                                                */ \
/*  Register Macro Identifier   Register Offset  Tunable Mask  Tunable Value  */ \
{   /*! AES_BLK_CONFIG */       0x4,             0x30000,      0x0            }, \
{                               -1,              -1,           -1             }

#define AES_TNBLES_DEFAULT_T8010_A0 \
/*  Key = spds_tunable_default                                                */ \
/*  Register Macro Identifier   Register Offset  Tunable Mask  Tunable Value  */ \
{   /*! AES_BLK_CONFIG */       0x4,             0x30000,      0x0            }, \
{                               -1,              -1,           -1             }

/*! @} aes */

#ifdef __ASSEMBLY__
#undef SPDS_ENABLE_ENUMS
#undef SPDS_ENABLE_STRUCTS
#endif /*! __ASSEMBLY__ */

#ifdef SPDS_ENABLE_STRUCTS
#include <stdint.h>
#endif /*! SPDS_ENABLE_STRUCTS */

/*! 
 *  @addtogroup group995868 aes
 *  @brief Address = 0x20a108000
 *  @details Version = 0.0.1 @n
 *  AES Registers
 *  @{
 */

/*! 
 *  @addtogroup group995869 blk (AES)
 *  @brief Offset = 0x0
 *  @details General Control registers
 *  @see @ref SAIAddressBlock
 *  @{
 */

/*! 
 *  @addtogroup group995870 version
 *  @brief Offset = 0x0
 *  @details IP Implementation Version
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Minor Release Number
         */
        uint32_t  minor_release  : 8;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Major Release Number
         */
        uint32_t  major_release  : 8;

        /*! 
         *  Range = 23:16 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Version Number
         */
        uint32_t  fld            : 8;

        /*! 
         *  Range = 31:24 | Width = 8 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 8;
    };
} aes_blk_version_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Minor Release Number
         */
        uint32_t  minor_release  : 8;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Major Release Number
         */
        uint32_t  major_release  : 8;

        /*! 
         *  Range = 23:16 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Version Number
         */
        uint32_t  fld            : 8;

        /*! 
         *  Range = 31:24 | Width = 8 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 8;
    };
} aes_blk_version_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Minor Release Number
         */
        uint32_t  minor_release  : 8;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Major Release Number
         */
        uint32_t  major_release  : 8;

        /*! 
         *  Range = 23:16 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Version Number
         */
        uint32_t  fld            : 8;

        /*! 
         *  Range = 31:24 | Width = 8 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 8;
    };
} aes_blk_version_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Minor Release Number
         */
        uint32_t  minor_release  : 8;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Major Release Number
         */
        uint32_t  major_release  : 8;

        /*! 
         *  Range = 23:16 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Version Number
         */
        uint32_t  fld            : 8;

        /*! 
         *  Range = 31:24 | Width = 8 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 8;
    };
} aes_blk_version_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Minor Release Number
         */
        uint32_t  minor_release  : 8;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Major Release Number
         */
        uint32_t  major_release  : 8;

        /*! 
         *  Range = 23:16 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Version Number
         */
        uint32_t  fld            : 8;

        /*! 
         *  Range = 31:24 | Width = 8 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 8;
    };
} aes_blk_version_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_version_v3_t             aes_blk_version_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_version_v4_t             aes_blk_version_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_version_v5_t             aes_blk_version_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_version_v6_t             aes_blk_version_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_version_v7_t             aes_blk_version_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} version */

/*! 
 *  @addtogroup group995876 config
 *  @brief Offset = 0x4
 *  @details Configuration register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 3:0 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  USER ID for AXI Address Read transactions
         */
        uint32_t  axi_aruser   : 4;

        /*! 
         *  Range = 7:4 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  ARCACHE for AXI Address Read transactions
         */
        uint32_t  axi_arcache  : 4;

        /*! 
         *  Range = 11:8 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  USER ID for AXI Address Write transactions
         */
        uint32_t  axi_awuser   : 4;

        /*! 
         *  Range = 15:12 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  AWCACHE for AXI Address Write transactions
         */
        uint32_t  axi_awcache  : 4;

        /*! 
         *  Range = 17:16 | Width = 2 | Access = read-write | Default = 0x0 @n
         *  0 = Full Size (default) 64 bytes, 1 = Half Size 32 bytes, 2 =
         *  Quarter Size 16 bytes, 3 = N/A
         */
        uint32_t  burst_size   : 2;

        /*! 
         *  Range = 31:18 | Width = 14 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0        : 14;
    };
} aes_blk_config_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 3:0 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  USER ID for AXI Address Read transactions
         */
        uint32_t  axi_aruser   : 4;

        /*! 
         *  Range = 7:4 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  ARCACHE for AXI Address Read transactions
         */
        uint32_t  axi_arcache  : 4;

        /*! 
         *  Range = 11:8 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  USER ID for AXI Address Write transactions
         */
        uint32_t  axi_awuser   : 4;

        /*! 
         *  Range = 15:12 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  AWCACHE for AXI Address Write transactions
         */
        uint32_t  axi_awcache  : 4;

        /*! 
         *  Range = 17:16 | Width = 2 | Access = read-write | Default = 0x0 @n
         *  0 = Full Size (default) 64 bytes, 1 = Half Size 32 bytes, 2 =
         *  Quarter Size 16 bytes, 3 = N/A
         */
        uint32_t  burst_size   : 2;

        /*! 
         *  Range = 31:18 | Width = 14 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0        : 14;
    };
} aes_blk_config_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 3:0 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  USER ID for AXI Address Read transactions
         */
        uint32_t  axi_aruser   : 4;

        /*! 
         *  Range = 7:4 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  ARCACHE for AXI Address Read transactions
         */
        uint32_t  axi_arcache  : 4;

        /*! 
         *  Range = 11:8 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  USER ID for AXI Address Write transactions
         */
        uint32_t  axi_awuser   : 4;

        /*! 
         *  Range = 15:12 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  AWCACHE for AXI Address Write transactions
         */
        uint32_t  axi_awcache  : 4;

        /*! 
         *  Range = 17:16 | Width = 2 | Access = read-write | Default = 0x0 @n
         *  0 = Full Size (default) 64 bytes, 1 = Half Size 32 bytes, 2 =
         *  Quarter Size 16 bytes, 3 = N/A
         */
        uint32_t  burst_size   : 2;

        /*! 
         *  Range = 31:18 | Width = 14 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0        : 14;
    };
} aes_blk_config_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 3:0 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  USER ID for AXI Address Read transactions
         */
        uint32_t  axi_aruser   : 4;

        /*! 
         *  Range = 7:4 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  ARCACHE for AXI Address Read transactions
         */
        uint32_t  axi_arcache  : 4;

        /*! 
         *  Range = 11:8 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  USER ID for AXI Address Write transactions
         */
        uint32_t  axi_awuser   : 4;

        /*! 
         *  Range = 15:12 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  AWCACHE for AXI Address Write transactions
         */
        uint32_t  axi_awcache  : 4;

        /*! 
         *  Range = 17:16 | Width = 2 | Access = read-write | Default = 0x0 @n
         *  0 = Full Size (default) 64 bytes, 1 = Half Size 32 bytes, 2 =
         *  Quarter Size 16 bytes, 3 = N/A
         */
        uint32_t  burst_size   : 2;

        /*! 
         *  Range = 31:18 | Width = 14 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0        : 14;
    };
} aes_blk_config_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 3:0 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  USER ID for AXI Address Read transactions
         */
        uint32_t  axi_aruser   : 4;

        /*! 
         *  Range = 7:4 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  ARCACHE for AXI Address Read transactions
         */
        uint32_t  axi_arcache  : 4;

        /*! 
         *  Range = 11:8 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  USER ID for AXI Address Write transactions
         */
        uint32_t  axi_awuser   : 4;

        /*! 
         *  Range = 15:12 | Width = 4 | Access = read-write | Default = 0x0 @n
         *  AWCACHE for AXI Address Write transactions
         */
        uint32_t  axi_awcache  : 4;

        /*! 
         *  Range = 17:16 | Width = 2 | Access = read-write | Default = 0x0 @n
         *  0 = Full Size (default) 64 bytes, 1 = Half Size 32 bytes, 2 =
         *  Quarter Size 16 bytes, 3 = N/A
         */
        uint32_t  burst_size   : 2;

        /*! 
         *  Range = 31:18 | Width = 14 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0        : 14;
    };
} aes_blk_config_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_config_v3_t              aes_blk_config_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_config_v4_t              aes_blk_config_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_config_v5_t              aes_blk_config_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_config_v6_t              aes_blk_config_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_config_v7_t              aes_blk_config_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} config */

/*! 
 *  @addtogroup group995885 control
 *  @brief Offset = 0x8
 *  @details Control Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Start executing commands in Command FIFO
         */
        uint32_t  start                : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Stop executing commands in Command FIFO
         */
        uint32_t  stop                 : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Empty Command FIFO
         */
        uint32_t  reset                : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Reset the AES Engine
         */
        uint32_t  reset_aes            : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Unused. May be used in future chips.
         */
        uint32_t  reset_read_channel   : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Unused. May be used in future chips.
         */
        uint32_t  reset_write_channel  : 1;

        /*! 
         *  Range = 31:6 | Width = 26 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                : 26;
    };
} aes_blk_control_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Start executing commands in Command FIFO
         */
        uint32_t  start                : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Stop executing commands in Command FIFO
         */
        uint32_t  stop                 : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Empty Command FIFO
         */
        uint32_t  reset                : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Reset the AES Engine
         */
        uint32_t  reset_aes            : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Unused. May be used in future chips.
         */
        uint32_t  reset_read_channel   : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Unused. May be used in future chips.
         */
        uint32_t  reset_write_channel  : 1;

        /*! 
         *  Range = 31:6 | Width = 26 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                : 26;
    };
} aes_blk_control_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Start executing commands in Command FIFO
         */
        uint32_t  start                : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Stop executing commands in Command FIFO
         */
        uint32_t  stop                 : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Empty Command FIFO
         */
        uint32_t  reset                : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Reset the AES Engine
         */
        uint32_t  reset_aes            : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Unused. May be used in future chips.
         */
        uint32_t  reset_read_channel   : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Unused. May be used in future chips.
         */
        uint32_t  reset_write_channel  : 1;

        /*! 
         *  Range = 31:6 | Width = 26 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                : 26;
    };
} aes_blk_control_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Start executing commands in Command FIFO
         */
        uint32_t  start                : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Stop executing commands in Command FIFO
         */
        uint32_t  stop                 : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Empty Command FIFO
         */
        uint32_t  reset                : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Reset the AES Engine
         */
        uint32_t  reset_aes            : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Unused. May be used in future chips.
         */
        uint32_t  reset_read_channel   : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Unused. May be used in future chips.
         */
        uint32_t  reset_write_channel  : 1;

        /*! 
         *  Range = 31:6 | Width = 26 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                : 26;
    };
} aes_blk_control_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Start executing commands in Command FIFO
         */
        uint32_t  start                : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Stop executing commands in Command FIFO
         */
        uint32_t  stop                 : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Empty Command FIFO
         */
        uint32_t  reset                : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Reset the AES Engine
         */
        uint32_t  reset_aes            : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Unused. May be used in future chips.
         */
        uint32_t  reset_read_channel   : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Unused. May be used in future chips.
         */
        uint32_t  reset_write_channel  : 1;

        /*! 
         *  Range = 31:6 | Width = 26 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                : 26;
    };
} aes_blk_control_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_control_v3_t             aes_blk_control_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_control_v4_t             aes_blk_control_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_control_v5_t             aes_blk_control_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_control_v6_t             aes_blk_control_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_control_v7_t             aes_blk_control_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} control */

/*! 
 *  @addtogroup group995894 status
 *  @brief Offset = 0xc
 *  @details Channel status register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Asserted when either the key configurator, IV setup, or AES cipher
         *  engines are busy
         */
        uint32_t  busy   : 1;

        /*! 
         *  Range = 31:1 | Width = 31 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0  : 31;
    };
} aes_blk_status_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Asserted when either the key configurator, IV setup, or AES cipher
         *  engines are busy
         */
        uint32_t  busy   : 1;

        /*! 
         *  Range = 31:1 | Width = 31 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0  : 31;
    };
} aes_blk_status_v2_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is reading data from System Memory
         */
        uint32_t  dma_read_active       : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is done reading data from System Memory but not all data
         *  has been pushed into the AES engine
         */
        uint32_t  dma_read_incomplete   : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is writing data to System Memory
         */
        uint32_t  dma_write_active      : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is done writing data to System Memory but not all data has
         *  been written
         */
        uint32_t  dma_write_incomplete  : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  AES module is busy
         */
        uint32_t  active                : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  A command is being executed from the Command FIFO
         */
        uint32_t  command_fifo_active   : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Indicates the Command FIFO has been enabled and ready to execute
         *  commands
         */
        uint32_t  command_fifo_enabled  : 1;

        /*! 
         *  Range = 31:7 | Width = 25 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                 : 25;
    };
} aes_blk_status_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is reading data from System Memory
         */
        uint32_t  dma_read_active       : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is done reading data from System Memory but not all data
         *  has been pushed into the AES engine
         */
        uint32_t  dma_read_incomplete   : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is writing data to System Memory
         */
        uint32_t  dma_write_active      : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is done writing data to System Memory but not all data has
         *  been written
         */
        uint32_t  dma_write_incomplete  : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  AES module is busy
         */
        uint32_t  active                : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  A command is being executed from the Command FIFO
         */
        uint32_t  command_fifo_active   : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Indicates the Command FIFO has been enabled and ready to execute
         *  commands
         */
        uint32_t  command_fifo_enabled  : 1;

        /*! 
         *  Range = 31:7 | Width = 25 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                 : 25;
    };
} aes_blk_status_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is reading data from System Memory
         */
        uint32_t  dma_read_active       : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is done reading data from System Memory but not all data
         *  has been pushed into the AES engine
         */
        uint32_t  dma_read_incomplete   : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is writing data to System Memory
         */
        uint32_t  dma_write_active      : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is done writing data to System Memory but not all data has
         *  been written
         */
        uint32_t  dma_write_incomplete  : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  AES module is busy
         */
        uint32_t  active                : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  A command is being executed from the Command FIFO
         */
        uint32_t  command_fifo_active   : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Indicates the Command FIFO has been enabled and ready to execute
         *  commands
         */
        uint32_t  command_fifo_enabled  : 1;

        /*! 
         *  Range = 31:7 | Width = 25 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                 : 25;
    };
} aes_blk_status_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is reading data from System Memory
         */
        uint32_t  dma_read_active               : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is done reading data from System Memory but not all data
         *  has been pushed into the AES engine
         */
        uint32_t  dma_read_incomplete           : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is writing data to System Memory
         */
        uint32_t  dma_write_active              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is done writing data to System Memory but not all data has
         *  been written
         */
        uint32_t  dma_write_incomplete          : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  AES module is busy
         */
        uint32_t  active                        : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  A command is being executed from the Command FIFO
         */
        uint32_t  command_fifo_active           : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Indicates the Command FIFO has been enabled and ready to execute
         *  commands
         */
        uint32_t  command_fifo_enabled          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The random number generator for text DPA has been seeded
         */
        uint32_t  text_dpa_random_seeded        : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The random number generator for key unwrap DPA has been seeded
         */
        uint32_t  key_unwrap_dpa_random_seeded  : 1;

        /*! 
         *  Range = 31:9 | Width = 23 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                         : 23;
    };
} aes_blk_status_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is reading data from System Memory
         */
        uint32_t  dma_read_active               : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is done reading data from System Memory but not all data
         *  has been pushed into the AES engine
         */
        uint32_t  dma_read_incomplete           : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is writing data to System Memory
         */
        uint32_t  dma_write_active              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The DMA is done writing data to System Memory but not all data has
         *  been written
         */
        uint32_t  dma_write_incomplete          : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  AES module is busy
         */
        uint32_t  active                        : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  A command is being executed from the Command FIFO
         */
        uint32_t  command_fifo_active           : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Indicates the Command FIFO has been enabled and ready to execute
         *  commands
         */
        uint32_t  command_fifo_enabled          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The random number generator for text DPA has been seeded
         */
        uint32_t  text_dpa_random_seeded        : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The random number generator for key unwrap DPA has been seeded
         */
        uint32_t  key_unwrap_dpa_random_seeded  : 1;

        /*! 
         *  Range = 31:9 | Width = 23 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                         : 23;
    };
} aes_blk_status_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_status_v1_t              aes_blk_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_status_v2_t              aes_blk_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_status_v3_t              aes_blk_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_status_v4_t              aes_blk_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_status_v5_t              aes_blk_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_status_v6_t              aes_blk_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_status_v7_t              aes_blk_status_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} status */

/*! 
 *  @addtogroup group995906 key_id
 *  @brief Offset = 0x10
 *  @details Current Key IDs
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  ID for Key in context 0
         */
        uint32_t  context_0  : 8;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  ID for Key in context 1
         */
        uint32_t  context_1  : 8;

        /*! 
         *  Range = 31:16 | Width = 16 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0      : 16;
    };
} aes_blk_key_id_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  ID for Key in context 0
         */
        uint32_t  context_0  : 8;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  ID for Key in context 1
         */
        uint32_t  context_1  : 8;

        /*! 
         *  Range = 31:16 | Width = 16 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0      : 16;
    };
} aes_blk_key_id_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  ID for Key in context 0
         */
        uint32_t  context_0  : 8;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  ID for Key in context 1
         */
        uint32_t  context_1  : 8;

        /*! 
         *  Range = 31:16 | Width = 16 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0      : 16;
    };
} aes_blk_key_id_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  ID for Key in context 0
         */
        uint32_t  context_0  : 8;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  ID for Key in context 1
         */
        uint32_t  context_1  : 8;

        /*! 
         *  Range = 31:16 | Width = 16 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0      : 16;
    };
} aes_blk_key_id_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 7:0 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  ID for Key in context 0
         */
        uint32_t  context_0  : 8;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  ID for Key in context 1
         */
        uint32_t  context_1  : 8;

        /*! 
         *  Range = 31:16 | Width = 16 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0      : 16;
    };
} aes_blk_key_id_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_key_id_v3_t              aes_blk_key_id_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_key_id_v4_t              aes_blk_key_id_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_key_id_v5_t              aes_blk_key_id_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_key_id_v6_t              aes_blk_key_id_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_key_id_v7_t              aes_blk_key_id_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} key_id */

/*! 
 *  @addtogroup group995911 axi_status
 *  @brief Offset = 0x14
 *  @details AXI status register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 1:0 | Width = 2 | Access = read-only | Default = 0x0 @n
         *  AXI response to read request
         */
        uint32_t  read_response   : 2;

        /*! 
         *  Range = 3:2 | Width = 2 | Access = read-only | Default = 0x0 @n
         *  AXI response to write request
         */
        uint32_t  write_response  : 2;

        /*! 
         *  Range = 31:4 | Width = 28 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0           : 28;
    };
} aes_blk_axi_status_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 1:0 | Width = 2 | Access = read-only | Default = 0x0 @n
         *  AXI response to read request
         */
        uint32_t  read_response   : 2;

        /*! 
         *  Range = 3:2 | Width = 2 | Access = read-only | Default = 0x0 @n
         *  AXI response to write request
         */
        uint32_t  write_response  : 2;

        /*! 
         *  Range = 31:4 | Width = 28 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0           : 28;
    };
} aes_blk_axi_status_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 1:0 | Width = 2 | Access = read-only | Default = 0x0 @n
         *  AXI response to read request
         */
        uint32_t  read_response   : 2;

        /*! 
         *  Range = 3:2 | Width = 2 | Access = read-only | Default = 0x0 @n
         *  AXI response to write request
         */
        uint32_t  write_response  : 2;

        /*! 
         *  Range = 31:4 | Width = 28 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0           : 28;
    };
} aes_blk_axi_status_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 1:0 | Width = 2 | Access = read-only | Default = 0x0 @n
         *  AXI response to read request
         */
        uint32_t  read_response   : 2;

        /*! 
         *  Range = 3:2 | Width = 2 | Access = read-only | Default = 0x0 @n
         *  AXI response to write request
         */
        uint32_t  write_response  : 2;

        /*! 
         *  Range = 31:4 | Width = 28 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0           : 28;
    };
} aes_blk_axi_status_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 1:0 | Width = 2 | Access = read-only | Default = 0x0 @n
         *  AXI response to read request
         */
        uint32_t  read_response   : 2;

        /*! 
         *  Range = 3:2 | Width = 2 | Access = read-only | Default = 0x0 @n
         *  AXI response to write request
         */
        uint32_t  write_response  : 2;

        /*! 
         *  Range = 31:4 | Width = 28 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0           : 28;
    };
} aes_blk_axi_status_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_axi_status_v3_t          aes_blk_axi_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_axi_status_v4_t          aes_blk_axi_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_axi_status_v5_t          aes_blk_axi_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_axi_status_v6_t          aes_blk_axi_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_axi_status_v7_t          aes_blk_axi_status_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} axi_status */

/*! 
 *  @addtogroup group995916 int_status
 *  @brief Offset = 0x18
 *  @details Channel interrupt status register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The number of entries in the Command FIFO has gone below
         *  CHAN.DMA_WATERMARKS.COMMAND_FIFO_LOW (not sticky)
         */
        uint32_t  command_fifo_low             : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  SW pushed (wrote) too many entries into the Command FIFO
         */
        uint32_t  command_fifo_overflow        : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  An invalid opcode detected.
         */
        uint32_t  invalid_command              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  AXI responded with an "error", "retry" or "split"
         */
        uint32_t  axi_read_response_not_okay   : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  AXI responded with an "error", "retry" or "split"
         */
        uint32_t  axi_write_response_not_okay  : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  A "flag" command has been executed.
         */
        uint32_t  flag_command                 : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Non-multiple of 16B data length.
         */
        uint32_t  invalid_data_length          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Keys are disabled
         */
        uint32_t  key_0_disabled               : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  CMAC Tag mismatch detected
         */
        uint32_t  key_0_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 9 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Key policy mismatch at load time
         */
        uint32_t  key_0_policy_mismatch        : 1;

        /*! 
         *  Range = 10 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys have expired
         */
        uint32_t  key_0_invalid_at_use_time    : 1;

        /*! 
         *  Range = 11 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  HDCP error detected
         */
        uint32_t  key_0_hdcp_err               : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys are disabled
         */
        uint32_t  key_1_disabled               : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  CMAC Tag mismatch detected
         */
        uint32_t  key_1_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 14 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Key policy mismatch at load time
         */
        uint32_t  key_1_policy_mismatch        : 1;

        /*! 
         *  Range = 15 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys have expired
         */
        uint32_t  key_1_invalid_at_use_time    : 1;

        /*! 
         *  Range = 16 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  HDCP error detected
         */
        uint32_t  key_1_hdcp_err               : 1;

        /*! 
         *  Range = 31:17 | Width = 15 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0                        : 15;
    };
} aes_blk_int_status_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The number of entries in the Command FIFO has gone below
         *  CHAN.DMA_WATERMARKS.COMMAND_FIFO_LOW (not sticky)
         */
        uint32_t  command_fifo_low             : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  SW pushed (wrote) too many entries into the Command FIFO
         */
        uint32_t  command_fifo_overflow        : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  An invalid opcode detected.
         */
        uint32_t  invalid_command              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  AXI responded with an "error", "retry" or "split"
         */
        uint32_t  axi_read_response_not_okay   : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  AXI responded with an "error", "retry" or "split"
         */
        uint32_t  axi_write_response_not_okay  : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  A "flag" command has been executed.
         */
        uint32_t  flag_command                 : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Non-multiple of 16B data length.
         */
        uint32_t  invalid_data_length          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Keys are disabled
         */
        uint32_t  key_0_disabled               : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  CMAC Tag mismatch detected
         */
        uint32_t  key_0_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 9 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Key policy mismatch at load time
         */
        uint32_t  key_0_policy_mismatch        : 1;

        /*! 
         *  Range = 10 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys have expired
         */
        uint32_t  key_0_invalid_at_use_time    : 1;

        /*! 
         *  Range = 11 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  HDCP error detected
         */
        uint32_t  key_0_hdcp_err               : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys are disabled
         */
        uint32_t  key_1_disabled               : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  CMAC Tag mismatch detected
         */
        uint32_t  key_1_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 14 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Key policy mismatch at load time
         */
        uint32_t  key_1_policy_mismatch        : 1;

        /*! 
         *  Range = 15 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys have expired
         */
        uint32_t  key_1_invalid_at_use_time    : 1;

        /*! 
         *  Range = 16 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  HDCP error detected
         */
        uint32_t  key_1_hdcp_err               : 1;

        /*! 
         *  Range = 31:17 | Width = 15 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0                        : 15;
    };
} aes_blk_int_status_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The number of entries in the Command FIFO has gone below
         *  CHAN.DMA_WATERMARKS.COMMAND_FIFO_LOW (not sticky)
         */
        uint32_t  command_fifo_low             : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  SW pushed (wrote) too many entries into the Command FIFO
         */
        uint32_t  command_fifo_overflow        : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  An invalid opcode detected.
         */
        uint32_t  invalid_command              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  AXI responded with an "error", "retry" or "split"
         */
        uint32_t  axi_read_response_not_okay   : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  AXI responded with an "error", "retry" or "split"
         */
        uint32_t  axi_write_response_not_okay  : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  A "flag" command has been executed.
         */
        uint32_t  flag_command                 : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Non-multiple of 16B data length.
         */
        uint32_t  invalid_data_length          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Keys are disabled
         */
        uint32_t  key_0_disabled               : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  CMAC Tag mismatch detected
         */
        uint32_t  key_0_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 9 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Key policy mismatch at load time
         */
        uint32_t  key_0_policy_mismatch        : 1;

        /*! 
         *  Range = 10 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys have expired
         */
        uint32_t  key_0_invalid_at_use_time    : 1;

        /*! 
         *  Range = 11 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  HDCP error detected
         */
        uint32_t  key_0_hdcp_err               : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys are disabled
         */
        uint32_t  key_1_disabled               : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  CMAC Tag mismatch detected
         */
        uint32_t  key_1_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 14 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Key policy mismatch at load time
         */
        uint32_t  key_1_policy_mismatch        : 1;

        /*! 
         *  Range = 15 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys have expired
         */
        uint32_t  key_1_invalid_at_use_time    : 1;

        /*! 
         *  Range = 16 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  HDCP error detected
         */
        uint32_t  key_1_hdcp_err               : 1;

        /*! 
         *  Range = 31:17 | Width = 15 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0                        : 15;
    };
} aes_blk_int_status_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The number of entries in the Command FIFO has gone below
         *  CHAN.DMA_WATERMARKS.COMMAND_FIFO_LOW (not sticky)
         */
        uint32_t  command_fifo_low             : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  SW pushed (wrote) too many entries into the Command FIFO
         */
        uint32_t  command_fifo_overflow        : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  An invalid opcode detected.
         */
        uint32_t  invalid_command              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  AXI responded with an "error", "retry" or "split"
         */
        uint32_t  axi_read_response_not_okay   : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  AXI responded with an "error", "retry" or "split"
         */
        uint32_t  axi_write_response_not_okay  : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  A "flag" command has been executed.
         */
        uint32_t  flag_command                 : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Non-multiple of 16B data length.
         */
        uint32_t  invalid_data_length          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Keys are disabled
         */
        uint32_t  key_0_disabled               : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  CMAC Tag mismatch detected
         */
        uint32_t  key_0_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 9 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Key policy mismatch at load time
         */
        uint32_t  key_0_policy_mismatch        : 1;

        /*! 
         *  Range = 10 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys have expired
         */
        uint32_t  key_0_invalid_at_use_time    : 1;

        /*! 
         *  Range = 11 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  HDCP error detected
         */
        uint32_t  key_0_hdcp_err               : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  DAP random number generator has not been seeded
         */
        uint32_t  key_0_dpa_random_unseeded    : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys are disabled
         */
        uint32_t  key_1_disabled               : 1;

        /*! 
         *  Range = 14 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  CMAC Tag mismatch detected
         */
        uint32_t  key_1_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 15 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Key policy mismatch at load time
         */
        uint32_t  key_1_policy_mismatch        : 1;

        /*! 
         *  Range = 16 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys have expired
         */
        uint32_t  key_1_invalid_at_use_time    : 1;

        /*! 
         *  Range = 17 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  HDCP error detected
         */
        uint32_t  key_1_hdcp_err               : 1;

        /*! 
         *  Range = 18 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  DAP random number generator has not been seeded
         */
        uint32_t  key_1_dpa_random_unseeded    : 1;

        /*! 
         *  Range = 31:19 | Width = 13 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0                        : 13;
    };
} aes_blk_int_status_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  The number of entries in the Command FIFO has gone below
         *  CHAN.DMA_WATERMARKS.COMMAND_FIFO_LOW (not sticky)
         */
        uint32_t  command_fifo_low             : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  SW pushed (wrote) too many entries into the Command FIFO
         */
        uint32_t  command_fifo_overflow        : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  An invalid opcode detected.
         */
        uint32_t  invalid_command              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  AXI responded with an "error", "retry" or "split"
         */
        uint32_t  axi_read_response_not_okay   : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  AXI responded with an "error", "retry" or "split"
         */
        uint32_t  axi_write_response_not_okay  : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  A "flag" command has been executed.
         */
        uint32_t  flag_command                 : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Non-multiple of 16B data length.
         */
        uint32_t  invalid_data_length          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Keys are disabled
         */
        uint32_t  key_0_disabled               : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  CMAC Tag mismatch detected
         */
        uint32_t  key_0_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 9 | Width = 1 | Access = write-once-clear | Default = 0x0 @n
         *  Key policy mismatch at load time
         */
        uint32_t  key_0_policy_mismatch        : 1;

        /*! 
         *  Range = 10 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys have expired
         */
        uint32_t  key_0_invalid_at_use_time    : 1;

        /*! 
         *  Range = 11 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  HDCP error detected
         */
        uint32_t  key_0_hdcp_err               : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  DAP random number generator has not been seeded
         */
        uint32_t  key_0_dpa_random_unseeded    : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys are disabled
         */
        uint32_t  key_1_disabled               : 1;

        /*! 
         *  Range = 14 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  CMAC Tag mismatch detected
         */
        uint32_t  key_1_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 15 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Key policy mismatch at load time
         */
        uint32_t  key_1_policy_mismatch        : 1;

        /*! 
         *  Range = 16 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  Keys have expired
         */
        uint32_t  key_1_invalid_at_use_time    : 1;

        /*! 
         *  Range = 17 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  HDCP error detected
         */
        uint32_t  key_1_hdcp_err               : 1;

        /*! 
         *  Range = 18 | Width = 1 | Access = write-once-clear | Default = 0x0
         *  @n
         *  DAP random number generator has not been seeded
         */
        uint32_t  key_1_dpa_random_unseeded    : 1;

        /*! 
         *  Range = 31:19 | Width = 13 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0                        : 13;
    };
} aes_blk_int_status_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_int_status_v3_t          aes_blk_int_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_int_status_v4_t          aes_blk_int_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_int_status_v5_t          aes_blk_int_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_int_status_v6_t          aes_blk_int_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_int_status_v7_t          aes_blk_int_status_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} int_status */

/*! 
 *  @addtogroup group995938 int_enable
 *  @brief Offset = 0x1c
 *  @details Channel interrupt enable register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable COMMAND_FIFO_LOW Interrupt.
         */
        uint32_t  command_fifo_low             : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable COMMAND_FIFO_OVERFLOW Interrupt.
         */
        uint32_t  command_fifo_overflow        : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable INVALID_COMMAND Interrupt.
         */
        uint32_t  invalid_command              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable AXI_READ_RESPONSE_NOT_OKAY Interrupt.
         */
        uint32_t  axi_read_response_not_okay   : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable AXI_WRITE_RESPONSE_NOT_OKAY Interrupt.
         */
        uint32_t  axi_write_response_not_okay  : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable FLAG_COMMAND Interrupt.
         */
        uint32_t  flag_command                 : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable INVALID_DATA_LENGTH Interrupt.
         */
        uint32_t  invalid_data_length          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_DISABLED Interrupt.
         */
        uint32_t  key_0_disabled               : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_CMAC_TAG_MISMATCH Interrupt.
         */
        uint32_t  key_0_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 9 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_POLICY_MISMATCH Interrupt.
         */
        uint32_t  key_0_policy_mismatch        : 1;

        /*! 
         *  Range = 10 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_INVALID_AT_USE_TIME Interrupt.
         */
        uint32_t  key_0_invalid_at_use_time    : 1;

        /*! 
         *  Range = 11 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_HDCP_ERR Interrupt.
         */
        uint32_t  key_0_hdcp_err               : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_DISABLED Interrupt.
         */
        uint32_t  key_1_disabled               : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_CMAC_TAG_MISMATCH Interrupt.
         */
        uint32_t  key_1_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 14 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_POLICY_MISMATCH Interrupt.
         */
        uint32_t  key_1_policy_mismatch        : 1;

        /*! 
         *  Range = 15 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_INVALID_AT_USE_TIME Interrupt.
         */
        uint32_t  key_1_invalid_at_use_time    : 1;

        /*! 
         *  Range = 16 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_HDCP_ERR Interrupt.
         */
        uint32_t  key_1_hdcp_err               : 1;

        /*! 
         *  Range = 31:17 | Width = 15 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0                        : 15;
    };
} aes_blk_int_enable_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable COMMAND_FIFO_LOW Interrupt.
         */
        uint32_t  command_fifo_low             : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable COMMAND_FIFO_OVERFLOW Interrupt.
         */
        uint32_t  command_fifo_overflow        : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable INVALID_COMMAND Interrupt.
         */
        uint32_t  invalid_command              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable AXI_READ_RESPONSE_NOT_OKAY Interrupt.
         */
        uint32_t  axi_read_response_not_okay   : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable AXI_WRITE_RESPONSE_NOT_OKAY Interrupt.
         */
        uint32_t  axi_write_response_not_okay  : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable FLAG_COMMAND Interrupt.
         */
        uint32_t  flag_command                 : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable INVALID_DATA_LENGTH Interrupt.
         */
        uint32_t  invalid_data_length          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_DISABLED Interrupt.
         */
        uint32_t  key_0_disabled               : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_CMAC_TAG_MISMATCH Interrupt.
         */
        uint32_t  key_0_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 9 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_POLICY_MISMATCH Interrupt.
         */
        uint32_t  key_0_policy_mismatch        : 1;

        /*! 
         *  Range = 10 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_INVALID_AT_USE_TIME Interrupt.
         */
        uint32_t  key_0_invalid_at_use_time    : 1;

        /*! 
         *  Range = 11 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_HDCP_ERR Interrupt.
         */
        uint32_t  key_0_hdcp_err               : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_DISABLED Interrupt.
         */
        uint32_t  key_1_disabled               : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_CMAC_TAG_MISMATCH Interrupt.
         */
        uint32_t  key_1_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 14 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_POLICY_MISMATCH Interrupt.
         */
        uint32_t  key_1_policy_mismatch        : 1;

        /*! 
         *  Range = 15 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_INVALID_AT_USE_TIME Interrupt.
         */
        uint32_t  key_1_invalid_at_use_time    : 1;

        /*! 
         *  Range = 16 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_HDCP_ERR Interrupt.
         */
        uint32_t  key_1_hdcp_err               : 1;

        /*! 
         *  Range = 31:17 | Width = 15 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0                        : 15;
    };
} aes_blk_int_enable_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable COMMAND_FIFO_LOW Interrupt.
         */
        uint32_t  command_fifo_low             : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable COMMAND_FIFO_OVERFLOW Interrupt.
         */
        uint32_t  command_fifo_overflow        : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable INVALID_COMMAND Interrupt.
         */
        uint32_t  invalid_command              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable AXI_READ_RESPONSE_NOT_OKAY Interrupt.
         */
        uint32_t  axi_read_response_not_okay   : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable AXI_WRITE_RESPONSE_NOT_OKAY Interrupt.
         */
        uint32_t  axi_write_response_not_okay  : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable FLAG_COMMAND Interrupt.
         */
        uint32_t  flag_command                 : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable INVALID_DATA_LENGTH Interrupt.
         */
        uint32_t  invalid_data_length          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_DISABLED Interrupt.
         */
        uint32_t  key_0_disabled               : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_CMAC_TAG_MISMATCH Interrupt.
         */
        uint32_t  key_0_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 9 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_POLICY_MISMATCH Interrupt.
         */
        uint32_t  key_0_policy_mismatch        : 1;

        /*! 
         *  Range = 10 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_INVALID_AT_USE_TIME Interrupt.
         */
        uint32_t  key_0_invalid_at_use_time    : 1;

        /*! 
         *  Range = 11 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_HDCP_ERR Interrupt.
         */
        uint32_t  key_0_hdcp_err               : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_DISABLED Interrupt.
         */
        uint32_t  key_1_disabled               : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_CMAC_TAG_MISMATCH Interrupt.
         */
        uint32_t  key_1_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 14 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_POLICY_MISMATCH Interrupt.
         */
        uint32_t  key_1_policy_mismatch        : 1;

        /*! 
         *  Range = 15 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_INVALID_AT_USE_TIME Interrupt.
         */
        uint32_t  key_1_invalid_at_use_time    : 1;

        /*! 
         *  Range = 16 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_HDCP_ERR Interrupt.
         */
        uint32_t  key_1_hdcp_err               : 1;

        /*! 
         *  Range = 31:17 | Width = 15 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0                        : 15;
    };
} aes_blk_int_enable_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable COMMAND_FIFO_LOW Interrupt.
         */
        uint32_t  command_fifo_low             : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable COMMAND_FIFO_OVERFLOW Interrupt.
         */
        uint32_t  command_fifo_overflow        : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable INVALID_COMMAND Interrupt.
         */
        uint32_t  invalid_command              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable AXI_READ_RESPONSE_NOT_OKAY Interrupt.
         */
        uint32_t  axi_read_response_not_okay   : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable AXI_WRITE_RESPONSE_NOT_OKAY Interrupt.
         */
        uint32_t  axi_write_response_not_okay  : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable FLAG_COMMAND Interrupt.
         */
        uint32_t  flag_command                 : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable INVALID_DATA_LENGTH Interrupt.
         */
        uint32_t  invalid_data_length          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_DISABLED Interrupt.
         */
        uint32_t  key_0_disabled               : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_CMAC_TAG_MISMATCH Interrupt.
         */
        uint32_t  key_0_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 9 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_POLICY_MISMATCH Interrupt.
         */
        uint32_t  key_0_policy_mismatch        : 1;

        /*! 
         *  Range = 10 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_INVALID_AT_USE_TIME Interrupt.
         */
        uint32_t  key_0_invalid_at_use_time    : 1;

        /*! 
         *  Range = 11 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_HDCP_ERR Interrupt.
         */
        uint32_t  key_0_hdcp_err               : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_DPA_RANDOM_UNSEEDED Interrupt.
         */
        uint32_t  key_0_dpa_random_unseeded    : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_DISABLED Interrupt.
         */
        uint32_t  key_1_disabled               : 1;

        /*! 
         *  Range = 14 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_CMAC_TAG_MISMATCH Interrupt.
         */
        uint32_t  key_1_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 15 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_POLICY_MISMATCH Interrupt.
         */
        uint32_t  key_1_policy_mismatch        : 1;

        /*! 
         *  Range = 16 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_INVALID_AT_USE_TIME Interrupt.
         */
        uint32_t  key_1_invalid_at_use_time    : 1;

        /*! 
         *  Range = 17 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_HDCP_ERR Interrupt.
         */
        uint32_t  key_1_hdcp_err               : 1;

        /*! 
         *  Range = 18 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_DPA_RANDOM_UNSEEDED Interrupt.
         */
        uint32_t  key_1_dpa_random_unseeded    : 1;

        /*! 
         *  Range = 31:19 | Width = 13 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0                        : 13;
    };
} aes_blk_int_enable_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable COMMAND_FIFO_LOW Interrupt.
         */
        uint32_t  command_fifo_low             : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable COMMAND_FIFO_OVERFLOW Interrupt.
         */
        uint32_t  command_fifo_overflow        : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable INVALID_COMMAND Interrupt.
         */
        uint32_t  invalid_command              : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable AXI_READ_RESPONSE_NOT_OKAY Interrupt.
         */
        uint32_t  axi_read_response_not_okay   : 1;

        /*! 
         *  Range = 4 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable AXI_WRITE_RESPONSE_NOT_OKAY Interrupt.
         */
        uint32_t  axi_write_response_not_okay  : 1;

        /*! 
         *  Range = 5 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable FLAG_COMMAND Interrupt.
         */
        uint32_t  flag_command                 : 1;

        /*! 
         *  Range = 6 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable INVALID_DATA_LENGTH Interrupt.
         */
        uint32_t  invalid_data_length          : 1;

        /*! 
         *  Range = 7 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_DISABLED Interrupt.
         */
        uint32_t  key_0_disabled               : 1;

        /*! 
         *  Range = 8 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_CMAC_TAG_MISMATCH Interrupt.
         */
        uint32_t  key_0_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 9 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_POLICY_MISMATCH Interrupt.
         */
        uint32_t  key_0_policy_mismatch        : 1;

        /*! 
         *  Range = 10 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_INVALID_AT_USE_TIME Interrupt.
         */
        uint32_t  key_0_invalid_at_use_time    : 1;

        /*! 
         *  Range = 11 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_HDCP_ERR Interrupt.
         */
        uint32_t  key_0_hdcp_err               : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_0_DPA_RANDOM_UNSEEDED Interrupt.
         */
        uint32_t  key_0_dpa_random_unseeded    : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_DISABLED Interrupt.
         */
        uint32_t  key_1_disabled               : 1;

        /*! 
         *  Range = 14 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_CMAC_TAG_MISMATCH Interrupt.
         */
        uint32_t  key_1_cmac_tag_mismatch      : 1;

        /*! 
         *  Range = 15 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_POLICY_MISMATCH Interrupt.
         */
        uint32_t  key_1_policy_mismatch        : 1;

        /*! 
         *  Range = 16 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_INVALID_AT_USE_TIME Interrupt.
         */
        uint32_t  key_1_invalid_at_use_time    : 1;

        /*! 
         *  Range = 17 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_HDCP_ERR Interrupt.
         */
        uint32_t  key_1_hdcp_err               : 1;

        /*! 
         *  Range = 18 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Enable KEY_1_DPA_RANDOM_UNSEEDED Interrupt.
         */
        uint32_t  key_1_dpa_random_unseeded    : 1;

        /*! 
         *  Range = 31:19 | Width = 13 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0                        : 13;
    };
} aes_blk_int_enable_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_int_enable_v3_t          aes_blk_int_enable_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_int_enable_v4_t          aes_blk_int_enable_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_int_enable_v5_t          aes_blk_int_enable_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_int_enable_v6_t          aes_blk_int_enable_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_int_enable_v7_t          aes_blk_int_enable_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} int_enable */

/*! 
 *  @addtogroup group995960 watermarks
 *  @brief Offset = 0x20
 *  @details Watermarks for FIFO interrupts.
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 6:0 | Width = 7 | Access = read-write | Default = 0x0 @n
         *  Command FIFO Level below which the COMMAND_FIFO_LOW interrupt will
         *  be asserted
         */
        uint32_t  command_fifo_low  : 7;

        /*! 
         *  Range = 31:7 | Width = 25 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0             : 25;
    };
} aes_blk_watermarks_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 6:0 | Width = 7 | Access = read-write | Default = 0x0 @n
         *  Command FIFO Level below which the COMMAND_FIFO_LOW interrupt will
         *  be asserted
         */
        uint32_t  command_fifo_low  : 7;

        /*! 
         *  Range = 31:7 | Width = 25 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0             : 25;
    };
} aes_blk_watermarks_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 6:0 | Width = 7 | Access = read-write | Default = 0x0 @n
         *  Command FIFO Level below which the COMMAND_FIFO_LOW interrupt will
         *  be asserted
         */
        uint32_t  command_fifo_low  : 7;

        /*! 
         *  Range = 31:7 | Width = 25 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0             : 25;
    };
} aes_blk_watermarks_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 6:0 | Width = 7 | Access = read-write | Default = 0x0 @n
         *  Command FIFO Level below which the COMMAND_FIFO_LOW interrupt will
         *  be asserted
         */
        uint32_t  command_fifo_low  : 7;

        /*! 
         *  Range = 31:7 | Width = 25 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0             : 25;
    };
} aes_blk_watermarks_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 6:0 | Width = 7 | Access = read-write | Default = 0x0 @n
         *  Command FIFO Level below which the COMMAND_FIFO_LOW interrupt will
         *  be asserted
         */
        uint32_t  command_fifo_low  : 7;

        /*! 
         *  Range = 31:7 | Width = 25 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0             : 25;
    };
} aes_blk_watermarks_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_watermarks_v3_t          aes_blk_watermarks_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_watermarks_v4_t          aes_blk_watermarks_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_watermarks_v5_t          aes_blk_watermarks_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_watermarks_v6_t          aes_blk_watermarks_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_watermarks_v7_t          aes_blk_watermarks_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} watermarks */

/*! 
 *  @addtogroup group995964 command_fifo_status
 *  @brief Offset = 0x24
 *  @details Status information for the Command Queue
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Command FIFO has gone below Low Watermark
         */
        uint32_t  low            : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  Command FIFO is empty
         */
        uint32_t  empty          : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Command FIFO is full
         */
        uint32_t  full           : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Software overflowed Command FIFO. This bit is not sticky
         */
        uint32_t  overflow       : 1;

        /*! 
         *  Range = 7:4 | Width = 4 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 4;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Number of 4 byte words in the Command FIFO
         */
        uint32_t  level          : 8;

        /*! 
         *  Range = 22:16 | Width = 7 | Access = read-only | Default = 0x0 @n
         *  Pointer to next command
         */
        uint32_t  read_pointer   : 7;

        /*! 
         *  Range = 23 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1          : 1;

        /*! 
         *  Range = 30:24 | Width = 7 | Access = read-only | Default = 0x0 @n
         *  Pointer to next empty location
         */
        uint32_t  write_pointer  : 7;

        /*! 
         *  Range = 31 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd2          : 1;
    };
} aes_blk_command_fifo_status_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Command FIFO has gone below Low Watermark
         */
        uint32_t  low            : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  Command FIFO is empty
         */
        uint32_t  empty          : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Command FIFO is full
         */
        uint32_t  full           : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Software overflowed Command FIFO. This bit is not sticky
         */
        uint32_t  overflow       : 1;

        /*! 
         *  Range = 7:4 | Width = 4 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 4;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Number of 4 byte words in the Command FIFO
         */
        uint32_t  level          : 8;

        /*! 
         *  Range = 22:16 | Width = 7 | Access = read-only | Default = 0x0 @n
         *  Pointer to next command
         */
        uint32_t  read_pointer   : 7;

        /*! 
         *  Range = 23 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1          : 1;

        /*! 
         *  Range = 30:24 | Width = 7 | Access = read-only | Default = 0x0 @n
         *  Pointer to next empty location
         */
        uint32_t  write_pointer  : 7;

        /*! 
         *  Range = 31 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd2          : 1;
    };
} aes_blk_command_fifo_status_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Command FIFO has gone below Low Watermark
         */
        uint32_t  low            : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  Command FIFO is empty
         */
        uint32_t  empty          : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Command FIFO is full
         */
        uint32_t  full           : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Software overflowed Command FIFO. This bit is not sticky
         */
        uint32_t  overflow       : 1;

        /*! 
         *  Range = 7:4 | Width = 4 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 4;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Number of 4 byte words in the Command FIFO
         */
        uint32_t  level          : 8;

        /*! 
         *  Range = 22:16 | Width = 7 | Access = read-only | Default = 0x0 @n
         *  Pointer to next command
         */
        uint32_t  read_pointer   : 7;

        /*! 
         *  Range = 23 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1          : 1;

        /*! 
         *  Range = 30:24 | Width = 7 | Access = read-only | Default = 0x0 @n
         *  Pointer to next empty location
         */
        uint32_t  write_pointer  : 7;

        /*! 
         *  Range = 31 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd2          : 1;
    };
} aes_blk_command_fifo_status_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Command FIFO has gone below Low Watermark
         */
        uint32_t  low            : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  Command FIFO is empty
         */
        uint32_t  empty          : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Command FIFO is full
         */
        uint32_t  full           : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Software overflowed Command FIFO. This bit is not sticky
         */
        uint32_t  overflow       : 1;

        /*! 
         *  Range = 7:4 | Width = 4 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 4;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Number of 4 byte words in the Command FIFO
         */
        uint32_t  level          : 8;

        /*! 
         *  Range = 22:16 | Width = 7 | Access = read-only | Default = 0x0 @n
         *  Pointer to next command
         */
        uint32_t  read_pointer   : 7;

        /*! 
         *  Range = 23 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1          : 1;

        /*! 
         *  Range = 30:24 | Width = 7 | Access = read-only | Default = 0x0 @n
         *  Pointer to next empty location
         */
        uint32_t  write_pointer  : 7;

        /*! 
         *  Range = 31 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd2          : 1;
    };
} aes_blk_command_fifo_status_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Command FIFO has gone below Low Watermark
         */
        uint32_t  low            : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  Command FIFO is empty
         */
        uint32_t  empty          : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Command FIFO is full
         */
        uint32_t  full           : 1;

        /*! 
         *  Range = 3 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Software overflowed Command FIFO. This bit is not sticky
         */
        uint32_t  overflow       : 1;

        /*! 
         *  Range = 7:4 | Width = 4 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 4;

        /*! 
         *  Range = 15:8 | Width = 8 | Access = read-only | Default = 0x0 @n
         *  Number of 4 byte words in the Command FIFO
         */
        uint32_t  level          : 8;

        /*! 
         *  Range = 22:16 | Width = 7 | Access = read-only | Default = 0x0 @n
         *  Pointer to next command
         */
        uint32_t  read_pointer   : 7;

        /*! 
         *  Range = 23 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1          : 1;

        /*! 
         *  Range = 30:24 | Width = 7 | Access = read-only | Default = 0x0 @n
         *  Pointer to next empty location
         */
        uint32_t  write_pointer  : 7;

        /*! 
         *  Range = 31 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd2          : 1;
    };
} aes_blk_command_fifo_status_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_command_fifo_status_v3_t  aes_blk_command_fifo_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_command_fifo_status_v4_t  aes_blk_command_fifo_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_command_fifo_status_v5_t  aes_blk_command_fifo_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_command_fifo_status_v6_t  aes_blk_command_fifo_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_command_fifo_status_v7_t  aes_blk_command_fifo_status_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} command_fifo_status */

/*! 
 *  @addtogroup group995976 history_fifo_status
 *  @brief Offset = 0x28
 *  @details Status information for the DMA Debug FIFO
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  History FIFO is empty
         */
        uint32_t  empty          : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  History FIFO is full
         */
        uint32_t  full           : 1;

        /*! 
         *  Range = 7:2 | Width = 6 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 6;

        /*! 
         *  Range = 13:8 | Width = 6 | Access = read-only | Default = 0x0 @n
         *  Number of 4 byte words in the History FIFO
         */
        uint32_t  level          : 6;

        /*! 
         *  Range = 15:14 | Width = 2 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1          : 2;

        /*! 
         *  Range = 20:16 | Width = 5 | Access = read-only | Default = 0x0 @n
         *  Pointer to next write location
         */
        uint32_t  write_pointer  : 5;

        /*! 
         *  Range = 31:21 | Width = 11 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd2          : 11;
    };
} aes_blk_history_fifo_status_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  History FIFO is empty
         */
        uint32_t  empty          : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  History FIFO is full
         */
        uint32_t  full           : 1;

        /*! 
         *  Range = 7:2 | Width = 6 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 6;

        /*! 
         *  Range = 13:8 | Width = 6 | Access = read-only | Default = 0x0 @n
         *  Number of 4 byte words in the History FIFO
         */
        uint32_t  level          : 6;

        /*! 
         *  Range = 15:14 | Width = 2 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1          : 2;

        /*! 
         *  Range = 20:16 | Width = 5 | Access = read-only | Default = 0x0 @n
         *  Pointer to next write location
         */
        uint32_t  write_pointer  : 5;

        /*! 
         *  Range = 31:21 | Width = 11 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd2          : 11;
    };
} aes_blk_history_fifo_status_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  History FIFO is empty
         */
        uint32_t  empty          : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  History FIFO is full
         */
        uint32_t  full           : 1;

        /*! 
         *  Range = 7:2 | Width = 6 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 6;

        /*! 
         *  Range = 13:8 | Width = 6 | Access = read-only | Default = 0x0 @n
         *  Number of 4 byte words in the History FIFO
         */
        uint32_t  level          : 6;

        /*! 
         *  Range = 15:14 | Width = 2 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1          : 2;

        /*! 
         *  Range = 20:16 | Width = 5 | Access = read-only | Default = 0x0 @n
         *  Pointer to next write location
         */
        uint32_t  write_pointer  : 5;

        /*! 
         *  Range = 31:21 | Width = 11 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd2          : 11;
    };
} aes_blk_history_fifo_status_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  History FIFO is empty
         */
        uint32_t  empty          : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  History FIFO is full
         */
        uint32_t  full           : 1;

        /*! 
         *  Range = 7:2 | Width = 6 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 6;

        /*! 
         *  Range = 13:8 | Width = 6 | Access = read-only | Default = 0x0 @n
         *  Number of 4 byte words in the History FIFO
         */
        uint32_t  level          : 6;

        /*! 
         *  Range = 15:14 | Width = 2 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1          : 2;

        /*! 
         *  Range = 20:16 | Width = 5 | Access = read-only | Default = 0x0 @n
         *  Pointer to next write location
         */
        uint32_t  write_pointer  : 5;

        /*! 
         *  Range = 31:21 | Width = 11 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd2          : 11;
    };
} aes_blk_history_fifo_status_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  History FIFO is empty
         */
        uint32_t  empty          : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  History FIFO is full
         */
        uint32_t  full           : 1;

        /*! 
         *  Range = 7:2 | Width = 6 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0          : 6;

        /*! 
         *  Range = 13:8 | Width = 6 | Access = read-only | Default = 0x0 @n
         *  Number of 4 byte words in the History FIFO
         */
        uint32_t  level          : 6;

        /*! 
         *  Range = 15:14 | Width = 2 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1          : 2;

        /*! 
         *  Range = 20:16 | Width = 5 | Access = read-only | Default = 0x0 @n
         *  Pointer to next write location
         */
        uint32_t  write_pointer  : 5;

        /*! 
         *  Range = 31:21 | Width = 11 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd2          : 11;
    };
} aes_blk_history_fifo_status_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_history_fifo_status_v3_t  aes_blk_history_fifo_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_history_fifo_status_v4_t  aes_blk_history_fifo_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_history_fifo_status_v5_t  aes_blk_history_fifo_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_history_fifo_status_v6_t  aes_blk_history_fifo_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_history_fifo_status_v7_t  aes_blk_history_fifo_status_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} history_fifo_status */

/*! 
 *  @addtogroup group995985 command_fifo_count
 *  @brief Offset = 0x2c
 *  @details Total count of commands since the Command FIFO was last enabled
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Number of commands popped from the Command FIFO since it was last
         *  turned on. (saturates at max)
         */
        uint32_t  total  : 32;
    };
} aes_blk_command_fifo_count_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Number of commands popped from the Command FIFO since it was last
         *  turned on. (saturates at max)
         */
        uint32_t  total  : 32;
    };
} aes_blk_command_fifo_count_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Number of commands popped from the Command FIFO since it was last
         *  turned on. (saturates at max)
         */
        uint32_t  total  : 32;
    };
} aes_blk_command_fifo_count_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Number of commands popped from the Command FIFO since it was last
         *  turned on. (saturates at max)
         */
        uint32_t  total  : 32;
    };
} aes_blk_command_fifo_count_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Number of commands popped from the Command FIFO since it was last
         *  turned on. (saturates at max)
         */
        uint32_t  total  : 32;
    };
} aes_blk_command_fifo_count_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_command_fifo_count_v3_t  aes_blk_command_fifo_count_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_command_fifo_count_v4_t  aes_blk_command_fifo_count_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_command_fifo_count_v5_t  aes_blk_command_fifo_count_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_command_fifo_count_v6_t  aes_blk_command_fifo_count_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_command_fifo_count_v7_t  aes_blk_command_fifo_count_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} command_fifo_count */

/*! 
 *  @addtogroup group995988 flag_command
 *  @brief Offset = 0x30
 *  @details Interrupt code that provides information about the flag interrupt
 *  that occurred.
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 15:0 | Width = 16 | Access = read-only | Default = 0x0 @n
         *  Interrupt code from the last flag command executed in the Command
         *  FIFO
         */
        uint32_t  code   : 16;

        /*! 
         *  Range = 31:16 | Width = 16 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0  : 16;
    };
} aes_blk_flag_command_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 15:0 | Width = 16 | Access = read-only | Default = 0x0 @n
         *  Interrupt code from the last flag command executed in the Command
         *  FIFO
         */
        uint32_t  code   : 16;

        /*! 
         *  Range = 31:16 | Width = 16 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0  : 16;
    };
} aes_blk_flag_command_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 15:0 | Width = 16 | Access = read-only | Default = 0x0 @n
         *  Interrupt code from the last flag command executed in the Command
         *  FIFO
         */
        uint32_t  code   : 16;

        /*! 
         *  Range = 31:16 | Width = 16 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0  : 16;
    };
} aes_blk_flag_command_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 15:0 | Width = 16 | Access = read-only | Default = 0x0 @n
         *  Interrupt code from the last flag command executed in the Command
         *  FIFO
         */
        uint32_t  code   : 16;

        /*! 
         *  Range = 31:16 | Width = 16 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0  : 16;
    };
} aes_blk_flag_command_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 15:0 | Width = 16 | Access = read-only | Default = 0x0 @n
         *  Interrupt code from the last flag command executed in the Command
         *  FIFO
         */
        uint32_t  code   : 16;

        /*! 
         *  Range = 31:16 | Width = 16 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd0  : 16;
    };
} aes_blk_flag_command_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_flag_command_v3_t        aes_blk_flag_command_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_flag_command_v4_t        aes_blk_flag_command_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_flag_command_v5_t        aes_blk_flag_command_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_flag_command_v6_t        aes_blk_flag_command_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_flag_command_v7_t        aes_blk_flag_command_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} flag_command */

/*! 
 *  @addtogroup group995992 skg_key
 *  @brief Offset = 0x34
 *  @details Secure Key Generation Key
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Count
         */
        uint32_t  count  : 32;
    };
} aes_blk_skg_key_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Count
         */
        uint32_t  count  : 32;
    };
} aes_blk_skg_key_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Count
         */
        uint32_t  count  : 32;
    };
} aes_blk_skg_key_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Count
         */
        uint32_t  count  : 32;
    };
} aes_blk_skg_key_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Count
         */
        uint32_t  count  : 32;
    };
} aes_blk_skg_key_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_skg_key_v3_t             aes_blk_skg_key_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_skg_key_v4_t             aes_blk_skg_key_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_skg_key_v5_t             aes_blk_skg_key_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_skg_key_v6_t             aes_blk_skg_key_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_skg_key_v7_t             aes_blk_skg_key_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} skg_key */

/*! 
 *  @addtogroup group995995 clear_fifos
 *  @brief Offset = 0x38
 *  @details Clear COMMAND and HISTORY FIFOs
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Write 1 to this field to reset the contents of the Command and
         *  History FIFOs to zero.
         */
        uint32_t  reset  : 1;

        /*! 
         *  Range = 31:1 | Width = 31 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0  : 31;
    };
} aes_blk_clear_fifos_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Write 1 to this field to reset the contents of the Command and
         *  History FIFOs to zero.
         */
        uint32_t  reset  : 1;

        /*! 
         *  Range = 31:1 | Width = 31 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0  : 31;
    };
} aes_blk_clear_fifos_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Write 1 to this field to reset the contents of the Command and
         *  History FIFOs to zero.
         */
        uint32_t  reset  : 1;

        /*! 
         *  Range = 31:1 | Width = 31 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0  : 31;
    };
} aes_blk_clear_fifos_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_clear_fifos_v5_t         aes_blk_clear_fifos_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_clear_fifos_v6_t         aes_blk_clear_fifos_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_clear_fifos_v7_t         aes_blk_clear_fifos_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} clear_fifos */

/*! 
 *  @addtogroup group995999 command_fifo
 *  @brief Offset = 0x200
 *  @details Command FIFO. FIFO Depth is (128) Words
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = write-only | Default = 0x0 @n
         *  Command Word
         */
        uint32_t  push_word  : 32;
    };
} aes_blk_command_fifo_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = write-only | Default = 0x0 @n
         *  Command Word
         */
        uint32_t  push_word  : 32;
    };
} aes_blk_command_fifo_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = write-only | Default = 0x0 @n
         *  Command Word
         */
        uint32_t  push_word  : 32;
    };
} aes_blk_command_fifo_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = write-only | Default = 0x0 @n
         *  Command Word
         */
        uint32_t  push_word  : 32;
    };
} aes_blk_command_fifo_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = write-only | Default = 0x0 @n
         *  Command Word
         */
        uint32_t  push_word  : 32;
    };
} aes_blk_command_fifo_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_command_fifo_v3_t        aes_blk_command_fifo_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_command_fifo_v4_t        aes_blk_command_fifo_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_command_fifo_v5_t        aes_blk_command_fifo_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_command_fifo_v6_t        aes_blk_command_fifo_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_command_fifo_v7_t        aes_blk_command_fifo_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} command_fifo */

/*! 
 *  @addtogroup group996003 history_fifo
 *  @brief Offset = 0x400
 *  @details Last (32) Commands words
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Unconnected FIFO output. Command words should be read from
         *  HISTORY_FIFO - 0x3600
         */
        uint32_t  pop_word  : 32;
    };
} aes_blk_history_fifo_v3_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Unconnected FIFO output. Command words should be read from
         *  HISTORY_FIFO - 0x3600
         */
        uint32_t  pop_word  : 32;
    };
} aes_blk_history_fifo_v4_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Unconnected FIFO output. Command words should be read from
         *  HISTORY_FIFO - 0x3600
         */
        uint32_t  pop_word  : 32;
    };
} aes_blk_history_fifo_v5_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Unconnected FIFO output. Command words should be read from
         *  HISTORY_FIFO - 0x3600
         */
        uint32_t  pop_word  : 32;
    };
} aes_blk_history_fifo_v6_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  Unconnected FIFO output. Command words should be read from
         *  HISTORY_FIFO - 0x3600
         */
        uint32_t  pop_word  : 32;
    };
} aes_blk_history_fifo_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_blk_history_fifo_v3_t        aes_blk_history_fifo_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_blk_history_fifo_v4_t        aes_blk_history_fifo_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_blk_history_fifo_v5_t        aes_blk_history_fifo_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_blk_history_fifo_v6_t        aes_blk_history_fifo_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_blk_history_fifo_v7_t        aes_blk_history_fifo_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} history_fifo */

/*! 
 *  @addtogroup group570682 disable (AES_DISABLE)
 *  @brief Offset = 0x4
 *  @details AES GID0, GID1, UID1 and Fairplay Descrambler Disable register
 *  @see @ref SAIRegister
 *  @{
 */

/*! 
 *  @addtogroup group570683 id (disable_id)
 *  @brief Range = 2:0 | Width = 3 | Access = write-only | Default = 0x0
 *  @details Write to the disable_id field to disable use of GID0, GID1, and
 *  UID1 keys until the next chip reset.
 *  @see @ref SAIField
 *  @{
 */

#ifdef SPDS_ENABLE_ENUMS
typedef enum
{
    /*! Write high to disable use of the GID1 key. */
    aes_blk_disable_id_gid1  = 4,

    /*! Write high to disable use of the GID0 key. */
    aes_blk_disable_id_gid0  = 2,

    /*! Write high to disable use of the UID1 key. */
    aes_blk_disable_id_uid1  = 1
} aes_blk_disable_id_v1_t;
#endif /*! SPDS_ENABLE_ENUMS */

/*! @} id (disable_id) */

/*! 
 *  @addtogroup group570689 id_disabled
 *  @brief Range = 10:8 | Width = 3 | Access = read-only | Default = 0x0
 *  @details The id_disabled field indicates which keys are disabled.  If the
 *  GID0, GID1, or UID1 keys are selected for use when disabled, then the key
 *  used in the AES operation is zero and an error interrupt is generated.
 *  This field is only cleared on a chip reset.
 *  @see @ref SAIField
 *  @{
 */

#ifdef SPDS_ENABLE_ENUMS
typedef enum
{
    /*! When set, the GID1 key is disabled. */
    aes_blk_disable_id_disabled_gid1_disabled  = 4,

    /*! When set, the GID0 key is disabled. */
    aes_blk_disable_id_disabled_gid0_disabled  = 2,

    /*! When set, the UID1 key is disabled. */
    aes_blk_disable_id_disabled_uid1_disabled  = 1
} aes_blk_disable_id_disabled_v1_t;
#endif /*! SPDS_ENABLE_ENUMS */

/*! @} id_disabled */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 2:0 | Width = 3 | Access = write-only | Default = 0x0 @n
         *  Write to the disable_id field to disable use of GID0, GID1, and
         *  UID1 keys until the next chip reset.
         */
        uint32_t  id            : 3;

        /*! 
         *  Range = 3 | Width = 1 | Access = write-only | Default = 0x0 @n
         *  Write to the disable_dsb field to disable use of the Fairplay
         *  descrambler until the next chip reset.
         */
        uint32_t  dsb           : 1;

        /*! 
         *  Range = 7:4 | Width = 4 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0         : 4;

        /*! 
         *  Range = 10:8 | Width = 3 | Access = read-only | Default = 0x0 @n
         *  The id_disabled field indicates which keys are disabled.  If the
         *  GID0, GID1, or UID1 keys are selected for use when disabled, then
         *  the key used in the AES operation is zero and an error interrupt is
         *  generated.  This field is only cleared on a chip reset.
         */
        uint32_t  id_disabled   : 3;

        /*! 
         *  Range = 11 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  When set, the dsb_disabled field indicates that the Fairplay key
         *  descrambler is disabled.  If the Fairplay key descrambler is
         *  selected for use when disabled, then the scrambling operation is
         *  bypassed and an error interrupt is generated.  This field is only
         *  cleared on a chip reset.
         */
        uint32_t  dsb_disabled  : 1;

        /*! 
         *  Range = 31:12 | Width = 20 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd1         : 20;
    };
} aes_blk_disable_v1_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_disable_v1_t             aes_blk_disable_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} disable (AES_DISABLE) */

/*! 
 *  @addtogroup group120226 txt_in_control (AES_TXT_IN_CONTROL)
 *  @brief Offset = 0x8
 *  @details AES Cipher TXT_IN Control Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Set this field to start an AES cipher operation on the 16B block
         *  stored in the AES_TXT_IN0/1/2/3 registers.  Before starting an AES
         *  cipher operation, software must check that the AES cipher engine is
         *  ready by checking the AES_TXT_IN_STATUS register.
         */
        uint32_t  txt_in_val      : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Select the key to use for the AES cipher operation.  Software is
         *  responsible for ensuring that the keys are configured and ready for
         *  use through the AES_KEY_IN registers.
         */
        uint32_t  txt_in_key_ctx  : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Select the IV to use for the AES CBC cipher operation.  Software is
         *  responsible for specifying the IV through the AES_IV_IN registers
         *  when starting a new operation.  When continuing an AES CBC cipher
         *  operation from the previous block, hardware updates the IV.
         */
        uint32_t  txt_in_iv_ctx   : 1;

        /*! 
         *  Range = 31:3 | Width = 29 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0           : 29;
    };
} aes_blk_txt_in_control_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0           : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Select the key to use for the AES cipher operation.  Software is
         *  responsible for ensuring that the keys are configured and ready for
         *  use through the AES_KEY_IN registers.
         */
        uint32_t  txt_in_key_ctx  : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Select the IV to use for the AES CBC cipher operation.  Software is
         *  responsible for specifying the IV through the AES_IV_IN registers
         *  when starting a new operation.  When continuing an AES CBC cipher
         *  operation from the previous block, hardware updates the IV.
         */
        uint32_t  txt_in_iv_ctx   : 1;

        /*! 
         *  Range = 31:3 | Width = 29 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1           : 29;
    };
} aes_blk_txt_in_control_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_txt_in_control_v1_t      aes_blk_txt_in_control_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_txt_in_control_v2_t      aes_blk_txt_in_control_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_in_control (AES_TXT_IN_CONTROL) */

/*! 
 *  @addtogroup group120232 txt_in_status (AES_TXT_IN_STATUS)
 *  @brief Offset = 0xc
 *  @details AES Cipher TXT_IN Status register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  Check that the txt_in_rdy bit is set before writing to the
         *  AES_TXT_IN_CONTROL register to start an AES operation.
         */
        uint32_t  txt_in_rdy  : 1;

        /*! 
         *  Range = 31:1 | Width = 31 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0       : 31;
    };
} aes_blk_txt_in_status_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  There are at least 16 bytes of space in the Tx fifo which can be
         *  written into.
         */
        uint32_t  tx_fifo_space_available  : 1;

        /*! 
         *  Range = 31:1 | Width = 31 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                    : 31;
    };
} aes_blk_txt_in_status_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_txt_in_status_v1_t       aes_blk_txt_in_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_txt_in_status_v2_t       aes_blk_txt_in_status_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_in_status (AES_TXT_IN_STATUS) */

/*! 
 *  @addtogroup group570706 txt_in0 (AES_TXT_IN0)
 *  @brief Offset = 0x40
 *  @details AES Cipher TXT_IN[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  txt_in[31:0]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_txt_in0_v1_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_txt_in0_v1_t             aes_blk_txt_in0_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_in0 (AES_TXT_IN0) */

/*! 
 *  @addtogroup group570709 txt_in1 (AES_TXT_IN1)
 *  @brief Offset = 0x44
 *  @details AES Cipher TXT_IN[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  txt_in[63:32]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_txt_in1_v1_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_txt_in1_v1_t             aes_blk_txt_in1_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_in1 (AES_TXT_IN1) */

/*! 
 *  @addtogroup group570712 txt_in2 (AES_TXT_IN2)
 *  @brief Offset = 0x48
 *  @details AES Cipher TXT_IN[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  txt_in[95:64]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_txt_in2_v1_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_txt_in2_v1_t             aes_blk_txt_in2_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_in2 (AES_TXT_IN2) */

/*! 
 *  @addtogroup group570715 txt_in3 (AES_TXT_IN3)
 *  @brief Offset = 0x4c
 *  @details AES Cipher TXT_IN[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  txt_in[127:96]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_txt_in3_v1_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_txt_in3_v1_t             aes_blk_txt_in3_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_in3 (AES_TXT_IN3) */

/*! 
 *  @addtogroup group120239 txt_out_status (AES_TXT_OUT_STATUS)
 *  @brief Offset = 0x50
 *  @details AES Cipher TXT_OUT Status Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  When set, AES Cipher data may be read from the TXT_OUT and IV_OUT
         *  registers.
         */
        uint32_t  txt_out_val      : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Identifies which key was used for the AES cipher operation.
         */
        uint32_t  txt_out_key_ctx  : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Identifies which IV was used for the AES cipher operation.
         */
        uint32_t  txt_out_iv_ctx   : 1;

        /*! 
         *  Range = 31:3 | Width = 29 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0            : 29;
    };
} aes_blk_txt_out_status_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  There are at least 16 bytes in the Rx fifo available for reading.
         */
        uint32_t  rx_fifo_data_available  : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Identifies which key was used for the AES cipher operation.
         */
        uint32_t  txt_out_key_ctx         : 1;

        /*! 
         *  Range = 2 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  Identifies which IV was used for the AES cipher operation.
         */
        uint32_t  txt_out_iv_ctx          : 1;

        /*! 
         *  Range = 31:3 | Width = 29 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0                   : 29;
    };
} aes_blk_txt_out_status_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_txt_out_status_v1_t      aes_blk_txt_out_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_txt_out_status_v2_t      aes_blk_txt_out_status_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_out_status (AES_TXT_OUT_STATUS) */

/*! 
 *  @addtogroup group570724 txt_out0 (AES_TXT_OUT0)
 *  @brief Offset = 0x80
 *  @details AES Cipher TXT_OUT[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  txt_out[31:0]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_txt_out0_v1_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_txt_out0_v1_t            aes_blk_txt_out0_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_out0 (AES_TXT_OUT0) */

/*! 
 *  @addtogroup group570727 txt_out1 (AES_TXT_OUT1)
 *  @brief Offset = 0x84
 *  @details AES Cipher TXT_OUT[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  txt_out[63:32]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_txt_out1_v1_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_txt_out1_v1_t            aes_blk_txt_out1_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_out1 (AES_TXT_OUT1) */

/*! 
 *  @addtogroup group570730 txt_out2 (AES_TXT_OUT2)
 *  @brief Offset = 0x88
 *  @details AES Cipher TXT_OUT[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  txt_out[95:64]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_txt_out2_v1_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_txt_out2_v1_t            aes_blk_txt_out2_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_out2 (AES_TXT_OUT2) */

/*! 
 *  @addtogroup group570733 txt_out3 (AES_TXT_OUT3)
 *  @brief Offset = 0x8c
 *  @details AES Cipher TXT_OUT[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  txt_out[127:96]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_txt_out3_v1_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_txt_out3_v1_t            aes_blk_txt_out3_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_out3 (AES_TXT_OUT3) */

/*! 
 *  @addtogroup group120248 key_in_control (AES_KEY_IN_CONTROL)
 *  @brief Offset = 0x90
 *  @details AES KEY_IN Control Register
 *  @see @ref SAIRegister
 *  @{
 */

/*! 
 *  @addtogroup group120252 key_in_sel
 *  @brief Range = 5:4 | Width = 2 | Access = read-write | Default = 0x0
 *  @details Selects which key to use as an input to the AES key configurator.
 *  @see @ref SAIField
 *  @{
 */

#ifdef SPDS_ENABLE_ENUMS
typedef enum
{
    /*! GID1 */
    aes_blk_key_in_control_key_in_sel_gid1  = 3,

    /*! GID0 */
    aes_blk_key_in_control_key_in_sel_gid0  = 2,

    /*! UID1 */
    aes_blk_key_in_control_key_in_sel_uid1  = 1,

    /*! Software key.  Selects the key described by the AES_KEY_IN0-7 registers. */
    aes_blk_key_in_control_key_in_sel_soft  = 0
} aes_blk_key_in_control_key_in_sel_v2_t;
#endif /*! SPDS_ENABLE_ENUMS */

/*! @} key_in_sel */

/*! 
 *  @addtogroup group120257 key_in_len
 *  @brief Range = 7:6 | Width = 2 | Access = read-write | Default = 0x0
 *  @details Key context length
 *  @see @ref SAIField
 *  @{
 */

#ifdef SPDS_ENABLE_ENUMS
typedef enum
{
    /*! 256-bit */
    aes_blk_key_in_control_key_in_len_key256  = 2,

    /*! 192-bit */
    aes_blk_key_in_control_key_in_len_key192  = 1,

    /*! 128-bit */
    aes_blk_key_in_control_key_in_len_key128  = 0
} aes_blk_key_in_control_key_in_len_v2_t;
#endif /*! SPDS_ENABLE_ENUMS */

/*! @} key_in_len */

/*! 
 *  @addtogroup group120261 key_in_fun
 *  @brief Range = 10:8 | Width = 3 | Access = read-write | Default = 0x0
 *  @details Key function
 *  @see @ref SAIField
 *  @{
 */

#ifdef SPDS_ENABLE_ENUMS
typedef enum
{
    /*! 
     *  Legacy SKG mode.  Under legacy SKG mode, the key unwrapper uses UID2 as
     *  a key and repeats AES operations on the input key for the number of
     *  iterations that is specified in the AES_SKG_KEY_CNT_IN register.  When
     *  legacy SKG mode is selected, bit 0 is ignored.
     */
    aes_blk_key_in_control_key_in_fun_skg       = 4,

    /*! 
     *  Fairplay key descrambler enabled.  The Fairplay descrambler uses the
     *  128b values stored in the AES_DSB_R1 and AES_DSB_R2 registers.
     */
    aes_blk_key_in_control_key_in_fun_fairplay  = 2,

    /*! Key unwrap enabled. */
    aes_blk_key_in_control_key_in_fun_unwrap    = 1
} aes_blk_key_in_control_key_in_fun_v2_t;
#endif /*! SPDS_ENABLE_ENUMS */

/*! @} key_in_fun */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Set this field to start an AES key configurator operation.  Before
         *  starting an AES key configurator operation, software must check
         *  that the AES key configurator engine is ready by checking the
         *  AES_KEY_IN_STATUS register.
         */
        uint32_t  key_in_val  : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Selects the key context that will be updated with the results of
         *  the AES key configurator operation.
         */
        uint32_t  key_in_ctx  : 1;

        /*! 
         *  Range = 3:2 | Width = 2 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0       : 2;

        /*! 
         *  Range = 5:4 | Width = 2 | Access = read-write | Default = 0x0 @n
         *  Selects which key to use as an input to the AES key configurator.
         */
        uint32_t  key_in_sel  : 2;

        /*! 
         *  Range = 7:6 | Width = 2 | Access = read-write | Default = 0x0 @n
         *  Key context length
         */
        uint32_t  key_in_len  : 2;

        /*! 
         *  Range = 10:8 | Width = 3 | Access = read-write | Default = 0x0 @n
         *  Key function
         */
        uint32_t  key_in_fun  : 3;

        /*! 
         *  Range = 11 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1       : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  When set, the key will be used for encryption.  When cleared, the
         *  key will be used for decryption.
         */
        uint32_t  key_in_enc  : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Block Cipher Mode:  When set, the AES cipher is configured to
         *  support CBC mode.  When cleared, the AES Cipher supports ECB mode.
         */
        uint32_t  key_in_mod  : 1;

        /*! 
         *  Range = 31:14 | Width = 18 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd2       : 18;
    };
} aes_blk_key_in_control_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Set this field to start an AES key configurator operation.  Before
         *  starting an AES key configurator operation, software must check
         *  that the AES key configurator engine is ready by checking the
         *  AES_KEY_IN_STATUS register.
         */
        uint32_t  key_in_val  : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Selects the key context that will be updated with the results of
         *  the AES key configurator operation.
         */
        uint32_t  key_in_ctx  : 1;

        /*! 
         *  Range = 3:2 | Width = 2 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0       : 2;

        /*! 
         *  Range = 5:4 | Width = 2 | Access = read-write | Default = 0x0 @n
         *  Selects which key to use as an input to the AES key configurator.
         */
        uint32_t  key_in_sel  : 2;

        /*! 
         *  Range = 7:6 | Width = 2 | Access = read-write | Default = 0x0 @n
         *  Key context length
         */
        uint32_t  key_in_len  : 2;

        /*! 
         *  Range = 10:8 | Width = 3 | Access = read-write | Default = 0x0 @n
         *  Key function
         */
        uint32_t  key_in_fun  : 3;

        /*! 
         *  Range = 11 | Width = 1 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd1       : 1;

        /*! 
         *  Range = 12 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  When set, the key will be used for encryption.  When cleared, the
         *  key will be used for decryption.
         */
        uint32_t  key_in_enc  : 1;

        /*! 
         *  Range = 13 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Block Cipher Mode:  When set, the AES cipher is configured to
         *  support CBC mode.  When cleared, the AES Cipher supports ECB mode.
         */
        uint32_t  key_in_mod  : 1;

        /*! 
         *  Range = 31:14 | Width = 18 | Access = read-as-zero | Default = 0x0
         *  @n
         *  Reserved
         */
        uint32_t  rsvd2       : 18;
    };
} aes_blk_key_in_control_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_key_in_control_v1_t      aes_blk_key_in_control_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_key_in_control_v2_t      aes_blk_key_in_control_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} key_in_control (AES_KEY_IN_CONTROL) */

/*! 
 *  @addtogroup group120270 key_in_status (AES_KEY_IN_STATUS)
 *  @brief Offset = 0x94
 *  @details AES KEY_IN Status Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  When set, the AES Key configurator operation is complete and the
         *  key may be used by the AES Cipher engine.  After starting a key
         *  configurator operation, software checks this register to determine
         *  that the key context is ready for use.
         */
        uint32_t  key_in_rdy  : 1;

        /*! 
         *  Range = 31:1 | Width = 31 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0       : 31;
    };
} aes_blk_key_in_status_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x1 @n
         *  When set, the AES Key configurator operation is complete and the
         *  key may be used by the AES Cipher engine.  After starting a key
         *  configurator operation, software checks this register to determine
         *  that the key context is ready for use.
         */
        uint32_t  key_in_rdy  : 1;

        /*! 
         *  Range = 31:1 | Width = 31 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0       : 31;
    };
} aes_blk_key_in_status_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_key_in_status_v1_t       aes_blk_key_in_status_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_key_in_status_v2_t       aes_blk_key_in_status_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} key_in_status (AES_KEY_IN_STATUS) */

/*! 
 *  @addtogroup group120274 key_in0 (AES_KEY_IN0)
 *  @brief Offset = 0xc0
 *  @details AES KEY_IN[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[31:0]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in0_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[31:0]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in0_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_key_in0_v1_t             aes_blk_key_in0_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_key_in0_v2_t             aes_blk_key_in0_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} key_in0 (AES_KEY_IN0) */

/*! 
 *  @addtogroup group120277 key_in1 (AES_KEY_IN1)
 *  @brief Offset = 0xc4
 *  @details AES KEY_IN[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[63:32]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in1_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[63:32]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in1_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_key_in1_v1_t             aes_blk_key_in1_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_key_in1_v2_t             aes_blk_key_in1_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} key_in1 (AES_KEY_IN1) */

/*! 
 *  @addtogroup group120280 key_in2 (AES_KEY_IN2)
 *  @brief Offset = 0xc8
 *  @details AES KEY_IN[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[95:64]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in2_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[95:64]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in2_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_key_in2_v1_t             aes_blk_key_in2_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_key_in2_v2_t             aes_blk_key_in2_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} key_in2 (AES_KEY_IN2) */

/*! 
 *  @addtogroup group120283 key_in3 (AES_KEY_IN3)
 *  @brief Offset = 0xcc
 *  @details AES KEY_IN[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[127:96]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in3_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[127:96]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in3_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_key_in3_v1_t             aes_blk_key_in3_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_key_in3_v2_t             aes_blk_key_in3_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} key_in3 (AES_KEY_IN3) */

/*! 
 *  @addtogroup group120286 key_in4 (AES_KEY_IN4)
 *  @brief Offset = 0xd0
 *  @details AES KEY_IN[159:128] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[159:128]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in4_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[159:128]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in4_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_key_in4_v1_t             aes_blk_key_in4_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_key_in4_v2_t             aes_blk_key_in4_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} key_in4 (AES_KEY_IN4) */

/*! 
 *  @addtogroup group120289 key_in5 (AES_KEY_IN5)
 *  @brief Offset = 0xd4
 *  @details AES KEY_IN[191:160] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[191:160]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in5_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[191:160]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in5_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_key_in5_v1_t             aes_blk_key_in5_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_key_in5_v2_t             aes_blk_key_in5_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} key_in5 (AES_KEY_IN5) */

/*! 
 *  @addtogroup group120292 key_in6 (AES_KEY_IN6)
 *  @brief Offset = 0xd8
 *  @details AES KEY_IN[223:192] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[223:192]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in6_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[223:192]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in6_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_key_in6_v1_t             aes_blk_key_in6_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_key_in6_v2_t             aes_blk_key_in6_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} key_in6 (AES_KEY_IN6) */

/*! 
 *  @addtogroup group120295 key_in7 (AES_KEY_IN7)
 *  @brief Offset = 0xdc
 *  @details AES KEY_IN[255:224] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[255:224]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in7_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  key_in[255:224]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_key_in7_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_key_in7_v1_t             aes_blk_key_in7_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_key_in7_v2_t             aes_blk_key_in7_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} key_in7 (AES_KEY_IN7) */

/*! 
 *  @addtogroup group120298 iv_in_control (AES_IV_IN_CONTROL)
 *  @brief Offset = 0xe0
 *  @details AES IV_IN Control Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Set this field to load the IV stored in the AES_IV_IN registers to
         *  the IV context specified by the iv_in_ctx field.
         */
        uint32_t  iv_in_val  : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Selects which IV context is updated
         */
        uint32_t  iv_in_ctx  : 1;

        /*! 
         *  Range = 31:2 | Width = 30 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0      : 30;
    };
} aes_blk_iv_in_control_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = write-auto-clear | Default = 0x0 @n
         *  Set this field to load the IV stored in the AES_IV_IN registers to
         *  the IV context specified by the iv_in_ctx field.
         */
        uint32_t  iv_in_val  : 1;

        /*! 
         *  Range = 1 | Width = 1 | Access = read-write | Default = 0x0 @n
         *  Selects which IV context is updated
         */
        uint32_t  iv_in_ctx  : 1;

        /*! 
         *  Range = 31:2 | Width = 30 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0      : 30;
    };
} aes_blk_iv_in_control_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv_in_control_v1_t       aes_blk_iv_in_control_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv_in_control_v2_t       aes_blk_iv_in_control_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv_in_control (AES_IV_IN_CONTROL) */

/*! 
 *  @addtogroup group120303 iv_in0 (AES_IV_IN0)
 *  @brief Offset = 0x100
 *  @details AES IV_IN[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  iv_in[31:0]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_iv_in0_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  iv_in[31:0]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_iv_in0_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv_in0_v1_t              aes_blk_iv_in0_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv_in0_v2_t              aes_blk_iv_in0_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv_in0 (AES_IV_IN0) */

/*! 
 *  @addtogroup group120306 iv_in1 (AES_IV_IN1)
 *  @brief Offset = 0x104
 *  @details AES IV_IN[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  iv_in[63:32]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_iv_in1_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  iv_in[63:32]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_iv_in1_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv_in1_v1_t              aes_blk_iv_in1_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv_in1_v2_t              aes_blk_iv_in1_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv_in1 (AES_IV_IN1) */

/*! 
 *  @addtogroup group120309 iv_in2 (AES_IV_IN2)
 *  @brief Offset = 0x108
 *  @details AES IV_IN[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  iv_in[95:64]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_iv_in2_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  iv_in[95:64]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_iv_in2_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv_in2_v1_t              aes_blk_iv_in2_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv_in2_v2_t              aes_blk_iv_in2_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv_in2 (AES_IV_IN2) */

/*! 
 *  @addtogroup group120312 iv_in3 (AES_IV_IN3)
 *  @brief Offset = 0x10c
 *  @details AES IV_IN[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  iv_in[127:96]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_iv_in3_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  iv_in[127:96]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_iv_in3_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv_in3_v1_t              aes_blk_iv_in3_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv_in3_v2_t              aes_blk_iv_in3_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv_in3 (AES_IV_IN3) */

/*! 
 *  @addtogroup group120315 iv0_out0 (AES_IV0_OUT0)
 *  @brief Offset = 0x140
 *  @details AES IV0_OUT[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV0_OUT[31:0]
         */
        uint32_t  iv_out0  : 32;
    };
} aes_blk_iv0_out0_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV0_OUT[31:0]
         */
        uint32_t  iv_out0  : 32;
    };
} aes_blk_iv0_out0_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv0_out0_v1_t            aes_blk_iv0_out0_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv0_out0_v2_t            aes_blk_iv0_out0_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv0_out0 (AES_IV0_OUT0) */

/*! 
 *  @addtogroup group120318 iv0_out1 (AES_IV0_OUT1)
 *  @brief Offset = 0x144
 *  @details AES IV0_OUT[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV0_OUT[63:32]
         */
        uint32_t  iv_out1  : 32;
    };
} aes_blk_iv0_out1_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV0_OUT[63:32]
         */
        uint32_t  iv_out1  : 32;
    };
} aes_blk_iv0_out1_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv0_out1_v1_t            aes_blk_iv0_out1_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv0_out1_v2_t            aes_blk_iv0_out1_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv0_out1 (AES_IV0_OUT1) */

/*! 
 *  @addtogroup group120321 iv0_out2 (AES_IV0_OUT2)
 *  @brief Offset = 0x148
 *  @details AES IV0_OUT[96:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV0_OUT[95:64]
         */
        uint32_t  iv_out2  : 32;
    };
} aes_blk_iv0_out2_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV0_OUT[95:64]
         */
        uint32_t  iv_out2  : 32;
    };
} aes_blk_iv0_out2_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv0_out2_v1_t            aes_blk_iv0_out2_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv0_out2_v2_t            aes_blk_iv0_out2_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv0_out2 (AES_IV0_OUT2) */

/*! 
 *  @addtogroup group120324 iv0_out3 (AES_IV0_OUT3)
 *  @brief Offset = 0x14c
 *  @details AES IV0_OUT[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV0_OUT[127:96]
         */
        uint32_t  iv_out3  : 32;
    };
} aes_blk_iv0_out3_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV0_OUT[127:96]
         */
        uint32_t  iv_out3  : 32;
    };
} aes_blk_iv0_out3_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv0_out3_v1_t            aes_blk_iv0_out3_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv0_out3_v2_t            aes_blk_iv0_out3_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv0_out3 (AES_IV0_OUT3) */

/*! 
 *  @addtogroup group120327 iv1_out0 (AES_IV1_OUT0)
 *  @brief Offset = 0x150
 *  @details AES IV1_OUT[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV1_OUT[31:0]
         */
        uint32_t  iv_out0  : 32;
    };
} aes_blk_iv1_out0_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV1_OUT[31:0]
         */
        uint32_t  iv_out0  : 32;
    };
} aes_blk_iv1_out0_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv1_out0_v1_t            aes_blk_iv1_out0_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv1_out0_v2_t            aes_blk_iv1_out0_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv1_out0 (AES_IV1_OUT0) */

/*! 
 *  @addtogroup group120330 iv1_out1 (AES_IV1_OUT1)
 *  @brief Offset = 0x154
 *  @details AES IV1_OUT[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV1_OUT[63:32]
         */
        uint32_t  iv_out1  : 32;
    };
} aes_blk_iv1_out1_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV1_OUT[63:32]
         */
        uint32_t  iv_out1  : 32;
    };
} aes_blk_iv1_out1_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv1_out1_v1_t            aes_blk_iv1_out1_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv1_out1_v2_t            aes_blk_iv1_out1_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv1_out1 (AES_IV1_OUT1) */

/*! 
 *  @addtogroup group120333 iv1_out2 (AES_IV1_OUT2)
 *  @brief Offset = 0x158
 *  @details AES IV1_OUT[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV1_OUT[95:64]
         */
        uint32_t  iv_out2  : 32;
    };
} aes_blk_iv1_out2_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV1_OUT[95:64]
         */
        uint32_t  iv_out2  : 32;
    };
} aes_blk_iv1_out2_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv1_out2_v1_t            aes_blk_iv1_out2_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv1_out2_v2_t            aes_blk_iv1_out2_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv1_out2 (AES_IV1_OUT2) */

/*! 
 *  @addtogroup group120336 iv1_out3 (AES_IV1_OUT3)
 *  @brief Offset = 0x15c
 *  @details AES IV1_OUT[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV1_OUT[127:96]
         */
        uint32_t  iv_out3  : 32;
    };
} aes_blk_iv1_out3_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  IV1_OUT[127:96]
         */
        uint32_t  iv_out3  : 32;
    };
} aes_blk_iv1_out3_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_iv1_out3_v1_t            aes_blk_iv1_out3_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_iv1_out3_v2_t            aes_blk_iv1_out3_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} iv1_out3 (AES_IV1_OUT3) */

/*! 
 *  @addtogroup group120339 skg_key_cnt_in (AES_SKG_KEY_CNT_IN)
 *  @brief Offset = 0x160
 *  @details AES SKG_KEY_CNT_IN Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  This register specifies the number of AES operations
         *  (skg_key_cnt_in+1) that are performed by legacy SKG unwrap logic.
         *  This field can also be used to abort SKG operations by writing 0 to
         *  this register
         */
        uint32_t  fld   : 32;
    };
} aes_blk_skg_key_cnt_in_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  This register specifies the number of AES operations
         *  (skg_key_cnt_in+1) that are performed by legacy SKG unwrap logic.
         *  This field can also be used to abort SKG operations by writing 0 to
         *  this register
         */
        uint32_t  fld   : 32;
    };
} aes_blk_skg_key_cnt_in_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_skg_key_cnt_in_v1_t      aes_blk_skg_key_cnt_in_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_skg_key_cnt_in_v2_t      aes_blk_skg_key_cnt_in_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} skg_key_cnt_in (AES_SKG_KEY_CNT_IN) */

/*! 
 *  @addtogroup group120342 skg_key_cnt_out (AES_SKG_KEY_CNT_OUT)
 *  @brief Offset = 0x164
 *  @details AES SKG_KEY_CNT_OUT Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  This register specifies the number of AES operations that have been
         *  performed during legacy SKG unwrap.
         */
        uint32_t  skg_key_cnt  : 32;
    };
} aes_blk_skg_key_cnt_out_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  This register specifies the number of AES operations that have been
         *  performed during legacy SKG unwrap.
         */
        uint32_t  skg_key_cnt  : 32;
    };
} aes_blk_skg_key_cnt_out_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_skg_key_cnt_out_v1_t     aes_blk_skg_key_cnt_out_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_skg_key_cnt_out_v2_t     aes_blk_skg_key_cnt_out_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} skg_key_cnt_out (AES_SKG_KEY_CNT_OUT) */

/*! 
 *  @addtogroup group120345 dsb_r1_in0 (AES_DSB_R1_IN0)
 *  @brief Offset = 0x180
 *  @details AES DSB_R1_IN[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R1_IN[31:0]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r1_in0_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R1_IN[31:0]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r1_in0_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_dsb_r1_in0_v1_t          aes_blk_dsb_r1_in0_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_dsb_r1_in0_v2_t          aes_blk_dsb_r1_in0_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} dsb_r1_in0 (AES_DSB_R1_IN0) */

/*! 
 *  @addtogroup group120348 dsb_r1_in1 (AES_DSB_R1_IN1)
 *  @brief Offset = 0x184
 *  @details AES DSB_R1_IN[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R1_IN[63:32]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r1_in1_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R1_IN[63:32]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r1_in1_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_dsb_r1_in1_v1_t          aes_blk_dsb_r1_in1_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_dsb_r1_in1_v2_t          aes_blk_dsb_r1_in1_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} dsb_r1_in1 (AES_DSB_R1_IN1) */

/*! 
 *  @addtogroup group120351 dsb_r1_in2 (AES_DSB_R1_IN2)
 *  @brief Offset = 0x188
 *  @details AES DSB_R1_IN[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R1_IN[95:64]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r1_in2_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R1_IN[95:64]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r1_in2_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_dsb_r1_in2_v1_t          aes_blk_dsb_r1_in2_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_dsb_r1_in2_v2_t          aes_blk_dsb_r1_in2_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} dsb_r1_in2 (AES_DSB_R1_IN2) */

/*! 
 *  @addtogroup group120354 dsb_r1_in3 (AES_DSB_R1_IN3)
 *  @brief Offset = 0x18c
 *  @details AES DSB_R1_IN[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R1_IN[127:96]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r1_in3_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R1_IN[127:96]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r1_in3_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_dsb_r1_in3_v1_t          aes_blk_dsb_r1_in3_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_dsb_r1_in3_v2_t          aes_blk_dsb_r1_in3_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} dsb_r1_in3 (AES_DSB_R1_IN3) */

/*! 
 *  @addtogroup group120357 dsb_r2_in0 (AES_DSB_R2_IN0)
 *  @brief Offset = 0x1c0
 *  @details AES DSB_R2_IN[31:0] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R2_IN[31:0]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r2_in0_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R2_IN[31:0]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r2_in0_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_dsb_r2_in0_v1_t          aes_blk_dsb_r2_in0_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_dsb_r2_in0_v2_t          aes_blk_dsb_r2_in0_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} dsb_r2_in0 (AES_DSB_R2_IN0) */

/*! 
 *  @addtogroup group120360 dsb_r2_in1 (AES_DSB_R2_IN1)
 *  @brief Offset = 0x1c4
 *  @details AES DSB_R2_IN[63:32] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R2_IN[63:32]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r2_in1_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R2_IN[63:32]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r2_in1_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_dsb_r2_in1_v1_t          aes_blk_dsb_r2_in1_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_dsb_r2_in1_v2_t          aes_blk_dsb_r2_in1_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} dsb_r2_in1 (AES_DSB_R2_IN1) */

/*! 
 *  @addtogroup group120363 dsb_r2_in2 (AES_DSB_R2_IN2)
 *  @brief Offset = 0x1c8
 *  @details AES DSB_R2_IN[95:64] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R2_IN[95:64]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r2_in2_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R2_IN[95:64]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r2_in2_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_dsb_r2_in2_v1_t          aes_blk_dsb_r2_in2_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_dsb_r2_in2_v2_t          aes_blk_dsb_r2_in2_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} dsb_r2_in2 (AES_DSB_R2_IN2) */

/*! 
 *  @addtogroup group120366 dsb_r2_in3 (AES_DSB_R2_IN3)
 *  @brief Offset = 0x1cc
 *  @details AES DSB_R2_IN[127:96] Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R2_IN[127:96]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r2_in3_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-write | Default = 0x0 @n
         *  DSB_R2_IN[127:96]
         */
        uint32_t  fld   : 32;
    };
} aes_blk_dsb_r2_in3_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_dsb_r2_in3_v1_t          aes_blk_dsb_r2_in3_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_dsb_r2_in3_v2_t          aes_blk_dsb_r2_in3_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} dsb_r2_in3 (AES_DSB_R2_IN3) */

/*! 
 *  @addtogroup group120369 err (AES_ERR)
 *  @brief Offset = 0x1d0
 *  @details AES Error Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  If the GID0, GID1, UID1, or Fairplay key descrambler is selected
         *  for use when disabled, then the error bit is set.  The error bit is
         *  sticky and is only cleared on a chip reset.
         */
        uint32_t  fld    : 1;

        /*! 
         *  Range = 31:1 | Width = 31 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0  : 31;
    };
} aes_blk_err_v1_t;

typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 0 | Width = 1 | Access = read-only | Default = 0x0 @n
         *  If the GID0, GID1, UID1, UID2, or Fairplay key descrambler is
         *  selected for use when disabled, then the error bit is set.  The
         *  error bit is sticky and is only cleared on a reset.
         */
        uint32_t  fld    : 1;

        /*! 
         *  Range = 31:1 | Width = 31 | Access = read-as-zero | Default = 0x0 @n
         *  Reserved
         */
        uint32_t  rsvd0  : 31;
    };
} aes_blk_err_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_blk_err_v1_t                 aes_blk_err_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_err_v2_t                 aes_blk_err_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} err (AES_ERR) */

/*! 
 *  @addtogroup group120236 txt_in_data (AES_TXT_IN_DATA)
 *  @brief Offset = 0x40
 *  @details AES Cipher TXT_IN Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = write_only | Default = 0x0 @n
         *  txt_in to fifo
         */
        uint32_t  txt_in  : 32;
    };
} aes_blk_txt_in_data_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_txt_in_data_v2_t         aes_blk_txt_in_data_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_in_data (AES_TXT_IN_DATA) */

/*! 
 *  @addtogroup group120245 txt_out_data (AES_TXT_OUT_DATA)
 *  @brief Offset = 0x80
 *  @details AES Cipher TXT_OUT Register
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t      raw;
    struct
    {
        /*! 
         *  Range = 31:0 | Width = 32 | Access = read-only | Default = 0x0 @n
         *  txt_out from fifo
         */
        uint32_t  txt_out  : 32;
    };
} aes_blk_txt_out_data_v2_t;

#if      SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_blk_txt_out_data_v2_t        aes_blk_txt_out_data_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} txt_out_data (AES_TXT_OUT_DATA) */

#ifdef SPDS_ENABLE_STRUCTS
typedef struct
{
    /*! 
     *  Offset = 0x0 @n
     *  IP Implementation Version
     */
    aes_blk_version_v3_t              version;

    /*! 
     *  Offset = 0x4 @n
     *  Configuration register
     */
    aes_blk_config_v3_t               config;

    /*! 
     *  Offset = 0x8 @n
     *  Control Register
     */
    aes_blk_control_v3_t              control;

    /*! 
     *  Offset = 0xc @n
     *  Channel status register
     */
    aes_blk_status_v3_t               status;

    /*! 
     *  Offset = 0x10 @n
     *  Current Key IDs
     */
    aes_blk_key_id_v3_t               key_id;

    /*! 
     *  Offset = 0x14 @n
     *  AXI status register
     */
    aes_blk_axi_status_v3_t           axi_status;

    /*! 
     *  Offset = 0x18 @n
     *  Channel interrupt status register
     */
    aes_blk_int_status_v3_t           int_status;

    /*! 
     *  Offset = 0x1c @n
     *  Channel interrupt enable register
     */
    aes_blk_int_enable_v3_t           int_enable;

    /*! 
     *  Offset = 0x20 @n
     *  Watermarks for FIFO interrupts.
     */
    aes_blk_watermarks_v3_t           watermarks;

    /*! 
     *  Offset = 0x24 @n
     *  Status information for the Command Queue
     */
    aes_blk_command_fifo_status_v3_t  command_fifo_status;

    /*! 
     *  Offset = 0x28 @n
     *  Status information for the DMA Debug FIFO
     */
    aes_blk_history_fifo_status_v3_t  history_fifo_status;

    /*! 
     *  Offset = 0x2c @n
     *  Total count of commands since the Command FIFO was last enabled
     */
    aes_blk_command_fifo_count_v3_t   command_fifo_count;

    /*! 
     *  Offset = 0x30 @n
     *  Interrupt code that provides information about the flag interrupt that
     *  occurred.
     */
    aes_blk_flag_command_v3_t         flag_command;

    /*! 
     *  Offset = 0x34 @n
     *  Secure Key Generation Key
     */
    aes_blk_skg_key_v3_t              skg_key;
    uint8_t                           rsvd0[200];

    /*! 
     *  Offset = 0x100 @n
     *  Command FIFO. FIFO Depth is (128) Words
     */
    aes_blk_command_fifo_v3_t         command_fifo;
    uint8_t                           rsvd1[252];

    /*! 
     *  Offset = 0x200 @n
     *  Last (32) Commands words
     */
    aes_blk_history_fifo_v3_t         history_fifo;
} aes_blk_v3_t;
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} blk (AES) */

/*! 
 *  @addtogroup group581457 command_fifo_direct_access
 *  @brief Offset = 0x4000
 *  @details Direct read access to 128 X 32 Command FIFO
 *  @see @ref SAIAddressBlock
 *  @{
 */

/*! 
 *  @addtogroup group581458 word
 *  @brief Offset = 0x0
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint64_t  raw[2];
} aes_command_fifo_direct_access_word_v3_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_command_fifo_direct_access_word_v3_t  aes_command_fifo_direct_access_word_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} word */

#ifdef SPDS_ENABLE_STRUCTS
typedef struct
{
    /*! Offset = 0x0 */
    aes_command_fifo_direct_access_word_v3_t  word;
} aes_command_fifo_direct_access_v3_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_command_fifo_direct_access_v3_t  aes_command_fifo_direct_access_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} command_fifo_direct_access */

/*! 
 *  @addtogroup group581460 history_fifo_direct_access
 *  @brief Offset = 0x4600
 *  @details Direct read access to 32 word History FIFO
 *  @see @ref SAIAddressBlock
 *  @{
 */

/*! 
 *  @addtogroup group581461 command
 *  @brief Offset = 0x0
 *  @details Command Word Data
 *  @see @ref SAIRegister
 *  @{
 */

#ifdef SPDS_ENABLE_STRUCTS
typedef union
{
    uint32_t  raw;
} aes_history_fifo_direct_access_command_v3_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_history_fifo_direct_access_command_v3_t  aes_history_fifo_direct_access_command_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} command */

#ifdef SPDS_ENABLE_STRUCTS
typedef struct
{
    /*! 
     *  Offset = 0x0 @n
     *  Command Word Data
     */
    aes_history_fifo_direct_access_command_v3_t  command;
} aes_history_fifo_direct_access_v3_t;

#if      SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_history_fifo_direct_access_v3_t  aes_history_fifo_direct_access_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} history_fifo_direct_access */

#ifdef SPDS_ENABLE_STRUCTS
typedef struct
{
    /*! 
     *  Offset = 0x0 @n
     *  AES Status Register
     */
    aes_blk_status_v1_t           status;

    /*! 
     *  Offset = 0x4 @n
     *  AES GID0, GID1, UID1 and Fairplay Descrambler Disable register
     */
    aes_blk_disable_v1_t          disable;

    /*! 
     *  Offset = 0x8 @n
     *  AES Cipher TXT_IN Control Register
     */
    aes_blk_txt_in_control_v1_t   txt_in_control;

    /*! 
     *  Offset = 0xc @n
     *  AES Cipher TXT_IN Status register
     */
    aes_blk_txt_in_status_v1_t    txt_in_status;
    uint8_t                       rsvd0[48];

    /*! 
     *  Offset = 0x40 @n
     *  AES Cipher TXT_IN[31:0] Register
     */
    aes_blk_txt_in0_v1_t          txt_in0;

    /*! 
     *  Offset = 0x44 @n
     *  AES Cipher TXT_IN[63:32] Register
     */
    aes_blk_txt_in1_v1_t          txt_in1;

    /*! 
     *  Offset = 0x48 @n
     *  AES Cipher TXT_IN[95:64] Register
     */
    aes_blk_txt_in2_v1_t          txt_in2;

    /*! 
     *  Offset = 0x4c @n
     *  AES Cipher TXT_IN[127:96] Register
     */
    aes_blk_txt_in3_v1_t          txt_in3;

    /*! 
     *  Offset = 0x50 @n
     *  AES Cipher TXT_OUT Status Register
     */
    aes_blk_txt_out_status_v1_t   txt_out_status;
    uint8_t                       rsvd1[44];

    /*! 
     *  Offset = 0x80 @n
     *  AES Cipher TXT_OUT[31:0] Register
     */
    aes_blk_txt_out0_v1_t         txt_out0;

    /*! 
     *  Offset = 0x84 @n
     *  AES Cipher TXT_OUT[63:32] Register
     */
    aes_blk_txt_out1_v1_t         txt_out1;

    /*! 
     *  Offset = 0x88 @n
     *  AES Cipher TXT_OUT[95:64] Register
     */
    aes_blk_txt_out2_v1_t         txt_out2;

    /*! 
     *  Offset = 0x8c @n
     *  AES Cipher TXT_OUT[127:96] Register
     */
    aes_blk_txt_out3_v1_t         txt_out3;

    /*! 
     *  Offset = 0x90 @n
     *  AES KEY_IN Control Register
     */
    aes_blk_key_in_control_v1_t   key_in_control;

    /*! 
     *  Offset = 0x94 @n
     *  AES KEY_IN Status Register
     */
    aes_blk_key_in_status_v1_t    key_in_status;
    uint8_t                       rsvd2[40];

    /*! 
     *  Offset = 0xc0 @n
     *  AES KEY_IN[31:0] Register
     */
    aes_blk_key_in0_v1_t          key_in0;

    /*! 
     *  Offset = 0xc4 @n
     *  AES KEY_IN[63:32] Register
     */
    aes_blk_key_in1_v1_t          key_in1;

    /*! 
     *  Offset = 0xc8 @n
     *  AES KEY_IN[95:64] Register
     */
    aes_blk_key_in2_v1_t          key_in2;

    /*! 
     *  Offset = 0xcc @n
     *  AES KEY_IN[127:96] Register
     */
    aes_blk_key_in3_v1_t          key_in3;

    /*! 
     *  Offset = 0xd0 @n
     *  AES KEY_IN[159:128] Register
     */
    aes_blk_key_in4_v1_t          key_in4;

    /*! 
     *  Offset = 0xd4 @n
     *  AES KEY_IN[191:160] Register
     */
    aes_blk_key_in5_v1_t          key_in5;

    /*! 
     *  Offset = 0xd8 @n
     *  AES KEY_IN[223:192] Register
     */
    aes_blk_key_in6_v1_t          key_in6;

    /*! 
     *  Offset = 0xdc @n
     *  AES KEY_IN[255:224] Register
     */
    aes_blk_key_in7_v1_t          key_in7;

    /*! 
     *  Offset = 0xe0 @n
     *  AES IV_IN Control Register
     */
    aes_blk_iv_in_control_v1_t    iv_in_control;
    uint8_t                       rsvd3[28];

    /*! 
     *  Offset = 0x100 @n
     *  AES IV_IN[31:0] Register
     */
    aes_blk_iv_in0_v1_t           iv_in0;

    /*! 
     *  Offset = 0x104 @n
     *  AES IV_IN[63:32] Register
     */
    aes_blk_iv_in1_v1_t           iv_in1;

    /*! 
     *  Offset = 0x108 @n
     *  AES IV_IN[95:64] Register
     */
    aes_blk_iv_in2_v1_t           iv_in2;

    /*! 
     *  Offset = 0x10c @n
     *  AES IV_IN[127:96] Register
     */
    aes_blk_iv_in3_v1_t           iv_in3;
    uint8_t                       rsvd4[48];

    /*! 
     *  Offset = 0x140 @n
     *  AES IV0_OUT[31:0] Register
     */
    aes_blk_iv0_out0_v1_t         iv0_out0;

    /*! 
     *  Offset = 0x144 @n
     *  AES IV0_OUT[63:32] Register
     */
    aes_blk_iv0_out1_v1_t         iv0_out1;

    /*! 
     *  Offset = 0x148 @n
     *  AES IV0_OUT[96:64] Register
     */
    aes_blk_iv0_out2_v1_t         iv0_out2;

    /*! 
     *  Offset = 0x14c @n
     *  AES IV0_OUT[127:96] Register
     */
    aes_blk_iv0_out3_v1_t         iv0_out3;

    /*! 
     *  Offset = 0x150 @n
     *  AES IV1_OUT[31:0] Register
     */
    aes_blk_iv1_out0_v1_t         iv1_out0;

    /*! 
     *  Offset = 0x154 @n
     *  AES IV1_OUT[63:32] Register
     */
    aes_blk_iv1_out1_v1_t         iv1_out1;

    /*! 
     *  Offset = 0x158 @n
     *  AES IV1_OUT[95:64] Register
     */
    aes_blk_iv1_out2_v1_t         iv1_out2;

    /*! 
     *  Offset = 0x15c @n
     *  AES IV1_OUT[127:96] Register
     */
    aes_blk_iv1_out3_v1_t         iv1_out3;

    /*! 
     *  Offset = 0x160 @n
     *  AES SKG_KEY_CNT_IN Register
     */
    aes_blk_skg_key_cnt_in_v1_t   skg_key_cnt_in;

    /*! 
     *  Offset = 0x164 @n
     *  AES SKG_KEY_CNT_OUT Register
     */
    aes_blk_skg_key_cnt_out_v1_t  skg_key_cnt_out;
    uint8_t                       rsvd5[24];

    /*! 
     *  Offset = 0x180 @n
     *  AES DSB_R1_IN[31:0] Register
     */
    aes_blk_dsb_r1_in0_v1_t       dsb_r1_in0;

    /*! 
     *  Offset = 0x184 @n
     *  AES DSB_R1_IN[63:32] Register
     */
    aes_blk_dsb_r1_in1_v1_t       dsb_r1_in1;

    /*! 
     *  Offset = 0x188 @n
     *  AES DSB_R1_IN[95:64] Register
     */
    aes_blk_dsb_r1_in2_v1_t       dsb_r1_in2;

    /*! 
     *  Offset = 0x18c @n
     *  AES DSB_R1_IN[127:96] Register
     */
    aes_blk_dsb_r1_in3_v1_t       dsb_r1_in3;
    uint8_t                       rsvd6[48];

    /*! 
     *  Offset = 0x1c0 @n
     *  AES DSB_R2_IN[31:0] Register
     */
    aes_blk_dsb_r2_in0_v1_t       dsb_r2_in0;

    /*! 
     *  Offset = 0x1c4 @n
     *  AES DSB_R2_IN[63:32] Register
     */
    aes_blk_dsb_r2_in1_v1_t       dsb_r2_in1;

    /*! 
     *  Offset = 0x1c8 @n
     *  AES DSB_R2_IN[95:64] Register
     */
    aes_blk_dsb_r2_in2_v1_t       dsb_r2_in2;

    /*! 
     *  Offset = 0x1cc @n
     *  AES DSB_R2_IN[127:96] Register
     */
    aes_blk_dsb_r2_in3_v1_t       dsb_r2_in3;

    /*! 
     *  Offset = 0x1d0 @n
     *  AES Error Register
     */
    aes_blk_err_v1_t              err;
} aes_v1_t;

typedef struct
{
    /*! 
     *  Offset = 0x0 @n
     *  AES Status Register
     */
    aes_blk_status_v2_t           status;
    uint8_t                       rsvd0[4];

    /*! 
     *  Offset = 0x8 @n
     *  AES Cipher TXT_IN Control Register
     */
    aes_blk_txt_in_control_v2_t   txt_in_control;

    /*! 
     *  Offset = 0xc @n
     *  AES Cipher TXT_IN Status register
     */
    aes_blk_txt_in_status_v2_t    txt_in_status;
    uint8_t                       rsvd1[48];

    /*! 
     *  Offset = 0x40 @n
     *  AES Cipher TXT_IN Register
     */
    aes_blk_txt_in_data_v2_t      txt_in_data;
    uint8_t                       rsvd2[12];

    /*! 
     *  Offset = 0x50 @n
     *  AES Cipher TXT_OUT Status Register
     */
    aes_blk_txt_out_status_v2_t   txt_out_status;
    uint8_t                       rsvd3[44];

    /*! 
     *  Offset = 0x80 @n
     *  AES Cipher TXT_OUT Register
     */
    aes_blk_txt_out_data_v2_t     txt_out_data;
    uint8_t                       rsvd4[12];

    /*! 
     *  Offset = 0x90 @n
     *  AES KEY_IN Control Register
     */
    aes_blk_key_in_control_v2_t   key_in_control;

    /*! 
     *  Offset = 0x94 @n
     *  AES KEY_IN Status Register
     */
    aes_blk_key_in_status_v2_t    key_in_status;
    uint8_t                       rsvd5[40];

    /*! 
     *  Offset = 0xc0 @n
     *  AES KEY_IN[31:0] Register
     */
    aes_blk_key_in0_v2_t          key_in0;

    /*! 
     *  Offset = 0xc4 @n
     *  AES KEY_IN[63:32] Register
     */
    aes_blk_key_in1_v2_t          key_in1;

    /*! 
     *  Offset = 0xc8 @n
     *  AES KEY_IN[95:64] Register
     */
    aes_blk_key_in2_v2_t          key_in2;

    /*! 
     *  Offset = 0xcc @n
     *  AES KEY_IN[127:96] Register
     */
    aes_blk_key_in3_v2_t          key_in3;

    /*! 
     *  Offset = 0xd0 @n
     *  AES KEY_IN[159:128] Register
     */
    aes_blk_key_in4_v2_t          key_in4;

    /*! 
     *  Offset = 0xd4 @n
     *  AES KEY_IN[191:160] Register
     */
    aes_blk_key_in5_v2_t          key_in5;

    /*! 
     *  Offset = 0xd8 @n
     *  AES KEY_IN[223:192] Register
     */
    aes_blk_key_in6_v2_t          key_in6;

    /*! 
     *  Offset = 0xdc @n
     *  AES KEY_IN[255:224] Register
     */
    aes_blk_key_in7_v2_t          key_in7;

    /*! 
     *  Offset = 0xe0 @n
     *  AES IV_IN Control Register
     */
    aes_blk_iv_in_control_v2_t    iv_in_control;
    uint8_t                       rsvd6[28];

    /*! 
     *  Offset = 0x100 @n
     *  AES IV_IN[31:0] Register
     */
    aes_blk_iv_in0_v2_t           iv_in0;

    /*! 
     *  Offset = 0x104 @n
     *  AES IV_IN[63:32] Register
     */
    aes_blk_iv_in1_v2_t           iv_in1;

    /*! 
     *  Offset = 0x108 @n
     *  AES IV_IN[95:64] Register
     */
    aes_blk_iv_in2_v2_t           iv_in2;

    /*! 
     *  Offset = 0x10c @n
     *  AES IV_IN[127:96] Register
     */
    aes_blk_iv_in3_v2_t           iv_in3;
    uint8_t                       rsvd7[48];

    /*! 
     *  Offset = 0x140 @n
     *  AES IV0_OUT[31:0] Register
     */
    aes_blk_iv0_out0_v2_t         iv0_out0;

    /*! 
     *  Offset = 0x144 @n
     *  AES IV0_OUT[63:32] Register
     */
    aes_blk_iv0_out1_v2_t         iv0_out1;

    /*! 
     *  Offset = 0x148 @n
     *  AES IV0_OUT[96:64] Register
     */
    aes_blk_iv0_out2_v2_t         iv0_out2;

    /*! 
     *  Offset = 0x14c @n
     *  AES IV0_OUT[127:96] Register
     */
    aes_blk_iv0_out3_v2_t         iv0_out3;

    /*! 
     *  Offset = 0x150 @n
     *  AES IV1_OUT[31:0] Register
     */
    aes_blk_iv1_out0_v2_t         iv1_out0;

    /*! 
     *  Offset = 0x154 @n
     *  AES IV1_OUT[63:32] Register
     */
    aes_blk_iv1_out1_v2_t         iv1_out1;

    /*! 
     *  Offset = 0x158 @n
     *  AES IV1_OUT[95:64] Register
     */
    aes_blk_iv1_out2_v2_t         iv1_out2;

    /*! 
     *  Offset = 0x15c @n
     *  AES IV1_OUT[127:96] Register
     */
    aes_blk_iv1_out3_v2_t         iv1_out3;

    /*! 
     *  Offset = 0x160 @n
     *  AES SKG_KEY_CNT_IN Register
     */
    aes_blk_skg_key_cnt_in_v2_t   skg_key_cnt_in;

    /*! 
     *  Offset = 0x164 @n
     *  AES SKG_KEY_CNT_OUT Register
     */
    aes_blk_skg_key_cnt_out_v2_t  skg_key_cnt_out;
    uint8_t                       rsvd8[24];

    /*! 
     *  Offset = 0x180 @n
     *  AES DSB_R1_IN[31:0] Register
     */
    aes_blk_dsb_r1_in0_v2_t       dsb_r1_in0;

    /*! 
     *  Offset = 0x184 @n
     *  AES DSB_R1_IN[63:32] Register
     */
    aes_blk_dsb_r1_in1_v2_t       dsb_r1_in1;

    /*! 
     *  Offset = 0x188 @n
     *  AES DSB_R1_IN[95:64] Register
     */
    aes_blk_dsb_r1_in2_v2_t       dsb_r1_in2;

    /*! 
     *  Offset = 0x18c @n
     *  AES DSB_R1_IN[127:96] Register
     */
    aes_blk_dsb_r1_in3_v2_t       dsb_r1_in3;
    uint8_t                       rsvd9[48];

    /*! 
     *  Offset = 0x1c0 @n
     *  AES DSB_R2_IN[31:0] Register
     */
    aes_blk_dsb_r2_in0_v2_t       dsb_r2_in0;

    /*! 
     *  Offset = 0x1c4 @n
     *  AES DSB_R2_IN[63:32] Register
     */
    aes_blk_dsb_r2_in1_v2_t       dsb_r2_in1;

    /*! 
     *  Offset = 0x1c8 @n
     *  AES DSB_R2_IN[95:64] Register
     */
    aes_blk_dsb_r2_in2_v2_t       dsb_r2_in2;

    /*! 
     *  Offset = 0x1cc @n
     *  AES DSB_R2_IN[127:96] Register
     */
    aes_blk_dsb_r2_in3_v2_t       dsb_r2_in3;

    /*! 
     *  Offset = 0x1d0 @n
     *  AES Error Register
     */
    aes_blk_err_v2_t              err;
} aes_v2_t;

typedef struct
{
    /*! 
     *  Offset = 0x0 @n
     *  General Control registers
     */
    aes_blk_v3_t                         blk;
    uint8_t                              rsvd0[15868];

    /*! 
     *  Offset = 0x4000 @n
     *  Direct read access to 128 X 32 Command FIFO
     */
    aes_command_fifo_direct_access_v3_t  command_fifo_direct_access;
    uint8_t                              rsvd1[1520];

    /*! 
     *  Offset = 0x4600 @n
     *  Direct read access to 32 word History FIFO
     */
    aes_history_fifo_direct_access_v3_t  history_fifo_direct_access;
} aes_v3_t;

typedef struct
{
    /*! 
     *  Offset = 0x0 @n
     *  IP Implementation Version
     */
    aes_blk_version_v4_t              version;

    /*! 
     *  Offset = 0x4 @n
     *  Configuration register
     */
    aes_blk_config_v4_t               config;

    /*! 
     *  Offset = 0x8 @n
     *  Control Register
     */
    aes_blk_control_v4_t              control;

    /*! 
     *  Offset = 0xc @n
     *  Channel status register
     */
    aes_blk_status_v4_t               status;

    /*! 
     *  Offset = 0x10 @n
     *  Current Key IDs
     */
    aes_blk_key_id_v4_t               key_id;

    /*! 
     *  Offset = 0x14 @n
     *  AXI status register
     */
    aes_blk_axi_status_v4_t           axi_status;

    /*! 
     *  Offset = 0x18 @n
     *  Channel interrupt status register
     */
    aes_blk_int_status_v4_t           int_status;

    /*! 
     *  Offset = 0x1c @n
     *  Channel interrupt enable register
     */
    aes_blk_int_enable_v4_t           int_enable;

    /*! 
     *  Offset = 0x20 @n
     *  Watermarks for FIFO interrupts.
     */
    aes_blk_watermarks_v4_t           watermarks;

    /*! 
     *  Offset = 0x24 @n
     *  Status information for the Command Queue
     */
    aes_blk_command_fifo_status_v4_t  command_fifo_status;

    /*! 
     *  Offset = 0x28 @n
     *  Status information for the DMA Debug FIFO
     */
    aes_blk_history_fifo_status_v4_t  history_fifo_status;

    /*! 
     *  Offset = 0x2c @n
     *  Total count of commands since the Command FIFO was last enabled
     */
    aes_blk_command_fifo_count_v4_t   command_fifo_count;

    /*! 
     *  Offset = 0x30 @n
     *  Interrupt code that provides information about the flag interrupt that
     *  occurred.
     */
    aes_blk_flag_command_v4_t         flag_command;

    /*! 
     *  Offset = 0x34 @n
     *  Secure Key Generation Key
     */
    aes_blk_skg_key_v4_t              skg_key;
    uint8_t                           rsvd0[200];

    /*! 
     *  Offset = 0x100 @n
     *  Command FIFO. FIFO Depth is (128) Words
     */
    aes_blk_command_fifo_v4_t         command_fifo;
    uint8_t                           rsvd1[252];

    /*! 
     *  Offset = 0x200 @n
     *  Last (32) Commands words
     */
    aes_blk_history_fifo_v4_t         history_fifo;
} aes_v4_t;

typedef struct
{
    /*! 
     *  Offset = 0x0 @n
     *  IP Implementation Version
     */
    aes_blk_version_v5_t              version;

    /*! 
     *  Offset = 0x4 @n
     *  Configuration register
     */
    aes_blk_config_v5_t               config;

    /*! 
     *  Offset = 0x8 @n
     *  Control Register
     */
    aes_blk_control_v5_t              control;

    /*! 
     *  Offset = 0xc @n
     *  Channel status register
     */
    aes_blk_status_v5_t               status;

    /*! 
     *  Offset = 0x10 @n
     *  Current Key IDs
     */
    aes_blk_key_id_v5_t               key_id;

    /*! 
     *  Offset = 0x14 @n
     *  AXI status register
     */
    aes_blk_axi_status_v5_t           axi_status;

    /*! 
     *  Offset = 0x18 @n
     *  Channel interrupt status register
     */
    aes_blk_int_status_v5_t           int_status;

    /*! 
     *  Offset = 0x1c @n
     *  Channel interrupt enable register
     */
    aes_blk_int_enable_v5_t           int_enable;

    /*! 
     *  Offset = 0x20 @n
     *  Watermarks for FIFO interrupts.
     */
    aes_blk_watermarks_v5_t           watermarks;

    /*! 
     *  Offset = 0x24 @n
     *  Status information for the Command Queue
     */
    aes_blk_command_fifo_status_v5_t  command_fifo_status;

    /*! 
     *  Offset = 0x28 @n
     *  Status information for the DMA Debug FIFO
     */
    aes_blk_history_fifo_status_v5_t  history_fifo_status;

    /*! 
     *  Offset = 0x2c @n
     *  Total count of commands since the Command FIFO was last enabled
     */
    aes_blk_command_fifo_count_v5_t   command_fifo_count;

    /*! 
     *  Offset = 0x30 @n
     *  Interrupt code that provides information about the flag interrupt that
     *  occurred.
     */
    aes_blk_flag_command_v5_t         flag_command;

    /*! 
     *  Offset = 0x34 @n
     *  Secure Key Generation Key
     */
    aes_blk_skg_key_v5_t              skg_key;

    /*! 
     *  Offset = 0x38 @n
     *  Clear COMMAND and HISTORY FIFOs
     */
    aes_blk_clear_fifos_v5_t          clear_fifos;
    uint8_t                           rsvd0[452];

    /*! 
     *  Offset = 0x200 @n
     *  Command FIFO. FIFO Depth is (128) Words
     */
    aes_blk_command_fifo_v5_t         command_fifo;
    uint8_t                           rsvd1[508];

    /*! Last (32) Commands words */
    aes_blk_history_fifo_v5_t         history_fifo[32];
} aes_v5_t;

typedef struct
{
    /*! 
     *  Offset = 0x0 @n
     *  IP Implementation Version
     */
    aes_blk_version_v6_t              version;

    /*! 
     *  Offset = 0x4 @n
     *  Configuration register
     */
    aes_blk_config_v6_t               config;

    /*! 
     *  Offset = 0x8 @n
     *  Control Register
     */
    aes_blk_control_v6_t              control;

    /*! 
     *  Offset = 0xc @n
     *  Channel status register
     */
    aes_blk_status_v6_t               status;

    /*! 
     *  Offset = 0x10 @n
     *  Current Key IDs
     */
    aes_blk_key_id_v6_t               key_id;

    /*! 
     *  Offset = 0x14 @n
     *  AXI status register
     */
    aes_blk_axi_status_v6_t           axi_status;

    /*! 
     *  Offset = 0x18 @n
     *  Channel interrupt status register
     */
    aes_blk_int_status_v6_t           int_status;

    /*! 
     *  Offset = 0x1c @n
     *  Channel interrupt enable register
     */
    aes_blk_int_enable_v6_t           int_enable;

    /*! 
     *  Offset = 0x20 @n
     *  Watermarks for FIFO interrupts.
     */
    aes_blk_watermarks_v6_t           watermarks;

    /*! 
     *  Offset = 0x24 @n
     *  Status information for the Command Queue
     */
    aes_blk_command_fifo_status_v6_t  command_fifo_status;

    /*! 
     *  Offset = 0x28 @n
     *  Status information for the DMA Debug FIFO
     */
    aes_blk_history_fifo_status_v6_t  history_fifo_status;

    /*! 
     *  Offset = 0x2c @n
     *  Total count of commands since the Command FIFO was last enabled
     */
    aes_blk_command_fifo_count_v6_t   command_fifo_count;

    /*! 
     *  Offset = 0x30 @n
     *  Interrupt code that provides information about the flag interrupt that
     *  occurred.
     */
    aes_blk_flag_command_v6_t         flag_command;

    /*! 
     *  Offset = 0x34 @n
     *  Secure Key Generation Key
     */
    aes_blk_skg_key_v6_t              skg_key;

    /*! 
     *  Offset = 0x38 @n
     *  Clear COMMAND and HISTORY FIFOs
     */
    aes_blk_clear_fifos_v6_t          clear_fifos;
    uint8_t                           rsvd0[452];

    /*! 
     *  Offset = 0x200 @n
     *  Command FIFO. FIFO Depth is (128) Words
     */
    aes_blk_command_fifo_v6_t         command_fifo;
    uint8_t                           rsvd1[508];

    /*! 
     *  Offset = 0x400 @n
     *  Last (32) Commands words
     */
    aes_blk_history_fifo_v6_t         history_fifo;
} aes_v6_t;

typedef struct
{
    /*! 
     *  Offset = 0x0 @n
     *  IP Implementation Version
     */
    aes_blk_version_v7_t              version;

    /*! 
     *  Offset = 0x4 @n
     *  Configuration register
     */
    aes_blk_config_v7_t               config;

    /*! 
     *  Offset = 0x8 @n
     *  Control Register
     */
    aes_blk_control_v7_t              control;

    /*! 
     *  Offset = 0xc @n
     *  Channel status register
     */
    aes_blk_status_v7_t               status;

    /*! 
     *  Offset = 0x10 @n
     *  Current Key IDs
     */
    aes_blk_key_id_v7_t               key_id;

    /*! 
     *  Offset = 0x14 @n
     *  AXI status register
     */
    aes_blk_axi_status_v7_t           axi_status;

    /*! 
     *  Offset = 0x18 @n
     *  Channel interrupt status register
     */
    aes_blk_int_status_v7_t           int_status;

    /*! 
     *  Offset = 0x1c @n
     *  Channel interrupt enable register
     */
    aes_blk_int_enable_v7_t           int_enable;

    /*! 
     *  Offset = 0x20 @n
     *  Watermarks for FIFO interrupts.
     */
    aes_blk_watermarks_v7_t           watermarks;

    /*! 
     *  Offset = 0x24 @n
     *  Status information for the Command Queue
     */
    aes_blk_command_fifo_status_v7_t  command_fifo_status;

    /*! 
     *  Offset = 0x28 @n
     *  Status information for the DMA Debug FIFO
     */
    aes_blk_history_fifo_status_v7_t  history_fifo_status;

    /*! 
     *  Offset = 0x2c @n
     *  Total count of commands since the Command FIFO was last enabled
     */
    aes_blk_command_fifo_count_v7_t   command_fifo_count;

    /*! 
     *  Offset = 0x30 @n
     *  Interrupt code that provides information about the flag interrupt that
     *  occurred.
     */
    aes_blk_flag_command_v7_t         flag_command;

    /*! 
     *  Offset = 0x34 @n
     *  Secure Key Generation Key
     */
    aes_blk_skg_key_v7_t              skg_key;

    /*! 
     *  Offset = 0x38 @n
     *  Clear COMMAND and HISTORY FIFOs
     */
    aes_blk_clear_fifos_v7_t          clear_fifos;
    uint8_t                           rsvd0[452];

    /*! 
     *  Offset = 0x200 @n
     *  Command FIFO. FIFO Depth is (128) Words
     */
    aes_blk_command_fifo_v7_t         command_fifo;
    uint8_t                           rsvd1[508];

    /*! Last (32) Commands words */
    aes_blk_history_fifo_v7_t         history_fifo[32];
} aes_v7_t;

#if      SPDS_AES_VERSION == SPDS_AES_V1
typedef  aes_v1_t                         aes_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V2
typedef  aes_v2_t                         aes_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V3
typedef  aes_v3_t                         aes_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V4
typedef  aes_v4_t                         aes_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V5
typedef  aes_v5_t                         aes_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V6
typedef  aes_v6_t                         aes_t;
#elif    SPDS_AES_VERSION == SPDS_AES_V7
typedef  aes_v7_t                         aes_t;
#endif
#endif /*! SPDS_ENABLE_STRUCTS */

/*! @} aes */

#endif /*! SPDS_AES_H */