/* 
 * Automatically generated by socgen. DO NOT EDIT!
 * 
 * Copyright (c) 2015 Apple Inc. All rights reserved.
 * 
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 * 
 * This document may not be reproduced or transmitted in any form
 * in whole or in part, without the express written permission of
 * Apple inc.
 */

#ifndef SPDS_S8000_B0_TUNABLE_AUSR_SHM_CFG_H
#define SPDS_S8000_B0_TUNABLE_AUSR_SHM_CFG_H

#define PCIE_APCIE_PHY_AUSR0_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1ef)
#define PCIE_APCIE_PHY_AUSR0_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xe7)

#define PCIE_APCIE_PHY_AUSR0_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
/* Key = default_tunable_key                                                      */ \
/* Register Macro Identifier       Register Offset Register Size     Tunable Mask Tunable Value */ \
{  /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50,           sizeof(uint32_t), 0x1ef,       0xe7          }, \
{                                  -1,             -1,               -1,          -1            }

#define PCIE_APCIE_PHY_AUSR1_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1ef)
#define PCIE_APCIE_PHY_AUSR1_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xe7)

#define PCIE_APCIE_PHY_AUSR1_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
/* Key = default_tunable_key                                                      */ \
/* Register Macro Identifier       Register Offset Register Size     Tunable Mask Tunable Value */ \
{  /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50,           sizeof(uint32_t), 0x1ef,       0xe7          }, \
{                                  -1,             -1,               -1,          -1            }

#define PCIE_APCIE_PHY_AUSR2_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1ef)
#define PCIE_APCIE_PHY_AUSR2_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xe7)

#define PCIE_APCIE_PHY_AUSR2_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
/* Key = default_tunable_key                                                      */ \
/* Register Macro Identifier       Register Offset Register Size     Tunable Mask Tunable Value */ \
{  /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50,           sizeof(uint32_t), 0x1ef,       0xe7          }, \
{                                  -1,             -1,               -1,          -1            }

#define PCIE_APCIE_PHY_AUSR3_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1ef)
#define PCIE_APCIE_PHY_AUSR3_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xe7)

#define PCIE_APCIE_PHY_AUSR3_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
/* Key = default_tunable_key                                                      */ \
/* Register Macro Identifier       Register Offset Register Size     Tunable Mask Tunable Value */ \
{  /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50,           sizeof(uint32_t), 0x1ef,       0xe7          }, \
{                                  -1,             -1,               -1,          -1            }

#define PCIE_APCIE_PHY_AUSR4_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_UMASK_S8000_B0 (0x1ef)
#define PCIE_APCIE_PHY_AUSR4_SHM_CFG_BLK_RXA_CFG2_DEFAULT_TUNABLE_VALUE_S8000_B0 (0xe7)

#define PCIE_APCIE_PHY_AUSR4_SHM_CFG_DEFAULT_TUNABLES_S8000_B0 \
/* Key = default_tunable_key                                                      */ \
/* Register Macro Identifier       Register Offset Register Size     Tunable Mask Tunable Value */ \
{  /* AUSR_SHM_CFG_BLK_RXA_CFG2 */ 0x50,           sizeof(uint32_t), 0x1ef,       0xe7          }, \
{                                  -1,             -1,               -1,          -1            }

#endif /* SPDS_S8000_B0_TUNABLE_AUSR_SHM_CFG_H */