# AMC Initialization Sequence

This file was created using the following files on: Tue Jul 14 10:45:09 2015
AMC Version: 14 Major Release: 2 Minor Release: 0
AMP Version: 3 Major Release: 1 Minor Release: 3
AMC UM Init sourced from: //depot/ip_lib/apple/amcc/a0.elba/amcc/tb/cfg/static/maqstb_cfg.pl#16
AMP UM Init sourced from: //depot/ip_lib/apple/amp/a0.elba/amp/tb/cfg/phy_helper_fxns.pl#7

#### Change Log

* ------------------------------------------------------------------
* Version:1 - Files Edited: all
* Initial fiji checkin
* ------------------------------------------------------------------
* Version:6 - cpolapra - Files Edited: maqs_gen_cfg.pl#6 - maqs_gen_cfg_c.pl#6 - maqstb_cfg.pl#13 - mcu_helper_fxns.c#8 -
* Fix compile errors from cortex boot
* ------------------------------------------------------------------
* Version:7 - cpolapra - Files Edited: maqstb_cfg.pl#17 - mcu_helper_fxns.c#10 -
* 1600 Mhz mcu init changes
* ------------------------------------------------------------------
* Version:8 - herb - Files Edited: gen_mcu_init.pl#7 -
* amp v0.9.2
* amcx v0.0.10
* amph V0007
* ------------------------------------------------------------------
* Version:9 - thuang - Files Edited: maqstb_cfg.pl#33 -
* add back SPLLCtrl programming now that <rdar://problem/16856111> is resolved
* ------------------------------------------------------------------

#### 0. AMC Prolog

Program SPLL registers

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

if (platform == ONE_CH_ONE_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050100 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x0
else if (platform == ONE_CH_TWO_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050100 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x0
else if (platform == FOUR_CH_ONE_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050110 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x1
else if (platform == TWO_CH_TWO_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050100 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x0
else if (platform == FOUR_CH_TWO_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050110 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x1
else if (platform == EIGHT_CH_ONE_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050120 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x2
else if (platform == TWO_CH_ONE_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050100 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x0
else
amcc_MccLockRegion_mccchnldec = 0x00050120 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x2

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spllctrl_SpllCtrl_ChargePump(n) = 0x00000068 slvpll_cp_boost = 0x0 slvpll_cp_i_set = 0x3 slvpll_cp_lp = 0x0 slvpll_cp_md = 0x0 slvpll_cp_pd = 0x0 slvpll_cp_r_set = 0x8

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spllctrl_SpllCtrl_ModeReg(n) = 0x00000001 override_spll_lock = 0x0 override_spllseq_outputs = 0x0 override_value_spll_lock = 0x0 slvpll_byp = 0x0 slvpll_mode = 0x1

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spllctrl_SpllCtrl_VCO(n) = 0x00000016 slvpll_vco_buf_pd = 0x0 slvpll_vco_cap = 0x1 slvpll_vco_kvco = 0x0 slvpll_vco_pd = 0x0 slvpll_vco_rv2i = 0x6

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spllctrl_SpllCtrl_VCO(n) = 0x00000015 slvpll_vco_buf_pd = 0x0 slvpll_vco_cap = 0x1 slvpll_vco_kvco = 0x0 slvpll_vco_pd = 0x0 slvpll_vco_rv2i = 0x5

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spllctrl_SpllCtrl_LDO(n) = 0x00000004 slvpll_bg_start_sel = 0x0 slvpll_reg_pd = 0x0 slvpll_vreg_adj = 0x4

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spllctrl_SpllCtrl_SPLLPwrDnCfg(n) = 0x00000011 bypass_en_stby_pd = 0x1 spll_fast_pd_exit = 0x0 spll_mode_dcs_pwrdn = 0x1 use_idle_for_pd = 0x0

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Call custom API provided in mcu_helper_fxns.c for setting PLL3 frequency to 132.33Mhz. This call is only applicable to Cold boot.
FPGA: Skip this step

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Call custom API provided in mcu_helper_fxns.c for setting PLL3 frequency to 132.33Mhz. This call is only applicable to Cold boot.
FPGA: Skip this step

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#### 1. AMC Initial Configuration

Perform the proper configurations of the AMC. Note that all the timing parameters should be programmed with respect to the normal clock, not the slow boot clock.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

#### Setting up MCU registers and FSP for Freq change

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

amcx_dramcfg_freqchngctl0_freq0(n) = 0x18cd104d freqchngmrw0_addr_freq0 = 0xd freqchngmrw0_ctrl_freq0 = 0x1 freqchngmrw0_data_freq0 = 0x10 freqchngmrw1_addr_freq0 = 0xd freqchngmrw1_ctrl_freq0 = 0x3 freqchngmrw1_data_freq0 = 0x18

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amcx_dramcfg_freqchngctl1_freq0(n) = 0x110c110e freqchngmrw2_addr_freq0 = 0xe freqchngmrw2_ctrl_freq0 = 0x0 freqchngmrw2_data_freq0 = 0x11 freqchngmrw3_addr_freq0 = 0xc freqchngmrw3_ctrl_freq0 = 0x0 freqchngmrw3_data_freq0 = 0x11

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if (platform == FPGA)
amcx_dramcfg_freqchngctl2_freq0(n) = 0xb303000b freqchngmrw4_addr_freq0 = 0xb freqchngmrw4_ctrl_freq0 = 0x0 freqchngmrw4_data_freq0 = 0x0 freqchngmrw5_addr_freq0 = 0x3 freqchngmrw5_ctrl_freq0 = 0x0 freqchngmrw5_data_freq0 = 0xb3
else
amcx_dramcfg_freqchngctl2_freq0(n) = 0xb303440b freqchngmrw4_addr_freq0 = 0xb freqchngmrw4_ctrl_freq0 = 0x0 freqchngmrw4_data_freq0 = 0x44 freqchngmrw5_addr_freq0 = 0x3 freqchngmrw5_ctrl_freq0 = 0x0 freqchngmrw5_data_freq0 = 0xb3

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amcx_dramcfg_freqchngctl3_freq0(n) = 0xde012d02 freqchngmrw6_addr_freq0 = 0x2 freqchngmrw6_ctrl_freq0 = 0x0 freqchngmrw6_data_freq0 = 0x2d freqchngmrw7_addr_freq0 = 0x1 freqchngmrw7_ctrl_freq0 = 0x0 freqchngmrw7_data_freq0 = 0xde

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amcx_dramcfg_freqchngctl4_freq0(n) = 0x00000416 freqchngmrw8_addr_freq0 = 0x16 freqchngmrw8_ctrl_freq0 = 0x0 freqchngmrw8_data_freq0 = 0x4 freqchngmrw9_addr_freq0 = 0x0 freqchngmrw9_ctrl_freq0 = 0x0 freqchngmrw9_data_freq0 = 0x0

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amcx_dramcfg_freqchngtim_freq0(n) = 0x000c1108 freqchngclkofflat_freq0 = 0x8 freqchngclkonlat_freq0 = 0x11 freqchngsocupdlat_freq0 = 0xc

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amcx_dramcfg_freqchngctl0_freq1(n) = 0x18cd104d freqchngmrw0_addr_freq1 = 0xd freqchngmrw0_ctrl_freq1 = 0x1 freqchngmrw0_data_freq1 = 0x10 freqchngmrw1_addr_freq1 = 0xd freqchngmrw1_ctrl_freq1 = 0x3 freqchngmrw1_data_freq1 = 0x18

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amcx_dramcfg_freqchngctl1_freq1(n) = 0x110c110e freqchngmrw2_addr_freq1 = 0xe freqchngmrw2_ctrl_freq1 = 0x0 freqchngmrw2_data_freq1 = 0x11 freqchngmrw3_addr_freq1 = 0xc freqchngmrw3_ctrl_freq1 = 0x0 freqchngmrw3_data_freq1 = 0x11

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if (platform == FPGA)
amcx_dramcfg_freqchngctl2_freq1(n) = 0xd303000b freqchngmrw4_addr_freq1 = 0xb freqchngmrw4_ctrl_freq1 = 0x0 freqchngmrw4_data_freq1 = 0x0 freqchngmrw5_addr_freq1 = 0x3 freqchngmrw5_ctrl_freq1 = 0x0 freqchngmrw5_data_freq1 = 0xd3
else
amcx_dramcfg_freqchngctl2_freq1(n) = 0xd303220b freqchngmrw4_addr_freq1 = 0xb freqchngmrw4_ctrl_freq1 = 0x0 freqchngmrw4_data_freq1 = 0x22 freqchngmrw5_addr_freq1 = 0x3 freqchngmrw5_ctrl_freq1 = 0x0 freqchngmrw5_data_freq1 = 0xd3

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amcx_dramcfg_freqchngctl3_freq1(n) = 0xae015202 freqchngmrw6_addr_freq1 = 0x2 freqchngmrw6_ctrl_freq1 = 0x0 freqchngmrw6_data_freq1 = 0x52 freqchngmrw7_addr_freq1 = 0x1 freqchngmrw7_ctrl_freq1 = 0x0 freqchngmrw7_data_freq1 = 0xae

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amcx_dramcfg_freqchngctl4_freq1(n) = 0x00000216 freqchngmrw8_addr_freq1 = 0x16 freqchngmrw8_ctrl_freq1 = 0x0 freqchngmrw8_data_freq1 = 0x2 freqchngmrw9_addr_freq1 = 0x0 freqchngmrw9_ctrl_freq1 = 0x0 freqchngmrw9_data_freq1 = 0x0

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amcx_dramcfg_freqchngtim_freq1(n) = 0x000c1108 freqchngclkofflat_freq1 = 0x8 freqchngclkonlat_freq1 = 0x11 freqchngsocupdlat_freq1 = 0xc

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amcx_dramcfg_freqchngctl0_freq2(n) = 0x18cd104d freqchngmrw0_addr_freq2 = 0xd freqchngmrw0_ctrl_freq2 = 0x1 freqchngmrw0_data_freq2 = 0x10 freqchngmrw1_addr_freq2 = 0xd freqchngmrw1_ctrl_freq2 = 0x3 freqchngmrw1_data_freq2 = 0x18

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amcx_dramcfg_freqchngctl1_freq2(n) = 0x590c590e freqchngmrw2_addr_freq2 = 0xe freqchngmrw2_ctrl_freq2 = 0x0 freqchngmrw2_data_freq2 = 0x59 freqchngmrw3_addr_freq2 = 0xc freqchngmrw3_ctrl_freq2 = 0x0 freqchngmrw3_data_freq2 = 0x59

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if (platform == FPGA)
amcx_dramcfg_freqchngctl2_freq2(n) = 0xf303000b freqchngmrw4_addr_freq2 = 0xb freqchngmrw4_ctrl_freq2 = 0x0 freqchngmrw4_data_freq2 = 0x0 freqchngmrw5_addr_freq2 = 0x3 freqchngmrw5_ctrl_freq2 = 0x0 freqchngmrw5_data_freq2 = 0xf3
else
amcx_dramcfg_freqchngctl2_freq2(n) = 0xf303000b freqchngmrw4_addr_freq2 = 0xb freqchngmrw4_ctrl_freq2 = 0x0 freqchngmrw4_data_freq2 = 0x0 freqchngmrw5_addr_freq2 = 0x3 freqchngmrw5_ctrl_freq2 = 0x0 freqchngmrw5_data_freq2 = 0xf3

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amcx_dramcfg_freqchngctl3_freq2(n) = 0x8e010002 freqchngmrw6_addr_freq2 = 0x2 freqchngmrw6_ctrl_freq2 = 0x0 freqchngmrw6_data_freq2 = 0x0 freqchngmrw7_addr_freq2 = 0x1 freqchngmrw7_ctrl_freq2 = 0x0 freqchngmrw7_data_freq2 = 0x8e

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amcx_dramcfg_freqchngctl4_freq2(n) = 0x00000016 freqchngmrw8_addr_freq2 = 0x16 freqchngmrw8_ctrl_freq2 = 0x0 freqchngmrw8_data_freq2 = 0x0 freqchngmrw9_addr_freq2 = 0x0 freqchngmrw9_ctrl_freq2 = 0x0 freqchngmrw9_data_freq2 = 0x0

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amcx_dramcfg_freqchngtim_freq2(n) = 0x000c1108 freqchngclkofflat_freq2 = 0x8 freqchngclkonlat_freq2 = 0x11 freqchngsocupdlat_freq2 = 0xc

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amcx_dramcfg_freqchngctl0_freq3(n) = 0x18cd104d freqchngmrw0_addr_freq3 = 0xd freqchngmrw0_ctrl_freq3 = 0x1 freqchngmrw0_data_freq3 = 0x10 freqchngmrw1_addr_freq3 = 0xd freqchngmrw1_ctrl_freq3 = 0x3 freqchngmrw1_data_freq3 = 0x18

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amcx_dramcfg_freqchngctl1_freq3(n) = 0x590c590e freqchngmrw2_addr_freq3 = 0xe freqchngmrw2_ctrl_freq3 = 0x0 freqchngmrw2_data_freq3 = 0x59 freqchngmrw3_addr_freq3 = 0xc freqchngmrw3_ctrl_freq3 = 0x0 freqchngmrw3_data_freq3 = 0x59

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if (platform == FPGA)
amcx_dramcfg_freqchngctl2_freq3(n) = 0xf303000b freqchngmrw4_addr_freq3 = 0xb freqchngmrw4_ctrl_freq3 = 0x0 freqchngmrw4_data_freq3 = 0x0 freqchngmrw5_addr_freq3 = 0x3 freqchngmrw5_ctrl_freq3 = 0x0 freqchngmrw5_data_freq3 = 0xf3
else
amcx_dramcfg_freqchngctl2_freq3(n) = 0xf303000b freqchngmrw4_addr_freq3 = 0xb freqchngmrw4_ctrl_freq3 = 0x0 freqchngmrw4_data_freq3 = 0x0 freqchngmrw5_addr_freq3 = 0x3 freqchngmrw5_ctrl_freq3 = 0x0 freqchngmrw5_data_freq3 = 0xf3

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amcx_dramcfg_freqchngctl3_freq3(n) = 0x8e010002 freqchngmrw6_addr_freq3 = 0x2 freqchngmrw6_ctrl_freq3 = 0x0 freqchngmrw6_data_freq3 = 0x0 freqchngmrw7_addr_freq3 = 0x1 freqchngmrw7_ctrl_freq3 = 0x0 freqchngmrw7_data_freq3 = 0x8e

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amcx_dramcfg_freqchngctl4_freq3(n) = 0x00000016 freqchngmrw8_addr_freq3 = 0x16 freqchngmrw8_ctrl_freq3 = 0x0 freqchngmrw8_data_freq3 = 0x0 freqchngmrw9_addr_freq3 = 0x0 freqchngmrw9_ctrl_freq3 = 0x0 freqchngmrw9_data_freq3 = 0x0

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amcx_dramcfg_freqchngtim_freq3(n) = 0x000c1108 freqchngclkofflat_freq3 = 0x8 freqchngclkonlat_freq3 = 0x11 freqchngsocupdlat_freq3 = 0xc

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ampsca_ampscaRdWrDqCal_WrDqCalVREFCodeControl(n) = 0x19191111 WrDqCalVREFCode_f0 = 0x11 WrDqCalVREFCode_f1 = 0x11 WrDqCalVREFCode_f2 = 0x19 WrDqCalVREFCode_f3 = 0x19

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ampsca_ampscaRdWrDqCal_RdDqCalVREFCodeControl(n) = 0x19191191 RdDqCalVREFCode_f0 = 0x91 RdDqCalVREFCode_f1 = 0x11 RdDqCalVREFCode_f2 = 0x19 RdDqCalVREFCode_f3 = 0x19

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ampsca_ampscaRdWrDqCal_HWRdDqCalVREFControl(n) = 0x02d0b060 HWRdDqCalVREFEnable = 0x0 HWRdDqCalVREFMax = 0xd0 HWRdDqCalVREFMaxOffsetScaleFactor = 0x2 HWRdDqCalVREFMaxScoreSel = 0x0 HWRdDqCalVREFMin = 0xb0 HWRdDqCalVREFNumPoints = 0x6 HWRdDqCalVREFScoreMinSel = 0x0 HWRdDqCalVREFStaticSel = 0x0

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ampsca_ampscaRdWrDqCal_HWRdDqCalVREFOffsetControl1(n) = 0x06040200 HWRdDqCalOffset0 = 0x0 HWRdDqCalOffset1 = 0x2 HWRdDqCalOffset2 = 0x4 HWRdDqCalOffset3 = 0x6

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ampsca_ampscaRdWrDqCal_HWRdDqCalVREFOffsetControl2(n) = 0x00fafcfe HWRdDqCalOffset4 = 0xfe HWRdDqCalOffset5 = 0xfc HWRdDqCalOffset6 = 0xfa HWRdDqCalOffset7 = 0x0

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ampsca_ampscaRdWrDqCal_HWWrDqCalVREFControl(n) = 0x02200060 HWWrDqCalVREFEnable = 0x0 HWWrDqCalVREFMax = 0x20 HWWrDqCalVREFMaxOffsetScaleFactor = 0x2 HWWrDqCalVREFMaxScoreSel = 0x0 HWWrDqCalVREFMin = 0x0 HWWrDqCalVREFNumPoints = 0x6 HWWrDqCalVREFScoreMinSel = 0x0 HWWrDqCalVREFStaticSel = 0x0

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ampsca_ampscaRdWrDqCal_HWWrDqCalVREFOffsetControl1(n) = 0x06040200 HWWrDqCalOffset0 = 0x0 HWWrDqCalOffset1 = 0x2 HWWrDqCalOffset2 = 0x4 HWWrDqCalOffset3 = 0x6

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ampsca_ampscaRdWrDqCal_HWWrDqCalVREFOffsetControl2(n) = 0x00fafcfe HWWrDqCalOffset4 = 0xfe HWWrDqCalOffset5 = 0xfc HWWrDqCalOffset6 = 0xfa HWWrDqCalOffset7 = 0x0

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glbtimer_GlbTimer_PerVrefCalCfg = 0x00000003 LegacyMode = 0x0 PreVrefDcc = 0x1 PreVrefMdll = 0x1 PreVrefTimCal = 0x0

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glbtimer_GlbTimer_VrefCntrl = 0x00060006 VrefPointsRd = 0x6 VrefPointsWr = 0x6 override_refready = 0x0

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amcx_dramtim_modereg(n) = 0x120c90b8 tMRRCyc = 0x8 tMRRICyc = 0xb tMRWCyc = 0x9 tVRCGOFFCyc = 0xc tZQLatCyc = 0x12

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if (platform == FPGA)
amcx_dramcfg_rwcfg(n) = 0x000210ef CasAPEn = 0x1 DBIRDEn_freq0 = 0x0 DBIRDEn_freq1 = 0x1 DBIRDEn_freq2 = 0x1 DBIRDEn_freq3 = 0x1 DBIWREn_freq0 = 0x1 DBIWREn_freq1 = 0x1 DBIWREn_freq2 = 0x1 DBIWREn_freq3 = 0x1 DBIWRType = 0x0 tCCDMWCyc = 0x2
else
amcx_dramcfg_rwcfg(n) = 0x000210ef CasAPEn = 0x1 DBIRDEn_freq0 = 0x0 DBIRDEn_freq1 = 0x1 DBIRDEn_freq2 = 0x1 DBIRDEn_freq3 = 0x1 DBIWREn_freq0 = 0x1 DBIWREn_freq1 = 0x1 DBIWREn_freq2 = 0x1 DBIWREn_freq3 = 0x1 DBIWRType = 0x0 tCCDMWCyc = 0x2

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ampsdq_ampsdqdllctl_dllupdtctrl(n) = 0x50017350 DllInitUpdtDur = 0x7 DllUpdtDur = 0x3 DllUpdtMode = 0x1 DllUpdtPhyUpdtTyp = 0x0 FreqChangeSDLLUpdDur = 0x50 SDLLUpdDur = 0x50

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ampsca_ampscadllctl_dllupdtctrl(n) = 0x50017350 DllInitUpdtDur = 0x7 DllUpdtDur = 0x3 DllUpdtMode = 0x1 DllUpdtPhyUpdtTyp = 0x0 FreqChangeSDLLUpdDur = 0x50 SDLLUpdDur = 0x50

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amcx_dramtim_pdn(n) = 0x72276265 tCKECyc = 0x5 tCKEPDECyc = 0x1 tCKESRCyc = 0x6 tCKEafSRCyc = 0x2 tCKEb4SRCyc = 0x7 tCKafCKECyc = 0x7 tCKb4CKECyc = 0x2 tXPCyc = 0x6

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Configure DRAM timing parameters for default frequencyset. Example here shows LPDDR4-3200 8Gb DRAM die. See Section 3.2.2.4 for other value.
Configure the PHY timing. These are determined by the design of the PHY and the interface between the PHY and AMC.

if (platform == FPGA)
amcx_dramtim_lat_freq0(n) = 0x001030c2 DRAMRL_freq0 = 0x3 DRAMWL_freq0 = 0x2 tDQSCKMaxCyc_freq0 = 0x3 tDQSCKMinCyc_freq0 = 0x0 tDQSSMaxCyc_freq0 = 0x1
else
amcx_dramtim_lat_freq0(n) = 0x00103387 DRAMRL_freq0 = 0xe DRAMWL_freq0 = 0x7 tDQSCKMaxCyc_freq0 = 0x3 tDQSCKMinCyc_freq0 = 0x0 tDQSSMaxCyc_freq0 = 0x1

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if (platform == FPGA)
amcx_dramtim_lat_freq1(n) = 0x001020c2 DRAMRL_freq1 = 0x3 DRAMWL_freq1 = 0x2 tDQSCKMaxCyc_freq1 = 0x2 tDQSCKMinCyc_freq1 = 0x0 tDQSSMaxCyc_freq1 = 0x1
else
amcx_dramtim_lat_freq1(n) = 0x00102206 DRAMRL_freq1 = 0x8 DRAMWL_freq1 = 0x6 tDQSCKMaxCyc_freq1 = 0x2 tDQSCKMinCyc_freq1 = 0x0 tDQSSMaxCyc_freq1 = 0x1

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if (platform == FPGA)
amcx_phytim_phyrdwrtim_freq0(n) = 0x00010d01 PHYRdLat_freq0 = 0xd PHYtPhyWrlat_freq0 = 0x1 PHYtRddataEn_freq0 = 0x1
else
amcx_phytim_phyrdwrtim_freq0(n) = 0x00060d0c PHYRdLat_freq0 = 0xd PHYtPhyWrlat_freq0 = 0x6 PHYtRddataEn_freq0 = 0xc

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if (platform == FPGA)
amcx_phytim_phyrdwrtim_freq1(n) = 0x00010b01 PHYRdLat_freq1 = 0xb PHYtPhyWrlat_freq1 = 0x1 PHYtRddataEn_freq1 = 0x1
else
amcx_phytim_phyrdwrtim_freq1(n) = 0x00050b06 PHYRdLat_freq1 = 0xb PHYtPhyWrlat_freq1 = 0x5 PHYtRddataEn_freq1 = 0x6

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if (platform == FPGA)
amcx_phytim_phyrdwrtim_freq2(n) = 0x00010b01 PHYRdLat_freq2 = 0xb PHYtPhyWrlat_freq2 = 0x1 PHYtRddataEn_freq2 = 0x1
else
amcx_phytim_phyrdwrtim_freq2(n) = 0x00010b01 PHYRdLat_freq2 = 0xb PHYtPhyWrlat_freq2 = 0x1 PHYtRddataEn_freq2 = 0x1

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if (platform == FPGA)
amcx_phytim_phyrdwrtim_freq3(n) = 0x00010901 PHYRdLat_freq3 = 0x9 PHYtPhyWrlat_freq3 = 0x1 PHYtRddataEn_freq3 = 0x1
else
amcx_phytim_phyrdwrtim_freq3(n) = 0x00010901 PHYRdLat_freq3 = 0x9 PHYtPhyWrlat_freq3 = 0x1 PHYtRddataEn_freq3 = 0x1

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if (platform == PALLADIUM)
amcx_dramtim_caspch_freq0(n) = 0x63e2080f tRASCyc_freq0 = 0x22 tRCDCyc_freq0 = 0xf tRTPCyc_freq0 = 0x6 tWRCyc_freq0 = 0xf tWTRCyc_freq0 = 0x8
else if (platform == FPGA)
amcx_dramtim_caspch_freq0(n) = 0x40c20402 tRASCyc_freq0 = 0x2 tRCDCyc_freq0 = 0x2 tRTPCyc_freq0 = 0x4 tWRCyc_freq0 = 0x3 tWTRCyc_freq0 = 0x4
else
amcx_dramtim_caspch_freq0(n) = 0x63e2080f tRASCyc_freq0 = 0x22 tRCDCyc_freq0 = 0xf tRTPCyc_freq0 = 0x6 tWRCyc_freq0 = 0xf tWTRCyc_freq0 = 0x8

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_act_freq0(n) = 0x2008110f tFAWCyc_freq0 = 0x20 tRPCyc_freq0 = 0xf tRPabCyc_freq0 = 0x11 tRRDCyc_freq0 = 0x8
else if (platform == FPGA)
amcx_dramtim_act_freq0(n) = 0x01020202 tFAWCyc_freq0 = 0x1 tRPCyc_freq0 = 0x2 tRPabCyc_freq0 = 0x2 tRRDCyc_freq0 = 0x2
else
amcx_dramtim_act_freq0(n) = 0x2008110f tFAWCyc_freq0 = 0x20 tRPCyc_freq0 = 0xf tRPabCyc_freq0 = 0x11 tRRDCyc_freq0 = 0x8

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_autoref_freq0(n) = 0x48900078 tRFCBaseCyc_freq0 = 0x78 tRFCCyc_freq0 = 0x90 tRFCpbCyc_freq0 = 0x48
else if (platform == FPGA)
amcx_dramtim_autoref_freq0(n) = 0x01010078 tRFCBaseCyc_freq0 = 0x78 tRFCCyc_freq0 = 0x1 tRFCpbCyc_freq0 = 0x1
else
amcx_dramtim_autoref_freq0(n) = 0x48900078 tRFCBaseCyc_freq0 = 0x78 tRFCCyc_freq0 = 0x90 tRFCpbCyc_freq0 = 0x48

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_selfref_freq0(n) = 0xa0096012 tFCCyc_freq0 = 0xa0 tXSRCyc_freq0 = 0x96 tZQCalCyc_freq0 = 0x12
else if (platform == FPGA)
amcx_dramtim_selfref_freq0(n) = 0x28002012 tFCCyc_freq0 = 0x28 tXSRCyc_freq0 = 0x2 tZQCalCyc_freq0 = 0x12
else
amcx_dramtim_selfref_freq0(n) = 0xa0096012 tFCCyc_freq0 = 0xa0 tXSRCyc_freq0 = 0x96 tZQCalCyc_freq0 = 0x12

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_modereg(n) = 0x1a0cc0f4 tMRRCyc = 0x4 tMRRICyc = 0xf tMRWCyc = 0xc tVRCGOFFCyc = 0xc tZQLatCyc = 0x1a
else if (platform == FPGA)
amcx_dramtim_modereg(n) = 0x060c5024 tMRRCyc = 0x4 tMRRICyc = 0x2 tMRWCyc = 0x5 tVRCGOFFCyc = 0xc tZQLatCyc = 0x6
else
amcx_dramtim_modereg(n) = 0x1a0cc0f4 tMRRCyc = 0x4 tMRRICyc = 0xf tMRWCyc = 0xc tVRCGOFFCyc = 0xc tZQLatCyc = 0x1a

-

-

-

Configure DRAM timing parameters for alternative frequency points. For the dynamic frequency change support, all frequency sets should be programmed. See Section 3.2.2.3 for details. The actual values should correspond to the desired frequency points and the actual device specifications.
(N=1/2/3)
*since mcu_clk freq1 = 200MHz and per-bank refresh is not enabled,
mcusch.mifcassch_freq1. HiTempRefRnkAgeOut_freq1 =0x0

if (platform == PALLADIUM)
amcx_dramtim_caspch_freq1(n) = 0x63e2080f tRASCyc_freq1 = 0x22 tRCDCyc_freq1 = 0xf tRTPCyc_freq1 = 0x6 tWRCyc_freq1 = 0xf tWTRCyc_freq1 = 0x8
else if (platform == FPGA)
amcx_dramtim_caspch_freq1(n) = 0x40c20402 tRASCyc_freq1 = 0x2 tRCDCyc_freq1 = 0x2 tRTPCyc_freq1 = 0x4 tWRCyc_freq1 = 0x3 tWTRCyc_freq1 = 0x4
else
amcx_dramtim_caspch_freq1(n) = 0x42110408 tRASCyc_freq1 = 0x11 tRCDCyc_freq1 = 0x8 tRTPCyc_freq1 = 0x4 tWRCyc_freq1 = 0x8 tWTRCyc_freq1 = 0x4

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_act_freq1(n) = 0x2008110f tFAWCyc_freq1 = 0x20 tRPCyc_freq1 = 0xf tRPabCyc_freq1 = 0x11 tRRDCyc_freq1 = 0x8
else if (platform == FPGA)
amcx_dramtim_act_freq1(n) = 0x01020202 tFAWCyc_freq1 = 0x1 tRPCyc_freq1 = 0x2 tRPabCyc_freq1 = 0x2 tRRDCyc_freq1 = 0x2
else
amcx_dramtim_act_freq1(n) = 0x10040908 tFAWCyc_freq1 = 0x10 tRPCyc_freq1 = 0x8 tRPabCyc_freq1 = 0x9 tRRDCyc_freq1 = 0x4

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_autoref_freq1(n) = 0x48900050 tRFCBaseCyc_freq1 = 0x50 tRFCCyc_freq1 = 0x90 tRFCpbCyc_freq1 = 0x48
else if (platform == FPGA)
amcx_dramtim_autoref_freq1(n) = 0x01010050 tRFCBaseCyc_freq1 = 0x50 tRFCCyc_freq1 = 0x1 tRFCpbCyc_freq1 = 0x1
else
amcx_dramtim_autoref_freq1(n) = 0x24480050 tRFCBaseCyc_freq1 = 0x50 tRFCCyc_freq1 = 0x48 tRFCpbCyc_freq1 = 0x24

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_selfref_freq1(n) = 0xa0096012 tFCCyc_freq1 = 0xa0 tXSRCyc_freq1 = 0x96 tZQCalCyc_freq1 = 0x12
else if (platform == FPGA)
amcx_dramtim_selfref_freq1(n) = 0x28002012 tFCCyc_freq1 = 0x28 tXSRCyc_freq1 = 0x2 tZQCalCyc_freq1 = 0x12
else
amcx_dramtim_selfref_freq1(n) = 0x5004b012 tFCCyc_freq1 = 0x50 tXSRCyc_freq1 = 0x4b tZQCalCyc_freq1 = 0x12

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_caspch_freq2(n) = 0x63e2080f tRASCyc_freq2 = 0x22 tRCDCyc_freq2 = 0xf tRTPCyc_freq2 = 0x6 tWRCyc_freq2 = 0xf tWTRCyc_freq2 = 0x8
else if (platform == FPGA)
amcx_dramtim_caspch_freq2(n) = 0x40c20402 tRASCyc_freq2 = 0x2 tRCDCyc_freq2 = 0x2 tRTPCyc_freq2 = 0x4 tWRCyc_freq2 = 0x3 tWTRCyc_freq2 = 0x4
else
amcx_dramtim_caspch_freq2(n) = 0x40c50402 tRASCyc_freq2 = 0x5 tRCDCyc_freq2 = 0x2 tRTPCyc_freq2 = 0x4 tWRCyc_freq2 = 0x3 tWTRCyc_freq2 = 0x4

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_act_freq2(n) = 0x2008110f tFAWCyc_freq2 = 0x20 tRPCyc_freq2 = 0xf tRPabCyc_freq2 = 0x11 tRRDCyc_freq2 = 0x8
else if (platform == FPGA)
amcx_dramtim_act_freq2(n) = 0x01020202 tFAWCyc_freq2 = 0x1 tRPCyc_freq2 = 0x2 tRPabCyc_freq2 = 0x2 tRRDCyc_freq2 = 0x2
else
amcx_dramtim_act_freq2(n) = 0x04020302 tFAWCyc_freq2 = 0x4 tRPCyc_freq2 = 0x2 tRPabCyc_freq2 = 0x3 tRRDCyc_freq2 = 0x2

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_autoref_freq2(n) = 0x48900014 tRFCBaseCyc_freq2 = 0x14 tRFCCyc_freq2 = 0x90 tRFCpbCyc_freq2 = 0x48
else if (platform == FPGA)
amcx_dramtim_autoref_freq2(n) = 0x01010014 tRFCBaseCyc_freq2 = 0x14 tRFCCyc_freq2 = 0x1 tRFCpbCyc_freq2 = 0x1
else
amcx_dramtim_autoref_freq2(n) = 0x09120014 tRFCBaseCyc_freq2 = 0x14 tRFCCyc_freq2 = 0x12 tRFCpbCyc_freq2 = 0x9

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_selfref_freq2(n) = 0xa0096012 tFCCyc_freq2 = 0xa0 tXSRCyc_freq2 = 0x96 tZQCalCyc_freq2 = 0x12
else if (platform == FPGA)
amcx_dramtim_selfref_freq2(n) = 0x28002012 tFCCyc_freq2 = 0x28 tXSRCyc_freq2 = 0x2 tZQCalCyc_freq2 = 0x12
else
amcx_dramtim_selfref_freq2(n) = 0x28013012 tFCCyc_freq2 = 0x28 tXSRCyc_freq2 = 0x13 tZQCalCyc_freq2 = 0x12

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_caspch_freq3(n) = 0x40c20402 tRASCyc_freq3 = 0x2 tRCDCyc_freq3 = 0x2 tRTPCyc_freq3 = 0x4 tWRCyc_freq3 = 0x3 tWTRCyc_freq3 = 0x4
else if (platform == FPGA)
amcx_dramtim_caspch_freq3(n) = 0x40c20402 tRASCyc_freq3 = 0x2 tRCDCyc_freq3 = 0x2 tRTPCyc_freq3 = 0x4 tWRCyc_freq3 = 0x3 tWTRCyc_freq3 = 0x4
else
amcx_dramtim_caspch_freq3(n) = 0x40c20402 tRASCyc_freq3 = 0x2 tRCDCyc_freq3 = 0x2 tRTPCyc_freq3 = 0x4 tWRCyc_freq3 = 0x3 tWTRCyc_freq3 = 0x4

-

-

-

Process act_freq3 for all platforms

if (platform == PALLADIUM)
amcx_dramtim_act_freq3(n) = 0x01020404 tFAWCyc_freq3 = 0x1 tRPCyc_freq3 = 0x4 tRPabCyc_freq3 = 0x4 tRRDCyc_freq3 = 0x2
else if (platform == FPGA)
amcx_dramtim_act_freq3(n) = 0x01020404 tFAWCyc_freq3 = 0x1 tRPCyc_freq3 = 0x4 tRPabCyc_freq3 = 0x4 tRRDCyc_freq3 = 0x2
else
amcx_dramtim_act_freq3(n) = 0x02020404 tFAWCyc_freq3 = 0x2 tRPCyc_freq3 = 0x4 tRPabCyc_freq3 = 0x4 tRRDCyc_freq3 = 0x2

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_autoref_freq3(n) = 0x03050005 tRFCBaseCyc_freq3 = 0x5 tRFCCyc_freq3 = 0x5 tRFCpbCyc_freq3 = 0x3
else if (platform == FPGA)
amcx_dramtim_autoref_freq3(n) = 0x01010005 tRFCBaseCyc_freq3 = 0x5 tRFCCyc_freq3 = 0x1 tRFCpbCyc_freq3 = 0x1
else
amcx_dramtim_autoref_freq3(n) = 0x03050005 tRFCBaseCyc_freq3 = 0x5 tRFCCyc_freq3 = 0x5 tRFCpbCyc_freq3 = 0x3

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_selfref_freq3(n) = 0x28005012 tFCCyc_freq3 = 0x28 tXSRCyc_freq3 = 0x5 tZQCalCyc_freq3 = 0x12
else if (platform == FPGA)
amcx_dramtim_selfref_freq3(n) = 0x28002012 tFCCyc_freq3 = 0x28 tXSRCyc_freq3 = 0x2 tZQCalCyc_freq3 = 0x12
else
amcx_dramtim_selfref_freq3(n) = 0x28006012 tFCCyc_freq3 = 0x28 tXSRCyc_freq3 = 0x6 tZQCalCyc_freq3 = 0x12

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_autoref_params(n) = 0x0015005d tREFBWtRFCcnt = 0x15 tREFICyc = 0x5d
else if (platform == FPGA)
amcx_dramtim_autoref_params(n) = 0x00150013 tREFBWtRFCcnt = 0x15 tREFICyc = 0x13
else
amcx_dramtim_autoref_params(n) = 0x0015005d tREFBWtRFCcnt = 0x15 tREFICyc = 0x5d

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_pdn(n) = 0x612762c6 tCKECyc = 0x6 tCKEPDECyc = 0x1 tCKESRCyc = 0xc tCKEafSRCyc = 0x2 tCKEb4SRCyc = 0x7 tCKafCKECyc = 0x6 tCKb4CKECyc = 0x1 tXPCyc = 0x6
else if (platform == FPGA)
amcx_dramtim_pdn(n) = 0x21272222 tCKECyc = 0x2 tCKEPDECyc = 0x1 tCKESRCyc = 0x2 tCKEafSRCyc = 0x2 tCKEb4SRCyc = 0x7 tCKafCKECyc = 0x2 tCKb4CKECyc = 0x1 tXPCyc = 0x2
else
amcx_dramtim_pdn(n) = 0x722762c6 tCKECyc = 0x6 tCKEPDECyc = 0x1 tCKESRCyc = 0xc tCKEafSRCyc = 0x2 tCKEb4SRCyc = 0x7 tCKafCKECyc = 0x7 tCKb4CKECyc = 0x2 tXPCyc = 0x6

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_derate_freq0(n) = 0x4d05a910 tDQSCKMaxDrtCyc_freq0 = 0x5 tRASDrtCyc_freq0 = 0x24 tRCDDrtCyc_freq0 = 0x10 tRPDrtCyc_freq0 = 0x10 tRPabDrtCyc_freq0 = 0x13 tRRDDrtCyc_freq0 = 0xa
else if (platform == FPGA)
amcx_dramtim_derate_freq0(n) = 0x08212082 tDQSCKMaxDrtCyc_freq0 = 0x1 tRASDrtCyc_freq0 = 0x2 tRCDDrtCyc_freq0 = 0x2 tRPDrtCyc_freq0 = 0x2 tRPabDrtCyc_freq0 = 0x2 tRRDDrtCyc_freq0 = 0x2
else
amcx_dramtim_derate_freq0(n) = 0x4d05a910 tDQSCKMaxDrtCyc_freq0 = 0x5 tRASDrtCyc_freq0 = 0x24 tRCDDrtCyc_freq0 = 0x10 tRPDrtCyc_freq0 = 0x10 tRPabDrtCyc_freq0 = 0x13 tRRDDrtCyc_freq0 = 0xa

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_derate_freq1(n) = 0x4d05a910 tDQSCKMaxDrtCyc_freq1 = 0x5 tRASDrtCyc_freq1 = 0x24 tRCDDrtCyc_freq1 = 0x10 tRPDrtCyc_freq1 = 0x10 tRPabDrtCyc_freq1 = 0x13 tRRDDrtCyc_freq1 = 0xa
else if (platform == FPGA)
amcx_dramtim_derate_freq1(n) = 0x08212082 tDQSCKMaxDrtCyc_freq1 = 0x1 tRASDrtCyc_freq1 = 0x2 tRCDDrtCyc_freq1 = 0x2 tRPDrtCyc_freq1 = 0x2 tRPabDrtCyc_freq1 = 0x2 tRRDDrtCyc_freq1 = 0x2
else
amcx_dramtim_derate_freq1(n) = 0x28835488 tDQSCKMaxDrtCyc_freq1 = 0x3 tRASDrtCyc_freq1 = 0x12 tRCDDrtCyc_freq1 = 0x8 tRPDrtCyc_freq1 = 0x8 tRPabDrtCyc_freq1 = 0xa tRRDDrtCyc_freq1 = 0x5

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_derate_freq2(n) = 0x4d05a910 tDQSCKMaxDrtCyc_freq2 = 0x5 tRASDrtCyc_freq2 = 0x24 tRCDDrtCyc_freq2 = 0x10 tRPDrtCyc_freq2 = 0x10 tRPabDrtCyc_freq2 = 0x13 tRRDDrtCyc_freq2 = 0xa
else if (platform == FPGA)
amcx_dramtim_derate_freq2(n) = 0x08212082 tDQSCKMaxDrtCyc_freq2 = 0x1 tRASDrtCyc_freq2 = 0x2 tRCDDrtCyc_freq2 = 0x2 tRPDrtCyc_freq2 = 0x2 tRPabDrtCyc_freq2 = 0x2 tRRDDrtCyc_freq2 = 0x2
else
amcx_dramtim_derate_freq2(n) = 0x0c212142 tDQSCKMaxDrtCyc_freq2 = 0x1 tRASDrtCyc_freq2 = 0x5 tRCDDrtCyc_freq2 = 0x2 tRPDrtCyc_freq2 = 0x2 tRPabDrtCyc_freq2 = 0x3 tRRDDrtCyc_freq2 = 0x2

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_derate_freq3(n) = 0x10412082 tDQSCKMaxDrtCyc_freq3 = 0x1 tRASDrtCyc_freq3 = 0x2 tRCDDrtCyc_freq3 = 0x2 tRPDrtCyc_freq3 = 0x4 tRPabDrtCyc_freq3 = 0x4 tRRDDrtCyc_freq3 = 0x2
else if (platform == FPGA)
amcx_dramtim_derate_freq3(n) = 0x10412082 tDQSCKMaxDrtCyc_freq3 = 0x1 tRASDrtCyc_freq3 = 0x2 tRCDDrtCyc_freq3 = 0x2 tRPDrtCyc_freq3 = 0x4 tRPabDrtCyc_freq3 = 0x4 tRRDDrtCyc_freq3 = 0x2
else
amcx_dramtim_derate_freq3(n) = 0x10412082 tDQSCKMaxDrtCyc_freq3 = 0x1 tRASDrtCyc_freq3 = 0x2 tRCDDrtCyc_freq3 = 0x2 tRPDrtCyc_freq3 = 0x4 tRPabDrtCyc_freq3 = 0x4 tRRDDrtCyc_freq3 = 0x2

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_lat_freq0(n) = 0x00123387 DRAMRL_freq0 = 0xe DRAMWL_freq0 = 0x7 tDQSCKMaxCyc_freq0 = 0x3 tDQSCKMinCyc_freq0 = 0x2 tDQSSMaxCyc_freq0 = 0x1
else if (platform == FPGA)
amcx_dramtim_lat_freq0(n) = 0x001110c2 DRAMRL_freq0 = 0x3 DRAMWL_freq0 = 0x2 tDQSCKMaxCyc_freq0 = 0x1 tDQSCKMinCyc_freq0 = 0x1 tDQSSMaxCyc_freq0 = 0x1
else
amcx_dramtim_lat_freq0(n) = 0x00123387 DRAMRL_freq0 = 0xe DRAMWL_freq0 = 0x7 tDQSCKMaxCyc_freq0 = 0x3 tDQSCKMinCyc_freq0 = 0x2 tDQSSMaxCyc_freq0 = 0x1

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_lat_freq1(n) = 0x00123206 DRAMRL_freq1 = 0x8 DRAMWL_freq1 = 0x6 tDQSCKMaxCyc_freq1 = 0x3 tDQSCKMinCyc_freq1 = 0x2 tDQSSMaxCyc_freq1 = 0x1
else if (platform == FPGA)
amcx_dramtim_lat_freq1(n) = 0x001110c2 DRAMRL_freq1 = 0x3 DRAMWL_freq1 = 0x2 tDQSCKMaxCyc_freq1 = 0x1 tDQSCKMinCyc_freq1 = 0x1 tDQSSMaxCyc_freq1 = 0x1
else
amcx_dramtim_lat_freq1(n) = 0x00112206 DRAMRL_freq1 = 0x8 DRAMWL_freq1 = 0x6 tDQSCKMaxCyc_freq1 = 0x2 tDQSCKMinCyc_freq1 = 0x1 tDQSSMaxCyc_freq1 = 0x1

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_lat_freq2(n) = 0x001230c2 DRAMRL_freq2 = 0x3 DRAMWL_freq2 = 0x2 tDQSCKMaxCyc_freq2 = 0x3 tDQSCKMinCyc_freq2 = 0x2 tDQSSMaxCyc_freq2 = 0x1
else if (platform == FPGA)
amcx_dramtim_lat_freq2(n) = 0x001110c2 DRAMRL_freq2 = 0x3 DRAMWL_freq2 = 0x2 tDQSCKMaxCyc_freq2 = 0x1 tDQSCKMinCyc_freq2 = 0x1 tDQSSMaxCyc_freq2 = 0x1
else
amcx_dramtim_lat_freq2(n) = 0x001110c2 DRAMRL_freq2 = 0x3 DRAMWL_freq2 = 0x2 tDQSCKMaxCyc_freq2 = 0x1 tDQSCKMinCyc_freq2 = 0x1 tDQSSMaxCyc_freq2 = 0x1

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_lat_freq3(n) = 0x001110c2 DRAMRL_freq3 = 0x3 DRAMWL_freq3 = 0x2 tDQSCKMaxCyc_freq3 = 0x1 tDQSCKMinCyc_freq3 = 0x1 tDQSSMaxCyc_freq3 = 0x1
else if (platform == FPGA)
amcx_dramtim_lat_freq3(n) = 0x001110c2 DRAMRL_freq3 = 0x3 DRAMWL_freq3 = 0x2 tDQSCKMaxCyc_freq3 = 0x1 tDQSCKMinCyc_freq3 = 0x1 tDQSSMaxCyc_freq3 = 0x1
else
amcx_dramtim_lat_freq3(n) = 0x001110c2 DRAMRL_freq3 = 0x3 DRAMWL_freq3 = 0x2 tDQSCKMaxCyc_freq3 = 0x1 tDQSCKMinCyc_freq3 = 0x1 tDQSSMaxCyc_freq3 = 0x1

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_tat_freq0(n) = 0x01412222 R2rRnkMissTatDeadCyc_freq0 = 0x2 R2rTatDeadCyc_freq0 = 0x1 R2wRnkMissTatDeadCyc_freq0 = 0x2 R2wTatDeadCyc_freq0 = 0x4 W2rRnkMissTatDeadCyc_freq0 = 0x2 W2wRnkMissTatDeadCyc_freq0 = 0x2 W2wTatDeadCyc_freq0 = 0x1
else if (platform == FPGA)
amcx_dramtim_tat_freq0(n) = 0x01212222 R2rRnkMissTatDeadCyc_freq0 = 0x2 R2rTatDeadCyc_freq0 = 0x1 R2wRnkMissTatDeadCyc_freq0 = 0x2 R2wTatDeadCyc_freq0 = 0x2 W2rRnkMissTatDeadCyc_freq0 = 0x2 W2wRnkMissTatDeadCyc_freq0 = 0x2 W2wTatDeadCyc_freq0 = 0x1
else
amcx_dramtim_tat_freq0(n) = 0x01412222 R2rRnkMissTatDeadCyc_freq0 = 0x2 R2rTatDeadCyc_freq0 = 0x1 R2wRnkMissTatDeadCyc_freq0 = 0x2 R2wTatDeadCyc_freq0 = 0x4 W2rRnkMissTatDeadCyc_freq0 = 0x2 W2wRnkMissTatDeadCyc_freq0 = 0x2 W2wTatDeadCyc_freq0 = 0x1

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_tat_freq1(n) = 0x01412222 R2rRnkMissTatDeadCyc_freq1 = 0x2 R2rTatDeadCyc_freq1 = 0x1 R2wRnkMissTatDeadCyc_freq1 = 0x2 R2wTatDeadCyc_freq1 = 0x4 W2rRnkMissTatDeadCyc_freq1 = 0x2 W2wRnkMissTatDeadCyc_freq1 = 0x2 W2wTatDeadCyc_freq1 = 0x1
else if (platform == FPGA)
amcx_dramtim_tat_freq1(n) = 0x01212222 R2rRnkMissTatDeadCyc_freq1 = 0x2 R2rTatDeadCyc_freq1 = 0x1 R2wRnkMissTatDeadCyc_freq1 = 0x2 R2wTatDeadCyc_freq1 = 0x2 W2rRnkMissTatDeadCyc_freq1 = 0x2 W2wRnkMissTatDeadCyc_freq1 = 0x2 W2wTatDeadCyc_freq1 = 0x1
else
amcx_dramtim_tat_freq1(n) = 0x01312222 R2rRnkMissTatDeadCyc_freq1 = 0x2 R2rTatDeadCyc_freq1 = 0x1 R2wRnkMissTatDeadCyc_freq1 = 0x2 R2wTatDeadCyc_freq1 = 0x3 W2rRnkMissTatDeadCyc_freq1 = 0x2 W2wRnkMissTatDeadCyc_freq1 = 0x2 W2wTatDeadCyc_freq1 = 0x1

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_tat_freq2(n) = 0x01412222 R2rRnkMissTatDeadCyc_freq2 = 0x2 R2rTatDeadCyc_freq2 = 0x1 R2wRnkMissTatDeadCyc_freq2 = 0x2 R2wTatDeadCyc_freq2 = 0x4 W2rRnkMissTatDeadCyc_freq2 = 0x2 W2wRnkMissTatDeadCyc_freq2 = 0x2 W2wTatDeadCyc_freq2 = 0x1
else if (platform == FPGA)
amcx_dramtim_tat_freq2(n) = 0x01212222 R2rRnkMissTatDeadCyc_freq2 = 0x2 R2rTatDeadCyc_freq2 = 0x1 R2wRnkMissTatDeadCyc_freq2 = 0x2 R2wTatDeadCyc_freq2 = 0x2 W2rRnkMissTatDeadCyc_freq2 = 0x2 W2wRnkMissTatDeadCyc_freq2 = 0x2 W2wTatDeadCyc_freq2 = 0x1
else
amcx_dramtim_tat_freq2(n) = 0x01212222 R2rRnkMissTatDeadCyc_freq2 = 0x2 R2rTatDeadCyc_freq2 = 0x1 R2wRnkMissTatDeadCyc_freq2 = 0x2 R2wTatDeadCyc_freq2 = 0x2 W2rRnkMissTatDeadCyc_freq2 = 0x2 W2wRnkMissTatDeadCyc_freq2 = 0x2 W2wTatDeadCyc_freq2 = 0x1

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amcx_dramcfg_rnkcfg(n) = 0x00006061 Rnk0Odts = 0x6 *read-only Rnk0Valid = 0x1 Rnk1Odts = 0x6 *read-only Rnk1Valid = 0x0

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amcx_mifqctrl_mifqmaxctrl_freq0(n) = 0x00000100 HiTempMifQMax_freq0 = 0x0 MifQMaxAlways = 0x1

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if (platform == FPGA)
amcx_mifqctrl_mifqmaxctrl_freq3(n) = 0x00000003 HiTempMifQMax_freq3 = 0x3
else
amcx_mifqctrl_mifqmaxctrl_freq3(n) = 0x00000001 HiTempMifQMax_freq3 = 0x1

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Turn off optional power- savingfeatures. This includes dynamic power down, auto self-refresh entry, and clock stopping.

amcx_dramcfg_pwrmngten(n) = 0x00000000 AutoSR = 0x0 DynPwrDnEn = 0x0 McPhyUpdDramClkOff = 0x0 PwrDnClkOff = 0x0 SRClkOff = 0x0 SRExitOpt = 0x0

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Turn off optional power- savingfeatures. This includes dynamic power down, auto self-refresh entry, and clock stopping.

amcx_dramcfg_odtszqc(n) = 0x00002000 DerateParamSRExit = 0x1 OdtsRdIntrvl = 0x0 SRExitZQCChnlQuiet = 0x0 ShareZQRes = 0x0 TempDrtEn = 0x0 ZQCChnlQuiet = 0x0 ZQCStack = 0x0 ZqCalIntrvl = 0x0

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Turn off transaction scheduling for non- initialization commands

amcx_amcgen_amcctrl(n) = 0x00000002 McuEn = 0x0 SchEn = 0x1

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Program AMC to
- wait tXP+2tCK after actual clock changes before valid command
- wait 2 cycles after all timing parameter are satisfied before actual clock change
- wait indefinitely for AMP to complete handshake.

amcx_dramcfg_mcphyupdtparam(n) = 0x15030000 FreqCSettleCyc = 0x5 McPhyTimeParamCyc = 0x3 PhyInitStartCyc = 0x0 PhyUpdMDLL = 0x1 UpdPhyLatCyc = 0x0 tPhyUpdGap = 0x0

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#### 2. AMP Initial Configurations

Perform the proper configurations of the AMP. There are two separate AMP register blocks; the code below must be repeated on both AMP0 and AMP1. (N=0..1)

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

amph_CFGH_DCC_BYPCK(n) = 0x00003f3f ck_bypass = 0x0 ck_bypn = 0x3f ck_bypp = 0x3f

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amph_CFGH_DCC_BYPCS(n) = 0x00003f3f cs_bypass = 0x0 cs_bypn = 0x3f cs_bypp = 0x3f

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amph_CFGH_DCC_BYPB0(n) = 0x00003f3f b0_bypass = 0x0 b0_bypn = 0x3f b0_bypp = 0x3f

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amph_CFGH_DCC_BYPDQS0(n) = 0x00003f3f dqs0_bypass = 0x0 dqs0_bypn = 0x3f dqs0_bypp = 0x3f

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amph_CFGH_DCC_BYPB1(n) = 0x00003f3f b1_bypass = 0x0 b1_bypn = 0x3f b1_bypp = 0x3f

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amph_CFGH_DCC_BYPDQS1(n) = 0x00003f3f dqs1_bypass = 0x0 dqs1_bypn = 0x3f dqs1_bypp = 0x3f

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amph_CFGH_DCC_BYPCA(n) = 0x00003f3f ca_bypass = 0x0 ca_bypn = 0x3f ca_bypp = 0x3f

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amph_CFGH_DCC_BYPCK(n) = 0x00013f3f ck_bypass = 0x1 ck_bypn = 0x3f ck_bypp = 0x3f

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amph_CFGH_DCC_BYPCS(n) = 0x00013f3f cs_bypass = 0x1 cs_bypn = 0x3f cs_bypp = 0x3f

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amph_CFGH_DCC_BYPB0(n) = 0x00013f3f b0_bypass = 0x1 b0_bypn = 0x3f b0_bypp = 0x3f

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amph_CFGH_DCC_BYPDQS0(n) = 0x00013f3f dqs0_bypass = 0x1 dqs0_bypn = 0x3f dqs0_bypp = 0x3f

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amph_CFGH_DCC_BYPB1(n) = 0x00013f3f b1_bypass = 0x1 b1_bypn = 0x3f b1_bypp = 0x3f

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amph_CFGH_DCC_BYPDQS1(n) = 0x00013f3f dqs1_bypass = 0x1 dqs1_bypn = 0x3f dqs1_bypp = 0x3f

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amph_CFGH_DCC_BYPCA(n) = 0x00013f3f ca_bypass = 0x1 ca_bypn = 0x3f ca_bypp = 0x3f

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Assert AMP enable

ampsca_ampscagen_ampen(n) = 0x00000001 AmpEn = 0x1

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Assert AMP enable

ampsdq_ampsdqgen_ampen(n) = 0x00000001 AmpEn = 0x1

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ampsca_ampscaodt_VRef_f0(n) = 0x00000003 VRefSel = 0x3

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ampsca_ampscaodt_VRef_f1(n) = 0x00000003 VRefSel = 0x3

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ampsca_ampscaodt_VRef_f2(n) = 0x00000003 VRefSel = 0x3

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ampsca_ampscaodt_VRef_f3(n) = 0x00000003 VRefSel = 0x3

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ODTEnable_f0

if (platform == PALLADIUM)
ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000000 ODTEnable = 0x0
else if (platform == FPGA)
ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000000 ODTEnable = 0x0
else
ampsca_ampscaodt_ODTEnable_f0(n) = 0x00000001 ODTEnable = 0x1

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ODTEnable_f1

if (platform == PALLADIUM)
ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000000 ODTEnable = 0x0
else if (platform == FPGA)
ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000000 ODTEnable = 0x0
else
ampsca_ampscaodt_ODTEnable_f1(n) = 0x00000001 ODTEnable = 0x1

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ODTEnable_f3

ampsca_ampscaodt_ODTEnable_f3(n) = 0x00000000 ODTEnable = 0x0

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ampsdq_ampsdqodt_VRef_f0(n) = 0x00c000c0 DqsVRefSel = 0xc0 VRefSel = 0xc0

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ampsdq_ampsdqodt_VRef_f1(n) = 0x00c000c0 DqsVRefSel = 0xc0 VRefSel = 0xc0

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ampsca_ampscasdllctrl_SDLLUpdateCtrl(n) = 0x03030305 ClkEn2Valid = 0x3 ReqWaitDelay = 0x5 Valid2ClkEn = 0x3 ValidLen = 0x3

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ampsdq_ampsdqsdllctrl_SDLLUpdateCtrl(n) = 0x00030005 ClkEn2Valid = 0x0 ReqWaitDelay = 0x5 Valid2ClkEn = 0x0 ValidLen = 0x3

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ampsdq_ampsdqsdllctrl_rd0sdllctrl(n) = 0x00ff0002 Rd0RunSDLLUpd = 0x0 Rd0RunSDLLUpdOverride = 0x1 Rd0RunSDLLUpdWrResult = 0x0 Rd0SDLLOvrVal = 0xff

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-

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Poll ampsdqsdllctrl rd0sdllctrl

Poll: ampsdqsdllctrl_rd0sdllctrl Rd0RunSDLLUpdOverride while((CSR(ampsdq_ampsdqsdllctrl_rd0sdllctrl(n)) & 0x2) != 0x0)

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ampsdq_ampsdqsdllctrl_rd0sdllctrl(n) = 0x00ff0000 Rd0RunSDLLUpd = 0x0 Rd0RunSDLLUpdOverride = 0x0 Rd0RunSDLLUpdWrResult = 0x0 Rd0SDLLOvrVal = 0xff

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ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000002
WrDqDqsRunSDLLUpd = 0x0
WrDqDqsRunSDLLUpdOverride = 0x1
WrDqDqsRunSDLLUpdWrResult = 0x0
WrDqDqsWrLvlReBalanceEn = 0x0
WrDqSDLLAddHalfClk_f0 = 0x0
WrDqSDLLAddHalfClk_f1 = 0x0
WrDqSDLLAddHalfClk_f2 = 0x0
WrDqSDLLAddHalfClk_f3 = 0x0
WrDqSDLLHalfClkEn = 0x0
WrDqSDLLHalfClkOvrVal = 0x0
WrDqSDLLHalfClkStatus = 0x0 *read-only
WrDqSDLLOvrVal = 0x0
WrDqsSDLLOvrVal = 0xff

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Poll ampsdqsdllctrl WrDqDqsSDLLCtrl

Poll: ampsdqsdllctrl_WrDqDqsSDLLCtrl WrDqDqsRunSDLLUpdOverride while((CSR(ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n)) & 0x2) != 0x0)

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ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000000
WrDqDqsRunSDLLUpd = 0x0
WrDqDqsRunSDLLUpdOverride = 0x0
WrDqDqsRunSDLLUpdWrResult = 0x0
WrDqDqsWrLvlReBalanceEn = 0x0
WrDqSDLLAddHalfClk_f0 = 0x0
WrDqSDLLAddHalfClk_f1 = 0x0
WrDqSDLLAddHalfClk_f2 = 0x0
WrDqSDLLAddHalfClk_f3 = 0x0
WrDqSDLLHalfClkEn = 0x0
WrDqSDLLHalfClkOvrVal = 0x0
WrDqSDLLHalfClkStatus = 0x0 *read-only
WrDqSDLLOvrVal = 0x0
WrDqsSDLLOvrVal = 0xff

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ampsca_ampscawrlvl_ampcawrlvlsdllcode(n) = 0x00ff01ff WrLvlMaxWrDqsSDLLCode = 0xff WrLvlRunUpdOverride = 0x1 WrLvlRunUpdWrResult = 0x0 WrLvlSDLLCode = 0xff

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Poll ampscawrlvl ampcawrlvlsdllcode

Poll: ampscawrlvl_ampcawrlvlsdllcode WrLvlRunUpdOverride while((CSR(ampsca_ampscawrlvl_ampcawrlvlsdllcode(n)) & 0x100) != 0x0)

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ampsca_ampscawrlvl_ampcawrlvlsdllcode(n) = 0x00ff00ff WrLvlMaxWrDqsSDLLCode = 0xff WrLvlRunUpdOverride = 0x0 WrLvlRunUpdWrResult = 0x0 WrLvlSDLLCode = 0xff

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Program DLL Init and Incr lock timers based on 24 MHz value
FPGA: Skip this step

ampsca_ampscadllctl_dlllocktim(n) = 0x00c801f4 DllIncLockTim = 0xc8 DllInitLockTim = 0x1f4

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Program DLL Init and Incr lock timers based on 24 MHz value
FPGA: Skip this step

ampsdq_ampsdqdllctl_dlllocktim(n) = 0x00c801f4 DllIncLockTim = 0xc8 DllInitLockTim = 0x1f4

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ampsca_DFICalTiming2_DFICalTiming_f1(n) = 0x04000410 tCA2CAEntry_f1 = 0x10 tCA2CAExit_f1 = 0x0 tCKEHEntry_f1 = 0x4 tCKEHExit_f1 = 0x4

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ampsca_DFICalTiming2_DFICalTiming_f2(n) = 0x04000410 tCA2CAEntry_f2 = 0x10 tCA2CAExit_f2 = 0x0 tCKEHEntry_f2 = 0x4 tCKEHExit_f2 = 0x4

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ampsca_DFICalTiming2_DFICalTiming_f3(n) = 0x04000410 tCA2CAEntry_f3 = 0x10 tCA2CAExit_f3 = 0x0 tCKEHEntry_f3 = 0x4 tCKEHExit_f3 = 0x4

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ampsdq_DFICalTiming_DFICalTiming_f0(n) = 0x06020404 tCA2CAEntry_f0 = 0x4 tCA2CAExit_f0 = 0x2 tCKEHEntry_f0 = 0x4 tCKEHExit_f0 = 0x6

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ampsdq_DFICalTiming_DFICalTiming_f1(n) = 0x04020402 tCA2CAEntry_f1 = 0x2 tCA2CAExit_f1 = 0x2 tCKEHEntry_f1 = 0x4 tCKEHExit_f1 = 0x4

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ampsdq_DFICalTiming_DFICalTiming_f2(n) = 0x04020402 tCA2CAEntry_f2 = 0x2 tCA2CAExit_f2 = 0x2 tCKEHEntry_f2 = 0x4 tCKEHExit_f2 = 0x4

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ampsdq_DFICalTiming_DFICalTiming_f3(n) = 0x04020404 tCA2CAEntry_f3 = 0x4 tCA2CAExit_f3 = 0x2 tCKEHEntry_f3 = 0x4 tCKEHExit_f3 = 0x4

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ampsdq_ampsdqdllctl_MDLLCodeCaptureControl(n) = 0x00000002 MDLLLoopCnt = 0x2

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ampsca_ampscaRdWrDqCal_RdWrDqCalTiming_f0(n) = 0x01040508 CoarseStepSize = 0x4 FineStepSize = 0x1 tRL = 0x8 tWL = 0x5

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ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f0(n) = 0x000c0012 tRdDqCalSegLen = 0x12 tWrDqCalSegLen = 0xc

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ampsca_ampscaRdWrDqCal_RdWrDqCalTiming_f1(n) = 0x01040402 CoarseStepSize = 0x4 FineStepSize = 0x1 tRL = 0x2 tWL = 0x4

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ampsca_ampscaRdWrDqCal_RdWrDqCalTiming_f3(n) = 0x01040508 CoarseStepSize = 0x4 FineStepSize = 0x1 tRL = 0x8 tWL = 0x5

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ampsca_ampscaRdWrDqCal_RdWrDqCalSegLen_f1(n) = 0x000c0012 tRdDqCalSegLen = 0x12 tWrDqCalSegLen = 0xc

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ampsca_ampscaRdWrDqCal_HWRdWrDqCalTimingCtrl1(n) = 0x0000381e tRd2SDLL = 0x0 tSDLL2Rd = 0x1e tSDLL2Wr = 0x38 tWr2SDLL = 0x0

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ampsca_ampscaRdWrDqCal_HWRdWrDqCalTimingCtrl2(n) = 0x01141101 tRd2Rd = 0x1 tRd2Wr = 0x11 tWr2Rd = 0x14 tWr2Wr = 0x1

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ampsca_ampscaRdWrDqCal_HWRdDqCalPatPRBS4I(n) = 0x55553c5a PatInvertMask = 0x5555 PatPRBS4 = 0x3c5a

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ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS4I(n) = 0x00003c5a PatInvertMask = 0x0 PatPRBS4 = 0x3c5a

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ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS7_0(n) = 0x87654321 PatPRBS7 = 0x87654321

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ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS7_1(n) = 0xcdedcba9 PatPRBS7 = 0xcdedcba9

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ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS7_2(n) = 0x456789ab PatPRBS7 = 0x456789ab

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ampsca_ampscaRdWrDqCal_HWWrDqCalPatPRBS7_3(n) = 0x5fa63123 PatPRBS7 = 0x5fa63123

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ampsca_ampscaRdWrDqCal_HWWrDqCalPatInvertMask(n) = 0x55550000 PatInvertMask = 0x5555

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ampsca_ampscaRdWrDqCal_RdDqCalWindow_f0(n) = 0x00ff01d1 EndPoint = 0xff StartPoint = 0x1d1

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ampsca_ampscaRdWrDqCal_WrDqCalWindow_f0(n) = 0x00ff0160 EndPoint = 0xff StartPoint = 0x160 *read-only

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ampsca_ampscaRdWrDqCal_RdDqCalWindow_f1(n) = 0x00ff01d1 EndPoint = 0xff StartPoint = 0x1d1

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ampsca_ampscaRdWrDqCal_WrDqCalWindow_f1(n) = 0x00ff0160 EndPoint = 0xff StartPoint = 0x160 *read-only

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ampsca_ampscaRdWrDqCal_MaxRdDqsSDLLMulFactor(n) = 0x00a01414 MaxRdDqsSDLLCodeStatus = 0xa0 *read-only RdDqsSDLLMulFactorF0 = 0x14 RdDqsSDLLMulFactorF1 = 0x14

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ampsca_ampscaRdWrDqCal_MaxWrDqsSDLLMulFactor(n) = 0xa0a00c0d MaxWrDqsSDLLCodeStatusF0 = 0xa0 *read-only MaxWrDqsSDLLCodeStatusF1 = 0xa0 *read-only WrDqsSDLLMulFactorF0 = 0xd WrDqsSDLLMulFactorF1 = 0xc

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ampsdq_ampsdqMulFactor_RdDqsMulFactor(n) = 0x20181000 Factor0 = 0x0 Factor1 = 0x10 Factor2 = 0x18 Factor3 = 0x20

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Program capture latency and recapture latency

if (platform == FPGA)
ampsdq_ampsdqrdtim_rdcapcfg_freq0(n) = 0x01000606 DqIeDeAssertPullIn_f0 = 0x0 DqsPdEn_f0 = 0x1 RdCapLat_f0 = 0x6 RdDatLat_f0 = 0x6 WrPhaseDelay_f0 = 0x0
else
ampsdq_ampsdqrdtim_rdcapcfg_freq0(n) = 0x01000810 DqIeDeAssertPullIn_f0 = 0x0 DqsPdEn_f0 = 0x1 RdCapLat_f0 = 0x10 RdDatLat_f0 = 0x8 WrPhaseDelay_f0 = 0x0

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Program capture latency and recapture latency

if (platform == FPGA)
ampsdq_ampsdqrdtim_rdcapcfg_freq1(n) = 0x21000606 DqIeDeAssertPullIn_f1 = 0x2 DqsPdEn_f1 = 0x1 RdCapLat_f1 = 0x6 RdDatLat_f1 = 0x6 WrPhaseDelay_f1 = 0x0
else
ampsdq_ampsdqrdtim_rdcapcfg_freq1(n) = 0x2100060a DqIeDeAssertPullIn_f1 = 0x2 DqsPdEn_f1 = 0x1 RdCapLat_f1 = 0xa RdDatLat_f1 = 0x6 WrPhaseDelay_f1 = 0x0

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Program capture latency and recapture latency

if (platform == FPGA)
ampsdq_ampsdqrdtim_rdcapcfg_freq2(n) = 0x41000606 DqIeDeAssertPullIn_f2 = 0x4 DqsPdEn_f2 = 0x1 RdCapLat_f2 = 0x6 RdDatLat_f2 = 0x6 WrPhaseDelay_f2 = 0x0
else
ampsdq_ampsdqrdtim_rdcapcfg_freq2(n) = 0x41000408 DqIeDeAssertPullIn_f2 = 0x4 DqsPdEn_f2 = 0x1 RdCapLat_f2 = 0x8 RdDatLat_f2 = 0x4 WrPhaseDelay_f2 = 0x0

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Program capture latency and recapture latency

if (platform == FPGA)
ampsdq_ampsdqrdtim_rdcapcfg_freq3(n) = 0x61000606 DqIeDeAssertPullIn_f3 = 0x6 DqsPdEn_f3 = 0x1 RdCapLat_f3 = 0x6 RdDatLat_f3 = 0x6 WrPhaseDelay_f3 = 0x0
else
ampsdq_ampsdqrdtim_rdcapcfg_freq3(n) = 0x61000408 DqIeDeAssertPullIn_f3 = 0x6 DqsPdEn_f3 = 0x1 RdCapLat_f3 = 0x8 RdDatLat_f3 = 0x4 WrPhaseDelay_f3 = 0x0

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Updating the programming of DLL*UpdtDur Fields
FPGA: Skip this step

ampsca_ampscadllctl_dllupdtctrl(n) = 0x80017580 DllInitUpdtDur = 0x7 DllUpdtDur = 0x5 DllUpdtMode = 0x1 DllUpdtPhyUpdtTyp = 0x0 FreqChangeSDLLUpdDur = 0x80 SDLLUpdDur = 0x80

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Updating the programming of DLL*UpdtDur Fields
FPGA: Skip this step

ampsdq_ampsdqdllctl_dllupdtctrl(n) = 0x80017580 DllInitUpdtDur = 0x7 DllUpdtDur = 0x5 DllUpdtMode = 0x1 DllUpdtPhyUpdtTyp = 0x0 FreqChangeSDLLUpdDur = 0x80 SDLLUpdDur = 0x80

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ampsca_ampscadllctl_dllupdtintvl(n) = 0x10200020 DllFastUpdtAlwaysON = 0x1 DllFastUpdtIntvl = 0x20 DllUpdtAlwaysON = 0x0 DllUpdtIntvl = 0x20

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ampsdq_ampsdqdllctl_dllupdtintvl(n) = 0x10200020 DllFastUpdtAlwaysON = 0x1 DllFastUpdtIntvl = 0x20 DllUpdtAlwaysON = 0x0 DllUpdtIntvl = 0x20

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Enable DLL

ampsdq_ampsdqdllctl_dllen(n) = 0x00000100 DLLEn = 0x1 MDllReset = 0x0

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ampsca_ampscaiocfg_DCCControl(n) = 0x10050b27 DCCEnable = 0x1 DCCIdle1Len = 0x27 DCCIdle2Len = 0x5 DCCStopClk2Upd = 0x0 DCCUpdLen = 0xb

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ampsca_ampscaiocfg_DCCTimer(n) = 0x00000190 DCCTimer = 0x190

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ampsca_ampscaRdWrDqCal_HWWrDqCalDynamicHalfClkDelayControl(n) = 0x00000001 DynamicHalfClkDelayEn = 0x1

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amph_CFGH_CB_WKPUPD(n) = 0x00000000 pdpwk_f0 = 0x0 pdpwk_f1 = 0x0 pdpwk_f2 = 0x0 pdpwk_f3 = 0x0 pupwk_f0 = 0x0 pupwk_f1 = 0x0 pupwk_f2 = 0x0 pupwk_f3 = 0x0 wkds = 0x0

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amph_CFGH_CB_DRIVE_STR(n) = 0x33838317 dspd_f0 = 0x7 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x8 dspu_f2 = 0x8 dspu_f3 = 0x3

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amph_CFGH_CB_IOCTL(n) = 0x00020023 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x0 en_pulse_tx_f3 = 0x0 isel = 0x0 protect_drvstren = 0x1 sel_rx_ac = 0x0 sel_rx_dc = 0x0 tx_ac_f0 = 0x2 tx_ac_f1 = 0x0 tx_ac_f2 = 0x0 tx_ac_f3 = 0x0

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amph_CFGH_CK_WKPUPD(n) = 0x00000000 pdpwk_f0 = 0x0 pdpwk_f1 = 0x0 pdpwk_f2 = 0x0 pdpwk_f3 = 0x0 pupwk_f0 = 0x0 pupwk_f1 = 0x0 pupwk_f2 = 0x0 pupwk_f3 = 0x0 wkds = 0x0

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amph_CFGH_CK_ZDET_BIASEN(n) = 0x00000000 bias_ena = 0x0 disable_zdet = 0x0 sel_zdet = 0x0

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-

-

amph_CFGH_CK_DRIVE_STR(n) = 0x33838317 dspd_f0 = 0x7 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x8 dspu_f2 = 0x8 dspu_f3 = 0x3

-

-

-

amph_CFGH_CK_IOCTL(n) = 0x00000027 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x1 en_pulse_tx_f3 = 0x0 isel = 0x0 sel_rx_ac = 0x0 sel_rx_dc = 0x0 tx_ac_f0 = 0x2 tx_ac_f1 = 0x0 tx_ac_f2 = 0x0 tx_ac_f3 = 0x0

-

-

-

amph_CFGH_B0_DRIVE_STR(n) = 0x33838317 dspd_f0 = 0x7 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x8 dspu_f2 = 0x8 dspu_f3 = 0x3

-

-

-

amph_CFGH_B0_WKPUPD(n) = 0x00000000 idle_active_en_f0 = 0x0 idle_active_en_f1 = 0x0 idle_active_en_f2 = 0x0 idle_active_en_f3 = 0x0 pdpwk_f0 = 0x0 pdpwk_f1 = 0x0 pdpwk_f2 = 0x0 pdpwk_f3 = 0x0 pupwk_f0 = 0x0 pupwk_f1 = 0x0 pupwk_f2 = 0x0 pupwk_f3 = 0x0 wkds = 0x0

-

-

-

amph_CFGH_B0_IOCTL(n) = 0x71500027 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x1 en_pulse_tx_f3 = 0x0 isel_f0 = 0x1 isel_f1 = 0x1 isel_f2 = 0x1 isel_f3 = 0x0 sel_rx_ac_f0 = 0x0 sel_rx_ac_f1 = 0x0 sel_rx_ac_f2 = 0x0 sel_rx_ac_f3 = 0x0 sel_rx_dc_f0 = 0x1 sel_rx_dc_f1 = 0x1 sel_rx_dc_f2 = 0x1 sel_rx_dc_f3 = 0x0 tx_ac_f0 = 0x2 tx_ac_f1 = 0x0 tx_ac_f2 = 0x0 tx_ac_f3 = 0x0

-

-

-

amph_CFGH_B0_ODT(n) = 0x01c00333 dspd_f0 = 0x3 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x0 zcpd_ovrr = 0x0 zcpd_val = 0x1c

-

-

-

if (platform == PALLADIUM)
amph_CFGH_B0_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else if (platform == FPGA)
amph_CFGH_B0_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else
amph_CFGH_B0_ODTCTRL(n) = 0x00000007 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x1 odten_f1 = 0x1 odten_f2 = 0x1 odten_f3 = 0x0

-

-

-

amph_CFGH_B1_DRIVE_STR(n) = 0x33838317 dspd_f0 = 0x7 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x8 dspu_f2 = 0x8 dspu_f3 = 0x3

-

-

-

if (platform == PALLADIUM)
amph_CFGH_B1_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else if (platform == FPGA)
amph_CFGH_B1_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else
amph_CFGH_B1_ODTCTRL(n) = 0x00000007 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x1 odten_f1 = 0x1 odten_f2 = 0x1 odten_f3 = 0x0

-

-

-

amph_CFGH_B1_WKPUPD(n) = 0x00000000 idle_active_en_f0 = 0x0 idle_active_en_f1 = 0x0 idle_active_en_f2 = 0x0 idle_active_en_f3 = 0x0 pdpwk_f0 = 0x0 pdpwk_f1 = 0x0 pdpwk_f2 = 0x0 pdpwk_f3 = 0x0 pupwk_f0 = 0x0 pupwk_f1 = 0x0 pupwk_f2 = 0x0 pupwk_f3 = 0x0 wkds = 0x0

-

-

-

amph_CFGH_B1_IOCTL(n) = 0x71500027 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x1 en_pulse_tx_f3 = 0x0 isel_f0 = 0x1 isel_f1 = 0x1 isel_f2 = 0x1 isel_f3 = 0x0 sel_rx_ac_f0 = 0x0 sel_rx_ac_f1 = 0x0 sel_rx_ac_f2 = 0x0 sel_rx_ac_f3 = 0x0 sel_rx_dc_f0 = 0x1 sel_rx_dc_f1 = 0x1 sel_rx_dc_f2 = 0x1 sel_rx_dc_f3 = 0x0 tx_ac_f0 = 0x2 tx_ac_f1 = 0x0 tx_ac_f2 = 0x0 tx_ac_f3 = 0x0

-

-

-

amph_CFGH_B1_ODT(n) = 0x01c00333 dspd_f0 = 0x3 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x0 zcpd_ovrr = 0x0 zcpd_val = 0x1c

-

-

-

amph_CFGH_DQS0_WKPUPD(n) = 0x00000782 idle_active_en_f0 = 0x0 idle_active_en_f1 = 0x0 idle_active_en_f2 = 0x0 idle_active_en_f3 = 0x0 pdpwk_f0 = 0x1 pdpwk_f1 = 0x0 pdpwk_f2 = 0x0 pdpwk_f3 = 0x1 pupwk_f0 = 0x0 pupwk_f1 = 0x0 pupwk_f2 = 0x0 pupwk_f3 = 0x0 wkds = 0x7

-

-

-

amph_CFGH_DQS0_DRIVE_STR(n) = 0x33838317 dspd_f0 = 0x7 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x8 dspu_f2 = 0x8 dspu_f3 = 0x3

-

-

-

amph_CFGH_DQS0_IOCTL(n) = 0x71500007 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x1 en_pulse_tx_f3 = 0x0 isel_f0 = 0x1 isel_f1 = 0x1 isel_f2 = 0x1 isel_f3 = 0x0 sel_rx_ac_f0 = 0x0 sel_rx_ac_f1 = 0x0 sel_rx_ac_f2 = 0x0 sel_rx_ac_f3 = 0x0 sel_rx_dc_f0 = 0x1 sel_rx_dc_f1 = 0x1 sel_rx_dc_f2 = 0x1 sel_rx_dc_f3 = 0x0 tx_ac_f0 = 0x0 tx_ac_f1 = 0x0 tx_ac_f2 = 0x0 tx_ac_f3 = 0x0

-

-

-

amph_CFGH_DQS0_ODT(n) = 0x01c00336 dspd_f0 = 0x6 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x0 zcpd_ovrr = 0x0 zcpd_val = 0x1c

-

-

-

amph_CFGH_DQS0_ZDET_BIASEN(n) = 0x00060028 bias_ena_f0 = 0x0 bias_ena_f1 = 0x1 bias_ena_f2 = 0x1 bias_ena_f3 = 0x0 disable_zdet_f0 = 0x0 disable_zdet_f1 = 0x0 disable_zdet_f2 = 0x0 disable_zdet_f3 = 0x0 sel_zdet_f0 = 0x0 sel_zdet_f1 = 0x2 sel_zdet_f2 = 0x2 sel_zdet_f3 = 0x0

-

-

-

if (platform == PALLADIUM)
amph_CFGH_DQS0_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else if (platform == FPGA)
amph_CFGH_DQS0_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else
amph_CFGH_DQS0_ODTCTRL(n) = 0x00000007 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x1 odten_f1 = 0x1 odten_f2 = 0x1 odten_f3 = 0x0

-

-

-

amph_CFGH_DQS1_WKPUPD(n) = 0x00000782 idle_active_en_f0 = 0x0 idle_active_en_f1 = 0x0 idle_active_en_f2 = 0x0 idle_active_en_f3 = 0x0 pdpwk_f0 = 0x1 pdpwk_f1 = 0x0 pdpwk_f2 = 0x0 pdpwk_f3 = 0x1 pupwk_f0 = 0x0 pupwk_f1 = 0x0 pupwk_f2 = 0x0 pupwk_f3 = 0x0 wkds = 0x7

-

-

-

amph_CFGH_DQS1_DRIVE_STR(n) = 0x33838317 dspd_f0 = 0x7 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x3 dspu_f0 = 0x1 dspu_f1 = 0x8 dspu_f2 = 0x8 dspu_f3 = 0x3

-

-

-

amph_CFGH_DQS1_IOCTL(n) = 0x71500007 en_pulse_tx_f0 = 0x1 en_pulse_tx_f1 = 0x1 en_pulse_tx_f2 = 0x1 en_pulse_tx_f3 = 0x0 isel_f0 = 0x1 isel_f1 = 0x1 isel_f2 = 0x1 isel_f3 = 0x0 sel_rx_ac_f0 = 0x0 sel_rx_ac_f1 = 0x0 sel_rx_ac_f2 = 0x0 sel_rx_ac_f3 = 0x0 sel_rx_dc_f0 = 0x1 sel_rx_dc_f1 = 0x1 sel_rx_dc_f2 = 0x1 sel_rx_dc_f3 = 0x0 tx_ac_f0 = 0x0 tx_ac_f1 = 0x0 tx_ac_f2 = 0x0 tx_ac_f3 = 0x0

-

-

-

amph_CFGH_DQS1_ODT(n) = 0x01c00336 dspd_f0 = 0x6 dspd_f1 = 0x3 dspd_f2 = 0x3 dspd_f3 = 0x0 zcpd_ovrr = 0x0 zcpd_val = 0x1c

-

-

-

amph_CFGH_DQS1_ZDET_BIASEN(n) = 0x00060028 bias_ena_f0 = 0x0 bias_ena_f1 = 0x1 bias_ena_f2 = 0x1 bias_ena_f3 = 0x0 disable_zdet_f0 = 0x0 disable_zdet_f1 = 0x0 disable_zdet_f2 = 0x0 disable_zdet_f3 = 0x0 sel_zdet_f0 = 0x0 sel_zdet_f1 = 0x2 sel_zdet_f2 = 0x2 sel_zdet_f3 = 0x0

-

-

-

if (platform == PALLADIUM)
amph_CFGH_DQS1_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else if (platform == FPGA)
amph_CFGH_DQS1_ODTCTRL(n) = 0x00000000 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x0 odten_f1 = 0x0 odten_f2 = 0x0 odten_f3 = 0x0
else
amph_CFGH_DQS1_ODTCTRL(n) = 0x00000007 dspu_f0 = 0x0 dspu_f1 = 0x0 dspu_f2 = 0x0 dspu_f3 = 0x0 odten_f0 = 0x1 odten_f1 = 0x1 odten_f2 = 0x1 odten_f3 = 0x0

-

-

-

amph_CFGH_DBG_DBG_REG0(n) = 0x00000000 cb_bias_ena = 0x0 cb_odte = 0x0 clk_en_sync_flop_rst = 0x0 mon_vdd_mem = 0x0 mon_vdd_soc = 0x0

-

-

-

amph_CFGH_ZC_ZCAL_FSM1(n) = 0x00887f7f bias_ena_dly = 0x88 io_pd = 0x7f *read-only io_pu = 0x7f *read-only

-

-

-

amph_CFGH_ZC_ZCAL_FSM0(n) = 0x000f031b zc_dly = 0x1b zc_dnbd = 0x0 zc_tap = 0x3 zc_upbd = 0xf

-

-

-

amph_CFGH_DEBUG_SPARE0(n) = 0x00000016 control = 0x16

-

-

-

Assert init_done

ampsca_ampscagen_ampinit(n) = 0x00000001 InitDone = 0x1

-

-

-

Assert init_done

ampsdq_ampsdqgen_ampinit(n) = 0x00000001 InitDone = 0x1

-

-

-

ampsca_ampscaRdWrDqCal_DFICalTiming(n) = 0x06000504 tCA2CAEntry = 0x4 tCA2CAExit = 0x0 tCKEHEntry = 0x5 tCKEHExit = 0x6

-

-

-

ampsca_ampscaRdWrDqCal_HWRdDqCaltVREF(n) = 0x08080808 HWRdDqCaltVREF_f0 = 0x8 HWRdDqCaltVREF_f1 = 0x8 HWRdDqCaltVREF_f2 = 0x8 HWRdDqCaltVREF_f3 = 0x8

-

-

-

#### 3. Self-Refresh Exit

Prior to this step, the DRAM is assumed to be in the self-refresh state, and CKE has been kept low, either by retention circuitry in the PHY/IO, or, after SOC power is up and the reset is done, by the controller. This step will take DRAM out of the self-refresh mode. Software must guarantee that at least 50 us have passed since the de- assertion of AMC reset before self-refresh exit, in the resume-boot case. The frequency change to 50MHz here is initiated by PMGR. For ResumeBoot, the auto-refresh must be enabled before exiting self-refresh state.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

Wait 5us after Impedance Calibration in Step2. This is to avoid McPhyPending preventing the SRFSM from exiting SR.

-

-

-

radar #8707478 has been fixed. SetSRExitRefCnt to 2.

amcx_dramcfg_arefparam(n) = 0x0d012019 FreqChngWaitThr = 0x1 PhyUpdWaitRefresh = 0x1 PhyUpdWaitThr = 0x1 PhyUpdWaittXSR = 0x0 PreFreqChngWaitThr = 0x2 RefAssertCnt = 0xd SRExitRefCnt = 0x1

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_autoref_freq3(n) = 0x03050005 tRFCBaseCyc_freq3 = 0x5 tRFCCyc_freq3 = 0x5 tRFCpbCyc_freq3 = 0x3
else if (platform == FPGA)
amcx_dramtim_autoref_freq3(n) = 0x01010001 tRFCBaseCyc_freq3 = 0x1 tRFCCyc_freq3 = 0x1 tRFCpbCyc_freq3 = 0x1
else
amcx_dramtim_autoref_freq3(n) = 0x03050005 tRFCBaseCyc_freq3 = 0x5 tRFCCyc_freq3 = 0x5 tRFCpbCyc_freq3 = 0x3

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_autoref_freq2(n) = 0x48900013 tRFCBaseCyc_freq2 = 0x13 tRFCCyc_freq2 = 0x90 tRFCpbCyc_freq2 = 0x48
else if (platform == FPGA)
amcx_dramtim_autoref_freq2(n) = 0x01010001 tRFCBaseCyc_freq2 = 0x1 tRFCCyc_freq2 = 0x1 tRFCpbCyc_freq2 = 0x1
else
amcx_dramtim_autoref_freq2(n) = 0x09120013 tRFCBaseCyc_freq2 = 0x13 tRFCCyc_freq2 = 0x12 tRFCpbCyc_freq2 = 0x9

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_autoref_freq1(n) = 0x48900049 tRFCBaseCyc_freq1 = 0x49 tRFCCyc_freq1 = 0x90 tRFCpbCyc_freq1 = 0x48
else if (platform == FPGA)
amcx_dramtim_autoref_freq1(n) = 0x01010001 tRFCBaseCyc_freq1 = 0x1 tRFCCyc_freq1 = 0x1 tRFCpbCyc_freq1 = 0x1
else
amcx_dramtim_autoref_freq1(n) = 0x24480049 tRFCBaseCyc_freq1 = 0x49 tRFCCyc_freq1 = 0x48 tRFCpbCyc_freq1 = 0x24

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_autoref_freq0(n) = 0x48900092 tRFCBaseCyc_freq0 = 0x92 tRFCCyc_freq0 = 0x90 tRFCpbCyc_freq0 = 0x48
else if (platform == FPGA)
amcx_dramtim_autoref_freq0(n) = 0x01010001 tRFCBaseCyc_freq0 = 0x1 tRFCCyc_freq0 = 0x1 tRFCpbCyc_freq0 = 0x1
else
amcx_dramtim_autoref_freq0(n) = 0x48900092 tRFCBaseCyc_freq0 = 0x92 tRFCCyc_freq0 = 0x90 tRFCpbCyc_freq0 = 0x48

-

-

-

if (platform == PALLADIUM)
amcx_dramtim_autoref_params(n) = 0x0017005d tREFBWtRFCcnt = 0x17 tREFICyc = 0x5d
else if (platform == FPGA)
amcx_dramtim_autoref_params(n) = 0x002f0013 tREFBWtRFCcnt = 0x2f tREFICyc = 0x13
else
amcx_dramtim_autoref_params(n) = 0x0017005d tREFBWtRFCcnt = 0x17 tREFICyc = 0x5d

-

-

-

Enable auto refresh derating by setting TempDrtEn to 1. However, we do not enable ODTS interval until the end of the init. Setting TempDrtEn to 1 allows the chip to be in the hi-temp state and become more conservative.

if (platform == FPGA)
amcx_dramcfg_odtszqc(n) = 0x00000000 DerateParamSRExit = 0x0 OdtsRdIntrvl = 0x0 SRExitZQCChnlQuiet = 0x0 ShareZQRes = 0x0 TempDrtEn = 0x0 ZQCChnlQuiet = 0x0 ZQCStack = 0x0 ZqCalIntrvl = 0x0
else
amcx_dramcfg_odtszqc(n) = 0x00001000 DerateParamSRExit = 0x0 OdtsRdIntrvl = 0x0 SRExitZQCChnlQuiet = 0x0 ShareZQRes = 0x0 TempDrtEn = 0x1 ZQCChnlQuiet = 0x0 ZQCStack = 0x0 ZqCalIntrvl = 0x0

-

-

-

set SRExtraRefCnt to correct value (which is 1) and set LongSRCnt to be tREFW/4 (32ms/4=8ms)
If RefCntrHiWaterMark is changed from its default value, then LongSRExitRefCnt needs to be programmed to the same value.
Palladium: LongSRCnt=0x1004 because Palladium uses 1Gb device.

amcx_dramcfg_longsr(n) = 0x01022008 LongSRCnt = 0x2008 LongSRExitRefCnt = 0x1 SRExtraRefCnt = 0x2

-

-

-

amcx_dramcfg_mcphyupdtparam(n) = 0x15030004 FreqCSettleCyc = 0x5 McPhyTimeParamCyc = 0x3 PhyInitStartCyc = 0x0 PhyUpdMDLL = 0x1 UpdPhyLatCyc = 0x0 tPhyUpdGap = 0x4

-

-

-

Call custom API provided by PMGR for changing mcu_clk to 55Mhz
// TO BE COMPLETED
FPGA: Skip this step

-

-

-

Wait 5us to avoid a race condition between frequency change to bucket 3 & MCU being enabled

-

-

-

Turn on enables for various AMC blocks MCU.

amcx_amcgen_amcctrl(n) = 0x00000003 McuEn = 0x1 SchEn = 0x1

-

-

-

Run impedance calibration and optionally enable periodic auto impedance calibration
FPGA: Skip this step

ampsca_ampscaiocfg_impcalcmd(n) = 0x00000001 RunImpCal = 0x1 RunImpCalType = 0x0

-

-

-

Poll ampscaiocfg impcalcmd
FPGA: Skip this step

Poll: ampscaiocfg_impcalcmd RunImpCal while((CSR(ampsca_ampscaiocfg_impcalcmd(n)) & 0x1) != 0x0)

-

-

-

amcx_dramcfg_arefen_freq3(n) = 0x10100000 ARpbEn_freq3 = 0x0 HiTempRefRnkAgeOut_freq3 = 0x1 RefCntrHiWaterMark_freq3 = 0x1 RefCntrLoWaterMark_freq3 = 0x0

-

Yes

-

amcx_dramcfg_arefen_freq2(n) = 0x10000000 ARpbEn_freq2 = 0x0 HiTempRefRnkAgeOut_freq2 = 0x0 RefCntrHiWaterMark_freq2 = 0x1 RefCntrLoWaterMark_freq2 = 0x0

-

Yes

-

amcx_dramcfg_arefen_freq1(n) = 0x10010000 ARpbEn_freq1 = 0x1 HiTempRefRnkAgeOut_freq1 = 0x0 RefCntrHiWaterMark_freq1 = 0x1 RefCntrLoWaterMark_freq1 = 0x0

-

Yes

-

Turn on auto refresh.

amcx_dramcfg_arefen_freq0(n) = 0x1011013f ARpbEn_freq0 = 0x1 AutoRefEn = 0x1 AutoRefSchEn = 0x1 DisableHiTempREFab = 0x1 EarlyCasAgeOut = 0x0 HiPriREFpbPch = 0x1 HiTempRefRnkAgeOut_freq0 = 0x1 REFpb2bank = 0x0 REFpbEarlyPch = 0x1 RefCntrHiWaterMark_freq0 = 0x1 RefCntrLoWaterMark_freq0 = 0x0 RefOpptEn = 0x1 tREFBWREFpb = 0x1

-

Yes

-

Wait 200us for tINIT1 in real init, which we have cooked down to 200ns for simulation.

-

-

-

Wait 2 ms for tINIT3 in real init, which we have cooked down to 200ns for simulation.

-

-

-

amcx_dramcfg_freqchngctl(n) = 0x01010000 freqchngfspop = 0x1 freqchngfspopupd = 0x0 freqchngmrwcnt_freq0 = 0x0 freqchngmrwcnt_freq1 = 0x0 freqchngmrwcnt_freq2 = 0x0 freqchngmrwcnt_freq3 = 0x0 freqchngrunsocupd = 0x1

-

-

-

Poll dramcfg freqchngctl

Poll: dramcfg_freqchngctl freqchngrunsocupd while((CSR(amcx_dramcfg_freqchngctl(n)) & 0x10000) != 0x0)

-

-

-

amcx_dramcfg_freqchngctl(n) = 0x01000000 freqchngfspop = 0x1 freqchngfspopupd = 0x0 freqchngmrwcnt_freq0 = 0x0 freqchngmrwcnt_freq1 = 0x0 freqchngmrwcnt_freq2 = 0x0 freqchngmrwcnt_freq3 = 0x0 freqchngrunsocupd = 0x0

-

-

-

Wait 2us for the soc update to finish

-

-

-

Assert MPC to Sending SR Exit during Resume Boot

amcx_dramcmd_mrinitcmd(n) = 0x00004000 MRCmdAddr = 0x0 MRCmdCs = 0x0 MRCmdData = 0x0 MRCmdIsMPC = 0x1 MRCmdIsRd = 0x0 RunMRCmd = 0x0 RunRdLvl = 0x0 RunSRExit = 0x0

-

Yes

-

Issue self-refresh exit command. One for each channel.
SW needs to guarantee that at least 50usec has passed since removal of reset to AMC before issuing the self-refresh exit command, in case of resume boot.

amcx_dramcmd_mrinitcmd(n) = 0x00004001 MRCmdAddr = 0x0 MRCmdCs = 0x0 MRCmdData = 0x0 MRCmdIsMPC = 0x1 MRCmdIsRd = 0x0 RunMRCmd = 0x0 RunRdLvl = 0x0 RunSRExit = 0x1

-

Yes

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunSRExit while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x1) != 0x0)

-

Yes

-

Assert MPC to Sending SR Exit during Resume Boot

amcx_dramcmd_mrinitcmd(n) = 0x00000000 MRCmdAddr = 0x0 MRCmdCs = 0x0 MRCmdData = 0x0 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x0 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Issue self-refresh exit command. One for each channel.
SW needs to guarantee that at least 50usec has passed since removal of reset to AMC before issuing the self-refresh exit command, in case of resume boot.

amcx_dramcmd_mrinitcmd(n) = 0x00000001 MRCmdAddr = 0x0 MRCmdCs = 0x0 MRCmdData = 0x0 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x0 RunRdLvl = 0x0 RunSRExit = 0x1

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunSRExit while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x1) != 0x0)

-

No

-

Wait 2 us for tINIT5 in real init, which we have cooked down to 200ns for simulation.

-

-

-

if (platform == FOUR_CH_ONE_RANK)
glbtimer_GlbTimer_ChEn = 0x0000000f ChEn = 0xf
else if (platform == EIGHT_CH_ONE_RANK)
glbtimer_GlbTimer_ChEn = 0x000000ff ChEn = 0xff
else
glbtimer_GlbTimer_ChEn = 0x000000ff ChEn = 0xff

-

-

-

#### 4. DRAM Reset, ZQ Calibration & Configuration (Cold Boot Only).

This step is only required for ColdBoot. This step is to be repeated for each of the number of ranks per channel. The dramcmd.mrcmdch{N}.MRCmdCsCh{N} bit (Noted by letter R in the section) should be incremented in each loop.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

Issue DRAM ZQ calibration START MPC command MRINIT CMD registers.
Note that the MPC command can be issued to different channels independently, as long as the system has separate ZQ reference resistor for eachchannel. TheZQcalibration MPC to each rank within the same channel must be issued in series.

amcx_dramcmd_mrinitcmd(n) = 0x4f004100 MRCmdAddr = 0x0 MRCmdCs = 0x0 MRCmdData = 0x4f MRCmdIsMPC = 0x1 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

-

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

-

-

Wait 1us for tZQCAL.

-

-

-

Issue DRAM ZQ calibration LATCH MPC command MRINIT CMD registers

amcx_dramcmd_mrinitcmd(n) = 0x51004100 MRCmdAddr = 0x0 MRCmdCs = 0x0 MRCmdData = 0x51 MRCmdIsMPC = 0x1 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

-

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

-

-

Wait 20ns for tZQLAT.

-

-

-

Configure DRAM MR2 register (latency) through MRR/MRW command registers. The example shows the nominal programming for LPDDR2-1066 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices.

amcx_dramcmd_mrinitcmd(n) = 0x00020100 MRCmdAddr = 0x2 MRCmdCs = 0x0 MRCmdData = 0x0 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

Configure DRAM MR1 register through MRR/MRW command registers.
This includes the following: WC=Wrap BT=Sequential BL=BL16.
nWR, the example shows the nominal programming for LPDDR3- 1600 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices.

amcx_dramcmd_mrinitcmd(n) = 0x8e010100 MRCmdAddr = 0x1 MRCmdCs = 0x0 MRCmdData = 0x8e MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

amcx_dramcmd_mrinitcmd(n) = 0xf3030100 MRCmdAddr = 0x3 MRCmdCs = 0x0 MRCmdData = 0xf3 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

amcx_dramcmd_mrinitcmd(n) = 0x00160100 MRCmdAddr = 0x16 MRCmdCs = 0x0 MRCmdData = 0x0 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

FPGA: Skip this step

amcx_dramcmd_mrinitcmd(n) = 0x000b0100 MRCmdAddr = 0xb MRCmdCs = 0x0 MRCmdData = 0x0 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd
FPGA: Skip this step

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

Poll dramcmd mrinitcmd
FPGA: Perform this step

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

Program VRCG and modified refresh to 1

amcx_dramcmd_mrinitcmd(n) = 0x180d0100 MRCmdAddr = 0xd MRCmdCs = 0x0 MRCmdData = 0x18 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

amcx_dramcmd_mrinitcmd(n) = 0x590c0100 MRCmdAddr = 0xc MRCmdCs = 0x0 MRCmdData = 0x59 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

amcx_dramcmd_mrinitcmd(n) = 0x590e0100 MRCmdAddr = 0xe MRCmdCs = 0x0 MRCmdData = 0x59 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

amcx_dramcmd_mrinitcmd(n) = 0x80170100 MRCmdAddr = 0x17 MRCmdCs = 0x0 MRCmdData = 0x80 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

Program MR15/20 to match PatInvertMask of HW RdDQ calibration

amcx_dramcmd_mrinitcmd(n) = 0x550f4100 MRCmdAddr = 0xf MRCmdCs = 0x0 MRCmdData = 0x55 MRCmdIsMPC = 0x1 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

Program MR15/20 to match PatInvertMask of HW RdDQ calibration

amcx_dramcmd_mrinitcmd(n) = 0x55144100 MRCmdAddr = 0x14 MRCmdCs = 0x0 MRCmdData = 0x55 MRCmdIsMPC = 0x1 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

Program MR32/40 to match the PatPRBS4 pattern for HW RdDQ calibration

amcx_dramcmd_mrinitcmd(n) = 0x5a204100 MRCmdAddr = 0x20 MRCmdCs = 0x0 MRCmdData = 0x5a MRCmdIsMPC = 0x1 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

Program MR32/40 to match the PatPRBS4 pattern for HW RdDQ calibration

amcx_dramcmd_mrinitcmd(n) = 0x3c284100 MRCmdAddr = 0x28 MRCmdCs = 0x0 MRCmdData = 0x3c MRCmdIsMPC = 0x1 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

#### 5. Topology-specific configuration.

Here we perform MRR's to the memory to find out device density and program addrcfg, DramAccCtrl and mccchnldec registers

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

if (platform == FPGA_LPDDR3)
amcc_MccLockRegion_addrcfg = 0x00030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x0 RowAddrWid = 0x3
else if (platform == ONE_CH_ONE_RANK)
amcc_MccLockRegion_addrcfg = 0x00030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x0 RowAddrWid = 0x3
else if (platform == ONE_CH_TWO_RANK)
amcc_MccLockRegion_addrcfg = 0x01030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x1 RowAddrWid = 0x3
else if (platform == FOUR_CH_ONE_RANK)
amcc_MccLockRegion_addrcfg = 0x00030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x0 RowAddrWid = 0x3
else if (platform == TWO_CH_TWO_RANK)
amcc_MccLockRegion_addrcfg = 0x01030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x1 RowAddrWid = 0x3
else if (platform == FPGA)
amcc_MccLockRegion_addrcfg = 0x00030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x0 RowAddrWid = 0x3
else if (platform == FOUR_CH_TWO_RANK)
amcc_MccLockRegion_addrcfg = 0x01030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x1 RowAddrWid = 0x3
else if (platform == EIGHT_CH_ONE_RANK)
amcc_MccLockRegion_addrcfg = 0x00030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x0 RowAddrWid = 0x3
else if (platform == TWO_CH_ONE_RANK)
amcc_MccLockRegion_addrcfg = 0x00030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x0 RowAddrWid = 0x3
else
amcc_MccLockRegion_addrcfg = 0x00030201 BnkAddrWid = 0x1 ColAddrWid = 0x2 CsWid = 0x0 RowAddrWid = 0x3

-

-

-

if (platform == FPGA_LPDDR3)
amcc_MccLockRegion_DramAccCtrl = 0x00000007 DramSize = 0x7
else if (platform == ONE_CH_ONE_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x00000003 DramSize = 0x3
else if (platform == ONE_CH_TWO_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x00000007 DramSize = 0x7
else if (platform == FOUR_CH_ONE_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x00000007 DramSize = 0x7
else if (platform == TWO_CH_TWO_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x00000007 DramSize = 0x7
else if (platform == FPGA)
amcc_MccLockRegion_DramAccCtrl = 0x0000000f DramSize = 0xf
else if (platform == FOUR_CH_TWO_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x0000000f DramSize = 0xf
else if (platform == EIGHT_CH_ONE_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x0000000f DramSize = 0xf
else if (platform == TWO_CH_ONE_RANK)
amcc_MccLockRegion_DramAccCtrl = 0x00000007 DramSize = 0x7
else
amcc_MccLockRegion_DramAccCtrl = 0x0000000f DramSize = 0xf

-

-

-

dram_Density_config();

-

-

-

if (platform == FPGA_LPDDR3)
amcc_MccLockRegion_mccchnldec = 0x00050120 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x2
else if (platform == ONE_CH_ONE_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050101 ChSelHiBits = 0x5 ChSelTyp = 0x1 ChnlStartBit = 0x1 NumMcuChnl = 0x0
else if (platform == ONE_CH_TWO_RANK)
amcc_MccLockRegion_mccchnldec = 0x00060101 ChSelHiBits = 0x6 ChSelTyp = 0x1 ChnlStartBit = 0x1 NumMcuChnl = 0x0
else if (platform == FOUR_CH_ONE_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050110 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x1
else if (platform == TWO_CH_TWO_RANK)
amcc_MccLockRegion_mccchnldec = 0x00060100 ChSelHiBits = 0x6 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x0
else if (platform == FPGA)
amcc_MccLockRegion_mccchnldec = 0x00050120 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x2
else if (platform == FOUR_CH_TWO_RANK)
amcc_MccLockRegion_mccchnldec = 0x00060110 ChSelHiBits = 0x6 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x1
else if (platform == EIGHT_CH_ONE_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050120 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x2
else if (platform == TWO_CH_ONE_RANK)
amcc_MccLockRegion_mccchnldec = 0x00050100 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x0
else
amcc_MccLockRegion_mccchnldec = 0x00050120 ChSelHiBits = 0x5 ChSelTyp = 0x0 ChnlStartBit = 0x1 NumMcuChnl = 0x2

-

-

-

#### 6. Prepare for switch from boot-clock speed to normal operation speed

The frequency change is initiated by PMGR.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

Wait 5us before issuing a freq change to make sure all refreshes have been flushed.

-

-

-

Enable AMC scheduler to allow normal transactions to be processed.
Scheduler has to be enabled to let AMC issue self-refresh entry and allow frequency change.

amcx_amcgen_amcctrl(n) = 0x00000003 McuEn = 0x1 SchEn = 0x1

-

-

-

#### 11. Setup registers for CA calibration for bucket 0

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

Program FSP-WR to 1 and FSP-OP to 0 and set VRCG and modified refresh

amcx_dramcmd_mrinitcmd(n) = 0x580d0100 MRCmdAddr = 0xd MRCmdCs = 0x0 MRCmdData = 0x58 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

Configure DRAM MR2 register (latency) through MRR/MRW command registers. The example shows the nominal programming for LPDDR2-1066 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices.
FPGA: Skip this step

amcx_dramcmd_mrinitcmd(n) = 0x2d020100 MRCmdAddr = 0x2 MRCmdCs = 0x0 MRCmdData = 0x2d MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd
FPGA: Skip this step

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

Configure DRAM MR1 register through MRR/MRW command registers.
This includes the following: WC=Wrap BT=Sequential BL=BL16.
nWR, the example shows the nominal programming for LPDDR3- 1600 devices based on the JEDEC specifications. See Section 3.2.2.3 for values for other devices.
FPGA: Skip this step

amcx_dramcmd_mrinitcmd(n) = 0xde010100 MRCmdAddr = 0x1 MRCmdCs = 0x0 MRCmdData = 0xde MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd
FPGA: Skip this step

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

FPGA: Skip this step

amcx_dramcmd_mrinitcmd(n) = 0xb3030100 MRCmdAddr = 0x3 MRCmdCs = 0x0 MRCmdData = 0xb3 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd
FPGA: Skip this step

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

amcx_dramcmd_mrinitcmd(n) = 0x04160100 MRCmdAddr = 0x16 MRCmdCs = 0x0 MRCmdData = 0x4 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

FPGA: Skip this step

amcx_dramcmd_mrinitcmd(n) = 0x440b0100 MRCmdAddr = 0xb MRCmdCs = 0x0 MRCmdData = 0x44 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd
FPGA: Skip this step

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

FPGA: Perform this step

amcx_dramcmd_mrinitcmd(n) = 0x000b0100 MRCmdAddr = 0xb MRCmdCs = 0x0 MRCmdData = 0x0 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd
FPGA: Perform this step

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

amcx_dramcmd_mrinitcmd(n) = 0x110c0100 MRCmdAddr = 0xc MRCmdCs = 0x0 MRCmdData = 0x11 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

amcx_dramcmd_mrinitcmd(n) = 0x110e0100 MRCmdAddr = 0xe MRCmdCs = 0x0 MRCmdData = 0x11 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

ampsca_ampscawrlvl_ampcawrlvlsdllcode(n) = 0x00000200 WrLvlMaxWrDqsSDLLCode = 0x0 WrLvlRunUpdOverride = 0x0 WrLvlRunUpdWrResult = 0x1 WrLvlSDLLCode = 0x0

-

No

-

Poll ampscawrlvl ampcawrlvlsdllcode

Poll: ampscawrlvl_ampcawrlvlsdllcode WrLvlRunUpdWrResult while((CSR(ampsca_ampscawrlvl_ampcawrlvlsdllcode(n)) & 0x200) != 0x0)

-

No

-

#### 12. AMP Dynamic Address Timing Calibration

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

step12Calibration(0, LPDDR3, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, CA_CALIB, 0, 0, 0, 0, 0, 0, 0, 28, 14);

-

-

-

Program DLL Init and Incr lock timers based on 24 MHz value
FPGA: Skip this step

ampsca_ampscadllctl_dlllocktim(n) = 0x00130013 DllIncLockTim = 0x13 DllInitLockTim = 0x13

Yes

Yes

-

Program DLL Init and Incr lock timers based on 24 MHz value
FPGA: Skip this step

ampsdq_ampsdqdllctl_dlllocktim(n) = 0x00130013 DllIncLockTim = 0x13 DllInitLockTim = 0x13

Yes

Yes

-

Disable AMP Clock Gating for RunDllUpdt to go through
FPGA: Skip this step

ampsca_ampscagen_ampclk(n) = 0x00100001 FMClkIdleDetectEn = 0x0 ForceDRAMClkEn = 0x0 ForceDiv2MClkTopGaterOn = 0x1 ForceFMClkWakeUp = 0x0 ForceMClkWakeUp = 0x0 TopClkGateDis = 0x1

Yes

Yes

-

Defer SDLL update until frequency change

ampsca_ampscasdllctrl_SDLLUpdateDeferEn(n) = 0x00000001 DeferEn = 0x1

Yes

Yes

-

Defer SDLL update until frequency change

ampsdq_ampsdqsdllctrl_SDLLUpdateDeferEn(n) = 0x00000001 DeferEn = 0x1

Yes

Yes

-

Set MDLL override to 0

ampsdq_ampsdqdllctl_MDLLOverride(n) = 0x00010000 MDLLOvrCode = 0x0 MDLLOvrSel = 0x1

Yes

Yes

-

Run MDLL update

ampsdq_ampsdqdllctl_dllupdtcmd(n) = 0x00000001 RunDllUpdt = 0x1

Yes

Yes

-

Poll ampsdqdllctl dllupdtcmd

Poll: ampsdqdllctl_dllupdtcmd RunDllUpdt while((CSR(ampsdq_ampsdqdllctl_dllupdtcmd(n)) & 0x1) != 0x0)

Yes

Yes

-

Enable back AMP Clock Gating for RunDllUpdt to go through
FPGA: Skip this step

ampsca_ampscagen_ampclk(n) = 0x00000000 FMClkIdleDetectEn = 0x0 ForceDRAMClkEn = 0x0 ForceDiv2MClkTopGaterOn = 0x0 ForceFMClkWakeUp = 0x0 ForceMClkWakeUp = 0x0 TopClkGateDis = 0x0

Yes

Yes

-

Program DLL Init and Incr lock timers based on 24 MHz value
FPGA: Skip this step

ampsca_ampscadllctl_dlllocktim(n) = 0x012c012c DllIncLockTim = 0x12c DllInitLockTim = 0x12c

Yes

Yes

-

Program DLL Init and Incr lock timers based on 24 MHz value
FPGA: Skip this step

ampsdq_ampsdqdllctl_dlllocktim(n) = 0x012c012c DllIncLockTim = 0x12c DllInitLockTim = 0x12c

Yes

Yes

-

amcx_dramcfg_freqchngctl1_freq0(n) = 0x110c110e freqchngmrw2_addr_freq0 = 0xe freqchngmrw2_ctrl_freq0 = 0x0 freqchngmrw2_data_freq0 = 0x11 freqchngmrw3_addr_freq0 = 0xc freqchngmrw3_ctrl_freq0 = 0x0 freqchngmrw3_data_freq0 = 0x11

Yes

Yes

-

HWRdWrDqCalFullScanEnable
PALLADIUM: Skip this step

ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000003 HWRdDqCalFullScanEnable = 0x1 HWRdDqCalFullScanEnable16bit = 0x0 HWWrDqCalFullScanEnable = 0x1

Yes

Yes

-

#### 13. Setup registers for DQ calibration for bucket 0

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

Program FSP-WR to 0, FSP-OP to 1 and set VRCG and modified refresh
FPGA: Skip this step

amcx_dramcmd_mrinitcmd(n) = 0x980d0100 MRCmdAddr = 0xd MRCmdCs = 0x0 MRCmdData = 0x98 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

Yes

No

-

Poll dramcmd mrinitcmd
FPGA: Skip this step

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

Yes

No

-

Wait 1us for FSP setting to take affect.

-

-

-

Program AutoSR

amcx_dramcfg_pwrmngten(n) = 0x00000132 AutoSR = 0x1 DynPwrDnEn = 0x0 McPhyUpdDramClkOff = 0x0 PwrDnClkOff = 0x1 SRClkOff = 0x1 SRExitOpt = 0x1

Yes

Yes

-

Program FreqChngMRW Cnt

amcx_dramcfg_freqchngctl(n) = 0x02009999 freqchngfspop = 0x0 freqchngfspopupd = 0x1 freqchngmrwcnt_freq0 = 0x9 freqchngmrwcnt_freq1 = 0x9 freqchngmrwcnt_freq2 = 0x9 freqchngmrwcnt_freq3 = 0x9 freqchngrunsocupd = 0x0

Yes

Yes

-

WrDqDqsSDLLCtrl

ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000008
WrDqDqsRunSDLLUpd = 0x0
WrDqDqsRunSDLLUpdOverride = 0x0
WrDqDqsRunSDLLUpdWrResult = 0x0
WrDqDqsWrLvlReBalanceEn = 0x1
WrDqSDLLAddHalfClk_f0 = 0x0
WrDqSDLLAddHalfClk_f1 = 0x0
WrDqSDLLAddHalfClk_f2 = 0x0
WrDqSDLLAddHalfClk_f3 = 0x0
WrDqSDLLHalfClkEn = 0x0
WrDqSDLLHalfClkOvrVal = 0x0
WrDqSDLLHalfClkStatus = 0x0 *read-only
WrDqSDLLOvrVal = 0x0
WrDqsSDLLOvrVal = 0xff

Yes

Yes

-

Re-enable SDLL updates

ampsca_ampscasdllctrl_SDLLUpdateDeferEn(n) = 0x00000000 DeferEn = 0x0

Yes

Yes

-

Re-enable SDLL updates

ampsdq_ampsdqsdllctrl_SDLLUpdateDeferEn(n) = 0x00000000 DeferEn = 0x0

Yes

Yes

-

Disable MDLL override

ampsdq_ampsdqdllctl_MDLLOverride(n) = 0x00000000 MDLLOvrCode = 0x0 MDLLOvrSel = 0x0

Yes

Yes

-

Call custom API provided by PMGR for changing mcu_clk to 1600Mhz
// TO BE COMPLETED
FPGA: Skip this step

-

-

-

-

-

-

amcx_dramcfg_freqchngctl(n) = 0x00010000 freqchngfspop = 0x0 freqchngfspopupd = 0x0 freqchngmrwcnt_freq0 = 0x0 freqchngmrwcnt_freq1 = 0x0 freqchngmrwcnt_freq2 = 0x0 freqchngmrwcnt_freq3 = 0x0 freqchngrunsocupd = 0x1

-

No

-

Poll dramcfg freqchngctl

Poll: dramcfg_freqchngctl freqchngrunsocupd while((CSR(amcx_dramcfg_freqchngctl(n)) & 0x10000) != 0x0)

-

No

-

amcx_dramcfg_freqchngctl(n) = 0x00000000 freqchngfspop = 0x0 freqchngfspopupd = 0x0 freqchngmrwcnt_freq0 = 0x0 freqchngmrwcnt_freq1 = 0x0 freqchngmrwcnt_freq2 = 0x0 freqchngmrwcnt_freq3 = 0x0 freqchngrunsocupd = 0x0

-

No

-

Wait 2us for the soc update to finish

-

-

-

#### 14. AMP Dynamic DQ Calibration

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WRLVL, 0, 0, 0, 0, 0, 28, 14);

-

-

-

FPGA: Skip this step

amph_CFGH_DQS0_WKPUPD(n) = 0x00010782 idle_active_en_f0 = 0x1 idle_active_en_f1 = 0x0 idle_active_en_f2 = 0x0 idle_active_en_f3 = 0x0 pdpwk_f0 = 0x1 pdpwk_f1 = 0x0 pdpwk_f2 = 0x0 pdpwk_f3 = 0x1 pupwk_f0 = 0x0 pupwk_f1 = 0x0 pupwk_f2 = 0x0 pupwk_f3 = 0x0 wkds = 0x7

-

-

-

FPGA: Skip this step

amph_CFGH_DQS1_WKPUPD(n) = 0x00010782 idle_active_en_f0 = 0x1 idle_active_en_f1 = 0x0 idle_active_en_f2 = 0x0 idle_active_en_f3 = 0x0 pdpwk_f0 = 0x1 pdpwk_f1 = 0x0 pdpwk_f2 = 0x0 pdpwk_f3 = 0x1 pupwk_f0 = 0x0 pupwk_f1 = 0x0 pupwk_f2 = 0x0 pupwk_f3 = 0x0 wkds = 0x7

-

-

-

step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, RD_DQ_CAL, 0, 0, 0, 0, 0, 28, 14);

-

-

-

step14Calibration(0, resume_boot, AMC_NUM_CHANS, AMC_NUM_RANKS, WR_DQ_CAL, 0, 0, 0, 0, 0, 28, 14);

-

-

-

#### 15. Setup registers for boot.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

Program FSP-WR to 0 and FSP-OP to 1 and reset VRCG
FPGA: Skip this step

amcx_dramcmd_mrinitcmd(n) = 0x900d0100 MRCmdAddr = 0xd MRCmdCs = 0x0 MRCmdData = 0x90 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

No

-

Poll dramcmd mrinitcmd
FPGA: Skip this step

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

No

-

Program FSP-WR to 1 and FSP-OP to 0 and reset VRCG
FPGA: Perform this step

amcx_dramcmd_mrinitcmd(n) = 0x500d0100 MRCmdAddr = 0xd MRCmdCs = 0x0 MRCmdData = 0x50 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x0 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

-

-

Poll dramcmd mrinitcmd
FPGA: Perform this step

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

-

-

Wait 1us for FSP setting to take affect.

-

-

-

Program FreqChngMRW Cnt

amcx_dramcfg_freqchngctl(n) = 0x00009999 freqchngfspop = 0x0 freqchngfspopupd = 0x0 freqchngmrwcnt_freq0 = 0x9 freqchngmrwcnt_freq1 = 0x9 freqchngmrwcnt_freq2 = 0x9 freqchngmrwcnt_freq3 = 0x9 freqchngrunsocupd = 0x0

-

No

-

ampsdq_ampsdqsdllctrl_WrDqDqsSDLLCtrl(n) = 0xff000008
WrDqDqsRunSDLLUpd = 0x0
WrDqDqsRunSDLLUpdOverride = 0x0
WrDqDqsRunSDLLUpdWrResult = 0x0
WrDqDqsWrLvlReBalanceEn = 0x1
WrDqSDLLAddHalfClk_f0 = 0x0
WrDqSDLLAddHalfClk_f1 = 0x0
WrDqSDLLAddHalfClk_f2 = 0x0
WrDqSDLLAddHalfClk_f3 = 0x0
WrDqSDLLHalfClkEn = 0x0
WrDqSDLLHalfClkOvrVal = 0x0
WrDqSDLLHalfClkStatus = 0x0 *read-only
WrDqSDLLOvrVal = 0x0
WrDqsSDLLOvrVal = 0xff

-

No

-

RdDqSDLLDelaySel
DO_CALIBRATION: Skip this step

ampsdq_ampsdqsdllctrl_RdDqSDLLDelaySel(n) = 0x00000000 RdDqSDLLDelaySel = 0x0

-

No

-

rd0sdllctrl
DO_CALIBRATION: Skip this step

ampsdq_ampsdqsdllctrl_rd0sdllctrl(n) = 0x00140004 Rd0RunSDLLUpd = 0x0 Rd0RunSDLLUpdOverride = 0x0 Rd0RunSDLLUpdWrResult = 0x1 Rd0SDLLOvrVal = 0x14

-

No

-

Poll ampsdqsdllctrl rd0sdllctrl
DO_CALIBRATION: Skip this step

Poll: ampsdqsdllctrl_rd0sdllctrl Rd0RunSDLLUpdWrResult while((CSR(ampsdq_ampsdqsdllctrl_rd0sdllctrl(n)) & 0x4) != 0x0)

-

No

-

FPGA: Skip this step
PALLADIUM: Skip this step

ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000000 HWRdDqCalFullScanEnable = 0x0 HWRdDqCalFullScanEnable16bit = 0x0 HWWrDqCalFullScanEnable = 0x0

-

-

-

FPGA: Skip this step
PALLADIUM: Skip this step

ampsca_ampscaRdWrDqCal_HWRdWrDqCalFullScanEnable(n) = 0x00000003 HWRdDqCalFullScanEnable = 0x1 HWRdDqCalFullScanEnable16bit = 0x0 HWWrDqCalFullScanEnable = 0x1

-

-

-

ampsca_ampscaRdWrDqCal_HWRdDqCalVREFControl(n) = 0x02d0b061 HWRdDqCalVREFEnable = 0x1 HWRdDqCalVREFMax = 0xd0 HWRdDqCalVREFMaxOffsetScaleFactor = 0x2 HWRdDqCalVREFMaxScoreSel = 0x0 HWRdDqCalVREFMin = 0xb0 HWRdDqCalVREFNumPoints = 0x6 HWRdDqCalVREFScoreMinSel = 0x0 HWRdDqCalVREFStaticSel = 0x0

-

-

-

ampsca_ampscaRdWrDqCal_HWWrDqCalVREFControl(n) = 0x02200061 HWWrDqCalVREFEnable = 0x1 HWWrDqCalVREFMax = 0x20 HWWrDqCalVREFMaxOffsetScaleFactor = 0x2 HWWrDqCalVREFMaxScoreSel = 0x0 HWWrDqCalVREFMin = 0x0 HWWrDqCalVREFNumPoints = 0x6 HWWrDqCalVREFScoreMinSel = 0x0 HWWrDqCalVREFStaticSel = 0x0

-

-

-

#### 16. Enable other features

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

Turn on the freq change waiting for refresh and self-refresh exit feature

amcx_dramcfg_arefparam(n) = 0x0d012019 FreqChngWaitThr = 0x1 PhyUpdWaitRefresh = 0x1 PhyUpdWaitThr = 0x1 PhyUpdWaittXSR = 0x0 PreFreqChngWaitThr = 0x2 RefAssertCnt = 0xd SRExitRefCnt = 0x1

-

-

-

Enable periodic ZQC. (Optional)
Note the ZqCalIntrvl setting shown here is based on tREFI=3.9us and the target interval is ~128ms (max supported value). The actual setting may vary depending on the DRAM and the system.

if (platform == FPGA)
amcx_dramcfg_odtszqc(n) = 0xc0000000 DerateParamSRExit = 0x0 OdtsRdIntrvl = 0x0 SRExitZQCChnlQuiet = 0x1 ShareZQRes = 0x0 TempDrtEn = 0x0 ZQCChnlQuiet = 0x0 ZQCStack = 0x1 ZqCalIntrvl = 0x0
else
amcx_dramcfg_odtszqc(n) = 0xc0001000 DerateParamSRExit = 0x0 OdtsRdIntrvl = 0x0 SRExitZQCChnlQuiet = 0x1 ShareZQRes = 0x0 TempDrtEn = 0x1 ZQCChnlQuiet = 0x0 ZQCStack = 0x1 ZqCalIntrvl = 0x0

-

-

-

Turn on the QBR enables.

amcx_mcusch_qbren(n) = 0x0000000d ErlyQbrEn = 0x1 LateQbrEn = 0x1 MifQbrEn = 0x1 PredictiveM2AReq = 0x0

-

-

-

amcx_dramcfg_arefen_freq3(n) = 0x10100000 ARpbEn_freq3 = 0x0 HiTempRefRnkAgeOut_freq3 = 0x1 RefCntrHiWaterMark_freq3 = 0x1 RefCntrLoWaterMark_freq3 = 0x0

-

No

-

amcx_dramcfg_arefen_freq2(n) = 0x10000000 ARpbEn_freq2 = 0x0 HiTempRefRnkAgeOut_freq2 = 0x0 RefCntrHiWaterMark_freq2 = 0x1 RefCntrLoWaterMark_freq2 = 0x0

-

No

-

amcx_dramcfg_arefen_freq1(n) = 0x10010000 ARpbEn_freq1 = 0x1 HiTempRefRnkAgeOut_freq1 = 0x0 RefCntrHiWaterMark_freq1 = 0x1 RefCntrLoWaterMark_freq1 = 0x0

-

No

-

Turn on auto refresh.

amcx_dramcfg_arefen_freq0(n) = 0x1011013f ARpbEn_freq0 = 0x1 AutoRefEn = 0x1 AutoRefSchEn = 0x1 DisableHiTempREFab = 0x1 EarlyCasAgeOut = 0x0 HiPriREFpbPch = 0x1 HiTempRefRnkAgeOut_freq0 = 0x1 REFpb2bank = 0x0 REFpbEarlyPch = 0x1 RefCntrHiWaterMark_freq0 = 0x1 RefCntrLoWaterMark_freq0 = 0x0 RefOpptEn = 0x1 tREFBWREFpb = 0x1

-

No

-

amph_CFGH_B0_DYN_ISEL_ASRTIME(n) = 0x00000019 rcvr_minisel_assrttime_f0 = 0x19 rcvr_minisel_assrttime_f1 = 0x0 rcvr_minisel_assrttime_f2 = 0x0 rcvr_minisel_assrttime_f3 = 0x0

-

-

-

amph_CFGH_B0_DYN_ISEL(n) = 0x00000001 dyn_isel_ctrl_en_f0 = 0x1 dyn_isel_ctrl_en_f1 = 0x0 dyn_isel_ctrl_en_f2 = 0x0 dyn_isel_ctrl_en_f3 = 0x0

-

-

-

#### 17. Enable the Fast Critical Word Forwarding feature (optional)

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

Configure the MIF FCWF pull- in cycles.
(Here we just use 0x8 as an example, please refer to register description for the valid programming range and refer to performance simulation results)

if (platform == FPGA)
amcx_mcusch_qbrparam(n) = 0x00000000 RdCwfEarlyCyc_freq0 = 0x0 RdCwfEarlyCyc_freq1 = 0x0 RdCwfEarlyCyc_freq2 = 0x0 RdCwfEarlyCyc_freq3 = 0x0 RdRemEarlyCyc_freq0 = 0x0 RdRemEarlyCyc_freq1 = 0x0 RdRemEarlyCyc_freq2 = 0x0 RdRemEarlyCyc_freq3 = 0x0
else
amcx_mcusch_qbrparam(n) = 0x000000a8 RdCwfEarlyCyc_freq0 = 0x8 RdCwfEarlyCyc_freq1 = 0x0 RdCwfEarlyCyc_freq2 = 0x0 RdCwfEarlyCyc_freq3 = 0x0 RdRemEarlyCyc_freq0 = 0xa RdRemEarlyCyc_freq1 = 0x0 RdRemEarlyCyc_freq2 = 0x0 RdRemEarlyCyc_freq3 = 0x0

-

-

-

Turn on the PredictiveM2AReq feature in MIF. (The other Qbr enables are turned on here, but not related to CWF feature)

if (platform == PALLADIUM)
amcx_mcusch_qbren(n) = 0x0000000d ErlyQbrEn = 0x1 LateQbrEn = 0x1 MifQbrEn = 0x1 PredictiveM2AReq = 0x0
else
amcx_mcusch_qbren(n) = 0x0000000f ErlyQbrEn = 0x1 LateQbrEn = 0x1 MifQbrEn = 0x1 PredictiveM2AReq = 0x1

-

-

-

amcc_mcccfg_MccGen = 0x00000126 DramAccessEn = 0x1 EccEn = 0x1 *read-only HitBypassEcc = 0x0 *read-only MccEn = 0x0 *read-only MccRamEn = 0x1 MccRamEnLock = 0x0 MccStop = 0x0 SpecRdEn = 0x0 SpecRdNum = 0x1

-

-

-

amcc_amccperfcntr_Mcc0QPropCtrl = 0x300011a2
Mcc0AfCacheRdPropQCmd = 0x1 *read-only
Mcc0AfCacheRdPropQTrakEnbl = 0x0 *read-only
Mcc0AfDramRdPropQCmd = 0x1
Mcc0AfDramRdPropQTrakEnbl = 0x0
Mcc0DpPropQCfg = 0x0
Mcc0DpPropQCmd = 0x1
Mcc0DpPropQTrakEnbl = 0x0
Mcc0MsqQPropCfg = 0x0
Mcc0MsqQPropQCmd = 0x0
Mcc0MsqQPropTrakEnbl = 0x0
Mcc0QpropOutSel = 0x3
Mcc0TpPropQCmd = 0x0
Mcc0TpPropQTrakEnbl = 0x1
Mcc0TpQPropSel = 0x4
Mcc0TpQpropMask = 0x0

-

-

-

amcc_amccperfcntr_Mcc1QPropCtrl = 0x300011a2
Mcc1AfCacheRdPropQCmd = 0x1 *read-only
Mcc1AfCacheRdPropQTrakEnbl = 0x0 *read-only
Mcc1AfDramRdPropQCmd = 0x1
Mcc1AfDramRdPropQTrakEnbl = 0x0
Mcc1DpPropQCfg = 0x0
Mcc1DpPropQCmd = 0x1
Mcc1DpPropQTrakEnbl = 0x0
Mcc1MsqQPropCfg = 0x0
Mcc1MsqQPropQCmd = 0x0
Mcc1MsqQPropTrakEnbl = 0x0
Mcc1QpropOutSel = 0x3
Mcc1TpPropQCmd = 0x0
Mcc1TpPropQTrakEnbl = 0x1
Mcc1TpQPropSel = 0x4
Mcc1TpQpropMask = 0x0

-

-

-

#### 18. Enable Power & ClockGating features and Configure the MCC and Global Timer

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

Enable AMPCA Fixed MCLK Clock Gating

ampsca_ampscagen_ampclk(n) = 0x00000000 FMClkIdleDetectEn = 0x0 ForceDRAMClkEn = 0x0 ForceDiv2MClkTopGaterOn = 0x0 ForceFMClkWakeUp = 0x0 ForceMClkWakeUp = 0x0 TopClkGateDis = 0x0

-

-

-

Enable AMPDQ Fixed MCLK Clock Gating

ampsdq_ampsdqgen_ampclk(n) = 0x00000000 FMClkIdleDetectEn = 0x0 ForceDRAMClkEn = 0x0 ForceDiv2MClkTopGaterOn = 0x0 ForceFMClkWakeUp = 0x0 ForceMClkWakeUp = 0x0 TopClkGateDis = 0x0

-

-

-

spllctrl_SpllCtrl_MDLLPwrDnCfg0(n) = 0x00000001 Freq3_en = 0x1 powergating_en = 0x0

-

-

-

disable dynamic power-down.

if (platform == FPGA)
amcx_dramcfg_pwrmngten(n) = 0x00000132 AutoSR = 0x1 DynPwrDnEn = 0x0 McPhyUpdDramClkOff = 0x0 PwrDnClkOff = 0x1 SRClkOff = 0x1 SRExitOpt = 0x1
else
amcx_dramcfg_pwrmngten(n) = 0x00000132 AutoSR = 0x1 DynPwrDnEn = 0x0 McPhyUpdDramClkOff = 0x0 PwrDnClkOff = 0x1 SRClkOff = 0x1 SRExitOpt = 0x1

-

-

-

enable dynamic power-down for cold boot.

if (platform == FPGA)
amcx_dramcfg_pwrmngten(n) = 0x00000132 AutoSR = 0x1 DynPwrDnEn = 0x0 McPhyUpdDramClkOff = 0x0 PwrDnClkOff = 0x1 SRClkOff = 0x1 SRExitOpt = 0x1
else
amcx_dramcfg_pwrmngten(n) = 0x00000133 AutoSR = 0x1 DynPwrDnEn = 0x1 McPhyUpdDramClkOff = 0x0 PwrDnClkOff = 0x1 SRClkOff = 0x1 SRExitOpt = 0x1

-

No

-

Enable wakeups from glbl timer to pmgr

glbtimer_GlbTimer_PmgrWakeUpCfg = 0x000001ff DccEn = 0x1 FreqChngEn = 0x1 IdtEn = 0x1 ImpCalEn = 0x1 MdllEn = 0x1 RdCalEn = 0x1 VoltRampEn = 0x1 WrCalEn = 0x1 ZQCalEn = 0x1

Yes

No

-

glbtimer_GlbTimer_PreFreq2AllBankDly0 = 0x00f000f0 PreFreqChng2AllBankDly_f0 = 0xf0 PreFreqChng2AllBankDly_f1 = 0xf0

-

-

-

glbtimer_GlbTimer_PreFreq2AllBankDly1 = 0x00f000f0 PreFreqChng2AllBankDly_f2 = 0xf0 PreFreqChng2AllBankDly_f3 = 0xf0

-

-

-

glbtimer_GlbTimer_PreFreqChng2FreqChngDly0 = 0x02400240 PreFreqChng2FreqChngDly_f0 = 0x240 PreFreqChng2FreqChngDly_f1 = 0x240

-

-

-

glbtimer_GlbTimer_PreFreqChng2FreqChngDly1 = 0x02400240 PreFreqChng2FreqChngDly_f2 = 0x240 PreFreqChng2FreqChngDly_f3 = 0x240

-

-

-

glbtimer_GlbTimer_CalSeg2AllBank0 = 0x00fa0120 CalSeg2AllBank_f0 = 0x120 CalSeg2AllBank_f1 = 0xfa

-

-

-

glbtimer_GlbTimer_AllBank2CalSeg0 = 0x00fa0120 AllBank2CalSeg_f0 = 0x120 AllBank2CalSeg_f1 = 0xfa

-

-

-

PALLADIUM: Skip this step

glbtimer_GlbTimer_MdllTimer = 0x00000bb8 MdllTimerCnt = 0xbb8

Yes

-

-

PALLADIUM: Skip this step

glbtimer_GlbTimer_DCCTimer = 0x00000bb8 DCCTimerCnt = 0xbb8

Yes

-

-

PALLADIUM: Skip this step

glbtimer_GlbTimer_MdllVoltRampTimer = 0x0000004b MdllVoltRampTimerCnt = 0x4b

Yes

-

-

PALLADIUM: Skip this step

glbtimer_GlbTimer_CtrlUpdMaskTimer = 0x0000000f CtrlUpdMaskTimerCnt = 0xf

Yes

-

-

PALLADIUM: Skip this step

glbtimer_GlbTimer_RdCalTimer = 0x002dc6bb RdCalTimerCnt = 0x2dc6bb

Yes

-

-

PALLADIUM: Skip this step

glbtimer_GlbTimer_WrCalTimer = 0x002dc6c0 WrCalTimerCnt = 0x2dc6c0

Yes

-

-

PALLADIUM: Skip this step

glbtimer_GlbTimer_ZQCTimer = 0x003d0900 ZQCTimerCnt = 0x3d0900

Yes

-

-

PALLADIUM: Skip this step

glbtimer_GlbTimer_PerCal_FreqChngTimer = 0x00000001 PerCal_FreqChngTimerCnt = 0x1

Yes

-

-

PALLADIUM: Skip this step

glbtimer_GlbTimer_ImpCalTimer = 0x00002ee0 ImpCalTimerCnt = 0x2ee0

Yes

-

-

Dynamic clk pwr gating reg

amcx_amcgen_amcclkpwrgate(n) = 0x050a0000 ClkPwrWaitCyc = 0xa MCUBCGClkGateEn = 0x0 MCUBCGPwrGateEn = 0x0 PwrRstCyc = 0x5

-

-

-

#### 19. Do a ODTS read and set ODTS interval so MR4 on-die temperature sensor read occurs periodically.

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

Perform an MRR to DRAM mode register MR4 to establish a base value for ODTS reading.
Another intention is to bring DRAM out of self-refresh. Done in both cold boot and resume boot.

amcx_dramcmd_mrinitcmd(n) = 0x50041100 MRCmdAddr = 0x4 MRCmdCs = 0x0 MRCmdData = 0x50 MRCmdIsMPC = 0x0 MRCmdIsRd = 0x1 RunMRCmd = 0x1 RunRdLvl = 0x0 RunSRExit = 0x0

-

-

-

Poll dramcmd mrinitcmd

Poll: dramcmd_mrinitcmd RunMRCmd while((CSR(amcx_dramcmd_mrinitcmd(n)) & 0x100) != 0x0)

-

-

-

Enable periodic ODTS and temperature based refresh rate modulation. (Optional)
Note the OdtsRdIntrvl setting shown here is based on tREFI=3.9us and the target interval is ~100. The actual setting may vary depending on the DRAM and the system.
Palladium: this step is skipped, ODTS is not supported
PALLADIUM: Skip this step

if (platform == FPGA)
amcx_dramcfg_odtszqc(n) = 0xc0002320 DerateParamSRExit = 0x1 OdtsRdIntrvl = 0x320 SRExitZQCChnlQuiet = 0x1 ShareZQRes = 0x0 TempDrtEn = 0x0 ZQCChnlQuiet = 0x0 ZQCStack = 0x1 ZqCalIntrvl = 0x0
else
amcx_dramcfg_odtszqc(n) = 0xc0003320 DerateParamSRExit = 0x1 OdtsRdIntrvl = 0x320 SRExitZQCChnlQuiet = 0x1 ShareZQRes = 0x0 TempDrtEn = 0x1 ZQCChnlQuiet = 0x0 ZQCStack = 0x1 ZqCalIntrvl = 0x0

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#### Mcc Cache Initialization. This section is not part of the essential init sequence. This should be run when the system is done using the CacheAsRam

Description | Register Programming | AOP AWAKE | Resume Boot | AOP DDR
--- | --- | --- | --- | ---

amcc_mcccfg_MccGen = 0x00000124 DramAccessEn = 0x1 EccEn = 0x1 *read-only HitBypassEcc = 0x0 *read-only MccEn = 0x0 *read-only MccRamEn = 0x0 MccRamEnLock = 0x0 MccStop = 0x0 SpecRdEn = 0x0 SpecRdNum = 0x1

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Program AF Allocation Hints, allocation does not happen unless there is a hint as the generic allocation policy

amcc_mcccfg_MccAlcHint = 0x00001110 MccAlcHintEn = 0x1 *read-only MccGenericAlc = 0x0 *read-only MccSclDtyEn = 0x1 *read-only MccStickyEn = 0x1 *read-only

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program mccgen

amcc_mcccfg_MccGen = 0x00000194 DramAccessEn = 0x1 EccEn = 0x1 *read-only HitBypassEcc = 0x0 *read-only MccEn = 0x0 *read-only MccRamEn = 0x0 MccRamEnLock = 0x0 MccStop = 0x0 SpecRdEn = 0x1 SpecRdNum = 0x4

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