/*
 * Copyright (C) 2012-2015 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */
#ifndef __PLATFORM_SOC_PMGR_H
#define __PLATFORM_SOC_PMGR_H

#include <lib/devicetree.h>
#include <platform/soc/hwregbase.h>
#include <soc/t8010/a0/acc.h>
#include <soc/t8010/a0/minipmgr.h>
#include <soc/t8010/a0/pmgr.h>

////////////////////////////////////////////////////////////
//
//  PMGR specific
//
////////////////////////////////////////////////////////////

enum coreTyp {
	kACC_CORETYP_ECORE,
	kACC_CORETYP_PCORE,
	kACC_CORETYP_FUSED
};

#define PMGR_PLL_COUNT			(7)

#define PMGR_PLL_REG_STRIDE		(PMGR_PLL1_OFFSET - PMGR_PLL0_OFFSET)

#define rPMGR_PLL_CTL(_p)		(*(volatile uint32_t *)(PMGR_BASE_ADDR + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
#define	 PMGR_PLL_ENABLE		(1 << PMGR_PLL0_CTL_ENABLE_SHIFT)
#define	 PMGR_PLL_LOAD			(1 << PMGR_PLL0_CTL_LOAD_SHIFT)
#define	 PMGR_PLL_BYPASS		(1 << PMGR_PLL0_CTL_BYPASS_SHIFT)
#define	 PMGR_PLL_PENDING		(1 << PMGR_PLL0_CTL_PLL_PENDING_SHIFT)
#define	 PMGR_PLL_M_SHIFT		PMGR_PLL0_CTL_FB_DIVN_SHIFT
#define	 PMGR_PLL_M_MASK		PMGR_PLL0_CTL_FB_DIVN_SMASK
#define	 PMGR_PLL_P_SHIFT		PMGR_PLL0_CTL_PRE_DIVN_SHIFT
#define	 PMGR_PLL_P_MASK		PMGR_PLL0_CTL_PRE_DIVN_SMASK
#define	 PMGR_PLL_S_SHIFT		PMGR_PLL0_CTL_OP_DIVN_SHIFT
#define	 PMGR_PLL_S_MASK		PMGR_PLL0_CTL_OP_DIVN_SMASK
#define	 PMGR_PLL_PCIE_S_MASK		PMGR_PLL_PCIE_CTL_OP_DIVN_SMASK
#define	 PMGR_PLL_M(_m)			(((_m) & PMGR_PLL_M_MASK) << PMGR_PLL_M_SHIFT)
#define	 PMGR_PLL_P(_p)			(((_p) & PMGR_PLL_P_MASK) << PMGR_PLL_P_SHIFT)
#define	 PMGR_PLL_S(_s)			(((_s) & PMGR_PLL_S_MASK) << PMGR_PLL_S_SHIFT)
#define	 PMGR_PLL_PCIE_S(_s)		(((_s) & PMGR_PLL_PCIE_S_MASK) << PMGR_PLL_S_SHIFT)
#define	 PMGR_PLL_FREQ(_m, _p, _s)	((((_m) * OSC_FREQ) / (_p))/((_s) + 1))

#define rPMGR_PLL_CFG(_p)		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0004 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
#define	 PMGR_PLL_OFF_MODE(_n)		PMGR_PLL0_CFG_OFF_MODE_INSRT(_n)
#define	 PMGR_PLL_OFF_MODE_RESET	(0)
#define	 PMGR_PLL_OFF_MODE_CLOCK_GATED	(1)
#define	 PMGR_PLL_OFF_MODE_POWER_DOWN	(2)
#define	 PMGR_PLL_LOCK_MODE(_n)		PMGR_PLL0_CFG_LOCK_MODE_INSRT(_n)
#define	 PMGR_PLL_LOCK_MODE_COUNTER	(0)
#define	 PMGR_PLL_LOCK_MODE_LOCK	(1)
#define	 PMGR_PLL_AUTO_DISABLE		(1 << PMGR_PLL0_CFG_AUTO_DISABLE_SHIFT)
#define	 PMGR_PLL_RELOCK_MODE_SHIFT	PMGR_PLL0_CFG_RELOCK_MODE_SHIFT
#define	 PMGR_PLL_RELOCK_MODE_MASK	PMGR_PLL0_CFG_RELOCK_MODE_SMASK
#define	 PMGR_PLL_RELOCK_MODE_STOP	(0)
#define	 PMGR_PLL_RELOCK_MODE_BYPASS	(1)
#define	 PMGR_PLL_FRAC_LOCK_TIME(_n)	PMGR_PLL0_CFG_FRAC_LOCK_TIME_INSRT(_n)
#define	 PMGR_PLL_LOCK_TIME(_n)		PMGR_PLL0_CFG_LOCK_TIME_INSRT(_n)

#define rPMGR_PLL_ANA_PARAMS1(_p)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x000c + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
#define rPMGR_PLL_ANA_PARAMS2(_p)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0010 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
#define rPMGR_PLL_ANA_PARAMS3(_p)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0014 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))

#define rPMGR_PLL_DEBUG1(_p)			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0014 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))
#define  PMGR_PLL_DEBUG1_RESERVE_IN_SHIFT	(20)
#define  PMGR_PLL_DEBUG1_RESERVE_IN_MASK 	(0x3f)

#define rPMGR_PLL_PCIE_DELAY_CTL0(_p)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0028 + ((_p == PLL_PCIE) ? PMGR_PLL_PCIE_OFFSET : ((_p) * PMGR_PLL_REG_STRIDE))))

#define rPMGR_CLK_CFG(_x)		(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_CLKCFG_##_x##_CLK_CFG_OFFSET))

#define PMGR_CLK_CFG_ENABLE		(1 << 31)
#define PMGR_CLK_CFG_PENDING		(1 << 30)
#define PMGR_CLK_CFG_PENDING_SHIFT	(30)
#define PMGR_CLK_CFG_SRC_SEL_MASK	(0xF)
#define PMGR_CLK_CFG_SRC_SEL_SHIFT	(24)
#define PMGR_CLK_CFG_DIVISOR_MASK	(0x3F)

#define PMGR_SPARE_COUNT		(7)

#define rPMGR_CLK_DIVIDER_ACG_CFG	(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_CLKCFG_CLK_DIVIDER_ACG_CFG_OFFSET))

#define PMGR_NCO_REG_STRIDE		(PMGR_NCO_1_CLK_CFG_OFFSET - PMGR_NCO_0_CLK_CFG_OFFSET)

#define rPMGR_NCO_CLK_CFG(_n)		(*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_CLK_CFG_OFFSET))
#define rPMGR_NCO_DIV_INT(_n)		(*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_INT_OFFSET))
#define rPMGR_NCO_DIV_FRAC_N1(_n)	(*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_FRAC_N1_OFFSET))
#define rPMGR_NCO_DIV_FRAC_N2(_n)	(*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_FRAC_N2_OFFSET))
#define rPMGR_NCO_DIV_FRAC_PRIME(_n)	(*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * PMGR_NCO_REG_STRIDE + PMGR_NCO_0_DIV_FRAC_PRIME_OFFSET))

#define PMGR_NCO_CLK_CFG_ENABLE		(1 << PMGR_NCO_0_CLK_CFG_ENABLE_SHIFT)
#define PMGR_NCO_CLK_CFG_PENDING	(1 << PMGR_NCO_0_CLK_CFG_PENDING_SHIFT)

#define PMGR_NUM_NCO			(5)

#define kSOC_PERF_STATE_BYPASS		(0)
#define kSOC_PERF_STATE_SECUREROM	(kSOC_PERF_STATE_BYPASS + 1)
#define kSOC_PERF_STATE_IBOOT		(kSOC_PERF_STATE_BYPASS + 2)
#define kSOC_PERF_STATE_VMIN		(kSOC_PERF_STATE_IBOOT + 0)
#define kSOC_PERF_STATE_VNOM		(kSOC_PERF_STATE_IBOOT + 1)

#define kSOC_PERF_STATE_VMAX		(kSOC_PERF_STATE_VNOM)

#define kSOC_PERF_STATE_IBOOT_CNT	(kSOC_PERF_STATE_VMAX + 1)
#define kSOC_PERF_STATE_MAX_CNT		(14)

#define rPMGR_SOC_PERF_STATE_CTL		(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_CTL_OFFSET))
#define  PMGR_SOC_PERF_STATE_CTL_PENDING_MASK	(1 << PMGR_SOC_PERF_STATE_CTL_PENDING_SHIFT)

#define PMGR_SOC_PERF_STATE_STRIDE		(PMGR_SOC_PERF_STATE_ENTRY_1A_OFFSET - PMGR_SOC_PERF_STATE_ENTRY_0A_OFFSET)

#define rPMGR_SOC_PERF_STATE_ENTRY_A(_n)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0A_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
#define rPMGR_SOC_PERF_STATE_ENTRY_B(_n)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0B_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
#define rPMGR_SOC_PERF_STATE_ENTRY_C(_n)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0C_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))
#define rPMGR_SOC_PERF_STATE_ENTRY_D(_n)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SOC_PERF_STATE_ENTRY_0D_OFFSET + (_n) * PMGR_SOC_PERF_STATE_STRIDE))

#define PMGR_SOC_PERF_STATE_ENTRY_MCU_REF_MASK		(PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_SRC_SEL_UMASK | PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_CFG_SEL_UMASK)
#define PMGR_SOC_PERF_STATE_ENTRY_MCU_REF(_cfg, _src)	(PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_SRC_SEL_INSRT(_src) | PMGR_SOC_PERF_STATE_ENTRY_0A_MCU_REF_CFG_SEL_INSRT(_cfg))
#define PMGR_SOC_PERF_STATE_ENTRY_VID0(_src)		(PMGR_SOC_PERF_STATE_ENTRY_0B_VID0_SRC_SEL_INSRT(_src))
#define PMGR_SOC_PERF_STATE_ENTRY_VOLTAGE(_v)		(PMGR_SOC_PERF_STATE_ENTRY_0C_VOLTAGE_INSRT(_v))

#define PMGR_SOC_PERF_STATE_ENTRY_COUNT (16)
// First two entries used by AOP Config Engine
#define PMGR_SOC_PERF_STATE_FIRST_ENTRY		(PMGR_SOC_PERF_STATE_ENTRY_COUNT - kSOC_PERF_STATE_MAX_CNT)
#define PMGR_SOC_PERF_STATE_TO_ENTRY(_s)	(PMGR_SOC_PERF_STATE_ENTRY_COUNT - (_s) - 1)

#define kPMGR_GFX_STATE_MAX			(16)
#define rPMGR_GFX_PERF_STATE_ENTRY_A(_n)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + (_n) * 0x10 + PMGR_GFX_PERF_STATE_ENTRY0A_OFFSET))
#define rPMGR_GFX_PERF_STATE_ENTRY_B(_n)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + (_n) * 0x10 + PMGR_GFX_PERF_STATE_ENTRY0B_OFFSET))
#define rPMGR_GFX_PERF_STATE_ENTRY_C(_n)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + (_n) * 0x10 + PMGR_GFX_PERF_STATE_ENTRY0C_OFFSET))
#define rPMGR_GFX_PERF_STATE_CTL		(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_GFX_PERF_STATE_CTL_OFFSET))
#define  PMGR_GFX_PERF_STATE_CTL_ENABLE		(1 << PMGR_GFX_PERF_STATE_CTL_ENABLE_SHIFT)
#define rPMGR_GFX_PERF_STATE_SOCHOT		(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_GFX_PERF_STATE_SOCHOT_OFFSET))

#define rPMGR_PS(_x)			(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_PS_##_x##_PS_OFFSET))

#define	 PMGR_PS_RESET			(1 << 31)
#define	 PMGR_PS_AUTO_PM_EN		(1 << 28)
#define	 PMGR_PS_FORCE_NOACCESS		(1 << 10)
#define	 PMGR_PS_ACTUAL_PS_SHIFT	(4)
#define	 PMGR_PS_ACTUAL_PS_MASK		(0xF)
#define	 PMGR_PS_MANUAL_PS_MASK		(0xF)
#define	 PMGR_PS_RUN_MAX		(0xF)
#define	 PMGR_PS_CLOCK_OFF		(0x4)
#define	 PMGR_PS_POWER_OFF		(0x0)

#define rPMGR_VOLMAN_CTL		(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CTL_OFFSET))
#define rPMGR_VOLMAN_BUCK_MAP		(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_BUCK_MAP_OFFSET))
#define rPMGR_VOLMAN_SOC_VOLTAGE	(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_SOC_VOLTAGE_OFFSET))
#define rPMGR_VOLMAN_GFX_SRAM_VOLTAGE	(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_SRAM_VOLTAGE_OFFSET))
#define rPMGR_VOLMAN_CPU_SRAM_VOLTAGE	(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_SRAM_VOLTAGE_OFFSET))
#define rPMGR_VOLMAN_GFX_VOLTAGE	(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_VOLTAGE_OFFSET))
#define rPMGR_VOLMAN_CPU_VOLTAGE	(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_VOLTAGE_OFFSET))
#define rPMGR_VOLMAN_SOC_DELAY		(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_SOC_DELAY_OFFSET))
#define rPMGR_VOLMAN_GFX_SRAM_DELAY	(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_SRAM_DELAY_OFFSET))
#define rPMGR_VOLMAN_CPU_SRAM_DELAY	(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_SRAM_DELAY_OFFSET))
#define rPMGR_VOLMAN_GFX_DELAY		(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_GFX_DELAY_OFFSET))
#define rPMGR_VOLMAN_CPU_DELAY		(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_VOLMAN_CPU_DELAY_OFFSET))

#define	 PMGR_VOLMAN_DISABLE_CPU_VOL_CHANGE		(1 << PMGR_VOLMAN_CTL_DISABLE_CPU_VOL_CHANGE_SHIFT)
#define	 PMGR_VOLMAN_DISABLE_GFX_VOL_CHANGE		(1 << PMGR_VOLMAN_CTL_DISABLE_GFX_VOL_CHANGE_SHIFT)
#define	 PMGR_VOLMAN_DISABLE_CPU_SRAM_VOL_CHANGE	(1 << PMGR_VOLMAN_CTL_DISABLE_CPU_SRAM_VOL_CHANGE_SHIFT)
#define	 PMGR_VOLMAN_DISABLE_GFX_SRAM_VOL_CHANGE	(1 << PMGR_VOLMAN_CTL_DISABLE_GFX_SRAM_VOL_CHANGE_SHIFT)
#define	 PMGR_VOLMAN_DISABLE_SOC_VOL_CHANGE		(1 << PMGR_VOLMAN_CTL_DISABLE_SOC_VOL_CHANGE_SHIFT)

#define  PMGR_VOLMAN_VOLTAGE_PENDING	(1 << 31)

#define rPMGR_EMA_FIXED_SOC0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_SOC0_OFFSET)
#define rPMGR_EMA_FIXED_SOC1		(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_SOC1_OFFSET)
#define rPMGR_EMA_GPU_SRAM_GFX		(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_GPU_SRAM_GFX_OFFSET)
#define rPMGR_EMA_FIXED_GFX		(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_FIXED_GFX_OFFSET)
#define rPMGR_EMA_FIXED_SEP0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + PMGR_EMA_FIXED_FIXED_SEP0_OFFSET)

#define rPMGR_SCRATCH(_n)		(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_SCRATCH_0_OFFSET + ((_n)*4)))
#define rPMGR_SCRATCH0			rPMGR_SCRATCH(0)		/* Flags */
#define rPMGR_SCRATCH1			rPMGR_SCRATCH(1)
#define rPMGR_SCRATCH2			rPMGR_SCRATCH(2)
#define rPMGR_SCRATCH3			rPMGR_SCRATCH(3)
#define rPMGR_SCRATCH4			rPMGR_SCRATCH(4)
#define rPMGR_SCRATCH5			rPMGR_SCRATCH(5)
#define rPMGR_SCRATCH6			rPMGR_SCRATCH(6)
#define rPMGR_SCRATCH7			rPMGR_SCRATCH(7)
#define rPMGR_SCRATCH8			rPMGR_SCRATCH(8)
// Use the symbolic functional name assignments below for these scratch registers
//#define rPMGR_SCRATCH9		rPMGR_SCRATCH(9)		/* Memory info */
//#define rPMGR_SCRATCH10		rPMGR_SCRATCH(10)		/* Boot Nonce 0 */
//#define rPMGR_SCRATCH11		rPMGR_SCRATCH(11)		/* Boot Nonce 1 */
//#define rPMGR_SCRATCH12		rPMGR_SCRATCH(12)		/* Boot Manifest Hash 0 */
//#define rPMGR_SCRATCH13		rPMGR_SCRATCH(13)		/* Boot Manifest Hash 1 */
//#define rPMGR_SCRATCH14		rPMGR_SCRATCH(14)		/* Boot Manifest Hash 2 */
//#define rPMGR_SCRATCH15		rPMGR_SCRATCH(15)		/* Boot Manifest Hash 3 */
//#define rPMGR_SCRATCH16		rPMGR_SCRATCH(16)		/* Boot Manifest Hash 4 */
//#define rPMGR_SCRATCH17		rPMGR_SCRATCH(17)		/* Boot Manifest Hash 5 */
//#define rPMGR_SCRATCH18		rPMGR_SCRATCH(18)		/* Boot Manifest Hash 6 */
//#define rPMGR_SCRATCH19		rPMGR_SCRATCH(19)		/* Boot Manifest Hash 7 */
//#define rPMGR_SCRATCH20		rPMGR_SCRATCH(20)		/* Boot Manifest Hash 8 */
//#define rPMGR_SCRATCH21		rPMGR_SCRATCH(21)		/* Boot Manifest Hash 9 */
//#define rPMGR_SCRATCH22		rPMGR_SCRATCH(22)		/* Boot Manifest Hash 10 */
//#define rPMGR_SCRATCH23		rPMGR_SCRATCH(23)		/* Boot Manifest Hash 11 */

#define rPMGR_SCRATCH_MEM_INFO			rPMGR_SCRATCH(9)
#define rPMGR_SCRATCH_BOOT_NONCE_0		rPMGR_SCRATCH(10)
#define rPMGR_SCRATCH_BOOT_NONCE_1		rPMGR_SCRATCH(11)
#define rPMGR_SCRATCH_BOOT_MANIFEST_HASH_FIRST	rPMGR_SCRATCH(12)
#define rPMGR_SCRATCH_BOOT_MANIFEST_HASH_LAST	rPMGR_SCRATCH(23)
#define PMGR_SCRATCH_BOOT_MANIFEST_REGISTERS	(384 / 32)

#define rMINIPMGR_SCRATCH(_n)		(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_SCRATCH_OFFSET + ((_n)*4)))
#define rMINIPMGR_SCRATCH0		rMINIPMGR_SCRATCH(0)
#define rMINIPMGR_SCRATCH1		rMINIPMGR_SCRATCH(1)		/* Consistent debug root pointer */
#define rMINIPMGR_SCRATCH2		rMINIPMGR_SCRATCH(2)
#define rMINIPMGR_SCRATCH3		rMINIPMGR_SCRATCH(3)
#define rMINIPMGR_SCRATCH4		rMINIPMGR_SCRATCH(4)
#define rMINIPMGR_SCRATCH5		rMINIPMGR_SCRATCH(5)
#define rMINIPMGR_SCRATCH6		rMINIPMGR_SCRATCH(6)
#define rMINIPMGR_SCRATCH7		rMINIPMGR_SCRATCH(7)
#define rMINIPMGR_SCRATCH8		rMINIPMGR_SCRATCH(8)
#define rMINIPMGR_SCRATCH9		rMINIPMGR_SCRATCH(9)
#define rMINIPMGR_SCRATCH10		rMINIPMGR_SCRATCH(10)
#define rMINIPMGR_SCRATCH11		rMINIPMGR_SCRATCH(11)

#define rPMGR_THERMAL0_CTL0_SET			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL0_SET_OFFSET))
#define rPMGR_THERMAL0_CTL0_CLR			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL0_CLR_OFFSET))
#define rPMGR_THERMAL0_CTL1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL1_OFFSET))
#define rPMGR_THERMAL0_CTL2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_CTL2_OFFSET))
#define rPMGR_THERMAL0_STATUS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_STATUS_OFFSET))
#define rPMGR_THERMAL0_PARAM			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_PARAM_OFFSET))
#define rPMGR_THERMAL0_RDBK0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_RDBK0_OFFSET))
#define rPMGR_THERMAL0_RDBK1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_RDBK1_OFFSET))
#define rPMGR_THERMAL0_SUM			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_SUM_OFFSET))
#define rPMGR_THERMAL0_SUM_CNT			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_SUM_CNT_OFFSET))
#define rPMGR_THERMAL0_PIECE0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_PIECE0_OFFSET))
#define rPMGR_THERMAL0_PIECE1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_PIECE1_OFFSET))
#define rPMGR_THERMAL0_PIECE2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_PIECE2_OFFSET))
#define rPMGR_THERMAL0_ALARM0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM0_OFFSET))
#define rPMGR_THERMAL0_ALARM1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM1_OFFSET))
#define rPMGR_THERMAL0_ALARM2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM2_OFFSET))
#define rPMGR_THERMAL0_ALARM3			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_ALARM3_OFFSET))
#define rPMGR_THERMAL0_FAILSAFE_TRIP_TEMP_0	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_FAILSAFE_TRIP_TEMP_0_OFFSET))
#define rPMGR_THERMAL0_FAILSAFE_TRIP_TEMP_1	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_0_FAILSAFE_TRIP_TEMP_1_OFFSET))
#define rPMGR_THERMAL1_CTL0_SET			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL0_SET_OFFSET))
#define rPMGR_THERMAL1_CTL0_CLR			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL0_CLR_OFFSET))
#define rPMGR_THERMAL1_CTL1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL1_OFFSET))
#define rPMGR_THERMAL1_CTL2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_CTL2_OFFSET))
#define rPMGR_THERMAL1_STATUS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_STATUS_OFFSET))
#define rPMGR_THERMAL1_PARAM			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_PARAM_OFFSET))
#define rPMGR_THERMAL1_RDBK0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_RDBK0_OFFSET))
#define rPMGR_THERMAL1_RDBK1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_RDBK1_OFFSET))
#define rPMGR_THERMAL1_SUM			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_SUM_OFFSET))
#define rPMGR_THERMAL1_SUM_CNT			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_SUM_CNT_OFFSET))
#define rPMGR_THERMAL1_PIECE0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_PIECE0_OFFSET))
#define rPMGR_THERMAL1_PIECE1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_PIECE1_OFFSET))
#define rPMGR_THERMAL1_PIECE2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_PIECE2_OFFSET))
#define rPMGR_THERMAL1_ALARM0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM0_OFFSET))
#define rPMGR_THERMAL1_ALARM1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM1_OFFSET))
#define rPMGR_THERMAL1_ALARM2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM2_OFFSET))
#define rPMGR_THERMAL1_ALARM3			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_ALARM3_OFFSET))
#define rPMGR_THERMAL1_FAILSAFE_TRIP_TEMP_0	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_FAILSAFE_TRIP_TEMP_0_OFFSET))
#define rPMGR_THERMAL1_FAILSAFE_TRIP_TEMP_1	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_1_FAILSAFE_TRIP_TEMP_1_OFFSET))
#define rPMGR_THERMAL2_CTL0_SET			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL0_SET_OFFSET))
#define rPMGR_THERMAL2_CTL0_CLR			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL0_CLR_OFFSET))
#define rPMGR_THERMAL2_CTL1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL1_OFFSET))
#define rPMGR_THERMAL2_CTL2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_CTL2_OFFSET))
#define rPMGR_THERMAL2_STATUS			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_STATUS_OFFSET))
#define rPMGR_THERMAL2_PARAM			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_PARAM_OFFSET))
#define rPMGR_THERMAL2_RDBK0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_RDBK0_OFFSET))
#define rPMGR_THERMAL2_RDBK1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_RDBK1_OFFSET))
#define rPMGR_THERMAL2_SUM			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_SUM_OFFSET))
#define rPMGR_THERMAL2_SUM_CNT			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_SUM_CNT_OFFSET))
#define rPMGR_THERMAL2_PIECE0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_PIECE0_OFFSET))
#define rPMGR_THERMAL2_PIECE1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_PIECE1_OFFSET))
#define rPMGR_THERMAL2_PIECE2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_PIECE2_OFFSET))
#define rPMGR_THERMAL2_ALARM0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM0_OFFSET))
#define rPMGR_THERMAL2_ALARM1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM1_OFFSET))
#define rPMGR_THERMAL2_ALARM2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM2_OFFSET))
#define rPMGR_THERMAL2_ALARM3			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_ALARM3_OFFSET))
#define rPMGR_THERMAL2_FAILSAFE_TRIP_TEMP_0	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_FAILSAFE_TRIP_TEMP_0_OFFSET))
#define rPMGR_THERMAL2_FAILSAFE_TRIP_TEMP_1	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_THERMAL_2_FAILSAFE_TRIP_TEMP_1_OFFSET))

#define  PMGR_THERMAL0_PIECE0(_c, _o, _s)	(PMGR_THERMAL_0_PIECE0_START_CODE_INSRT(_c) | PMGR_THERMAL_0_PIECE0_OFFSET_INSRT(_o) | PMGR_THERMAL_0_PIECE0_SLOPE_INSRT(_s))
#define  PMGR_THERMAL0_PIECE1(_c, _o, _s)	(PMGR_THERMAL_0_PIECE1_START_CODE_INSRT(_c) | PMGR_THERMAL_0_PIECE1_OFFSET_INSRT(_o) | PMGR_THERMAL_0_PIECE1_SLOPE_INSRT(_s))
#define  PMGR_THERMAL0_PIECE2(_c, _o, _s)	(PMGR_THERMAL_0_PIECE2_START_CODE_INSRT(_c) | PMGR_THERMAL_0_PIECE2_OFFSET_INSRT(_o) | PMGR_THERMAL_0_PIECE2_SLOPE_INSRT(_s))
#define  PMGR_THERMAL1_PIECE0(_c, _o, _s)	(PMGR_THERMAL_1_PIECE0_START_CODE_INSRT(_c) | PMGR_THERMAL_1_PIECE0_OFFSET_INSRT(_o) | PMGR_THERMAL_1_PIECE0_SLOPE_INSRT(_s))
#define  PMGR_THERMAL1_PIECE1(_c, _o, _s)	(PMGR_THERMAL_1_PIECE1_START_CODE_INSRT(_c) | PMGR_THERMAL_1_PIECE1_OFFSET_INSRT(_o) | PMGR_THERMAL_1_PIECE1_SLOPE_INSRT(_s))
#define  PMGR_THERMAL1_PIECE2(_c, _o, _s)	(PMGR_THERMAL_1_PIECE2_START_CODE_INSRT(_c) | PMGR_THERMAL_1_PIECE2_OFFSET_INSRT(_o) | PMGR_THERMAL_1_PIECE2_SLOPE_INSRT(_s))
#define  PMGR_THERMAL2_PIECE0(_c, _o, _s)	(PMGR_THERMAL_2_PIECE0_START_CODE_INSRT(_c) | PMGR_THERMAL_2_PIECE0_OFFSET_INSRT(_o) | PMGR_THERMAL_2_PIECE0_SLOPE_INSRT(_s))
#define  PMGR_THERMAL2_PIECE1(_c, _o, _s)	(PMGR_THERMAL_2_PIECE1_START_CODE_INSRT(_c) | PMGR_THERMAL_2_PIECE1_OFFSET_INSRT(_o) | PMGR_THERMAL_2_PIECE1_SLOPE_INSRT(_s))
#define  PMGR_THERMAL2_PIECE2(_c, _o, _s)	(PMGR_THERMAL_2_PIECE2_START_CODE_INSRT(_c) | PMGR_THERMAL_2_PIECE2_OFFSET_INSRT(_o) | PMGR_THERMAL_2_PIECE2_SLOPE_INSRT(_s))

#define rPMGR_SOC_TVM_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_CTL_OFFSET))
#define rPMGR_SOC_TVM_THRESH0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH0_OFFSET))
#define rPMGR_SOC_TVM_THRESH1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH1_OFFSET))
#define rPMGR_SOC_TVM_THRESH2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH2_OFFSET))
#define rPMGR_SOC_TVM_TEMP0_CFG			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP0_CFG_OFFSET))
#define rPMGR_SOC_TVM_TEMP1_CFG			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP1_CFG_OFFSET))
#define rPMGR_SOC_TVM_DEBUG0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG0_OFFSET))
#define rPMGR_SOC_TVM_DEBUG1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG1_OFFSET))
#define rPMGR_SOC_TVM_DEBUG2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG2_OFFSET))

#define rPMGR_GFX_TVM_CTL			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_CTL_OFFSET))
#define rPMGR_GFX_TVM_THRESH0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH0_OFFSET))
#define rPMGR_GFX_TVM_THRESH1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH1_OFFSET))
#define rPMGR_GFX_TVM_THRESH2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_THRESH2_OFFSET))
#define rPMGR_GFX_TVM_TEMP0_CFG			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP0_CFG_OFFSET))
#define rPMGR_GFX_TVM_TEMP1_CFG			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_TEMP1_CFG_OFFSET))
#define rPMGR_GFX_TVM_DEBUG0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG0_OFFSET))
#define rPMGR_GFX_TVM_DEBUG1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG1_OFFSET))
#define rPMGR_GFX_TVM_DEBUG2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + PMGR_TVM_DEBUG2_OFFSET))

#define  PMGR_TVM_THRESH(_t)			((_t) & 0x1FF)
#define  PMGR_TVM_TEMP_CFG_MAX_OFFSET(_mo)	(((_mo) & 0x1FF) << 16)
#define  PMGR_TVM_TEMP_CFG_MIN_OFFSET(_mo)	(((_mo) & 0x1FF) << 0)

#define rPMGR_MISC_CFG_ACG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_MISC_CFG_ACG_OFFSET))

#define rPMGR_MISC_SPARE0			(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_MISC_SPARE_SPARE0_OFFSET))

#define rPMGR_DEBUG_PMGR_DEBUG20		(*(volatile uint32_t *)(PMGR_BASE_ADDR + PMGR_DEBUG_20_OFFSET))
#define rPMGR_PCIE_REFCLK_GOOD			rPMGR_DEBUG_PMGR_DEBUG20
#define  PMGR_PCIE_REFCLK_GOOD_UMASK		(PMGR_DEBUG_20_CLKGEN_PMGR_PCIE_REF_CLK_GOOD_UMASK)

#define rPMGR_CHIP_WDOG_TMR			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_TIMER_OFFSET))
#define rPMGR_CHIP_WDOG_RST_CNT			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_RESET_COUNT_OFFSET))
#define rPMGR_CHIP_WDOG_INTR_CNT		(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_INTERRUPT_COUNT_OFFSET))
#define rPMGR_CHIP_WDOG_CTL			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_CHIP_WATCHDOG_CONTROL_OFFSET))
#define rPMGR_SYS_WDOG_TMR			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_TIMER_OFFSET))
#define rPMGR_SYS_WDOG_RST_CNT			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_RESET_COUNT_OFFSET))
#define rPMGR_SYS_WDOG_CTL			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_WATCHDOG_SYS_WATCHDOG_CONTROL_OFFSET))

#define rMINIPMGR_LPPLL_CTL			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_LPPLL_CTL_OFFSET))
#define	 MINIPMGR_LPPLL_CTL_ENABLE		(1 << MINIPMGR_LPPLL_CTL_ENABLE_SHIFT)
#define	 MINIPMGR_LPPLL_CTL_PENDING		(1 << MINIPMGR_LPPLL_CTL_PENDING_SHIFT)
#define rMINIPMGR_LPPLL_CFG			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_LPPLL_CFG_OFFSET))

#define rMINIPMGR_CLK_CFG(_x)			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_CLKCFG_##_x##_CLK_CFG_OFFSET))
#define rMINIPMGR_CLK_DIVIDER_ACG_CFG		(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_CLKCFG_CLK_DIVIDER_ACG_CFG_OFFSET))

#define rMINIPMGR_PS(_x)			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_PS_##_x##_PS_OFFSET))

#define rMINIPMGR_MISC_CFG_ACG			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_MISC_CFG_ACG_OFFSET))
#define rMINIPMGR_MISC_CFG_CPU			(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_MINI_MISC_CFG_CPU_CFG_OFFSET))

#if SUB_PLATFORM_T8010
enum {
	PMGR_CLK_OSC = 0,			// 0x00
	PMGR_CLK_PLL0,				// 0x01
	PMGR_CLK_PLL1,				// 0x02
	PMGR_CLK_PLL2,				// 0x03
	PMGR_CLK_PLL3,				// 0x04
	PMGR_CLK_PLL4,				// 0x05
	PMGR_CLK_PLL5,				// 0x06
	PMGR_CLK_PLL_PCIE,			// 0x07
	PMGR_CLK_CPU,				// 0x08
	PMGR_CLK_GFX_FENDER,			// 0x09
	PMGR_CLK_FIRST = PMGR_CLK_GFX_FENDER,
	PMGR_CLK_MCU_REF,			// 0x0A
	PMGR_CLK_PMP,				// 0x0B
	PMGR_CLK_TEMP_MIPI_DSI,			// 0x0C
	PMGR_CLK_NCO_REF0,			// 0x0D
	PMGR_CLK_NCO_REF1,			// 0x0E
	PMGR_CLK_NCO_ALG0,			// 0x0F
	PMGR_CLK_NCO_ALG1,			// 0x10
	PMGR_CLK_HSICPHY_REF_12M,		// 0x11
	PMGR_CLK_USB480_0,			// 0x12
	PMGR_CLK_USB_OHCI_48M,			// 0x13
	PMGR_CLK_USB,				// 0x14
	PMGR_CLK_USB_FREE_60M,			// 0x15
	PMGR_CLK_SIO_C,				// 0x16
	PMGR_CLK_SIO_P,				// 0x17
	PMGR_CLK_SIO_AES,			// 0x18
	PMGR_CLK_HFD,				// 0x19
	PMGR_CLK_ISP_C,				// 0x1A
	PMGR_CLK_ISP_AHFD,			// 0x1B
	PMGR_CLK_ISP_PEARL,			// 0x1C
	PMGR_CLK_ISP,				// 0x1D
	PMGR_CLK_ISP_SENSOR0_REF,		// 0x1E
	PMGR_CLK_ISP_SENSOR1_REF,		// 0x1F
	PMGR_CLK_ISP_SENSOR2_REF,		// 0x20
	PMGR_CLK_VDEC,				// 0x21
	PMGR_CLK_VENC,				// 0x22
	PMGR_CLK_VID0,				// 0x23
	PMGR_CLK_DISP0,				// 0x24
	PMGR_CLK_AJPEG_IP,			// 0x25
	PMGR_CLK_AJPEG_WRAP,			// 0x26
	PMGR_CLK_MSR,				// 0x27
	PMGR_CLK_FAST_AF,			// 0x28
	PMGR_CLK_SLOW_AF,			// 0x29
	PMGR_CLK_SBR,				// 0x2A
	PMGR_CLK_MCA0_M,			// 0x2B
	PMGR_CLK_MCA1_M,			// 0x2C
	PMGR_CLK_MCA2_M,			// 0x2D
	PMGR_CLK_MCA3_M,			// 0x2E
	PMGR_CLK_MCA4_M,			// 0x2F
	PMGR_CLK_SEP,				// 0x30
	PMGR_CLK_GPIO,				// 0x31
	PMGR_CLK_SPI0_N,			// 0x32
	PMGR_CLK_SPI1_N,			// 0x33
	PMGR_CLK_SPI2_N,			// 0x34
	PMGR_CLK_SPI3_N,			// 0x35
	PMGR_CLK_TMPS,				// 0x36
	PMGR_CLK_CPU_UVD,			// 0x37
	PMGR_CLK_GFX_UVD,			// 0x38
	PMGR_CLK_SOC_UVD,			// 0x39
	PMGR_CLK_LPDP_RX_REF,			// 0x3A
	PMGR_CLK_LAST = PMGR_CLK_LPDP_RX_REF,
	PMGR_CLK_S0,				// 0x3B
	PMGR_CLK_SPARE_FIRST = PMGR_CLK_S0,
	PMGR_CLK_S1,				// 0x3C
	PMGR_CLK_S2,				// 0x3D
	PMGR_CLK_S3,				// 0x3E
	PMGR_CLK_ISP_REF0,			// 0x3F
	PMGR_CLK_ISP_REF1,			// 0x40
	PMGR_CLK_ISP_REF2,			// 0x41
	PMGR_CLK_SPARE_LAST = PMGR_CLK_ISP_REF2,
	PMGR_CLK_LPO,				// 0x42
	PMGR_CLK_AOP,				// 0x43
	PMGR_CLK_MINI_FIRST = PMGR_CLK_AOP,
	PMGR_CLK_UART0,				// 0x44
	PMGR_CLK_UART1,				// 0x45
	PMGR_CLK_UART2,				// 0x46
	PMGR_CLK_AOP_MCA0_M,			// 0x47
	PMGR_CLK_I2CM,				// 0x48
	PMGR_CLK_PDM_REF,			// 0x49
	PMGR_CLK_SENSE_2X,			// 0x4A
	PMGR_CLK_DETECT,			// 0x4B
	PMGR_CLK_PROXY_FABRIC,			// 0x4C
	PMGR_CLK_PROXY_MCU_REF,			// 0x4D
	PMGR_CLK_MINI_LAST = PMGR_CLK_PROXY_MCU_REF,
	PMGR_CLK_COUNT,				// 0x4E
	PMGR_CLK_NOT_SUPPORTED
};

#else
#error "Unknown platform"
#endif

////////////////////////////////////////////////////////////
//
//  CCC specific
//
////////////////////////////////////////////////////////////

#define rACC_PRE_TD_TMR			(*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PRE_TD_TMR_OFFSET))
#define rACC_PRE_FLUSH_TMR		(*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PRE_FLUSH_TMR_OFFSET))

#define rACC_APSC_SCR			(*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_APSC_SCR_OFFSET))
#define ACC_APSC_PENDING		(1 << ACC_PWRCTL_APSC_SCR_MANUAL_PENDING_SHIFT)
#define ACC_APSC_MANUAL_CHANGE(_d)	((1 << ACC_PWRCTL_APSC_SCR_MANUAL_CHANGE_SHIFT) | ACC_PWRCTL_APSC_SCR_MANUAL_ST_INSRT((uint64_t)_d))

#define rACC_DVFM_CFG			(*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_CFG_OFFSET))

#define rACC_DVFM_SCR			(*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_SCR_OFFSET))	// 64-bit
#define  ACC_DVFM_SCR_TEMPSENSORMODE	(ACC_PWRCTL_DVFM_MODE_INSRT((uint64_t)1))

#define rACC_DVFM_CFG_SEL		(*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_CFG_SEL_OFFSET))

#define rACC_DVFM_CFG1			(*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_DVFM_CFG1_OFFSET))

#define kDVFM_STATE_BYPASS		(0)
#define kDVFM_STATE_SECUREROM		(kDVFM_STATE_BYPASS + 1)
#define kDVFM_STATE_IBOOT		(kDVFM_STATE_BYPASS + 2)
#define kDVFM_STATE_V0			(kDVFM_STATE_IBOOT + 0)

#define kDVFM_STATE_VMAX		(kDVFM_STATE_IBOOT) // !!! FIXME !!! (kDVFM_STATE_V5)

#define kDVFM_STATE_VNOM		(kDVFM_STATE_V0)
#define kDVFM_STATE_VBOOST		(kDVFM_STATE_VNOM + 1)

#define kDVFM_STATE_IBOOT_CNT		(kDVFM_STATE_VMAX + 1)

#define kVOLTAGE_STATES1_COUNT		(kDVFM_STATE_VMAX - kDVFM_STATE_V0 + 1)
#define kVOLTAGE_STATES1_SIZE		(kVOLTAGE_STATES1_COUNT*2)  // Minimum size of voltage-state1 property in devicetree

#define kDVFM_STATE_MAX_CNT		(16)

// TODO: Remove these when added to EmbeddedHeaders
#define ACC_PWRCTL_DVFM_ST0_PRE_DIV_P_INSRT(f) ((((uint64_t)f) & 0x1f) << 13)
#define ACC_PWRCTL_DVFM_ST0_FBK_DIV_M_INSRT(f) ((((uint64_t)f) & 0x1ff) << 4)
#define ACC_PWRCTL_DVFM_ST0_PST_DIV_S_INSRT(f) ((((uint64_t)f) & 0xf) << 0)

#define ACC_DVFM_ST_STRIDE		(ACC_DVFM_ST1_OFFSET - ACC_DVFM_ST0_OFFSET)

#define rACC_DVFM_ST(_n)		(*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_DVFM_ST0_OFFSET + ((_n) * ACC_DVFM_ST_STRIDE)))
#define  ACC_DVFM_ST_SAFE_VOL_INSRT(_sv)	(ACC_DVFM_ST0_SAFE_VOL_INSRT((uint64_t)_sv))
#define  ACC_DVFM_ST_SAFE_VOL_XTRCT(_sv)	(ACC_DVFM_ST0_SAFE_VOL_XTRCT((uint64_t)_sv))
#define  ACC_DVFM_ST_VOL_ADJ3(_va)		(ACC_DVFM_ST0_VOL_ADJ3_INSRT((uint64_t)_va))
#define  ACC_DVFM_ST_VOL_ADJ2(_va)		(ACC_DVFM_ST0_VOL_ADJ2_INSRT((uint64_t)_va))
#define  ACC_DVFM_ST_VOL_ADJ1(_va)		(ACC_DVFM_ST0_VOL_ADJ1_INSRT((uint64_t)_va))
#define  ACC_DVFM_ST_VOL_ADJ0(_va)		(ACC_DVFM_ST0_VOL_ADJ0_INSRT((uint64_t)_va))
#define  ACC_DVFM_ST_CORE_TYP(_ct)		(ACC_DVFM_ST0_CORE_TYP_INSRT((uint64_t)_ct))
#define  ACC_DVFM_ST_VOL_BYP(_vb)		(ACC_DVFM_ST0_VOL_BYP_INSRT((uint64_t)_vb))
#define  ACC_DVFM_ST_CLK_SRC(_s)		(ACC_DVFM_ST0_CLK_SRC_INSRT((uint64_t)_s))
#define  ACC_DVFM_ST_MIG_DIV_S(_s)		(ACC_DVFM_ST0_MIG_DIV_S_INSRT((uint64_t)_s))
#define  ACC_DVFM_ST_FCW_FRAC_INSRT(_f)		(ACC_DVFM_ST0_FCW_FRAC_INSRT((uint64_t)_f))
#define  ACC_DVFM_ST_FCW_INT_INSRT(_i)		(ACC_DVFM_ST0_FCW_INT_INSRT((uint64_t)_i))
#define  ACC_DVFM_ST_PST_DIV_S_INSRT(_s)	(ACC_DVFM_ST0_PST_DIV_S_INSRT((uint64_t)_s))
#define  ACC_DVFM_ST_FCW_FRAC_XTRCT(_f)		(ACC_DVFM_ST0_FCW_FRAC_XTRCT((uint64_t)_f))
#define  ACC_DVFM_ST_FCW_INT_XTRCT(_i)		(ACC_DVFM_ST0_FCW_INT_XTRCT((uint64_t)_i))
#define  ACC_DVFM_ST_PST_DIV_S_XTRCT(_s)	(ACC_DVFM_ST0_PST_DIV_S_XTRCT((uint64_t)_s))

#define rACC_DVFM_ST_EXT(_n)		(*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_DVFM_ST0_EXT_OFFSET + ((_n) * ACC_DVFM_ST_STRIDE)))
#define  ACC_DVFM_ST_BIU_DIV_HI_VOL(_d)	(ACC_DVFM_ST0_EXT_BIU_DIV4_HI_VOL_INSRT((uint64_t)(_d)))
#define  ACC_DVFM_ST_BIU_DIV_LO_VOL(_d)	(ACC_DVFM_ST0_EXT_BIU_DIV4_LO_VOL_INSRT((uint64_t)(_d)))
#define  ACC_DVFM_ST_DVMR_MAX_WGT(_w)	(ACC_DVFM_ST0_EXT_DVMR_MAX_WGT_INSRT((uint64_t)(_w)))
#define  ACC_DVFM_ST_SRAM_VOL(_v)	(ACC_DVFM_ST0_EXT_SRAM_VOL_INSRT((uint64_t)(_v)))
#define  ACC_DVFM_ST_DVFM_MAX_ADJ(_a)	(ACC_DVFM_ST0_EXT_MAX_ADJ_INSRT((uint64_t)(_a)))
#define  ACC_DVFM_ST_DVMR_ADJ2(_a)	(ACC_DVFM_ST0_EXT_DVMR_ADJ2_INSRT((uint64_t)(_a)))
#define  ACC_DVFM_ST_DVMR_ADJ1(_a)	(ACC_DVFM_ST0_EXT_DVMR_ADJ1_INSRT((uint64_t)(_a)))
#define  ACC_DVFM_ST_DVMR_ADJ0(_a)	(ACC_DVFM_ST0_EXT_DVMR_ADJ0_INSRT((uint64_t)(_a)))

#define rACC_DVFM_ST_EXT2(_n)		(*(volatile uint64_t *)(ACC_BASE_ADDR + ACC_DVFM_ST0_EXT2_OFFSET + ((_n) * ACC_DVFM_ST_STRIDE)))
#define  ACC_DVFM_ST_ADCLK_EN(_a)	(ACC_DVFM_ST0_EXT2_ADCLK_EN_INSRT((uint64_t)(_a)))

#define rACC_PLL_SCR1			(*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PLL_SCR1_OFFSET))
#define rACC_PLL_CFG2			(*(volatile uint32_t *)(ACC_BASE_ADDR + ACC_PWRCTL_PLL_CFG2_OFFSET))
#define rACC_DVMR_SCR			(*(volatile uint64_t *)(ACC_BASE_ADDR + DVMR_SCR_OFFSET))

#define rMINIPMGR_SIO_AES_DISABLE	(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SIO_AES_DISABLE_OFFSET))
#define rMINIPMGR_SECURITY_GPIO_STRAPS	(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_GPIO_STRAPS_OFFSET))
#define rMINIPMGR_SET_ONLY		(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SET_ONLY_OFFSET))
#define  MINIPMGR_SET_ONLY_MIX_N_MATCH	(1 << 31)
#define rMINIPMGR_SEAL_DATA_A_FIRST	(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_DATA_A0_OFFSET))
#define rMINIPMGR_SEAL_DATA_A_LAST	(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_DATA_A7_OFFSET))
#define rMINIPMGR_SEAL_CTL_A		(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_CTL_A_OFFSET))
#define rMINIPMGR_SEAL_DATA_B_FIRST	(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_DATA_B0_OFFSET))
#define rMINIPMGR_SEAL_DATA_B_LAST	(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_DATA_B7_OFFSET))
#define rMINIPMGR_SEAL_CTL_B		(*(volatile uint32_t *)(AOP_MINIPMGR_BASE_ADDR + MINIPMGR_SECURITY_SEAL_CTL_B_OFFSET))

#define rACC_THRM0_CTL0_SET		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_CTL0_SET_OFFSET))
#define rACC_THRM0_CTL1			(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_CTL1_OFFSET))
#define rACC_THRM0_PARAM		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_PARAM_OFFSET))
#define rACC_THRM0_PIECE0		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_PIECE0_OFFSET))
#define rACC_THRM0_PIECE1		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_PIECE1_OFFSET))
#define rACC_THRM0_PIECE2		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM0_PIECE2_OFFSET))

#define rACC_THRM1_CTL0_SET		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_CTL0_SET_OFFSET))
#define rACC_THRM1_CTL1			(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_CTL1_OFFSET))
#define rACC_THRM1_PARAM		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_PARAM_OFFSET))
#define rACC_THRM1_PIECE0		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_PIECE0_OFFSET))
#define rACC_THRM1_PIECE1		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_PIECE1_OFFSET))
#define rACC_THRM1_PIECE2		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM1_PIECE2_OFFSET))

#define rACC_THRM2_CTL0_SET		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_CTL0_SET_OFFSET))
#define rACC_THRM2_CTL1			(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_CTL1_OFFSET))
#define rACC_THRM2_PARAM		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_PARAM_OFFSET))
#define rACC_THRM2_PIECE0		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_PIECE0_OFFSET))
#define rACC_THRM2_PIECE1		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_PIECE1_OFFSET))
#define rACC_THRM2_PIECE2		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_THRM2_PIECE2_OFFSET))

#define rACC_DVFM_FSHOT_IDX		(*(volatile uint64_t*)(ACC_BASE_ADDR + ACC_THERMAL_DVFM_FSHOT_IDX_OFFSET))

#define  ACC_THRM0_PIECE0(_c, _o, _s)	(ACC_THERMAL_THRM0_PIECE0_START_CODE_INSRT(_c) | ACC_THERMAL_THRM0_PIECE0_OFFSET_INSRT(_o) | ACC_THERMAL_THRM0_PIECE0_SLOPE_INSRT(_s))
#define  ACC_THRM0_PIECE1(_c, _o, _s)	(ACC_THERMAL_THRM0_PIECE1_START_CODE_INSRT(_c) | ACC_THERMAL_THRM0_PIECE1_OFFSET_INSRT(_o) | ACC_THERMAL_THRM0_PIECE1_SLOPE_INSRT(_s))
#define  ACC_THRM0_PIECE2(_c, _o, _s)	(ACC_THERMAL_THRM0_PIECE2_START_CODE_INSRT(_c) | ACC_THERMAL_THRM0_PIECE2_OFFSET_INSRT(_o) | ACC_THERMAL_THRM0_PIECE2_SLOPE_INSRT(_s))
#define  ACC_THRM1_PIECE0(_c, _o, _s)	(ACC_THERMAL_THRM1_PIECE0_START_CODE_INSRT(_c) | ACC_THERMAL_THRM1_PIECE0_OFFSET_INSRT(_o) | ACC_THERMAL_THRM1_PIECE0_SLOPE_INSRT(_s))
#define  ACC_THRM1_PIECE1(_c, _o, _s)	(ACC_THERMAL_THRM1_PIECE1_START_CODE_INSRT(_c) | ACC_THERMAL_THRM1_PIECE1_OFFSET_INSRT(_o) | ACC_THERMAL_THRM1_PIECE1_SLOPE_INSRT(_s))
#define  ACC_THRM1_PIECE2(_c, _o, _s)	(ACC_THERMAL_THRM1_PIECE2_START_CODE_INSRT(_c) | ACC_THERMAL_THRM1_PIECE2_OFFSET_INSRT(_o) | ACC_THERMAL_THRM1_PIECE2_SLOPE_INSRT(_s))
#define  ACC_THRM2_PIECE0(_c, _o, _s)	(ACC_THERMAL_THRM2_PIECE0_START_CODE_INSRT(_c) | ACC_THERMAL_THRM2_PIECE0_OFFSET_INSRT(_o) | ACC_THERMAL_THRM2_PIECE0_SLOPE_INSRT(_s))
#define  ACC_THRM2_PIECE1(_c, _o, _s)	(ACC_THERMAL_THRM2_PIECE1_START_CODE_INSRT(_c) | ACC_THERMAL_THRM2_PIECE1_OFFSET_INSRT(_o) | ACC_THERMAL_THRM2_PIECE1_SLOPE_INSRT(_s))
#define  ACC_THRM2_PIECE2(_c, _o, _s)	(ACC_THERMAL_THRM2_PIECE2_START_CODE_INSRT(_c) | ACC_THERMAL_THRM2_PIECE2_OFFSET_INSRT(_o) | ACC_THERMAL_THRM2_PIECE2_SLOPE_INSRT(_s))

////////////////////////////////////////////////////////////
//
//  Externs
//
////////////////////////////////////////////////////////////

extern void pmgr_update_device_tree(DTNode *pmgr_node);
extern void pmgr_gfx_update_device_tree(DTNode *gfx_node);

#endif /* ! __PLATFORM_SOC_PMGR_H */
