/*
 * Copyright (C) 2010 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */
#ifndef __PLATFORM_SOC_HWCLOCKS_H
#define __PLATFORM_SOC_HWCLOCKS_H

#include <platform/clocks.h>

#if SUPPORT_FPGA
#define OSC_FREQ			(5000000UL)
#else
#define OSC_FREQ			(24000000UL)
#endif

#define CLK_FCLK	(HWCLOCK_BASE+0)
#define CLK_ACLK	(HWCLOCK_BASE+1)
#define CLK_HCLK	(HWCLOCK_BASE+2)
#define CLK_PCLK	(HWCLOCK_BASE+3)
#define CLK_VCLK0	(HWCLOCK_BASE+4)
#define CLK_VCLK1	(HWCLOCK_BASE+5)
#define CLK_MCLK	(HWCLOCK_BASE+6)
#define CLK_NCLK	(HWCLOCK_BASE+7)
#define CLK_USBPHYCLK	(HWCLOCK_BASE+8)
#define CLK_NCOREF	(HWCLOCK_BASE+9)
#define CLK_FMI		(HWCLOCK_BASE+10)

/* S5L8945X clock gate devices */
enum {
	CLK_CPU0 = 0,
	CLK_CPU1,
	CLK_SCU,
	CLK_L2RAM0,
	CLK_L2RAM1,
	CLK_CPU_REGS,
	CLK_MCU,
	CLK_GFX_SYS,
	CLK_GFX_CORES,
	CLK_HPERFNRT,
	CLK_VDEC,
	CLK_SCALER0,
	CLK_SCALER1,
	CLK_JPG0,
	CLK_JPG1,
	CLK_VENCD,
	CLK_HPERFRT,
	CLK_ISP,
	CLK_resv0,
	CLK_DISP0,
	CLK_DISP1,
	CLK_DISPOUT,
	CLK_EDPLINK,
	CLK_CLCD,
	CLK_TVDAC,
	CLK_RGBOUT,
	CLK_DPLINK,
	CLK_CDIO,
	CLK_CDMA,
	CLK_IOP,
	CLK_UPERF,
	CLK_UPERF1,
	CLK_USBOTG,
	CLK_USB20,
	CLK_USB11,
	CLK_USBOHCI0,
	CLK_USBOHCI1,
	CLK_USBPHY,
	CLK_USB1_OTG,
	CLK_USB1_20,
	CLK_USB1_11,
	CLK_USB1_OHCI0,
	CLK_USB1_OHCI1,
	CLK_USB1_PHY,
	CLK_AUDIO,
	CLK_I2S0,
	CLK_I2S1,
	CLK_I2S2,
	CLK_I2S3,
	CLK_SPDIF,
	CLK_HPARK,
	CLK_SDIO,
	CLK_SHA1,
	CLK_SHA2,
	CLK_FMI0,
	CLK_FMI0BCH,
	CLK_FMI1,
	CLK_FMI1BCH,
	CLK_FMI2,
	CLK_FMI2BCH,
	CLK_FMI3,
	CLK_FMI3BCH,
	CLK_SPI0,
	CLK_SPI1,
	CLK_SPI2,
	CLK_SPI3,
	CLK_SPI4,
	CLK_UART0,
	CLK_UART1,
	CLK_UART2,
	CLK_UART3,
	CLK_UART4,
	CLK_UART5,
	CLK_UART6,
	CLK_PKE,
	CLK_I2C0,
	CLK_I2C1,
	CLK_I2C2,
	CLK_PWM,
	CLK_SCRT,
	CLK_GPIO,
	CLK_SWI,
	CLK_DWI,
	CLK_DEBUG,
	CLK_AIC,
};

#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */
