/*
 * Copyright (C) 2009-2014 Apple Inc. All rights reserved.
 *
 * This document is the property of Apple Inc.
 * It is considered confidential and proprietary.
 *
 * This document may not be reproduced or transmitted in any form,
 * in whole or in part, without the express written permission of
 * Apple Inc.
 */

/* Default P105/6/7 SoC Pin Configuration from rev 2.1 */

/* Different drive strength for AP and DEV. */
#if PIN_CFG_AP
#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##ap
#elif PIN_CFG_DEV
#define AP_DEV_DRIVE_STR(ap, dev) DRIVE_##dev
#endif

#if TARGET_HAS_BASEBAND
#define IF_BB(x, y) (x)
#else
#define IF_BB(x, y) (y)
#endif

#if PIN_CFG_AP
static const u_int32_t gpio_default_cfg_ap[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#elif PIN_CFG_DEV
static const u_int32_t gpio_default_cfg_dev[GPIO_GROUP_COUNT * GPIOPADPINS] = {
#endif
/* Port  0 */
	CFG_IN,								// GPIO0		-> MENU_KEY (REQUEST_DFU2)
	CFG_IN,								// GPIO1		-> HOLD_KEY (REQUEST_DFU1)
	CFG_IN | PULL_UP,						// GPIO2		-> GPIO_BTN_VOL_UP_L
	CFG_IN | PULL_UP,						// GPIO3		-> GPIO_BTN_VOL_DOWN_L
	CFG_IN,								// GPIO4		-> GPIO_BTN_SRL_L
	CFG_OUT_0 | DRIVE_X1,						// GPIO5		-> GPIO_SPKAMP_RST_L
	CFG_OUT_0 | DRIVE_X1,						// GPIO6		-> GPIO_SPKAMP_KEEPALIVE
	CFG_IN | PULL_UP,						// GPIO7		-> GPIO_SPKAMP_LEFT_IRQ_L

/* Port  1 */
	CFG_IN | PULL_UP,						// GPIO8		-> GPIO_CODEC_IRQ_L
	CFG_OUT_0 | DRIVE_X1,						// GPIO9		-> GPIO_BT_WAKE
	IF_BB(CFG_IN, CFG_DISABLED | PULL_DOWN),			// GPIO10		-> GPIO_BB_RST_L
	CFG_DISABLED | PULL_DOWN,					// GPIO11		-> GPIO_BB_GSM_TXBURST
	IF_BB(CFG_OUT_0, CFG_DISABLED | PULL_DOWN) | DRIVE_X1,		// GPIO12		-> GPIO_BB_IPC_GPIO
	IF_BB(CFG_IN, CFG_DISABLED) | PULL_DOWN,			// GPIO13		-> GPIO_BB_HSIC1_REMOTE_WAKE
	CFG_DISABLED | PULL_DOWN,					// GPIO14		-> GPIO_BB_GPS_SYNC
	IF_BB(CFG_IN, CFG_DISABLED) | PULL_DOWN,			// GPIO15		-> GPIO_BB_RST_DET_L

/* Port  2 */
	CFG_DISABLED,							// GPIO16		-> GPIO_BOARD_ID3
	IF_BB(CFG_OUT_0, CFG_DISABLED | PULL_DOWN) | DRIVE_X1,			// GPIO17		-> GPIO_BB_HSIC_HOST_RDY
	CFG_DISABLED,							// GPIO18		-> GPIO_BOOT_CONFIG0
	CFG_IN | PULL_UP,						// GPIO19		-> GPIO_PMU_IRQ_L
	CFG_OUT_0 | DRIVE_X1,						// GPIO20		-> GPIO_PMU_KEEPACT
	CFG_OUT_0 | DRIVE_X1,						// GPIO21		-> GPIO_GRAPE_RST_L
	CFG_IN | PULL_UP,						// GPIO22		-> GPIO_GRAPE_IRQ_L
	IF_BB(CFG_IN, CFG_DISABLED | PULL_DOWN) | DRIVE_X1,		// GPIO23		-> GPIO_BB_RADIO_ON_L

/* Port  3 */
	IF_BB(CFG_IN, CFG_DISABLED) | PULL_DOWN,			// GPIO24		-> GPIO_BB_HSIC_DEV_RDY
	CFG_DISABLED,							// GPIO25		-> GPIO_BOOT_CONFIG1
	CFG_IN | PULL_DOWN,						// GPIO26		-> GPIO_FORCE_DFU
	CFG_OUT_0 | PULL_DOWN | DRIVE_X1,				// GPIO27		-> GPIO_DFU_STATUS
	CFG_DISABLED,							// GPIO28		-> GPIO_BOOT_CONFIG2
	CFG_DISABLED,							// GPIO29		-> GPIO_BOOT_CONFIG3
	IF_BB(CFG_IN, CFG_DISABLED | PULL_DOWN),			// GPIO30		-> GPIO_PROX_IRQ_L
	CFG_DISABLED,							// GPIO31		->

/* Port  4 */
	CFG_IN | PULL_DOWN,						// GPIO32		-> GPIO_ACCEL_IRQ2_L
	CFG_IN | PULL_DOWN,						// GPIO33		-> GPIO_GYRO_IRQ1
	CFG_IN | PULL_DOWN,						// GPIO34		-> GPIO_WLAN_HSIC_RESUME
	CFG_OUT_0 | DRIVE_X1,						// GPIO35		-> GPIO_MLC_PWR_EN
	CFG_OUT_0 | DRIVE_X1,						// GPIO36		-> GPIO_MLC_RST_1V8_L
	CFG_DISABLED,							// EHCI_PORT_PWR[0]	-> GPIO_BOARD_REV0
	CFG_DISABLED,							// EHCI_PORT_PWR[1]	-> GPIO_BOARD_REV1
	CFG_DISABLED,							// EHCI_PORT_PWR[2]	-> GPIO_BOARD_REV2

/* Port  5 */
	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X3),				// UART1_TXD		-> UART1_BT_TXD
	CFG_FUNC0,							// UART1_RXD		-> UART1_BT_RXD
	CFG_OUT_1 | AP_DEV_DRIVE_STR(X1, X3),				// UART1_RTSN		-> UART1_BT_RTS_L
	CFG_FUNC0,							// UART1_CTSN		-> UART1_BT_CTS_L
	CFG_FUNC0 | DRIVE_X1,						// UART2_TXD		-> UART2_ACC_TXD
	CFG_FUNC0,							// UART2_RXD		-> UART2_ACC_RXD
	CFG_IN | PULL_UP,						// UART2_RTSN		-> GPIO_SPKAMP_RIGHT_IRQ_L
	CFG_IN | PULL_UP,						// UART2_CTSN		-> GPIO_ALS_IRQ_L

/* Port  6 */
	CFG_FUNC0 | AP_DEV_DRIVE_STR(X1, X3),				// UART3_TXD		-> UART3_WLAN_TXD
	CFG_FUNC0,							// UART3_RXD		-> UART3_WLAN_RXD
	CFG_OUT_0 | DRIVE_X1,						// UART3_RTSN		-> GPIO_WLAN_HSIC_HOST_RDY
	CFG_IN | PULL_DOWN,						// UART3_CTSN		-> GPIO_WLAN_HSIC_DEV_RDY
	CFG_FUNC0 | DRIVE_X2,						// I2C0_SDA		-> I2C0_SDA
	CFG_FUNC0 | DRIVE_X2,						// I2C0_SCL		-> I2C0_SCL
	CFG_FUNC0 | DRIVE_X2,						// I2C1_SDA		-> I2C1_SDA
	CFG_FUNC0 | DRIVE_X2,						// I2C1_SCL		-> I2C1_SCL

/* Port  7 */
	CFG_FUNC0 | DRIVE_X2,						// ISP0_SDA		-> ISP0_CAM_REAR_SDA
	CFG_FUNC0 | DRIVE_X2,						// ISP0_SCL		-> ISP0_CAM_REAR_SCL
	CFG_FUNC0 | DRIVE_X2,						// ISP1_SDA		-> ISP1_CAM_FRONT_SDA
	CFG_FUNC0 | DRIVE_X2,						// ISP1_SCL		-> ISP1_CAM_FRONT_SCL
	CFG_DISABLED | PULL_DOWN,					// MIPI_VSYNC		-> DISPLAY_SYNC
	CFG_FUNC0 | PULL_DOWN,						// TMR32_PWM0		-> GPIO_GYRO_IRQ2
	CFG_FUNC0 | PULL_DOWN,						// TMR32_PWM1		-> GPIO_ACCEL_IRQ1_L
	CFG_FUNC0 | DRIVE_X2,						// TMR32_PWM2		-> AP_CLK_32K_CUMULUS

/* Port  8 */
	CFG_DISABLED,							// SWI_DATA		->
	CFG_FUNC0 | PULL_DOWN,						// DWI_DI		-> DWI_DI
	CFG_FUNC0 | DRIVE_X2,						// DWI_DO		-> DWI_DO
	CFG_FUNC0 | DRIVE_X2,						// DWI_CLK		-> DWI_CLK
	CFG_OUT_1 | DRIVE_X1,						// SENSOR0_RST		-> ISP0_CAM_REAR_SHUTDOWN
	CFG_OUT_0 | DRIVE_X3,						// SENSOR0_CLK		-> ISP0_CAM_REAR_CLK_R
	CFG_OUT_1 | DRIVE_X1,						// SENSOR1_RST		-> ISP1_CAM_FRONT_SHUTDOWN
	CFG_OUT_0 | DRIVE_X3,						// SENSOR1_CLK		-> ISP1_CAM_FRONT_CLK_R

/* Port  9 */
	CFG_DISABLED,							// ISP0_PRE_FLASH	->
	CFG_DISABLED,							// ISP0_FLASH		->
	CFG_DISABLED,							// ISP1_PRE_FLASH	->
	CFG_DISABLED,							// ISP1_FLASH		->
	CFG_FUNC0 | DRIVE_X3,						// I2S0_MCK		-> I2S0_CODEC_ASP_MCK_R
	CFG_FUNC0 | DRIVE_X2,						// I2S0_LRCK		-> I2S0_CODEC_ASP_LRCK
	CFG_FUNC0 | DRIVE_X2,						// I2S0_BCLK		-> I2S0_CODEC_ASP_BCLK
	CFG_FUNC0 | DRIVE_X2,						// I2S0_DOUT		-> I2S0_CODEC_ASP_DOUT

/* Port 10 */
	CFG_FUNC0,							// I2S0_DIN		-> I2S0_CODEC_ASP_DIN
	CFG_FUNC0 | DRIVE_X3,						// I2S1_MCK		-> I2S1_SPKAMP_MCK_R
	CFG_FUNC0 | DRIVE_X2,						// I2S1_LRCK		-> I2S1_SPKAMP_LRCK
	CFG_FUNC0 | DRIVE_X2,						// I2S1_BCLK		-> I2S1_SPKAMP_BCLK
	CFG_FUNC0 | DRIVE_X2,						// I2S1_DOUT		-> I2S1_SPKAMP_DOUT
	CFG_FUNC0,							// I2S1_DIN		-> I2S1_SPKAMP_DIN
	CFG_IN,								// I2S2_MCK		-> PMU_GPIO_TRISTAR_IRQ
	CFG_FUNC0 | DRIVE_X2,						// I2S2_LRCK		-> I2S2_CODEC_XSP_LRCK

/* Port 11 */
	CFG_FUNC0 | DRIVE_X2,						// I2S2_BCLK		-> I2S2_CODEC_XSP_BCLK
	CFG_FUNC0 | DRIVE_X2,						// I2S2_DOUT		-> I2S2_CODEC_XSP_DOUT
	CFG_FUNC0,							// I2S2_DIN		-> I2S2_CODEC_XSP_DIN
	CFG_IN,								// I2S3_MCK		-> GPIO_ACC_SW_POK_L
	CFG_FUNC0 | DRIVE_X2,						// I2S3_LRCK		-> I2S3_BT_LRCK
	CFG_FUNC0 | DRIVE_X2,						// I2S3_BCLK		-> I2S3_BT_BCLK
	CFG_FUNC0 | DRIVE_X2,						// I2S3_DOUT		-> I2S3_BT_DOUT
	CFG_FUNC0,							// I2S3_DIN		-> I2S3_BT_DIN

/* Port 12 */
	CFG_DISABLED,							// SPI0_SCLK		-> GPIO_BOARD_ID0
	CFG_DISABLED,							// SPI0_MOSI		-> GPIO_BOARD_ID1
	CFG_DISABLED,							// SPI0_MISO		-> GPIO_BOARD_ID2
	CFG_DISABLED | PULL_UP,						// SPI0_SSIN		->
	CFG_FUNC0 | DRIVE_X2,						// SPI1_SCLK		-> SPI1_GRAPE_SCLK
	CFG_FUNC0 | DRIVE_X2,						// SPI1_MOSI		-> SPI1_GRAPE_MOSI
	CFG_FUNC0,							// SPI1_MISO		-> SPI1_GRAPE_MISO
	CFG_OUT_1 | DRIVE_X1,						// SPI1_SSIN		-> SPI1_GRAPE_CS_L

/* Port 13 */
	CFG_FUNC0 | DRIVE_X2,						// SPI2_SCLK		-> SPI2_CODEC_SCLK
	CFG_FUNC0 | DRIVE_X2,						// SPI2_MOSI		-> SPI2_CODEC_MOSI
	CFG_FUNC0,							// SPI2_MISO		-> SPI2_CODEC_MISO
	CFG_OUT_1 | DRIVE_X1,						// SPI2_SSIN		-> SPI2_CODEC_CS_L
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->

/* Port 14 */
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->

/* Port 15 */
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->

/* Port 16 */
	IF_BB(CFG_IN, CFG_DISABLED | PULL_DOWN) | AP_DEV_DRIVE_STR(X1, X3),	// UART4_TXD		-> UART4_BB_TXD
	IF_BB(CFG_FUNC0, CFG_DISABLED | PULL_DOWN),			// UART4_RXD		-> UART4_BB_RXD
	IF_BB(CFG_IN, CFG_DISABLED | PULL_DOWN) | AP_DEV_DRIVE_STR(X1, X3),	// UART4_RTSN		-> UART4_BB_RTS_L
	IF_BB(CFG_FUNC0, CFG_DISABLED | PULL_DOWN),			// UART4_CTSN		-> UART4_BB_CTS_L
	CFG_OUT_0 | DRIVE_X1,						// SDIO0_DATA3		-> GPIO_ACC_SW_EN
	IF_BB(CFG_DISABLED, CFG_DISABLED | PULL_DOWN),			// SDIO0_DATA2		-> BB_JTAG_TRST_L
	IF_BB(CFG_DISABLED, CFG_DISABLED | PULL_DOWN),			// SDIO0_DATA1		-> BB_JTAG_TDO
	IF_BB(CFG_DISABLED, CFG_DISABLED | PULL_DOWN),			// SDIO0_DATA0		-> BB_JTAG_TDI

/* Port 17 */
	IF_BB(CFG_DISABLED, CFG_DISABLED | PULL_DOWN),			// SDIO0_CMD		-> BB_JTAG_TMS
	IF_BB(CFG_DISABLED, CFG_DISABLED | PULL_DOWN),			// SDIO0_CLK		-> BB_JTAG_TCK
	CFG_DISABLED,							// FMI0_CEN3		->
	CFG_DISABLED,							// FMI0_CEN2		->
	CFG_DISABLED,							// FMI0_CEN1		->
	CFG_FUNC0 | DRIVE_X1,						// FMI0_CEN0		-> FMI0_CE0_L
	CFG_FUNC0 | DRIVE_X1,						// FMI0_CLE		-> FMI0_CLE
	CFG_FUNC0 | DRIVE_X1,						// FMI0_ALE		-> FMI0_ALE

/* Port 18 */
	CFG_FUNC0 | DRIVE_X1,						// FMI0_REN		-> FMI0_RE_N
	CFG_FUNC0 | DRIVE_X1,						// FMI0_WEN		-> FMI0_WE_L
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI0_IO7		-> FMI0_AD<7>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI0_IO6		-> FMI0_AD<6>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI0_IO5		-> FMI0_AD<5>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI0_IO4		-> FMI0_AD<4>
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->

/* Port 19 */
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->

/* Port 20 */
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI0_DQS		-> FMI0_DQS_P
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI0_IO3		-> FMI0_AD<3>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI0_IO2		-> FMI0_AD<2>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI0_IO1		-> FMI0_AD<1>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI0_IO0		-> FMI0_AD<0>
	CFG_DISABLED,							// FMI1_CEN3		->
	CFG_DISABLED,							// FMI1_CEN2		->
	CFG_DISABLED,							// FMI1_CEN1		->

/* Port 21 */
	CFG_FUNC0 | DRIVE_X1,						// FMI1_CEN0		-> FMI1_CE0_L
	CFG_FUNC0 | DRIVE_X1,						// FMI1_CLE		-> FMI1_CLE
	CFG_FUNC0 | DRIVE_X1,						// FMI1_ALE		-> FMI1_ALE
	CFG_FUNC0 | DRIVE_X1,						// FMI1_REN		-> FMI1_RE_N
	CFG_FUNC0 | DRIVE_X1,						// FMI1_WEN		-> FMI1_WE_L
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI1_IO7		-> FMI1_AD<7>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI1_IO6		-> FMI1_AD<6>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI1_IO5		-> FMI1_AD<5>

/* Port 22 */
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI1_IO4		-> FMI1_AD<4>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI1_DQS		-> FMI1_DQS_P
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI1_IO3		-> FMI1_AD<3>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI1_IO2		-> FMI1_AD<2>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI1_IO1		-> FMI1_AD<1>
	CFG_FUNC0 | BUS_HOLD | DRIVE_X1,				// FMI1_IO0		-> FMI1_AD<0>
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->

/* Port 23 */
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->

/* Port 24 */
	CFG_FUNC0 | DRIVE_X2,						// I2C2_SDA		-> I2C2_SDA
	CFG_FUNC0 | DRIVE_X2,						// I2C2_SCL		-> I2C2_SCL
	CFG_FUNC0 | DRIVE_X1,						// UART0_TXD		-> UART0_DEBUG_TXD
	CFG_FUNC0,							// UART0_RXD		-> UART0_DEBUG_RXD
	CFG_FUNC0 | DRIVE_X2,						// UART5_RTXD		-> UART5_BATT_RTXD
	CFG_DISABLED,							// DP_HPD		->
	CFG_DISABLED,							// TST_CLKOUT		-> TP_SOC_TST_CLKOUT
	CFG_DISABLED,							// TST_STPCLK		-> SOC_TST_STPCLK

/* Port 25 */
	CFG_FUNC0 | DRIVE_X1,						// WDOG			-> SOC_WDOG
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
	CFG_DISABLED,							// 			->
};

#undef AP_DEV_DRIVE_STR
#undef IF_BB
