174 lines
4.0 KiB
C
174 lines
4.0 KiB
C
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/*
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* Copyright (C) 2007-2009 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <arch.h>
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#include <debug.h>
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#include <drivers/arm7m/arm7m.h>
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#include <platform.h>
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#include <platform/clocks.h>
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#include <platform/int.h>
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#include <platform/soc/arm7m.h>
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#include <platform/soc/hwisr.h>
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#include <sys.h>
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#include <sys/boot.h>
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#include <sys/callout.h>
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#include <sys/task.h>
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/*
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* Early init is done every time the ARM7 starts.
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*/
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int
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arm7m_init(void)
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{
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/*
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* Cache starts off. Invalidate and then turn it on.
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*/
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rARM7M_CACHE_INV = 1;
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rARM7M_CACHE_ON = ARM7M_CACHE_ON_ENABLE;
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return(0);
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}
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/*
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* Halt waiting for an interrupt.
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*/
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void
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arm7m_halt(void)
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{
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/* XXX need to avoid doing this until cache operations are complete */
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rARM7M_SLEEP = 1;
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}
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/*
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* Cache control
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*/
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void
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arm7m_cache_operation(int operation, void *address, u_int32_t length)
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{
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uint32_t actual_base, lines;
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if (length == 0) {
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/*
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* To perform whole-cache operations, we have to turn the cache off.
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*
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* Since this introduces both a coherency risk and also since our use
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* of the hardware needs to be exclusive, we disable interrupts.
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*/
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enter_critical_section();
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rARM7M_CACHE_ON = 0;
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if (operation & CACHE_CLEAN)
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rARM7M_CACHE_SYNC = 0;
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if (operation & CACHE_INVALIDATE)
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rARM7M_CACHE_INV = 0;
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/* on the panic path, leave the cache off */
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if (!(operation & CACHE_PANIC))
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rARM7M_CACHE_ON = ARM7M_CACHE_ON_ENABLE;
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exit_critical_section();
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} else {
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actual_base = (uint32_t)address;
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ASSERT((actual_base & ARM7M_CACHE_LINE_MASK) == actual_base);
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ASSERT((length % ARM7M_CACHE_LINE_SIZE) == 0);
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lines = length >> ARM7M_CACHE_LINE_SHIFT;
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ASSERT(lines > 0);
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/*
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* Disable interrupts to prevent re-entrance from an interrupt
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* handler.
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*/
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enter_critical_section();
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for (;;) {
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rARM7M_CLINE_ADDR = actual_base;
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if (operation & CACHE_CLEAN)
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rARM7M_CLINE_SYNC = 0;
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if (operation & CACHE_INVALIDATE)
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rARM7M_CLINE_INV = 0;
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if (--lines < 1)
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break;
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actual_base += ARM7M_CACHE_LINE_SIZE;
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}
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exit_critical_section();
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}
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}
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#if SUPPORT_SLEEP
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static struct task *sleeping_task;
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extern u_int32_t arch_sleep_magic;
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void
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platform_sleep(void)
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{
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/*
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* Disable interrupts; this is matched by the
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* exit_critical_section call in interrupt_init on the wake
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* path.
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*/
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enter_critical_section();
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/* we are the sleeping task */
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sleeping_task = task_get_current_task();
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/* fool the upcoming test on the sleep path */
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arch_sleep_magic = SLEEP_MAGIC_NOT_ASLEEP;
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/* save our current context - on wake we will return from this call */
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arch_task_context_switch(&sleeping_task->arch, &sleeping_task->arch);
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/* if we are on the wake path, go back */
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if (SLEEP_MAGIC_WAKEY_WAKEY == arch_sleep_magic)
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return;
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/* flip the switch and wait for us to go to sleep */
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arch_sleep_magic = SLEEP_MAGIC_WAKEY_WAKEY;
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/* disable and flush the cache, since we're about to be turned off */
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rARM7M_CACHE_ON = 0;
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rARM7M_CACHE_SYNC = 0;
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/* XXX really need to know how long the cache operation will take to complete */
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for (;;) {
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}
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}
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void
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platform_wakeup(void)
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{
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/*
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* Cache starts off. Invalidate and then turn it on.
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*/
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rARM7M_CACHE_INV = 1;
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rARM7M_CACHE_ON = ARM7M_CACHE_ON_ENABLE;
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/*
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* The VIC init is sleep/wake friendly - note this unmasks
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* interrupts that were unmasked at sleep time, so handlers
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* must be ready (or interrupt sources should be masked before
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* sleep).
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*
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* This call also exits the critical section that was entered
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* in platform_sleep (current_task has not changed).
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*/
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interrupt_init();
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/* kick the callout system to re-evaluate deadlines */
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callout_reset_deadline();
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/* and switch back to the context that went to sleep */
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arch_task_context_restore(&sleeping_task->arch);
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panic("arch_task_context_restore didn't");
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}
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#endif /* SUPPORT_SLEEP */
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