75 lines
3.4 KiB
C
75 lines
3.4 KiB
C
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/*
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* Copyright (C) 2009-2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __SAMSUNG_CLCD_REGS_H
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#define __SAMSUNG_CLCD_REGS_H
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#include <platform/soc/hwregbase.h>
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#define rCLCD_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0000))
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#define rCLCD_CFG (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0004))
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#define rCLCD_INT_EN (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0008))
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#define rCLCD_INT_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x000C))
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#define rCLCD_VER (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0010))
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#define rCLCD_DITH_CFG (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0014))
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#define rCLCD_DITH_CONST (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0018))
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#define rCLCD_DPHSYNC_CTRL (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0020))
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#define rCLCD_DPVSYNC_CTRL (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0024))
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#define rCLCD_GM_CON (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x002C))
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#define CLCD_GM_CON_GM_CO_ENABLE (1 << 0)
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#define CLCD_GM_CON_GM_CO_TBL_UPDATED (1 << 6)
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#define rCLCD_GM_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0030))
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#define rCLCD_GM_TBL_ACC_CON (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0034))
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#define CLCD_GM_OFF (0)
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#define CLCD_GM_DEC_RED (1)
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#define CLCD_GM_DEC_GREEN (2)
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#define CLCD_GM_DEC_BLUE (3)
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#define CLCD_GM_COR_RED (4)
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#define CLCD_GM_COR_GREEN (5)
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#define CLCD_GM_COR_BLUE (6)
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#define CLCD_GM_ENC (7)
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#define rCLCD_GM_TBL_WDATA (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0038))
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#define rCLCD_GM_TBL_RDATA (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x003C))
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#define rCLCD_OTF_CON1 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0050))
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#define rCLCD_OTF_CON2 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0054))
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#define rCLCD_OTF_TCON1 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0058))
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#if (DISP_VERSION < 3)
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#define CLCD_OTF_TCON1_VSPP (1 << 24)
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#define CLCD_OTF_TCON1_VBPD(_l) (((_l)-1) << 16)
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#define CLCD_OTF_TCON1_VFPD(_l) (((_l)-1) << 8)
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#define CLCD_OTF_TCON1_VSPW(_l) (((_l)-1) << 0)
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#else
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#define CLCD_OTF_TCON1_VSPP (1 << 30)
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#define CLCD_OTF_TCON1_VBPD(_l) (((_l)-1) << 20)
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#define CLCD_OTF_TCON1_VFPD(_l) (((_l)-1) << 10)
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#define CLCD_OTF_TCON1_VSPW(_l) (((_l)-1) << 0)
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#endif
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#define rCLCD_OTF_TCON2 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x005C))
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#if (DISP_VERSION < 4)
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#define CLCD_OTF_TCON2_HBPD(_p) (((_p)-1) << 16)
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#define CLCD_OTF_TCON2_HFPD(_p) (((_p)-1) << 8)
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#define CLCD_OTF_TCON2_HSPW(_p) (((_p)-1) << 0)
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#else
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#define CLCD_OTF_TCON2_HBPD(_p) (((_p)-1) << 20)
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#define CLCD_OTF_TCON2_HFPD(_p) (((_p)-1) << 10)
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#define CLCD_OTF_TCON2_HSPW(_p) (((_p)-1) << 0)
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#endif
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#define rCLCD_OTF_TCON3 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0060))
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#define CLCD_OTF_TCON3_HOZVAL(_p) (((_p)-1) << 16)
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#define CLCD_OTF_TCON3_LINEVAL(_p) (((_p)-1) << 0)
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#define rCLCD_OTF_INT_EN (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0064))
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#define rCLCD_OTF_INT_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0068))
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#define rCLCD_MIE_SAT_CON (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0074))
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#define rCLCD_DITHER_ENABLE (*(volatile u_int32_t *)(CLCD_DITHER_BASE_ADDR + 0x0000))
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#define rCLCD_DITHER_METHOD (*(volatile u_int32_t *)(CLCD_DITHER_BASE_ADDR + 0x0004))
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#endif /* __SAMSUNG_CLCD_REGS_H */
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