96 lines
3.6 KiB
C
96 lines
3.6 KiB
C
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/* -*- tab-width: 8; Mode: C; c-basic-offset: 8; indent-tabs-mode: t -*-
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*
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* Copyright (C) 2010 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Computer, Inc.
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*/
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/*
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* Register layout for a memory-mapped 16x50-style UART.
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*
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* Register and bit names/definitions from the National Semiconductor PC16550D datasheet.
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*
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* Note that the register set described here is a subset containing just those registers
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* useful for the iBoot environment. In particular, no modem support registers/definitions
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* are included.
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*/
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#ifndef __UART_16x50_H
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#define __UART_16x50_H
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/* allow an override of the spacing between registers */
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#ifndef UART16x50_REGISTER_STRIDE
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# define UART16x50_REGISTER_STRIDE 4
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#endif
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/* allow an override of the datatype used for reading/writing the registers */
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#ifndef UART16x50_REGISTER_TYPE
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# define UART16x50_REGISTER_TYPE uint32_t
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#endif
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/* produce a pointer to a UART register, assuming base registers in uart_ports */
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#define UART_REG(_port, _offset) \
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(*(volatile UART16x50_REGISTER_TYPE *)((uint8_t *)uart_ports[(_port)] + ((_offset) * UART16x50_REGISTER_STRIDE)))
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//
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// UART Registers for UART _port
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//
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#define rRBR(_port) UART_REG(_port, 0) // receiver buffer register (RO)
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#define rTHR(_port) UART_REG(_port, 0) // transmitter holding register (WO)
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#define rIER(_port) UART_REG(_port, 1) // interrupt enable register
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#define rIIR(_port) UART_REG(_port, 2) // interrupt ident. register (RO)
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#define rFCR(_port) UART_REG(_port, 2) // FIFO control register (WO)
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#define rLCR(_port) UART_REG(_port, 3) // line control register
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#define rLSR(_port) UART_REG(_port, 5) // line status register
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#define rDLL(_port) UART_REG(_port, 0) // divisor latch (LS)
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#define rDLM(_port) UART_REG(_port, 1) // divisor latch (MS)
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// IER
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#define IER_ERBFI (1<<0) // enable received data available interrupt
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#define IER_ETBEI (1<<1) // enable transmit holding register empty interrupt
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#define IER_ELSI (1<<2) // enable receiver line status interrupt
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// IIR
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#define IIR_NOTPEND (1<<0) // interrupt not pending
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#define IIR_IID_MASK 0xe // interrupt pending/ID mask
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#define IIR_IID_THRE 0x2 // transmitter holding register empty
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#define IIR_IID_RBF 0x4 // received data available
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#define IIR_IID_LSR 0x6 // receiver line status
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#define IIR_IID_CTI 0xc // character timeout indication
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// FCR
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#define FCR_FIFO_EN (1<<0) // FIFO enable
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#define FCR_RXSR (1<<1) // reciever fifo reset
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#define FCR_TXSR (1<<2) // transmitter fifo reset
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#define FCR_TL1 (0<<6) // RCVR FIFO trigger level - 1 byte
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#define FCR_TL4 (1<<6) // 4 bytes
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#define FCR_TL8 (2<<6) // 8 bytes
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#define FCR_TL14 (3<<6) // 14 bytes
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// LCR
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#define LCR_WLS_8 (3<<0) // 8 bit data (seriously, who uses anything else?)
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#define LCR_1_STB (0<<2) // 1 stop bit
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#define LCR_2_STB (1<<2) // 2 stop bits
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#define LCR_PEN (1<<3) // parity enable
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#define LCR_EPS (1<<4) // even parity select
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#define LCR_STICK (1<<5) // stick parity
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#define LCR_SBRK (1<<6) // set break
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#define LCR_DLAB (1<<7) // divisor latch access bit
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// LSR
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#define LSR_DR (1<<0) // data ready
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#define LSR_OE (1<<1) // overrun
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#define LSR_PE (1<<2) // parity error
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#define LSR_FE (1<<3) // framing error
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#define LSR_BI (1<<4) // break
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#define LSR_THRE (1<<5) // transmit holding register empty
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#define LSR_TEMT (1<<6) // transmitter empty
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#define LSR_RFERR (1<<7) // error in receiver FIFO
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#endif /* __UART_16x50_H */
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