310 lines
18 KiB
C
310 lines
18 KiB
C
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/*
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* Copyright (C) 2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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//
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// Please update test plan version to know what is the reference.
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//
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// Elba Test Plan Version 1.6
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// Elba Tunables Specification Revision 0.46
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//
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#include <platform/pmgr.h>
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#include <platform/soc/chipid.h>
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//
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// Fuses in MINIPMGR are linearly mapped
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//
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static const struct pmgr_binning_fuse_to_register minipmgr_fuse_register[] = {
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// binning_low
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// | binning_high
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// | | register_low
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// | | | register_64bit
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// | | | | register_address
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// | | | | |
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{ 0, 369, 0, 0, AOP_MINIPMGR_BASE_ADDR + MINIPMGR_FUSE_CFG_FUSE0_OFFSET},
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{ 0, 0, 0, 0, 0},
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};
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//
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// Fuses in ACC (UDR) are sparsely mapped
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//
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static const struct pmgr_binning_fuse_to_register acc_fuse_register[] = {
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// binning_low
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// | binning_high
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// | | register_low
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// | | | register_64bit
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// | | | | register_address
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// | | | | |
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{ 0, 2, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
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{ 3, 6, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST0_EXT2_OFFSET},
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{ 7, 9, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
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{ 10, 13, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST1_EXT2_OFFSET},
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{ 14, 16, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
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{ 17, 20, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST2_EXT2_OFFSET},
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{ 21, 23, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
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{ 24, 27, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST3_EXT2_OFFSET},
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{ 28, 30, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
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{ 31, 34, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST4_EXT2_OFFSET},
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{ 35, 37, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
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{ 38, 41, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST5_EXT2_OFFSET},
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{ 42, 44, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
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{ 45, 48, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST6_EXT2_OFFSET},
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{ 40, 51, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
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{ 52, 55, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST7_EXT2_OFFSET},
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{ 56, 58, 0, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
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{ 59, 62, 4, 1, ACC_BASE_ADDR + ACC_PWRCTL_DVFM_ST8_EXT2_OFFSET},
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{ 112, 114,29, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
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{ 115, 119,24, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
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{ 120, 127,16, 0, ACC_BASE_ADDR + ACC_PWRCTL_EFUSE_REV_OFFSET},
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{ 0, 0, 0, 0, 0},
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};
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const struct pmgr_binning_mode_to_fuse pmgr_binning_mode_to_fuse_data[] = {
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//
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// CPU
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//
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//type
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//| mode
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//| | bingroup
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//| | | low
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//| | | | high
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//| | | | | fuse_to_register
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//| | | | | |
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{PMGR_BINNING_CPU, 1, PMGR_BINNING_GROUP_ALL, 0, 6, acc_fuse_register},
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{PMGR_BINNING_CPU, 2, PMGR_BINNING_GROUP_ALL, 7, 13, acc_fuse_register},
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{PMGR_BINNING_CPU, 3, PMGR_BINNING_GROUP_ALL, 14, 20, acc_fuse_register},
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{PMGR_BINNING_CPU, 4, PMGR_BINNING_GROUP_ALL, 21, 27, acc_fuse_register},
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{PMGR_BINNING_CPU, 5, PMGR_BINNING_GROUP_ALL, 28, 34, acc_fuse_register},
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{PMGR_BINNING_CPU, 6, PMGR_BINNING_GROUP_ALL, 35, 41, acc_fuse_register},
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{PMGR_BINNING_CPU, 7, PMGR_BINNING_GROUP_ALL, 42, 48, acc_fuse_register},
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{PMGR_BINNING_CPU, 8, PMGR_BINNING_GROUP_ALL, 49, 55, acc_fuse_register},
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//
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// GPU/SOC
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//
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//type
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//| mode
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//| | bingroup
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//| | | low
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//| | | | high
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//| | | | | fuse_to_register
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//| | | | | |
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{PMGR_BINNING_GPU, 1, PMGR_BINNING_GROUP_ALL, 238, 244, minipmgr_fuse_register},
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{PMGR_BINNING_GPU, 2, PMGR_BINNING_GROUP_ALL, 245, 251, minipmgr_fuse_register},
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{PMGR_BINNING_GPU, 3, PMGR_BINNING_GROUP_ALL, 252, 258, minipmgr_fuse_register},
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{PMGR_BINNING_GPU, 4, PMGR_BINNING_GROUP_ALL, 259, 265, minipmgr_fuse_register},
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{PMGR_BINNING_GPU, 5, PMGR_BINNING_GROUP_ALL, 266, 272, minipmgr_fuse_register},
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{PMGR_BINNING_SOC, 1, PMGR_BINNING_GROUP_ALL, 224, 230, minipmgr_fuse_register},
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{PMGR_BINNING_SOC, 2, PMGR_BINNING_GROUP_ALL, 231, 237, minipmgr_fuse_register},
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{PMGR_BINNING_BASE, 0, PMGR_BINNING_GROUP_ALL, 115, 119, acc_fuse_register},
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{PMGR_BINNING_REV, 0, PMGR_BINNING_GROUP_ALL, 142, 147, minipmgr_fuse_register},
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{PMGR_BINNING_END_OF_LIST, 0, PMGR_BINNING_GROUP_ALL, 0, 0, NULL},
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};
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//
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// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
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//
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const struct pmgr_binning_voltage_index_to_config pmgr_binning_voltage_index_to_config_data[] = {
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// voltage index
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// | safe voltage
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// | | mode
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// | | | type
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// | | | | binning group
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// | | | | | fuse revision minimun
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{CHIPID_CPU_VOLTAGE_BYPASS, 606, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_CPU_VOLTAGE_SECUREROM, 606, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_CPU_VOLTAGE_396, 606, 1, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_CPU_VOLTAGE_720, 606, 2, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_CPU_VOLTAGE_1080, 720, 3, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_CPU_VOLTAGE_1440, 833, 4, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_CPU_VOLTAGE_1800, 947, 5, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_CPU_VOLTAGE_2160, 1060, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_CPU_VOLTAGE_2256_1core, 1060, 6, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_CPU_VOLTAGE_2256, 1090, 7, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_CPU_VOLTAGE_2352, 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_CPU_VOLTAGE_2448, 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU, PMGR_BINNING_GROUP_ALL, 0},
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// There is only one SOC voltage state on S8001
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// But Test Plan named MS001 for J99a and MS002 for J127
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// and this is like S8000 which call MS1 for VMIN and MS2 for VNOM
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{CHIPID_SOC_VOLTAGE_VMIN, 800, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_SOC_VOLTAGE_VNOM, 900, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SOC, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_GPU_VOLTAGE_OFF, 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_GPU_VOLTAGE_360, 670, 1, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_GPU_VOLTAGE_520, 800, 2, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_GPU_VOLTAGE_650, 920, 3, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_GPU_VOLTAGE_723, 1030, 4, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_GPU_VOLTAGE_800, 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
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{CHIPID_GPU_VOLTAGE_804, 1100, 5, PMGR_BINNING_GPU, PMGR_BINNING_GROUP_ALL, 0},
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};
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//
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// Safe voltage of 0 and binning mode != PMGR_BINNING_MODE_NONE
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// means data are store in pmgr_binning_mode_to_const_data
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//
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const struct pmgr_binning_voltage_config pmgr_binning_voltage_config_sram_data[] = {
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// safe voltage (0 means lookup data in pmgr_binning_mode_to_const_data)
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// | mode
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// | | type
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// | | |
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[CHIPID_CPU_VOLTAGE_396] = { 0, 1, PMGR_BINNING_CPU_SRAM},
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[CHIPID_CPU_VOLTAGE_720] = { 0, 2, PMGR_BINNING_CPU_SRAM},
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[CHIPID_CPU_VOLTAGE_1080] = { 0, 3, PMGR_BINNING_CPU_SRAM},
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[CHIPID_CPU_VOLTAGE_1440] = { 0, 4, PMGR_BINNING_CPU_SRAM},
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[CHIPID_CPU_VOLTAGE_1800] = { 0, 5, PMGR_BINNING_CPU_SRAM},
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[CHIPID_CPU_VOLTAGE_2160] = { 0, 6, PMGR_BINNING_CPU_SRAM},
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[CHIPID_CPU_VOLTAGE_2256_1core] = { 0, 7, PMGR_BINNING_CPU_SRAM},
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[CHIPID_CPU_VOLTAGE_2256] = { 1090, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
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[CHIPID_CPU_VOLTAGE_2352] = { 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
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[CHIPID_CPU_VOLTAGE_2448] = { 1130, PMGR_BINNING_MODE_NONE, PMGR_BINNING_CPU_SRAM},
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[CHIPID_GPU_VOLTAGE_OFF] = { 0, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
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[CHIPID_GPU_VOLTAGE_360] = { 0, 1, PMGR_BINNING_GPU_SRAM},
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[CHIPID_GPU_VOLTAGE_520] = { 0, 2, PMGR_BINNING_GPU_SRAM},
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[CHIPID_GPU_VOLTAGE_650] = { 0, 3, PMGR_BINNING_GPU_SRAM},
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[CHIPID_GPU_VOLTAGE_723] = { 0, 4, PMGR_BINNING_GPU_SRAM},
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[CHIPID_GPU_VOLTAGE_800] = { 1030, PMGR_BINNING_MODE_NONE, PMGR_BINNING_GPU_SRAM},
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[CHIPID_GPU_VOLTAGE_804] = { 0, 5, PMGR_BINNING_GPU_SRAM},
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[CHIPID_VOLTAGE_FIXED] = { 900, PMGR_BINNING_MODE_NONE, PMGR_BINNING_SRAM},
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};
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//
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// Group-specific entries must come before the corresponding entry with PMGR_BINNING_GROUP_ALL.
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//
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const struct pmgr_binning_mode_to_const pmgr_binning_mode_to_const_data[] = {
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// Voltage
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// | Mode
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// | | Type
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// | | | Binning group
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// | | | | fuse revision minimun
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// | | | | |
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{ 820, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
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{ 930, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
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{ 990, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
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{1000, 7, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 8},
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{ 835, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
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{ 885, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
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{1000, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
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{1000, 7, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
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{ 800, 1, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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{ 800, 2, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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{ 800, 3, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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{ 833, 4, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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{ 947, 5, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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{1060, 6, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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{1060, 7, PMGR_BINNING_CPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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{1100, 5, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 10},
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{ 850, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
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{ 930, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
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{1000, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 6},
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{ 800, 1, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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{ 800, 2, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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{ 920, 3, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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{1030, 4, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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{1100, 5, PMGR_BINNING_GPU_SRAM, PMGR_BINNING_GROUP_ALL, 0},
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};
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const struct pmgr_binning_board_id_to_offsets pmgr_binning_board_id_to_offsets_data[] = {
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// type
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// | voltage offset array
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// | | voltage offset array size
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// | | | chip rev
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// | | | | board id
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// | | | | | binning group
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// | | | | | |
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};
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// .voltages = {volAdj0, volAdj1, volAdj2, volAdj3, dvfmMaxAdj, dvmrAdj0, dvmrAdj1, dvmrAdj2}
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const struct pmgr_binning_voltadj_entry pmgr_binning_voltadj_entry_data[] = {
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//
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// CPU
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//
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// volAdj0
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// | volAdj1
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// | | volAdj2
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// | | | volAdj3
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// | | | | dvfmMaxAdj
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// | | | | | dvmrAdj0
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// | | | | | | dvmrAdj1
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// | | | | | | | dvmrAdj2
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// | | | | | | | |
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{CHIPID_CPU_VOLTAGE_396 , CHIP_REVISION_B0, 0, .voltages = {0, 9375, 18750, 18750, 40625, 0, 0, 0}},
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||
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{CHIPID_CPU_VOLTAGE_720 , CHIP_REVISION_B0, 0, .voltages = {0, 0, 18750, 21875, 40625, 0, 0, 0}},
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{CHIPID_CPU_VOLTAGE_1080, CHIP_REVISION_B0, 0, .voltages = {0, 0, 15625, 15625, 40625, 0, 0, 0}},
|
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|
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{CHIPID_CPU_VOLTAGE_1440, CHIP_REVISION_B0, 0, .voltages = {0, 0, 12500, 12500, 40625, 0, 0, 0}},
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|
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{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||
|
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{CHIPID_CPU_VOLTAGE_2160, CHIP_REVISION_B0, 0, .voltages = {21875,0, 0, 0, 40625, 0, 0, 0}},
|
||
|
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{CHIPID_CPU_VOLTAGE_2256_1core,CHIP_REVISION_B0,0,.voltages={21875,0, 0, 0, 40625, 0, 0, 0}},
|
||
|
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{CHIPID_CPU_VOLTAGE_2256, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_2352, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_2448, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||
|
|
|
||
|
|
|
||
|
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{CHIPID_CPU_VOLTAGE_BYPASS,CHIP_REVISION_A0,0, .voltages = {0, 0, 0, 0, 40625, 0, 0, 0}},
|
||
|
|
{CHIPID_SOC_VOLTAGE_SECUREROM,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0, 0, 0, 0, 0}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_396 , CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 18750, 40625, 0, 0, 0}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_720 , CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 18750, 40625, 0, 0, 0}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_1080, CHIP_REVISION_A0, 0, .voltages = {0, 3125, 6250, 12500, 40625, 6250, 6250, 0}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_1440, CHIP_REVISION_A0, 0, .voltages = {0, 3125, 6250, 12500, 40625, 9375, 9375, 0}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_1800, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 18750, 15625, 3125}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_2160, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 25000, 21875, 3125}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_2256_1core,CHIP_REVISION_A0,0,.voltages={0, 0, 0, 0, 40625, 3125, 0, 0}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_2256, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 25000, 21875, 3125}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_2352, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 28125, 25000, 3125}},
|
||
|
|
{CHIPID_CPU_VOLTAGE_2448, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0, 40625, 3125, 0, 0}},
|
||
|
|
|
||
|
|
// GFX
|
||
|
|
//
|
||
|
|
// volAdj0
|
||
|
|
// | volAdj1
|
||
|
|
// | | volAdj2
|
||
|
|
// | | | volAdj3
|
||
|
|
// | | | | N/A
|
||
|
|
// | | | | | N/A
|
||
|
|
// | | | | | | N/A
|
||
|
|
// | | | | | | | N/A
|
||
|
|
// | | | | | | | |
|
||
|
|
{CHIPID_GPU_VOLTAGE_360, CHIP_REVISION_B0, 0, .voltages = {0, 3125, 18750, 21875,0,0,0,0}},
|
||
|
|
{CHIPID_GPU_VOLTAGE_520, CHIP_REVISION_B0, 0, .voltages = {0, 0, 12500, 12500,0,0,0,0}},
|
||
|
|
{CHIPID_GPU_VOLTAGE_650, CHIP_REVISION_B0, 0, .voltages = {0, 0, 6125, 6125,0,0,0,0}},
|
||
|
|
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||
|
|
{CHIPID_GPU_VOLTAGE_804, CHIP_REVISION_B0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||
|
|
|
||
|
|
{CHIPID_GPU_VOLTAGE_360, CHIP_REVISION_A0, 0, .voltages = {0, 12500, 25000, 25000,0,0,0,0}},
|
||
|
|
{CHIPID_GPU_VOLTAGE_520, CHIP_REVISION_A0, 0, .voltages = {0, 6250, 12500, 12500,0,0,0,0}},
|
||
|
|
{CHIPID_GPU_VOLTAGE_650, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||
|
|
{CHIPID_GPU_VOLTAGE_723, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||
|
|
{CHIPID_GPU_VOLTAGE_804, CHIP_REVISION_A0, 0, .voltages = {0, 0, 0, 0,0,0,0,0}},
|
||
|
|
};
|
||
|
|
|
||
|
|
const uint32_t pmgr_binning_voltage_config_sram_data_size =
|
||
|
|
sizeof(pmgr_binning_voltage_config_sram_data)/sizeof(pmgr_binning_voltage_config_sram_data[0]);
|
||
|
|
const uint32_t pmgr_binning_mode_to_const_data_size = sizeof(pmgr_binning_mode_to_const_data)/sizeof(pmgr_binning_mode_to_const_data[0]);
|
||
|
|
const uint32_t pmgr_binning_voltadj_entry_data_size = sizeof(pmgr_binning_voltadj_entry_data) / sizeof(pmgr_binning_voltadj_entry_data[0]);
|
||
|
|
const uint32_t pmgr_binning_voltage_index_to_config_data_size = sizeof(pmgr_binning_voltage_index_to_config_data)/sizeof(pmgr_binning_voltage_index_to_config_data[0]);
|
||
|
|
const uint32_t pmgr_binning_board_id_to_offsets_data_size = sizeof(pmgr_binning_board_id_to_offsets_data)/sizeof(pmgr_binning_board_id_to_offsets_data[0]);
|