67 lines
3.6 KiB
C
67 lines
3.6 KiB
C
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/*
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* Copyright (C) 2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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/* This file contains Tunables for s8001 ipad6b */
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#include <platform/tunables.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwregbase.h>
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#include <soc/module/address_map.h>
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/**************************************** BEGIN CHIP_REVISION_ALL ****************************************/
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// <rdar://problem/22709991> Update iBoot/PMGR driver settings for enabling UV_WARN for J127/J105
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#define SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_IPAD6B_EXTRA \
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{ /*! GFX_THROTTLE_DITHER0_INT */ 0x7403c, sizeof(uint32_t), 0xffffffffu, 0x480000u}, \
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{ /*! GFX_THROTTLE_DITHER0 */ 0x74040, sizeof(uint32_t), 0xffffffffu, 0x10555u}, \
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{ /*! GFX_THROTTLE_DITHER1 */ 0x74044, sizeof(uint32_t), 0xffffffffu, 0x106dbu}, \
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{ /*! GFX_THROTTLE_DITHER2 */ 0x74048, sizeof(uint32_t), 0xffffffffu, 0x10fffu}, \
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{ /*! GFX_THROTTLE_DITHER3 */ 0x7404c, sizeof(uint32_t), 0xffffffffu, 0x00fffu}, \
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{ /*! GFX_THROTTLE_DITHER4 */ 0x74050, sizeof(uint32_t), 0xffffffffu, 0x00fffu}, \
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{ /*! GFX_THROTTLE_DITHER5 */ 0x74054, sizeof(uint32_t), 0xffffffffu, 0x00fffu}, \
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{ /*! GFX_THROTTLE_SRC2_CTL */ 0x74078, sizeof(uint32_t), 0xffffffffu, 0x00003u}, \
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{ /*! GFX_THROTTLE_SRC2_ASSERT_COUNT */ 0x7407c, sizeof(uint32_t), 0xffffffffu, 0x00000u}, \
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{ /*! GFX_THROTTLE_SRC2_DEASSERT_COUNT */ 0x74080, sizeof(uint32_t), 0xffffffffu, 0x00000u}, \
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{ /*! GFX_THROTTLE_SRC2_MIN_ACTIVE_COUNT */ 0x74084, sizeof(uint32_t), 0xffffffffu, 0x00000u}, \
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{ /*! GFX_PERF_CFG4 */ 0xfc140, sizeof(uint32_t), 0xffffffffu, 0x10003u}, \
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{ /*! GFX_PERF_CFG5 */ 0xfc150, sizeof(uint32_t), 0xffffffffu, 0x10001u}, \
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{ /*! GFX_PERF_CTL */ 0xfc000, sizeof(uint32_t), 0xffffffffu, 0x00003u}, \
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{ -1, -1, -1, -1 }
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/**************************************** END CHIP_REVISION_ALL ****************************************/
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/**************************************** BEGIN CHIP_REVISION_B0 ****************************************/
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#include <soc/s8001/b0/tunable/pmgr.h>
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static const struct tunable_struct pmgr_tunable_b0[] = {
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SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_IPAD6B_EXTRA
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};
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/***************************************** END CHIP_REVISION_B0 *****************************************/
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/**************************************** BEGIN CHIP_REVISION_A0 ****************************************/
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#include <soc/s8001/a0/tunable/pmgr.h>
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static const struct tunable_struct pmgr_tunable_a0[] = {
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SOUTH_BRIDGE_PMS_PMGR_DEFAULT_TUNABLES_S8001_IPAD6B_EXTRA
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};
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/***************************************** END CHIP_REVISION_A0 *****************************************/
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// For each chip, highest revision must come first.
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// Notice reconfig == false for minipmgr, since it's an AOP.
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const struct tunable_chip_struct tunables_pmgr_product[] = {
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// B0
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{CHIP_REVISION_B0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8001_B0, pmgr_tunable_b0, NULL, true},
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// A0
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{CHIP_REVISION_A0, SOUTH_BRIDGE_PMS_PMGR_PADDR_S8001_A0, pmgr_tunable_a0, NULL, true},
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{0, 0, NULL, NULL, 0}
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};
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