381 lines
11 KiB
C
381 lines
11 KiB
C
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/*
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* Copyright (C) 2010-2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include "pl080dmac_ae2.h"
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#include "ae2_i2s.h"
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#include "ae2_mca.h"
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#include <drivers/audio/audio.h>
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#include <debug.h>
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#include <stdlib.h>
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#ifdef MAP_SRAM_CACHED
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#error DMA requires the SRAM to be uncached
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#endif
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typedef struct
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{
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uint32_t mDMAChannel;
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int_handler mInterruptHandler;
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void * mInterruptHandlerData;
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int_handler mErrorHandler;
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void * mErrorHandlerData;
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} internal_dma_object_t;
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#define validDMAChannel(dmaChannel) (dmaChannel!=0xffffffff)
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//Per AE2 Local DMA Controller/Requests
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static const uint32_t sDMARequestInterfaceRx[kAudioDevice_Last] = {0, 2, 4, 6, 10, 6};
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static const uint32_t sDMARequestInterfaceTx[kAudioDevice_Last] = {1, 3, 5, 7, 11, 7};
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static void* sDMAAddressRX[kAudioDevice_Last] = { (void*)rI2S0_RXDB, (void*)rI2S1_RXDB, (void*)rI2S2_RXDB, (void*)rI2S3_RXDB, (void*)rMCA0_RXDATA, (void*)rMCA1_RXDATA };
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static void* sDMAAddressTX[kAudioDevice_Last] = { (void*)rI2S0_TXDB, (void*)rI2S1_TXDB, (void*)rI2S2_TXDB, (void*)rI2S3_TXDB, (void*)rMCA0_TXDATA, (void*)rMCA1_TXDATA };
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static internal_dma_object_t* sDMAChannelObjects[kDMAChannelsPerController] = { NULL };
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static uint32_t sDMACC0InUse = 0;
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static uint32_t sDMACC0Running = 0;
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uint32_t readReg(uint32_t address)
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{
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return *(volatile uint32_t *)address;
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}
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void writeReg(uint32_t address, uint32_t value)
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{
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*(volatile uint32_t *)address = value;
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}
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uint32_t readDMAReg(uint32_t offset)
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{
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return readReg(kDMACBase + offset);
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}
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void writeDMAReg(uint32_t offset, uint32_t value)
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{
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writeReg(kDMACBase + offset, value);
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}
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uint32_t readDMAChannelReg(uint32_t channel, uint32_t offset)
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{
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uint32_t dmaChannelOffset = kDMAC0Base + channel * kDMACRegisterSize;
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return readReg(dmaChannelOffset + offset);
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}
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void writeDMAChannelReg(uint32_t channel, uint32_t offset, uint32_t value)
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{
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uint32_t dmaChannelOffset = kDMAC0Base + channel * kDMACRegisterSize;
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writeReg(dmaChannelOffset + offset, value);
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}
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dma_object_t create_dma_object(void *buffer, AudioDevice_Index device, DMALinkedListItem *chain, DMADirection direction, size_t bytesToTransfer)
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{
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dprintf(DEBUG_CRITICAL, "Creating a DMA object\n");
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if ((device >= kAudioDevice_Last) || ((direction != kDirectionIn) && (direction != kDirectionOut)))
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{
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dprintf(DEBUG_CRITICAL, "oops, bad arg\n");
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return NULL;
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}
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internal_dma_object_t *This = (internal_dma_object_t*)malloc(sizeof(internal_dma_object_t));
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if (This)
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{
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uint32_t dmaChannel = acquireDMAChannel();
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dprintf(DEBUG_CRITICAL, "channel is %d\n", dmaChannel);
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if (dmaChannel == 0xFFFFFFFF)
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{
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free(This);
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return NULL;
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}
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This->mDMAChannel = dmaChannel;
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This->mInterruptHandler = NULL;
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This->mInterruptHandlerData = NULL;
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This->mErrorHandler = NULL;
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This->mErrorHandlerData = NULL;
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configureDMA(This->mDMAChannel);
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if (direction == kDirectionIn)
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{
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setupDMA(This->mDMAChannel, sDMAAddressRX[device], buffer, chain, kDirectionIn, sDMARequestInterfaceRx[device], bytesToTransfer);
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}
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else
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{
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setupDMA(This->mDMAChannel, buffer, sDMAAddressTX[device], chain, kDirectionOut, sDMARequestInterfaceTx[device], bytesToTransfer);
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}
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sDMAChannelObjects[This->mDMAChannel] = This;
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// we can do this here repeatedly
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install_int_handler(AE2_INT_DMACINTTC, handleAudioDeviceDMAInterrupt, NULL);
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install_int_handler(AE2_INT_DMACINTERR, handleAudioDeviceDMAInterruptError, NULL);
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}
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return This;
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}
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void destroy_dma_object(dma_object_t dma)
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{
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// preliminary stop
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stopDMAObject(dma, true);
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internal_dma_object_t *This = (internal_dma_object_t*)dma;
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if (This)
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{
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sDMAChannelObjects[This->mDMAChannel] = NULL;
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freeDMAChannel(This->mDMAChannel);
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free(This);
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}
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}
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uint32_t getErrorCount(dma_object_t, Error_Index)
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{
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return 0;
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}
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void setupInterruptHandler(dma_object_t dma, int_handler handler, void *arg)
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{
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internal_dma_object_t *This = (internal_dma_object_t*)dma;
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if (This)
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{
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This->mInterruptHandler = handler;
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This->mInterruptHandlerData = arg;
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}
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}
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void setupErrorHandler(dma_object_t dma, int_handler handler, void *arg)
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{
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internal_dma_object_t *This = (internal_dma_object_t*)dma;
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if (This)
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{
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This->mErrorHandler = handler;
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This->mErrorHandlerData = arg;
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}
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}
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void startDMAObject(dma_object_t dma)
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{
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internal_dma_object_t *This = (internal_dma_object_t*)dma;
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if (This)
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{
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startDMA(This->mDMAChannel);
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sDMACC0Running |= (1 << This->mDMAChannel);
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if (sDMACC0Running)
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{
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unmask_int(AE2_INT_DMACINTTC);
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unmask_int(AE2_INT_DMACINTERR);
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}
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}
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}
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void stopDMAObject(dma_object_t dma, bool immediate)
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{
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internal_dma_object_t *This = (internal_dma_object_t*)dma;
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if (This)
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{
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if (immediate)
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{
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disableDMAImmediate(This->mDMAChannel);
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}
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else
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{
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disableDMA(This->mDMAChannel);
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}
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sDMACC0Running &= ~(1 << This->mDMAChannel);
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if (!sDMACC0Running)
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{
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mask_int(AE2_INT_DMACINTTC);
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mask_int(AE2_INT_DMACINTERR);
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}
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}
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}
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void handleAudioDeviceDMAInterrupt()
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{
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uint32_t status = readDMAReg(kDMACIntTCStatus);
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for (uint32_t channel = 0; channel < kDMAChannelsPerController; channel++)
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{
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uint32_t mask = 1 << channel;
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if (status & mask)
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{
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writeDMAReg(kDMACIntTCClear, mask); //clear int
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if(sDMAChannelObjects[channel] != NULL && sDMAChannelObjects[channel]->mInterruptHandler)
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{
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sDMAChannelObjects[channel]->mInterruptHandler(sDMAChannelObjects[channel]->mInterruptHandlerData);
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}
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}
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}
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}
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void handleAudioDeviceDMAInterruptError()
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{
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uint32_t status = readDMAReg(kDMACIntErrStatus);
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for (uint32_t channel = 0; channel < kDMAChannelsPerController; channel++)
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{
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uint32_t mask = 1 << channel;
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if (status & mask)
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{
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writeDMAReg(kDMACIntErrClear, mask); //clear int
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if(sDMAChannelObjects[channel] != NULL && sDMAChannelObjects[channel]->mInterruptHandler)
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{
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sDMAChannelObjects[channel]->mInterruptHandler(sDMAChannelObjects[channel]->mInterruptHandlerData);
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}
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}
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}
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}
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uint32_t acquireDMAChannel(void)
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{
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uint32_t result = 0xFFFFFFFF;
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for(uint32_t channel = 0; channel < kDMAChannelsPerController; channel++)
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{
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if(!(sDMACC0InUse & (1 << channel)))
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{
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sDMACC0InUse |= (1 << channel);
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result = channel;
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break;
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}
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}
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if (sDMACC0InUse)
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{
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writeReg(kDMACClockGating, 0);
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writeDMAReg(kDMACConfiguration, DMACConfiguration_M2_Little | DMACConfiguration_M1_Little | DMACConfiguration_E_Enable);
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}
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return result;
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}
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void freeDMAChannel(uint32_t dmaChannel)
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{
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sDMACC0InUse &= ~(1 << dmaChannel);
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// if there are no channels in use, shut down DMA
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if (!sDMACC0InUse)
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{
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uint32_t config = readDMAReg(kDMACConfiguration);
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writeDMAReg(kDMACConfiguration, config & ~DMACConfiguration_E_Enable);
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}
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}
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void configureDMA(uint32_t dmaChannel)
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{
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if(!validDMAChannel(dmaChannel)) return;
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uint32_t control = DMACCxControl_I_Enable |
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DMACCxControl_D_Master1 |
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DMACCxControl_S_Master1 |
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DMACCxControl_SWidth_Halfword |
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DMACCxControl_DWidth_Halfword |
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DMACCxControl_SBSize_4 |
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DMACCxControl_DBSize_4;
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writeDMAChannelReg(dmaChannel, kDMACCtrlOffset, control);
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}
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void setupDMA(uint32_t dmaChannel, void *src, void *dst, DMALinkedListItem *chain, DMADirection direction, uint32_t peripheral, size_t bytesToTransfer)
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{
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if(!validDMAChannel(dmaChannel)) return;
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uint32_t transferSize = bytesToTransfer >> 1; //assuming burst size of DMACCxControl_DWidth_Halfword
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uint32_t control = readDMAChannelReg(dmaChannel, kDMACCtrlOffset);
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control &= ~(DMACCxControl_TransferSizeMask | // Clear transfer size
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DMACCxControl_SI_Mask | // Clear source increment
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DMACCxControl_DI_Mask); // Clear destination increment
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control |= (transferSize & 0x0FFF);
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uint32_t flowControl, sourcePeripheral, destinationPeripheral;
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if(direction == kDirectionIn) // -> peripheral-to-memory
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{
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control |= DMACCxControl_SI_No_Increment;
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control |= DMACCxControl_DI_Increment;
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flowControl = DMACCxConfiguration_FlowCntrl_Peripheral_to_Memory_DMA;
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sourcePeripheral = peripheral;
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destinationPeripheral = 0; //mem
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}
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else if(direction == kDirectionOut) //kDirectionOut -> memory-to-peripheral
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{
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control |= DMACCxControl_SI_Increment;
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control |= DMACCxControl_DI_No_Increment;
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flowControl = DMACCxConfiguration_FlowCntrl_Memory_to_Peripheral_DMA;
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sourcePeripheral = 0; //mem
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destinationPeripheral = peripheral;
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}
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else //kDirectionNone -> mem-to-mem here
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{
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control |= DMACCxControl_SI_Increment;
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control |= DMACCxControl_DI_Increment;
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flowControl = DMACCxConfiguration_FlowCntrl_Memory_to_Memory_DMA;
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sourcePeripheral = 0; //mem
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destinationPeripheral = 0; //mem
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}
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DMALinkedListItem *chainElement = chain;
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while(chainElement != NULL)
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{
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chainElement->control = (uint32_t)control;
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chainElement = chainElement->next;
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if(chainElement == chain)
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{
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//We've populated all of the control values in this circular linked list, we are done here
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break;
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}
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}
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writeDMAChannelReg(dmaChannel, kDMACSourceOffset, (uint32_t)src);
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writeDMAChannelReg(dmaChannel, kDMACDestOffset, (uint32_t)dst);
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writeDMAChannelReg(dmaChannel, kDMACLLIOffset, (uint32_t)chain);
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writeDMAChannelReg(dmaChannel, kDMACCtrlOffset, control);
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flowControl |= DMACCxConfiguration_ITC_Enable;
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flowControl |= DMACCxConfiguration_IError_Enable;
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flowControl |= ((destinationPeripheral & 0xF) << 6);
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flowControl |= ((sourcePeripheral & 0xF) << 1);
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// do this in the start
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//flowControl |= DMACCxConfiguration_E_Enable;
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writeDMAChannelReg(dmaChannel, kDMACConfigOffset, flowControl);
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}
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void startDMA(uint32_t dmaChannel)
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{
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if(!validDMAChannel(dmaChannel)) return;
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uint32_t flowControl = readDMAChannelReg(dmaChannel, kDMACConfigOffset);
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writeDMAChannelReg(dmaChannel, kDMACConfigOffset, flowControl |= DMACCxConfiguration_E_Enable);
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}
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void disableDMA(uint32_t dmaChannel)
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{
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if(!validDMAChannel(dmaChannel)) return;
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uint32_t config = readDMAChannelReg(dmaChannel, kDMACConfigOffset);
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writeDMAChannelReg(dmaChannel, kDMACConfigOffset, config | DMACCxConfiguration_Halt);
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config = readDMAChannelReg(dmaChannel, kDMACConfigOffset);
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// give a chance for the DMA to timeout. But don't wait forever...
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int timeToWait = 0x100;
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while(config & DMACCxConfiguration_Active && (timeToWait-- > 0))
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{
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config = readDMAChannelReg(dmaChannel, kDMACConfigOffset);
|
||
|
|
}
|
||
|
|
disableDMAImmediate(dmaChannel);
|
||
|
|
}
|
||
|
|
|
||
|
|
void disableDMAImmediate(uint32_t dmaChannel)
|
||
|
|
{
|
||
|
|
if(!validDMAChannel(dmaChannel)) return;
|
||
|
|
|
||
|
|
uint32_t config = readDMAChannelReg(dmaChannel, kDMACConfigOffset);
|
||
|
|
writeDMAChannelReg(dmaChannel, kDMACConfigOffset, config & ~DMACCxConfiguration_E_Enable);
|
||
|
|
|
||
|
|
writeDMAReg(kDMACIntTCClear, 1 << dmaChannel); // clear any outstanding ints
|
||
|
|
writeDMAReg(kDMACIntErrClear, 1 << dmaChannel); // clear any outstanding ints
|
||
|
|
}
|
||
|
|
|