90 lines
4.8 KiB
C
90 lines
4.8 KiB
C
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/*
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* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __ADBE_REGS_H
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#define __ADBE_REGS_H
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#include <platform/soc/hwregbase.h>
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#define rDBEMODECNTL (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x4))
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#define DBEMODECNTL_AAP_ENABLE (1 << 31)
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#define DBEMODECNTL_DPB_ENABLE (1 << 30)
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#define DBEMODECNTL_BN_DITHER_ENABLE (1 << 29)
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#define DBEMODECNTL_ST_DITHER_ENABLE (1 << 28)
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#define DBEMODECNTL_DPB_BUSY_MASK (1 << 23)
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#define DBEMODECNTL_PMGR_CLK_GATE_ENABLE (1 << 22)
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#define DBEMODECNTL_DYN_CLK_GATE_ENABLE (1 << 21)
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#define DBEMODECNTL_BLK_CLK_GATE_ENABLE (1 << 20)
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#define DBEMODECNTL_DITHER_ENABLE (1 << 28)
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#define DBEMODECNTL_PRC_ENABLE (1 << 27)
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#define DBEMODECNTL_WPC_ENABLE (1 << 26)
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#define rDBEVFTGCTL (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x8))
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#define DBEVFTGCT_VFTG_ENABLE (1 << 31)
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#define DBEVFTGCT_VFTG_STATUS (1 << 30)
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#define DBEVFTGCT_FRAME_COUNT_ENABLE (1 << 29)
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#define DBEVFTGCT_FRAME_COUNT_RESET (1 << 28)
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#define DBEVFTGCT_IDLE_FRAME_VBLANK_ENABLE (1 << 24)
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#define DBEVFTGCT_VSYNC_POLARITY(n) ((n) << 19)
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#define DBEVFTGCT_HSYNC_POLARITY(n) ((n) << 18)
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#define DBEVFTGCT_SCAN_SELECT(n) ((n) << 16)
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#define DBEVFTGCT_UPDATE_ENABLE_TIMING (1 << 15)
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#define DBEVFTGCT_UPDATE_REQ_TIMING (1 << 14)
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#define DBEVFTGCT_CH2_SEL(n) ((n) << 12)
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#define DBEVFTGCT_CH1_SEL(n) ((n) << 10)
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#define DBEVFTGCT_CH0_SEL(n) ((n) << 8)
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#define DBEVFTGCT_VERTICAL_STATUS(n) ((n) << 4)
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#define DBEVFTGCT_HORIZONTAL_STATUS(n) ((n) << 0)
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#define rDBESCRNSZ (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0xC))
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#define rDBEFRONTPORCH (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x10))
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#define rDBESYNCPULSE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x14))
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#define rDBEBACKPORCH (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x18))
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#define rDBECOUNTER_STATUS (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x1C))
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#define rDBECOUNTER_POSITION (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x20))
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#define rDBEVBLANK_POSITION (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x24))
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#define rDBEVBLANKCLKGATE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x28))
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#define rDBEVBLANKBUSY (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x2C))
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#define rDBEISR (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x30))
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#define rDBECONST_COLOR (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x34))
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#define rDBECRC_CTL (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x38))
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#define rDBECRCWINDOW (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x3C))
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#define rDBECRCRESULT (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x40))
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#define rDBEFIFO_CONFIG (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x44))
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#define rDBEFIFO_STATUS (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x48))
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#define rDBESPARE_CONFIG0 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x4C))
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#define rDBESPARE_CONFIG1 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x50))
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#define rDBESPARE_CONFIG2 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x54))
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#define rDBESPARE_CONFIG3 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x58))
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#define rDBESPARE_STATUS0 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x5C))
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#define rDBESPARE_STATUS1 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x60))
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#define rDBESPARE_STATUS2 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x64))
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#define rDBESPARE_STATUS3 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x68))
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#define rAAP_FORMAT_CONTROL_REG0 (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x0))
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#define rAAP_FORMAT_CONTROL_REG1 (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x4))
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#define AAP_FORMAT_CONTROL_REG1_AUTOSIZE (1 << 7)
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#define AAP_FORMAT_CONTROL_REG1_AUTOPOS (1 << 6)
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#define AAP_FORMAT_CONTROL_REG1_FCMODE(n) ((n & 0x3) << 4)
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#define AAP_FORMAT_CONTROL_REG1_RSVD(n) ((n & 0xf) << 2)
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#define AAP_FORMAT_CONTROL_REG1_VS_POL (1 << 1)
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#define AAP_FORMAT_CONTROL_REG1_HS_POL (1 << 0)
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#define rAAP_FORMAT_HS_POS_LSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x8))
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#define rAAP_FORMAT_HS_POS_MSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0xC))
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#define rAAP_FORMAT_FRAME_WIDTH_LSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x10))
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#define rAAP_FORMAT_FRAME_WIDTH_MSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x14))
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#define rAAP_FORMAT_FRAME_HEIGHT_LSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x18))
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#define rAAP_FORMAT_FRAME_HEIGHT_MSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x1C))
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#define rAAP_FORMAT_VS_POS_LSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x20))
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#define rAAP_FORMAT_VS_POS_MSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x24))
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#endif /* __ADBE_REGS_H */
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