285 lines
9.7 KiB
C
285 lines
9.7 KiB
C
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/*
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* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <drivers/apple/gpio.h>
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#include <platform/soc/hwregbase.h>
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#include <target.h>
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/* S5L8942X FPGA Pin Configuration */
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#define DFU_STATUS_DRIVE_STR DRIVE_X1
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#define FMI_DRIVE_STR DRIVE_X2
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static const u_int32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
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/* Port 0 */
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CFG_IN, // GPIO0 -> MENU_KEY (REQUEST_DFU2)
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CFG_IN, // GPIO1 -> HOLD_KEY (REQUEST_DFU1)
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CFG_DISABLED, // GPIO2 ->
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CFG_DISABLED, // GPIO3 ->
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CFG_DISABLED, // GPIO4 ->
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CFG_DISABLED, // GPIO5 ->
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CFG_DISABLED, // GPIO6 ->
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CFG_DISABLED, // GPIO7 ->
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/* Port 1 */
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CFG_OUT_1, // GPIO8 -> BT_EN
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CFG_IN, // GPIO9 -> BT_WAKE
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CFG_DISABLED, // GPIO10 ->
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CFG_IN, // GPIO11 -> LAN_HSIC_DEVICE_RDY
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CFG_DISABLED, // GPIO12 ->
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CFG_IN | PULL_UP, // GPIO13 -> PMU_IRQ_L
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CFG_DISABLED, // GPIO14 ->
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CFG_DISABLED, // GPIO15 ->
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/* Port 2 */
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CFG_IN | PULL_DOWN, // GPIO16 -> BOARD_ID[3]
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CFG_DISABLED, // GPIO17 ->
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CFG_IN | PULL_DOWN, // GPIO18 -> BOOT_CONFIG[0]
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CFG_OUT_0, // GPIO19 -> KEEPACT
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CFG_IN, // GPIO20 -> WLAN0_HSIC_DEVICE_READY
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CFG_IN, // GPIO21 -> USB_DEVMUX_SEL_C0
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CFG_IN, // GPIO22 -> USB_DEVMUX_SEL_C0
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CFG_DISABLED, // GPIO23 ->
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/* Port 3 */
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CFG_DISABLED, // GPIO24 ->
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CFG_IN | PULL_DOWN, // GPIO25 -> BOOT_CONFIG[1]
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CFG_IN | PULL_DOWN, // GPIO26 -> FORCE_DFU
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CFG_OUT_0 | DFU_STATUS_DRIVE_STR | PULL_DOWN, // GPIO27 -> DFU_STATUS
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CFG_IN | PULL_DOWN, // GPIO28 -> BOOT_CONFIG[2]
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CFG_IN | PULL_DOWN, // GPIO29 -> BOOT_CONFIG[3]
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CFG_DISABLED, // GPIO30 ->
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CFG_OUT, // GPIO31 -> WLAN0_HSIC_HOST_READY
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/* Port 4 */
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CFG_DISABLED, // GPIO32 ->
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CFG_DISABLED, // GPIO33 ->
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CFG_DISABLED, // GPIO34 ->
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CFG_IN, // GPIO35 -> LAN_PHY_INT
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CFG_DISABLED, // GPIO36 ->
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CFG_IN | PULL_DOWN, // EHCI_PORT_PWR[0] -> BOARD_REV[0]
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CFG_IN | PULL_DOWN, // EHCI_PORT_PWR[1] -> BOARD_REV[1]
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CFG_IN | PULL_DOWN, // EHCI_PORT_PWR[2] -> BOARD_REV[2]
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/* Port 5 */
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CFG_FUNC0, // UART1_TXD -> BT_UART_TXD
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CFG_FUNC0, // UART1_RXD -> BT_UART_RXD
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CFG_OUT_1, // UART1_RTSN -> BT_UART_RTSN
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CFG_FUNC0, // UART1_CTSN -> BT_UART_CTSN
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CFG_FUNC0, // UART2_TXD -> AP_UART2_TXD
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CFG_FUNC0, // UART2_RXD -> AP_UART2_RXD
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CFG_DISABLED, // UART2_RTSN ->
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CFG_DISABLED, // UART2_CTSN ->
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/* Port 6 */
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CFG_FUNC1, // UART3_TXD -> AP_SPDIF_OUT_1V8
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CFG_DISABLED, // UART3_RXD ->
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CFG_DISABLED, // UART3_RTSN ->
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CFG_DISABLED, // UART3_CTSN ->
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CFG_FUNC0, // I2C0_SDA -> I2C0_SDA_1V8
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CFG_FUNC0, // I2C0_SCL -> I2C0_SCL_1V8
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CFG_DISABLED, // I2C1_SDA ->
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CFG_DISABLED, // I2C1_SCL ->
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/* Port 7 */
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CFG_DISABLED, // ISP0_SDA ->
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CFG_DISABLED, // ISP0_SCL ->
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CFG_DISABLED, // ISP1_SDA ->
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CFG_DISABLED, // ISP1_SCL ->
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CFG_DISABLED, // UART5_TXD/MIPI_VSYNC ->
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CFG_IN | PULL_DOWN, // TMR32_PWM0 -> BOARD_REV[3]
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CFG_DISABLED, // TMR32_PWM1 -> IRRCVR_OUT_TO_AP_AMR_R
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CFG_DISABLED, // TMR32_PWM2
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/* Port 8 */
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CFG_FUNC0, // SWI_DATA -> SWI_AP
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CFG_DISABLED, // DWI_DI ->
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CFG_DISABLED, // DWI_DO ->
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CFG_DISABLED, // DWI_CLK ->
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CFG_DISABLED, // SENSOR0_RST ->
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CFG_DISABLED, // SENSOR0_CLK ->
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CFG_DISABLED, // SENSOR1_RST ->
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CFG_DISABLED, // SENSOR1_CLK ->
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/* Port 9 */
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CFG_DISABLED, // ISP0_PRE_FLASH ->
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CFG_DISABLED, // ISP0_FLASH ->
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CFG_DISABLED, // ISP1_PRE_FLASH ->
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CFG_DISABLED, // ISP1_FLASH ->
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CFG_DISABLED, // I2S0_MCK ->
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CFG_FUNC0, // I2S0_LRCK -> AP_I2S0_LRCK
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CFG_FUNC0, // I2S0_SCLK -> AP_I2S0_SCLK
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CFG_FUNC0, // I2S0_DOUT -> AP_I2S0_DOUT
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/* Port 10 */
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CFG_DISABLED, // I2S0_DIN ->
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CFG_DISABLED, // I2S1_MCK ->
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CFG_DISABLED, // I2S1_LRCK ->
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CFG_DISABLED, // I2S1_SCLK ->
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CFG_DISABLED, // I2S1_DOUT ->
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CFG_DISABLED, // I2S1_DIN ->
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CFG_DISABLED, // I2S2_MCK ->
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CFG_DISABLED, // I2S2_LRCK ->
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/* Port 11 */
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CFG_DISABLED, // I2S2_BCLK ->
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CFG_DISABLED, // I2S2_DOUT ->
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CFG_DISABLED, // I2S2_DIN ->
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CFG_DISABLED, // I2S2_MCK ->
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CFG_DISABLED, // I2S3_LRCK ->
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CFG_DISABLED, // I2S3_BCLK ->
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CFG_DISABLED, // I2S3_DOUT ->
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CFG_DISABLED, // I2S3_DIN ->
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/* Port 12 */
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CFG_IN | PULL_DOWN, // SPI0_SCLK -> BOARD_ID[0]
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CFG_IN | PULL_DOWN, // SPI0_MOSI -> BOARD_ID[1]
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CFG_IN | PULL_DOWN, // SPI0_MISO -> BOARD_ID[2]
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CFG_DISABLED | PULL_UP, // SPI0_SSIN ->
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CFG_DISABLED, // SPI1_SCLK ->
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CFG_DISABLED, // SPI1_MOSI ->
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CFG_DISABLED, // SPI1_MISO ->
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CFG_DISABLED, // SPI1_SSIN ->
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/* Port 13 */
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CFG_DISABLED, // SPI2_SCLK ->
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CFG_DISABLED, // SPI2_MOSI ->
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CFG_DISABLED, // SPI2_MISO ->
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CFG_DISABLED, // SPI2_SSIN ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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/* Port 14 */
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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/* Port 15 */
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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/* Port 16 */
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CFG_FUNC0, // UART4_TXD -> UART4_TXD
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CFG_FUNC0, // UART4_RXD -> UART4_RXD
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CFG_DISABLED, // UART4_RTSN ->
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CFG_DISABLED, // UART4_CTSN ->
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CFG_IN, // SDIO0_DATA3 -> AP_MCU_RESET
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CFG_IN, // SDIO0_DATA2 -> AP_MCU_INT
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CFG_OUT, // SDIO0_DATA1 -> PME_MODE_SEL
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CFG_IN, // SDIO0_DATA0 -> AP_MCU_TCK_3V0
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/* Port 17 */
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CFG_DISABLED, // SDIO0_CMD ->
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CFG_DISABLED, // SDIO0_CLK ->
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CFG_DISABLED, // FMI0_CEN3 ->
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CFG_DISABLED, // FMI0_CEN2 ->
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN1 -> FMI0_CEN1
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CEN0 -> FMI0_CEN0
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_CLE -> FMI0_CLE
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_ALE -> FMI0_ALE
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/* Port 18 */
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_REN -> FMI0_REN
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI0_WEN -> FMI0_WEN
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO7 -> FMI0_IO7
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO6 -> FMI0_IO6
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO5 -> FMI0_IO5
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO4 -> FMI0_IO4
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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/* Port 19 */
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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/* Port 20 */
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CFG_DISABLED | PULL_DOWN, // FMI0_DQS -> FMI0_DQS
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO3 -> FMI0_IO3
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO2 -> FMI0_IO2
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO1 -> FMI0_IO1
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI0_IO0 -> FMI0_IO0
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CFG_DISABLED, // FMI1_CEN3 ->
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CFG_DISABLED, // FMI1_CEN2 ->
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN1 -> FMI1_CEN1
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/* Port 21 */
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CEN0 -> FMI1_CEN0
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_CLE -> FMI1_CLE
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_ALE -> FMI1_ALE
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_REN -> FMI1_REN
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CFG_FUNC0 | FMI_DRIVE_STR, // FMI1_WEN -> FMI1_WEN
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO7 -> FMI1_IO7
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO6 -> FMI1_IO6
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO5 -> FMI1_IO5
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/* Port 22 */
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO4 -> FMI1_IO4
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CFG_DISABLED | PULL_DOWN, // FMI1_DQS -> FMI1_DQS
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO3 -> FMI1_IO3
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO2 -> FMI1_IO2
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO1 -> FMI1_IO1
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CFG_FUNC0 | BUS_HOLD | FMI_DRIVE_STR, // FMI1_IO0 -> FMI1_IO7
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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/* Port 23 */
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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/* Port 24 */
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CFG_FUNC0, // I2C2_SDA -> I2C2_SDA_3V0
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CFG_FUNC0, // I2C2_SCL -> I2C2_SCL_3V0
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CFG_FUNC0, // UART0_TXD -> AP_UART0_TXD
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CFG_FUNC0, // UART0_RXD -> AP_UART0_RXD
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CFG_FUNC0, // UART5_RTXD ->
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CFG_FUNC0, // DP_HPD ->
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CFG_DISABLED, // TST_CLKOUT ->
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CFG_DISABLED, // TST_STPCLK ->
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/* Port 25 */
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CFG_FUNC0, // WDOG -> AP_WDOG
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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CFG_DISABLED, // ->
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};
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const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
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{
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return gpio_default_cfg;
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}
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