254 lines
7.8 KiB
C
254 lines
7.8 KiB
C
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <stdint.h>
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#include <drivers/apple/gpio.h>
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#include <platform/soc/hwregbase.h>
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/* Default T7001 FPGA Pin Configuration - Capri I/O Spreadsheet v10.29 */
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static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
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/* Port 0 */
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CFG_IN, // MENU_KEY_L -> REQUEST_DFU2
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CFG_IN, // HOLD_KEY_L -> REQUEST_DFU1
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CFG_DISABLED, // ISP0_SDA ->
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CFG_DISABLED, // ISP0_SCL ->
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CFG_DISABLED, // ISP1_SDA ->
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CFG_DISABLED, // ISP1_SCL ->
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CFG_DISABLED, // SENSOR0_RST ->
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CFG_DISABLED, // SENSOR0_CLK ->
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/* Port 1 */
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CFG_DISABLED, // SENSOR0_XSHUTDOWN ->
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CFG_DISABLED, // SENSOR0_ISTRB ->
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CFG_DISABLED, // SENSOR1_RST ->
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CFG_DISABLED, // SENSOR1_CLK ->
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CFG_DISABLED, // SENSOR1_XSHUTDOWN ->
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CFG_DISABLED, // SENSOR1_ISTRB ->
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CFG_DISABLED, // UART3_TXD ->
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CFG_DISABLED, // UART3_RXD ->
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/* Port 2 */
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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/* Port 3 */
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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/* Port 4 */
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CFG_DISABLED, // UART3_RTSN ->
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CFG_DISABLED, // UART3_CTSN ->
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CFG_DISABLED, // UART5_RTXD ->
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CFG_DISABLED, // DWI0_DO ->
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CFG_DISABLED, // DWI0_CLK ->
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CFG_DISABLED, // I2C0_SDA ->
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CFG_DISABLED, // I2C0_SCL ->
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CFG_DISABLED, // I2S0_LRCK ->
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/* Port 5 */
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CFG_DISABLED, // I2S0_BCLK ->
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CFG_DISABLED, // I2S0_DOUT ->
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CFG_DISABLED, // I2S0_DIN ->
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CFG_DISABLED, // I2S1_MCK ->
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CFG_DISABLED, // I2S1_LRCK ->
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CFG_DISABLED, // I2S1_BCLK ->
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CFG_DISABLED, // I2S1_DOUT ->
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CFG_DISABLED, // I2S1_DIN ->
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/* Port 6 */
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CFG_DISABLED, // SPI3_MOSI ->
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CFG_DISABLED, // SPI3_MISO ->
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CFG_DISABLED, // SPI3_SCLK ->
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CFG_DISABLED, // SPI3_SSIN ->
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CFG_DISABLED, // TMR32_PWM0 ->
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CFG_DISABLED, // TMR32_PWM1 ->
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CFG_DISABLED, // TMR32_PWM2 ->
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CFG_DISABLED, // DISP_VSYNC ->
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/* Port 7 */
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CFG_FUNC0, // WDOG ->
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CFG_DISABLED, // SOCHOT0 ->
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CFG_DISABLED, // SOCHOT1 ->
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CFG_DISABLED, // CPU_SLEEP_STATUS ->
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CFG_DISABLED, // TST_CLKOUT ->
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CFG_DISABLED, // ISP_UART0_TXD ->
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CFG_DISABLED, // ISP_UART0_RXD ->
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CFG_DISABLED, // UART7_TXD ->
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/* Port 8 */
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CFG_DISABLED, // UART7_RXD ->
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CFG_DISABLED, // I2C1_SDA ->
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CFG_DISABLED, // I2C1_SCL ->
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CFG_FUNC0, // SPI0_SCLK -> BOARD_ID0
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CFG_FUNC0, // SPI0_MOSI -> BOARD_ID1
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CFG_FUNC0, // SPI0_MISO -> BOARD_ID2
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CFG_OUT_1, // SPI0_SSIN ->
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CFG_DISABLED, // I2S3_MCK ->
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/* Port 9 */
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CFG_DISABLED, // I2S3_LRCK ->
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CFG_DISABLED, // I2S3_BCLK ->
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CFG_DISABLED, // I2S3_DOUT ->
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CFG_DISABLED, // I2S3_DIN ->
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CFG_DISABLED, // UART4_TXD ->
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CFG_DISABLED, // UART4_RXD ->
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CFG_DISABLED, // UART4_RTSN ->
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CFG_DISABLED, // UART4_CTSN ->
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/* Port 10 */
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CFG_DISABLED, // GPIO0 ->
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CFG_DISABLED, // GPIO1 ->
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CFG_DISABLED, // GPIO2 ->
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CFG_DISABLED, // GPIO3 ->
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CFG_DISABLED, // GPIO4 ->
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CFG_DISABLED, // GPIO5 ->
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CFG_DISABLED, // GPIO6 ->
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CFG_DISABLED, // GPIO7 ->
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/* Port 11 */
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CFG_DISABLED, // GPIO8 ->
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CFG_DISABLED, // GPIO9 ->
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CFG_DISABLED, // GPIO10 ->
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CFG_DISABLED, // GPIO11 ->
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CFG_DISABLED, // GPIO12 ->
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CFG_DISABLED, // GPIO13 ->
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CFG_DISABLED, // GPIO14 ->
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CFG_DISABLED, // GPIO15 ->
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/* Port 12 */
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CFG_DISABLED, // GPIO16 -> BOARD_ID3
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CFG_DISABLED, // GPIO17 ->
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CFG_DISABLED, // GPIO18 -> BOOT_CONFIG0
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CFG_DISABLED, // GPIO19 ->
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CFG_DISABLED, // GPIO20 ->
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CFG_DISABLED, // GPIO21 ->
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CFG_DISABLED, // GPIO22 ->
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CFG_DISABLED, // GPIO23 ->
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/* Port 13 */
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CFG_DISABLED, // GPIO24 ->
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CFG_DISABLED, // GPIO25 -> BOOT_CONFIG1
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CFG_IN, // GPIO26 -> FORCE_DFU
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CFG_DISABLED, // GPIO27 -> DFU_STATUS
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CFG_DISABLED, // GPIO28 -> BOOT_CONFIG2
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CFG_DISABLED, // GPIO29 -> BOARD_ID4
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CFG_DISABLED, // GPIO30 ->
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CFG_DISABLED, // GPIO31 -> BOOT_CONFIG3
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/* Port 14 */
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CFG_DISABLED, // GPIO32 ->
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CFG_DISABLED, // GPIO33 ->
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CFG_DISABLED, // GPIO34 ->
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CFG_DISABLED, // GPIO35 ->
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CFG_DISABLED, // GPIO36 ->
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CFG_DISABLED, // GPIO37 ->
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CFG_DISABLED, // SPI2_SCLK ->
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CFG_DISABLED, // SPI2_MOSI ->
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/* Port 15 */
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CFG_DISABLED, // SPI2_MISO ->
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CFG_DISABLED, // SPI2_SSIN ->
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CFG_DISABLED, // UART8_TXD ->
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CFG_DISABLED, // UART8_RXD ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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CFG_DISABLED, // NULL ->
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/* Port 16 */
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CFG_FUNC0, // UART0_TXD ->
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CFG_FUNC0, // UART0_RXD ->
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CFG_DISABLED, // UART6_TXD ->
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CFG_DISABLED, // UART6_RXD ->
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CFG_DISABLED, // I2C2_SDA ->
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CFG_DISABLED, // I2C2_SCL ->
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CFG_DISABLED, // I2C3_SDA ->
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CFG_DISABLED, // I2C3_SCL ->
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/* Port 17 */
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CFG_DISABLED, // UART2_TXD ->
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CFG_DISABLED, // UART2_RXD ->
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CFG_DISABLED, // UART2_RTSN ->
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CFG_DISABLED, // UART2_CTSN ->
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CFG_DISABLED, // UART1_TXD ->
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CFG_DISABLED, // UART1_RXD ->
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CFG_DISABLED, // UART1_RTSN ->
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CFG_DISABLED, // UART1_CTSN ->
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/* Port 18 */
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CFG_DISABLED, // EDP_HPD ->
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CFG_DISABLED, // I2S4_MCK ->
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CFG_DISABLED, // I2S4_LRCK ->
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CFG_DISABLED, // I2S4_BCLK ->
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CFG_DISABLED, // I2S4_DOUT ->
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CFG_DISABLED, // I2S4_DIN ->
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CFG_DISABLED, // I2S2_LRCK ->
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CFG_DISABLED, // I2S2_BCLK ->
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/* Port 19 */
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CFG_DISABLED, // I2S2_DOUT ->
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CFG_DISABLED, // I2S2_DIN ->
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CFG_DISABLED, // SPI1_SCLK ->
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CFG_DISABLED, // SPI1_MOSI ->
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CFG_DISABLED, // SPI1_MISO ->
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CFG_DISABLED, // SPI1_SSIN ->
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CFG_DISABLED, // CLK32K_OUT ->
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CFG_DISABLED, // ULPI_DIR ->
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/* Port 20 */
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CFG_DISABLED, // ULPI_STP ->
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CFG_DISABLED, // ULPI_NXT ->
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CFG_DISABLED, // ULPI_DATA7 ->
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CFG_DISABLED, // ULPI_DATA6 ->
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CFG_DISABLED, // ULPI_DATA5 ->
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CFG_DISABLED, // ULPI_DATA4 ->
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CFG_DISABLED, // ULPI_CLK ->
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CFG_DISABLED, // ULPI_DATA3 ->
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/* Port 21 */
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CFG_DISABLED, // ULPI_DATA2 ->
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CFG_DISABLED, // ULPI_DATA1 ->
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CFG_DISABLED, // ULPI_DATA0 ->
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CFG_DISABLED, // DWI1_DO ->
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CFG_DISABLED, // DWI1_CLK ->
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CFG_DISABLED, // PCIE_CLKREQ0_N ->
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CFG_DISABLED, // PCIE_CLKREQ1_N ->
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CFG_DISABLED, // PCIE_CLKREQ2_N ->
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/* Port 22 */
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CFG_DISABLED, // PCIE_CLKREQ3_N ->
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CFG_DISABLED, // NAND_SYS_CLK ->
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CFG_DISABLED, // PCIE_PERST0_N ->
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CFG_DISABLED, // PCIE_PERST1_N ->
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CFG_DISABLED, // PCIE_PERST2_N ->
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CFG_DISABLED, // PCIE_PERST3_N ->
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CFG_DISABLED, // I2S0_MCK ->
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CFG_DISABLED, // I2S2_MCK ->
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};
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const uint32_t *target_get_default_gpio_cfg(uint32_t gpioc)
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{
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return gpio_default_cfg;
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}
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