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@@ -0,0 +1,64 @@
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/*
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* Copyright (C) 2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/display.h>
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#include <platform/gpiodef.h>
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#include <lib/syscfg.h>
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#include <platform.h>
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#include <platform/soc/chipid.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/hwregbase.h>
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#include <drivers/dither.h>
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#include <drivers/dpb.h>
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#include <drivers/wpc.h>
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#include <drivers/prc.h>
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#include <drivers/adbe/adbe.h>
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void adbe_enable_clocks(bool enable)
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{
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int device;
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if (ADBE_DISPLAYPIPE_BASE_ADDR == DISP0_BASE_ADDR)
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device = CLK_DISP0;
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#ifdef DISP1_BASE_ADDR
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else
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device = CLK_DISP1;
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#endif //DISP1_BASE_ADDR
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if (enable)
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clock_gate(device, true);
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else
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clock_gate(device, false);
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}
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void adbe_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl)
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{
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RELEASE_ASSERT(red_lut != NULL);
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RELEASE_ASSERT(green_lut != NULL);
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RELEASE_ASSERT(blue_lut != NULL);
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RELEASE_ASSERT(wpcl != NULL);
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#ifdef WITH_DPB
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//gamma correction is done in the dpb block
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dpb_install_gamma_table(red_lut, green_lut, blue_lut, wpcl);
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#endif
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#ifdef WITH_WPC
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//gamma correction is done in the wpc block
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wpc_install_gamma_table(red_lut, green_lut, blue_lut, wpcl);
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#endif
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#ifdef WITH_PRC
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//gamma correction is done in the prc block
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prc_install_gamma_table(red_lut, green_lut, blue_lut, wpcl);
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#endif
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}
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@@ -0,0 +1,97 @@
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/*
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* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __ADBE_REGS_H
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#define __ADBE_REGS_H
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#include <platform/soc/hwregbase.h>
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#define rDBEMODECNTL (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x4))
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#define DBEMODECNTL_ENABLE (1 << 31)
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#define DBEMODECNTL_PRE_CSC_LUT_ENABLE (1 << 30)
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#define DBEMODECNTL_CSC_ENABLE (1 << 29)
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#define DBEMODECNTL_POST_CSC_LUT_ENABLE (1 << 28)
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#define DBEMODECNTL_AAP_ENABLE (1 << 27)
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#define DBEMODECNTL_DPB_ENABLE (1 << 26)
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#define DBEMODECNTL_BN_DITHER_ENABLE (1 << 25)
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#define DBEMODECNTL_ST_DITHER_ENABLE (1 << 24)
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#define DBEMODECNTL_DYN_CLK_GATE_ENABLE (1 << 23)
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#define DBEMODECNTL_AFC_TEARDOWN_ENABLE (1 << 22)
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#define DBEMODECNTL_PMGR_CLK_GATE_ENABL (1 << 21)
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#define DBEMODECNTL_BLK_CLK_GATE_ENABLE (1 << 20)
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#define DBEMODECNTL_VSYNC_POLARITY (1 << 19)
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#define DBEMODECNTL_HSYNC_POLARITY (1 << 18)
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#define DBEMODECNTL_I_P_SELECT(x) (x << 16)
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#define DBEMODECNTL_UPDATE_ENABLE_TIMING (1 << 15)
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#define DBEMODECNTL_UPDATE_REQ_TIMING (1 << 14)
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#define DBEMODECNTL_CH2_SEL(x) (x << 12)
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#define DBEMODECNTL_CH1_SEL(x) (x << 10)
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#define DBEMODECNTL_CH0_SEL(x) (x << 8)
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#define DBEMODECNTL_CRC_ENABLE (1 << 7)
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#define DBEMODECNTL_CRC_MULTIFRAME_ENABLE (1 << 6)
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#define DBEMODECNTL_CRC_WINDOW_ENABLE (1 << 5)
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#define DBEMODECNTL_CRC_VALID (1 << 4)
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#define DBEMODECNTL_VFTG_STATUS (1 << 0)
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#define rDBECONSTCOLOR (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x8))
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#define rDBESCRNSZ (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0xC))
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#define rDBEFRONTPORCH (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x10))
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#define rDBESYNCPULSE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x14))
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#define rDBEBACKPORCH (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x18))
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#define rDBEVBLANKPOS (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x1C))
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#define rDBEVBLANKCLKGATE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x20))
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#define rDBEVBLANKIDLE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x24))
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#define rDBECRCWINDOW (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x28))
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#define rDBECRCRESULT (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x2C))
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//Only Alcatraz has the color manager on the back end. No need to generated a new driver just for it.
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#define rCM_DEGAMMA_RED(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x0400 + ((n) * 4)))
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#define rCM_DEGAMMA_GREEN(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x0800 + ((n) * 4)))
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#define rCM_DEGAMMA_BLUE(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x0c00 + ((n) * 4)))
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#define rCM_CSC_00 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1000)
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#define rCM_MATRIX_BASE(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1000 + ((n) * 4)))
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#define rCM_CSC_01 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1004))
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#define rCM_CSC_02 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1008))
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#define rCM_CSC_C0 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x100c))
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#define rCM_CSC_CI0 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1010))
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#define rCM_CSC_10 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1014))
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#define rCM_CSC_11 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1018))
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#define rCM_CSC_12 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x101c))
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#define rCM_CSC_C1 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1020))
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#define rCM_CSC_CI1 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1024))
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#define rCM_CSC_20 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1028))
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#define rCM_CSC_21 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1020))
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#define rCM_CSC_22 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1030))
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#define rCM_CSC_C2 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1034))
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#define rCM_CSC_CI2 (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1038))
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#define rCM_LUT_CTL (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x103c))
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#define CM_LUT_CTL (DISP_CM_BASE_ADDR + 0x103c)
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#define CM_LUT_CTL_UPDATE_ENABLE_ENG_BLUE (1 << 23)
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#define CM_LUT_CTL_UPDATE_REQ_ENG_BLUE (1 << 22)
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#define CM_LUT_CTL_BYPASS_ENG_BLUE (1 << 21)
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#define CM_LUT_CTL_UPDATE_ENABLE_DEG_BLUE (1 << 19)
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#define CM_LUT_CTL_UPDATE_REQ_DEG_BLUE (1 << 18)
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#define CM_LUT_CTL_BYPASS_DEG_BLUE (1 << 17)
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#define CM_LUT_CTL_UPDATE_ENABLE_ENG_GREEN (1 << 15)
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#define CM_LUT_CTL_UPDATE_REQ_ENG_GREEN (1 << 14)
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#define CM_LUT_CTL_BYPASS_ENG_GREEN (1 << 13)
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#define CM_LUT_CTL_UPDATE_ENABLE_DEG_GREEN (1 << 11)
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#define CM_LUT_CTL_UPDATE_REQ_DEG_GREEN (1 << 10)
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#define CM_LUT_CTL_BYPASS_DEG_GREEN (1 << 9)
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#define CM_LUT_CTL_UPDATE_ENABLE_ENG_RED (1 << 7)
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#define CM_LUT_CTL_UPDATE_REQ_ENG_RED (1 << 6)
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#define CM_LUT_CTL_BYPASS_ENG_RED (1 << 5)
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#define CM_LUT_CTL_UPDATE_ENABLE_DEG_RED (1 << 3)
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#define CM_LUT_CTL_UPDATE_REQ_DEG_RED (1 << 2)
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#define CM_LUT_CTL_BYPASS_DEG_RED (1 << 1)
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#define rCM_ENGAMMA_RED(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x1200 + ((n) * 4)))
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#define rCM_ENGAMMA_GREEN(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x2200 + ((n) * 4)))
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#define rCM_ENGAMMA_BLUE(n) (*(volatile u_int32_t *)(DISP_CM_BASE_ADDR + 0x3200 + ((n) * 4)))
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#endif /* __ADBE_REGS_H */
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@@ -0,0 +1,89 @@
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/*
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* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __ADBE_REGS_H
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#define __ADBE_REGS_H
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#include <platform/soc/hwregbase.h>
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#define rDBEMODECNTL (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x4))
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#define DBEMODECNTL_AAP_ENABLE (1 << 31)
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#define DBEMODECNTL_DPB_ENABLE (1 << 30)
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#define DBEMODECNTL_BN_DITHER_ENABLE (1 << 29)
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#define DBEMODECNTL_ST_DITHER_ENABLE (1 << 28)
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#define DBEMODECNTL_DPB_BUSY_MASK (1 << 23)
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#define DBEMODECNTL_PMGR_CLK_GATE_ENABLE (1 << 22)
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#define DBEMODECNTL_DYN_CLK_GATE_ENABLE (1 << 21)
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#define DBEMODECNTL_BLK_CLK_GATE_ENABLE (1 << 20)
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#define DBEMODECNTL_DITHER_ENABLE (1 << 28)
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#define DBEMODECNTL_PRC_ENABLE (1 << 27)
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#define DBEMODECNTL_WPC_ENABLE (1 << 26)
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#define rDBEVFTGCTL (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x8))
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#define DBEVFTGCT_VFTG_ENABLE (1 << 31)
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#define DBEVFTGCT_VFTG_STATUS (1 << 30)
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#define DBEVFTGCT_FRAME_COUNT_ENABLE (1 << 29)
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#define DBEVFTGCT_FRAME_COUNT_RESET (1 << 28)
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#define DBEVFTGCT_IDLE_FRAME_VBLANK_ENABLE (1 << 24)
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#define DBEVFTGCT_VSYNC_POLARITY(n) ((n) << 19)
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#define DBEVFTGCT_HSYNC_POLARITY(n) ((n) << 18)
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#define DBEVFTGCT_SCAN_SELECT(n) ((n) << 16)
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#define DBEVFTGCT_UPDATE_ENABLE_TIMING (1 << 15)
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#define DBEVFTGCT_UPDATE_REQ_TIMING (1 << 14)
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#define DBEVFTGCT_CH2_SEL(n) ((n) << 12)
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#define DBEVFTGCT_CH1_SEL(n) ((n) << 10)
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#define DBEVFTGCT_CH0_SEL(n) ((n) << 8)
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#define DBEVFTGCT_VERTICAL_STATUS(n) ((n) << 4)
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#define DBEVFTGCT_HORIZONTAL_STATUS(n) ((n) << 0)
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#define rDBESCRNSZ (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0xC))
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#define rDBEFRONTPORCH (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x10))
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#define rDBESYNCPULSE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x14))
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#define rDBEBACKPORCH (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x18))
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#define rDBECOUNTER_STATUS (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x1C))
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#define rDBECOUNTER_POSITION (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x20))
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#define rDBEVBLANK_POSITION (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x24))
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#define rDBEVBLANKCLKGATE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x28))
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#define rDBEVBLANKBUSY (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x2C))
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#define rDBEISR (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x30))
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#define rDBECONST_COLOR (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x34))
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#define rDBECRC_CTL (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x38))
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#define rDBECRCWINDOW (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x3C))
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#define rDBECRCRESULT (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x40))
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#define rDBEFIFO_CONFIG (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x44))
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#define rDBEFIFO_STATUS (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x48))
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#define rDBESPARE_CONFIG0 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x4C))
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#define rDBESPARE_CONFIG1 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x50))
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#define rDBESPARE_CONFIG2 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x54))
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#define rDBESPARE_CONFIG3 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x58))
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#define rDBESPARE_STATUS0 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x5C))
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#define rDBESPARE_STATUS1 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x60))
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#define rDBESPARE_STATUS2 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x64))
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#define rDBESPARE_STATUS3 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x68))
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#define rAAP_FORMAT_CONTROL_REG0 (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x0))
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#define rAAP_FORMAT_CONTROL_REG1 (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x4))
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#define AAP_FORMAT_CONTROL_REG1_AUTOSIZE (1 << 7)
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#define AAP_FORMAT_CONTROL_REG1_AUTOPOS (1 << 6)
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#define AAP_FORMAT_CONTROL_REG1_FCMODE(n) ((n & 0x3) << 4)
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#define AAP_FORMAT_CONTROL_REG1_RSVD(n) ((n & 0xf) << 2)
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#define AAP_FORMAT_CONTROL_REG1_VS_POL (1 << 1)
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#define AAP_FORMAT_CONTROL_REG1_HS_POL (1 << 0)
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#define rAAP_FORMAT_HS_POS_LSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x8))
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#define rAAP_FORMAT_HS_POS_MSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0xC))
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#define rAAP_FORMAT_FRAME_WIDTH_LSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x10))
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#define rAAP_FORMAT_FRAME_WIDTH_MSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x14))
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#define rAAP_FORMAT_FRAME_HEIGHT_LSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x18))
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#define rAAP_FORMAT_FRAME_HEIGHT_MSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x1C))
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#define rAAP_FORMAT_VS_POS_LSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x20))
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#define rAAP_FORMAT_VS_POS_MSB (*(volatile u_int32_t *)(DISP0_AAP_BASE_ADDR + 0x24))
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#endif /* __ADBE_REGS_H */
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@@ -0,0 +1,153 @@
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/*
|
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* Copyright (C) 2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
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#ifndef __ADBE_REGS_V3_H
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#define __ADBE_REGS_V3_H
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#define rADBE_VERSION (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0000))
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#define rADBE_NRT_CTL (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0004))
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#define ADBE_NRT_CTL_VFTG_MODE_COMMAND (1 << 25)
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#define ADBE_NRT_CTL_TE_ENABLE_SEL_SW (1 << 24)
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#define ADBE_NRT_CTL_TE_MODE_MASK (3 << 22)
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#define ADBE_NRT_CTL_TE_MODE_IDLE (0 << 22)
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#define ADBE_NRT_CTL_TE_MODE_POS (1 << 22)
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#define ADBE_NRT_CTL_TE_MODE_NEG (2 << 22)
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#define ADBE_NRT_CTL_TE_MODE_TOGGLE (3 << 22)
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#define ADBE_NRT_CTL_AAP_ENABLE (1 << 21)
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#define ADBE_NRT_CTL_BN_DITHER_ENABLE (1 << 20)
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#define ADBE_NRT_CTL_ST_DITHER_ENABLE (1 << 19)
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#define ADBE_NRT_CTL_ADISP_CLK_GATE_ENABLE (1 << 18)
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#define ADBE_NRT_CTL_ADBE_CLK_GATE_ENABLE (1 << 17)
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#define ADBE_NRT_CTL_BLK_CLK_GATE_ENABLE (1 << 16)
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#define ADBE_NRT_CTL_VSYNC_POLARITY(n) ((n) << 9)
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#define ADBE_NRT_CTL_HSYNC_POLARITY(n) ((n) << 8)
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#define ADBE_NRT_CTL_SCAN_SELECT_PROG_NOCHG (0 << 6)
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#define ADBE_NRT_CTL_SCAN_SELECT_INT_ODD (1 << 6)
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#define ADBE_NRT_CTL_SCAN_SELECT_PROG_CHG (2 << 6)
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#define ADBE_NRT_CTL_SCAN_SELECT_INT_EVEN (3 << 6)
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#define ADBE_NRT_CTL_CH2_SEL_RED (0 << 4)
|
||||
#define ADBE_NRT_CTL_CH2_SEL_GREEN (1 << 4)
|
||||
#define ADBE_NRT_CTL_CH2_SEL_BLUE (2 << 4)
|
||||
#define ADBE_NRT_CTL_CH2_SEL_CONST (3 << 4)
|
||||
#define ADBE_NRT_CTL_CH1_SEL_RED (0 << 2)
|
||||
#define ADBE_NRT_CTL_CH1_SEL_GREEN (1 << 2)
|
||||
#define ADBE_NRT_CTL_CH1_SEL_BLUE (2 << 2)
|
||||
#define ADBE_NRT_CTL_CH1_SEL_CONST (3 << 2)
|
||||
#define ADBE_NRT_CTL_CH0_SEL_RED (0 << 0)
|
||||
#define ADBE_NRT_CTL_CH0_SEL_GREEN (1 << 0)
|
||||
#define ADBE_NRT_CTL_CH0_SEL_BLUE (2 << 0)
|
||||
#define ADBE_NRT_CTL_CH0_SEL_CONST (3 << 0)
|
||||
|
||||
#define rADBE_RT_CTL (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0008))
|
||||
#define ADBE_RT_CTL_VFTG_STATUS_EN (1 << 16)
|
||||
#define ADBE_RT_CTL_VERTICAL_STATUS_IDLE (0 << 12)
|
||||
#define ADBE_RT_CTL_VERTICAL_STATUS_ACTIVE (8 << 12)
|
||||
#define ADBE_RT_CTL_VERTICAL_STATUS_FRONT (4 << 12)
|
||||
#define ADBE_RT_CTL_VERTICAL_STATUS_SYNC (2 << 12)
|
||||
#define ADBE_RT_CTL_VERTICAL_STATUS_BACK (1 << 12)
|
||||
#define ADBE_RT_CTL_HORIZONTAL_STATUS_IDLE (0 << 8)
|
||||
#define ADBE_RT_CTL_HORIZONTAL_STATUS_ACTIVE (8 << 8)
|
||||
#define ADBE_RT_CTL_HORIZONTAL_STATUS_FRONT (4 << 8)
|
||||
#define ADBE_RT_CTL_HORIZONTAL_STATUS_SYNC (2 << 8)
|
||||
#define ADBE_RT_CTL_HORIZONTAL_STATUS_BACK (1 << 8)
|
||||
#define ADBE_RT_CTL_VFTG_ENABLE_CMD_EN (1 << 5)
|
||||
#define ADBE_RT_CTL_VFTG_ENABLE_VID_EN (1 << 4)
|
||||
#define ADBE_RT_CTL_UPDATE_ENABLE_TIMING_READY (1 << 3)
|
||||
#define ADBE_RT_CTL_UPDATE_REQ_TIMING_NOSYNC (1 << 2)
|
||||
#define ADBE_RT_CTL_FRAME_COUNT_ENABLE (1 << 1)
|
||||
#define ADBE_RT_CTL_FRAME_COUNT_RESET_EN (1 << 0)
|
||||
|
||||
#define rADBE_ACTIVE_SIZE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x000c))
|
||||
#define ADBE_ACTIVE_SIZE_VERTICAL(n) ((n) << 16)
|
||||
#define ADBE_ACTIVE_SIZE_HORIZONTAL(n) ((n) << 0)
|
||||
|
||||
#define rADBE_FRONT_PORCH (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0010))
|
||||
#define ADBE_FRONT_PORCH_VERTICAL(n) ((n) << 16)
|
||||
#define ADBE_FRONT_PORCH_HORIZONTAL(n) ((n) << 0)
|
||||
|
||||
#define rADBE_SYNC_PULSE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0014))
|
||||
#define ADBE_SYNC_PULSE_VERTICAL(n) ((n) << 16)
|
||||
#define ADBE_SYNC_PULSE_HORIZONTAL(n) ((n) << 0)
|
||||
|
||||
#define rADBE_BACK_PORCH (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0018))
|
||||
#define ADBE_BACK_PORCH_VERTICAL(n) ((n) << 16)
|
||||
#define ADBE_BACK_PORCH_HORIZONTAL(n) ((n) << 0)
|
||||
|
||||
#define rADBE_COUNTER_STATUS (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x001c))
|
||||
#define ADBE_COUNTER_STATUS_FRAME_COUNTER(n) ((n) << 16)
|
||||
#define ADBE_COUNTER_STATUS_LINE_COUNTER(n) ((n) << 0)
|
||||
|
||||
#define rADBE_COUNTER_POSITION (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0020))
|
||||
#define ADBE_COUNTER_POSITION_FRAME_COUNTER(n) ((n) << 16)
|
||||
#define ADBE_COUNTER_POSITION_LINE_COUNTER(n) ((n) << 0)
|
||||
|
||||
#define rADBE_VBLANK_POSITION (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0024))
|
||||
#define ADBE_VBLANK_POSITION_FIELD_OUT(n) ((n) << 16)
|
||||
#define ADBE_VBLANK_POSITION_VBI_PULSE(n) ((n) << 0)
|
||||
|
||||
#define rADBE_VBLANK_CLK_GATE (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0028))
|
||||
#define ADBE_VBLANK_CLK_GATE_WAKEUP(n) ((n) << 16)
|
||||
#define ADBE_VBLANK_CLK_GATE_IDLE(n) ((n) << 0)
|
||||
|
||||
#define rADBE_VBLANK_BUSY (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x002c))
|
||||
#define ADBE_VBLANK_BUSY_FINISH(n) ((n) << 16)
|
||||
#define ADBE_VBLANK_BUSY_START(n) ((n) << 0)
|
||||
|
||||
#define rADBE_INTERRUPT (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0030))
|
||||
#define ADBE_INTERRUPT_COUNTER_MASK (1 << 18)
|
||||
#define ADBE_INTERRUPT_VFTG_DOWN_MASK (1 << 17)
|
||||
#define ADBE_INTERRUPT_VBI_TE_MASK (1 << 16)
|
||||
#define ADBE_INTERRUPT_COUNTER_STATUS (1 << 2)
|
||||
#define ADBE_INTERRUPT_VFTG_DOWN_STATUS (1 << 1)
|
||||
#define ADBE_INTERRUPT_VBI_TE_STATUS (1 << 0 )
|
||||
|
||||
#define rADBE_CONST_COLOR (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0034))
|
||||
#define ADBE_CONST_COLOR_VALUE_CH2(n) ((n) << 20)
|
||||
#define ADBE_CONST_COLOR_VALUE_CH1(n) ((n) << 10)
|
||||
#define ADBE_CONST_COLOR_VALUE_CH0(n) ((n) << 0)
|
||||
|
||||
#define rADBE_CRC_CTL (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0038))
|
||||
#define ADBE_CRC_CTL_ENABLE (1 << 3)
|
||||
#define ADBE_CRC_CTL_MULTIFRAME_ENABLE (1 << 2)
|
||||
#define ADBE_CRC_CTL_WINDOW_ENABLE (1 << 1)
|
||||
#define ADBE_CRC_CTL_VALID (1 << 0)
|
||||
|
||||
#define rADBE_CRC_WINDOW (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x003c))
|
||||
#define ADBE_CRC_WINDOW_RIGHT ((n) << 16)
|
||||
#define ADBE_CRC_WINDOW_LEFT ((n) << 0)
|
||||
|
||||
#define rADBE_CRC_RESULT (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0040))
|
||||
|
||||
#define rADBE_FIFO_CONFIG (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0044))
|
||||
#define ADBE_FIFO_CONFIG_UNDERRUN_MODE_DEFAULT (0 << 30)
|
||||
#define ADBE_FIFO_CONFIG_UNDERRUN_MODE_NORMAL (1 << 30)
|
||||
#define ADBE_FIFO_CONFIG_UNDERRUN_MODE_FRAME (2 << 30)
|
||||
#define ADBE_FIFO_CONFIG_UNDERRUN_MODE_STICKY (3 << 30)
|
||||
#define ADBE_FIFO_CONFIG_UNDERRUN_CH2(n) ((n) << 20)
|
||||
#define ADBE_FIFO_CONFIG_UNDERRUN_CH1(n) ((n) << 10)
|
||||
#define ADBE_FIFO_CONFIG_UNDERRUN_CH0(n) ((n) << 0)
|
||||
|
||||
#define rADBE_FIFO_STATUS (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0048))
|
||||
#define ADBE_FIFO_STATUS_FULL (1 << 25)
|
||||
#define ADBE_FIFO_STATUS_EMPTY (1 << 24)
|
||||
#define ADBE_FIFO_STATUS_PUSH_COUNT_GRAY(n) ((n) << 12)
|
||||
#define ADBE_FIFO_STATUS_POP_COUNT_GRAY(n) ((n) << 0)
|
||||
|
||||
#define rADBE_SPARE_CONFIG0 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x004c))
|
||||
#define rADBE_SPARE_CONFIG1 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0050))
|
||||
#define rADBE_SPARE_CONFIG2 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0054))
|
||||
#define rADBE_SPARE_CONFIG3 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0058))
|
||||
|
||||
#define rADBE_SPARE_STATUS0 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x005c))
|
||||
#define rADBE_SPARE_STATUS1 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0060))
|
||||
#define rADBE_SPARE_STATUS2 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0064))
|
||||
#define rADBE_SPARE_STATUS3 (*(volatile u_int32_t *)(DISP0_ADBE_BASE_ADDR + 0x0068))
|
||||
#endif // __ADBE_REGS_V3_H
|
||||
@@ -0,0 +1,185 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include "adbe_regs_v1.h"
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/display.h>
|
||||
#include <lib/paint.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <drivers/dither.h>
|
||||
#include <drivers/dpb.h>
|
||||
#include <drivers/adbe/adbe.h>
|
||||
#include <lib/mib.h>
|
||||
|
||||
struct adbe_v1_tuneable {
|
||||
char *name;
|
||||
uint32_t adbe0_tunable_mode_ctrl;
|
||||
uint32_t adbe0_vblank_pos_vbi_pulse;
|
||||
uint32_t adbe0_vblank_clk_gate_wakeup;
|
||||
uint32_t adbe0_vblank_clk_gate_idle;
|
||||
uint32_t adbe0_vblank_blk_idle_dpb;
|
||||
uint32_t adbe0_vblank_blk_idle_aap;
|
||||
uint32_t adbe0_aap_support;
|
||||
};
|
||||
|
||||
#include <target/adbe_settings.h>
|
||||
|
||||
static struct adbe_v1_tuneable *adbe_tuneables_info;
|
||||
static const int32_t adbe_tuneables_list_size = sizeof(adbe_tuneables) / sizeof(struct adbe_v1_tuneable);
|
||||
|
||||
static void adbe_program_color_manager()
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t engamma_table_count = mib_get_u32(kMIBTargetDisplayCMEngammaTableCount);
|
||||
uint32_t degamma_table_count = mib_get_u32(kMIBTargetDisplayCMDegammaTableCount);
|
||||
uint32_t matrix_table_count = mib_get_u32(kMIBTargetDisplayCMMatrixTableCount);
|
||||
|
||||
if (engamma_table_count != 0 && degamma_table_count != 0 && matrix_table_count != 0) {
|
||||
const uint32_t * engamma_table_base = (const uint32_t *)mib_get_ptr(kMIBTargetDisplayCMEngammaTablePtr);
|
||||
const uint32_t * degamma_table_base = (const uint32_t *)mib_get_ptr(kMIBTargetDisplayCMDegammaTablePtr);
|
||||
const uint32_t * matrix_table_base = (const uint32_t *)mib_get_ptr(kMIBTargetDisplayCMMatrixTablePtr);
|
||||
|
||||
for (i = 0; i < degamma_table_count; i++) {
|
||||
rCM_DEGAMMA_RED(i) = degamma_table_base[i];
|
||||
rCM_DEGAMMA_GREEN(i) = degamma_table_base[i];
|
||||
rCM_DEGAMMA_BLUE(i) = degamma_table_base[i];
|
||||
}
|
||||
|
||||
for (i = 0; i < matrix_table_count; i++) {
|
||||
rCM_MATRIX_BASE(i) = matrix_table_base[i];
|
||||
}
|
||||
for (i = 0; i < engamma_table_count; i++) {
|
||||
rCM_ENGAMMA_RED(i) = engamma_table_base[i];
|
||||
rCM_ENGAMMA_GREEN(i) = engamma_table_base[i];
|
||||
rCM_ENGAMMA_BLUE(i) = engamma_table_base[i];
|
||||
}
|
||||
|
||||
|
||||
//enabe LUTs in the lut register
|
||||
rCM_LUT_CTL = CM_LUT_CTL_UPDATE_ENABLE_ENG_BLUE |
|
||||
CM_LUT_CTL_UPDATE_REQ_ENG_BLUE |
|
||||
CM_LUT_CTL_UPDATE_ENABLE_DEG_BLUE |
|
||||
CM_LUT_CTL_UPDATE_REQ_DEG_BLUE |
|
||||
CM_LUT_CTL_UPDATE_ENABLE_ENG_GREEN |
|
||||
CM_LUT_CTL_UPDATE_REQ_ENG_GREEN |
|
||||
CM_LUT_CTL_UPDATE_ENABLE_DEG_GREEN |
|
||||
CM_LUT_CTL_UPDATE_REQ_DEG_GREEN |
|
||||
CM_LUT_CTL_UPDATE_ENABLE_ENG_RED |
|
||||
CM_LUT_CTL_UPDATE_REQ_ENG_RED |
|
||||
CM_LUT_CTL_UPDATE_ENABLE_DEG_RED |
|
||||
CM_LUT_CTL_UPDATE_REQ_DEG_RED;
|
||||
}
|
||||
}
|
||||
|
||||
void adbe_init(struct display_timing *timing)
|
||||
{
|
||||
const char *env;
|
||||
int32_t cnt;
|
||||
|
||||
env = env_get("adbe-tunable");
|
||||
if (env == 0) env = "default";
|
||||
|
||||
for (cnt = 0; cnt < adbe_tuneables_list_size; cnt++) {
|
||||
if (strcmp(env, adbe_tuneables[cnt].name)) continue;
|
||||
|
||||
adbe_tuneables_info = adbe_tuneables + cnt;
|
||||
}
|
||||
if (adbe_tuneables_info == 0) {
|
||||
dprintf(DEBUG_INFO, "Failed to find adbe tunables info, bailing adbe_init()\n");
|
||||
return;
|
||||
}
|
||||
|
||||
rDBESCRNSZ = (timing->v_active << 16) | (timing->h_active << 0);
|
||||
rDBEFRONTPORCH = (timing->v_front_porch << 16) | (timing->h_front_porch << 0);
|
||||
rDBESYNCPULSE = (timing->v_pulse_width << 16) | (timing->h_pulse_width << 0);
|
||||
rDBEBACKPORCH = (timing->v_back_porch << 16) | (timing->h_back_porch << 0);
|
||||
|
||||
rDBEVBLANKPOS = adbe_tuneables_info->adbe0_vblank_pos_vbi_pulse;
|
||||
|
||||
#ifdef TARGET_ADBE0_VBLANK_POSITION
|
||||
rDBEVBLANKPOS |= TARGET_ADBE0_VBLANK_POSITION;
|
||||
#endif
|
||||
|
||||
adbe_tuneables_info->adbe0_vblank_clk_gate_wakeup = timing->v_back_porch + timing->v_front_porch + timing->v_pulse_width - 5;
|
||||
|
||||
rDBEVBLANKCLKGATE = ((adbe_tuneables_info->adbe0_vblank_clk_gate_wakeup << 16) | adbe_tuneables_info->adbe0_vblank_clk_gate_idle);
|
||||
rDBEVBLANKIDLE = ((adbe_tuneables_info->adbe0_vblank_blk_idle_dpb << 16) | adbe_tuneables_info->adbe0_vblank_blk_idle_aap);
|
||||
|
||||
//csc lut programming should occur here
|
||||
|
||||
//Set AAP
|
||||
rDBEMODECNTL |= (adbe_tuneables_info->adbe0_aap_support) ? DBEMODECNTL_AAP_ENABLE: 0;
|
||||
|
||||
#ifdef WITH_DPB
|
||||
// Need to enable block first in order to access its registers
|
||||
rDBEMODECNTL |= DBEMODECNTL_DPB_ENABLE;
|
||||
dpb_init();
|
||||
#endif
|
||||
|
||||
// Dither
|
||||
#ifdef WITH_HW_DITHER
|
||||
//Currently, no product uses BN on H6.
|
||||
uint8_t dither_type = DITHER_SPATIO_TEMPORAL;
|
||||
#ifdef TARGET_DITHER_TYPE
|
||||
dither_type = TARGET_DITHER_TYPE;
|
||||
#endif //TARGET_DITHER_TYPE
|
||||
|
||||
//Dithering gets enabled in this block, no need to call into dithering to enable
|
||||
//We need to enable to block to access their corresponding registers
|
||||
switch(dither_type) {
|
||||
case DITHER_SPATIO_TEMPORAL:
|
||||
rDBEMODECNTL |= DBEMODECNTL_ST_DITHER_ENABLE;
|
||||
break;
|
||||
case DITHER_BLUE_NOISE:
|
||||
rDBEMODECNTL |= DBEMODECNTL_BN_DITHER_ENABLE;
|
||||
break;
|
||||
case DITHER_NONE:
|
||||
default:
|
||||
rDBEMODECNTL &= ~(DBEMODECNTL_ST_DITHER_ENABLE | DBEMODECNTL_BN_DITHER_ENABLE);
|
||||
break;
|
||||
}
|
||||
|
||||
dither_init(timing->display_depth);
|
||||
#endif
|
||||
#ifdef TARGET_ENABLE_CM
|
||||
rDBEMODECNTL |= (DBEMODECNTL_PRE_CSC_LUT_ENABLE | DBEMODECNTL_CSC_ENABLE | DBEMODECNTL_POST_CSC_LUT_ENABLE);
|
||||
adbe_program_color_manager();
|
||||
|
||||
#endif
|
||||
|
||||
rDBEMODECNTL |= adbe_tuneables_info->adbe0_tunable_mode_ctrl;
|
||||
|
||||
// Radar <rdar://problem/13402498> J72dev2 - Innsbruck11A289 | Playing a video in full screen causes the screen to go blank
|
||||
// need to force an update to the timing before enabling the timing generator
|
||||
rDBEMODECNTL |= (DBEMODECNTL_UPDATE_ENABLE_TIMING | DBEMODECNTL_UPDATE_REQ_TIMING);
|
||||
}
|
||||
|
||||
void adbe_enable_timing_generator(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
rDBEMODECNTL |= DBEMODECNTL_ENABLE; // Enable VFTG
|
||||
while ((rDBEMODECNTL & DBEMODECNTL_VFTG_STATUS) == 0); // Wait for it to be enabled
|
||||
}
|
||||
else {
|
||||
rDBEMODECNTL &= ~DBEMODECNTL_ENABLE; // Enable VFTG
|
||||
while ((rDBEMODECNTL & DBEMODECNTL_VFTG_STATUS) == 1); // Wait for it to be disabled
|
||||
}
|
||||
}
|
||||
|
||||
bool adbe_get_enable_timing_generator(void)
|
||||
{
|
||||
return ((rDBEMODECNTL & DBEMODECNTL_ENABLE) == (uint32_t)DBEMODECNTL_ENABLE);
|
||||
}
|
||||
@@ -0,0 +1,166 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include "adbe_regs_v2.h"
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/display.h>
|
||||
#include <lib/paint.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <drivers/dither.h>
|
||||
#include <drivers/dpb.h>
|
||||
#include <drivers/wpc.h>
|
||||
#include <drivers/prc.h>
|
||||
#include <drivers/adbe/adbe.h>
|
||||
|
||||
struct adbe_v2_tuneable {
|
||||
char *name;
|
||||
uint32_t adbe0_tunable_mode_ctrl;
|
||||
uint32_t adbe0_vftgctl_idle_frame_vblank_enable;
|
||||
uint32_t adbe0_vblank_pos_vbi_pulse;
|
||||
uint32_t adbe0_vblank_clk_gate_wakeup;
|
||||
uint32_t adbe0_vblank_clk_gate_idle;
|
||||
uint32_t adbe0_vblank_busy_finish;
|
||||
uint32_t adbe0_aap_support;
|
||||
uint32_t adbe0_aap_format_control_reg1;
|
||||
};
|
||||
|
||||
#include <target/adbe_settings.h>
|
||||
|
||||
static struct adbe_v2_tuneable *adbe_tuneables_info;
|
||||
static const int32_t adbe_tuneables_list_size = sizeof(adbe_tuneables) / sizeof(struct adbe_v2_tuneable);
|
||||
|
||||
void adbe_init(struct display_timing *timing)
|
||||
{
|
||||
const char *env;
|
||||
int32_t cnt;
|
||||
|
||||
env = env_get("adbe-tunables");
|
||||
if (env == 0) env = "default";
|
||||
|
||||
for (cnt = 0; cnt < adbe_tuneables_list_size; cnt++) {
|
||||
if (strcmp(env, adbe_tuneables[cnt].name)) continue;
|
||||
|
||||
adbe_tuneables_info = adbe_tuneables + cnt;
|
||||
}
|
||||
if (adbe_tuneables_info == 0) {
|
||||
dprintf(DEBUG_INFO, "Failed to find adbe tunables info, bailing adbe_init()\n");
|
||||
return;
|
||||
}
|
||||
|
||||
rDBESCRNSZ = (timing->v_active << 16) | (timing->h_active << 0);
|
||||
rDBEFRONTPORCH = (timing->v_front_porch << 16) | (timing->h_front_porch << 0);
|
||||
rDBESYNCPULSE = (timing->v_pulse_width << 16) | (timing->h_pulse_width << 0);
|
||||
rDBEBACKPORCH = (timing->v_back_porch << 16) | (timing->h_back_porch << 0);
|
||||
|
||||
rDBEVFTGCTL |= (DBEVFTGCT_VSYNC_POLARITY(timing->neg_vsync) | DBEVFTGCT_HSYNC_POLARITY(timing->neg_hsync));
|
||||
rDBEVFTGCTL |= DBEVFTGCT_FRAME_COUNT_ENABLE | DBEVFTGCT_SCAN_SELECT(0x2);
|
||||
rDBEVFTGCTL |= adbe_tuneables_info->adbe0_vftgctl_idle_frame_vblank_enable ? DBEVFTGCT_IDLE_FRAME_VBLANK_ENABLE : 0 ;
|
||||
|
||||
rDBEVBLANK_POSITION = (rDBEVBLANK_POSITION & ~0xFFFF) | adbe_tuneables_info->adbe0_vblank_pos_vbi_pulse;
|
||||
|
||||
rDBEVBLANKCLKGATE = ((adbe_tuneables_info->adbe0_vblank_clk_gate_wakeup << 16) | adbe_tuneables_info->adbe0_vblank_clk_gate_idle);
|
||||
|
||||
rDBEVBLANKBUSY = (adbe_tuneables_info->adbe0_vblank_busy_finish << 16);
|
||||
|
||||
//csc lut programming should occur here
|
||||
|
||||
rAAP_FORMAT_CONTROL_REG1 = adbe_tuneables_info->adbe0_aap_format_control_reg1;
|
||||
|
||||
//Set AAP
|
||||
rDBEMODECNTL |= (adbe_tuneables_info->adbe0_aap_support) ? DBEMODECNTL_AAP_ENABLE: 0;
|
||||
|
||||
#ifdef WITH_DPB
|
||||
// Need to enable block first in order to access its registers
|
||||
rDBEMODECNTL |= DBEMODECNTL_DPB_ENABLE;
|
||||
#if DPB_VERSION < 2
|
||||
dpb_init();
|
||||
#else
|
||||
dpb_init(timing->h_active, timing->v_active);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef WITH_WPC
|
||||
// Need to enable block first in order to access its registers
|
||||
rDBEMODECNTL |= DBEMODECNTL_WPC_ENABLE;
|
||||
wpc_init(timing->h_active, timing->v_active);
|
||||
#endif
|
||||
|
||||
#ifdef WITH_PRC
|
||||
// Need to enable block first in order to access its registers
|
||||
rDBEMODECNTL |= DBEMODECNTL_PRC_ENABLE;
|
||||
prc_init(timing->h_active, timing->v_active);
|
||||
#endif
|
||||
|
||||
// Dither
|
||||
#if DITHER_VERSION < 4
|
||||
#ifdef WITH_HW_DITHER
|
||||
//Currently, no product uses BN on H6.
|
||||
uint8_t dither_type = DITHER_SPATIO_TEMPORAL;
|
||||
#ifdef TARGET_DITHER_TYPE
|
||||
dither_type = TARGET_DITHER_TYPE;
|
||||
#endif //TARGET_DITHER_TYPE
|
||||
//Dithering gets enabled in this block, no need to call into dithering to enable
|
||||
//We need to enable to block to access their corresponding registers
|
||||
switch(dither_type) {
|
||||
case DITHER_SPATIO_TEMPORAL:
|
||||
rDBEMODECNTL |= DBEMODECNTL_ST_DITHER_ENABLE;
|
||||
break;
|
||||
case DITHER_BLUE_NOISE:
|
||||
rDBEMODECNTL |= DBEMODECNTL_BN_DITHER_ENABLE;
|
||||
break;
|
||||
case DITHER_NONE:
|
||||
default:
|
||||
rDBEMODECNTL &= ~(DBEMODECNTL_ST_DITHER_ENABLE | DBEMODECNTL_BN_DITHER_ENABLE);
|
||||
break;
|
||||
}
|
||||
|
||||
dither_init(timing->display_depth);
|
||||
#endif
|
||||
|
||||
#else // DITHER_VERSION >= 4
|
||||
#ifdef WITH_HW_DITHER
|
||||
// Enable Dither Block
|
||||
rDBEMODECNTL |= DBEMODECNTL_DITHER_ENABLE;
|
||||
|
||||
dither_init(timing->h_active, timing->v_active, timing->display_depth);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
rDBEMODECNTL |= adbe_tuneables_info->adbe0_tunable_mode_ctrl;
|
||||
|
||||
rDBEFIFO_CONFIG = 0x400003ff;
|
||||
|
||||
//disable interrupts
|
||||
rDBEISR = ((1 << 18) | (1 << 17) | (1 << 16));
|
||||
|
||||
rDBEVFTGCTL |= (DBEVFTGCT_UPDATE_ENABLE_TIMING | DBEVFTGCT_UPDATE_REQ_TIMING);
|
||||
}
|
||||
|
||||
void adbe_enable_timing_generator(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
rDBEVFTGCTL |= DBEVFTGCT_VFTG_ENABLE; // Enable VFTG
|
||||
while ((rDBEVFTGCTL & DBEVFTGCT_VFTG_STATUS) == 0); // Wait for it to be enabled
|
||||
} else {
|
||||
rDBEVFTGCTL &= ~DBEVFTGCT_VFTG_ENABLE; // Disable VFTG
|
||||
while ((rDBEVFTGCTL & DBEVFTGCT_VFTG_STATUS) == DBEVFTGCT_VFTG_STATUS); // Wait for it to be disabled
|
||||
}
|
||||
}
|
||||
|
||||
bool adbe_get_enable_timing_generator(void)
|
||||
{
|
||||
return ((rDBEVFTGCTL & DBEVFTGCT_VFTG_ENABLE) == (uint32_t)DBEVFTGCT_VFTG_ENABLE);
|
||||
}
|
||||
@@ -0,0 +1,163 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include "adbe_regs_v3.h"
|
||||
|
||||
#include <debug.h>
|
||||
#include <drivers/display.h>
|
||||
#include <lib/paint.h>
|
||||
#include <platform/gpiodef.h>
|
||||
#include <lib/syscfg.h>
|
||||
#include <platform.h>
|
||||
#include <platform/soc/chipid.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <drivers/dither.h>
|
||||
#include <drivers/dpb.h>
|
||||
#include <drivers/adbe/adbe.h>
|
||||
|
||||
struct adbe_v3_tuneable {
|
||||
char *name;
|
||||
uint32_t adbe0_vblank_clk_gate_wakeup;
|
||||
uint32_t adbe0_vblank_clk_gate_idle;
|
||||
uint32_t adbe0_tunable_nrt_ctl;
|
||||
uint32_t adbe0_aap_support;
|
||||
};
|
||||
|
||||
#include <target/adbe_settings.h>
|
||||
|
||||
static bool is_video_mode = true;
|
||||
|
||||
static struct adbe_v3_tuneable *adbe_tuneables_info;
|
||||
static const int32_t adbe_tuneables_list_size = sizeof(adbe_tuneables) / sizeof(struct adbe_v3_tuneable);
|
||||
|
||||
void adbe_init(struct display_timing *timing)
|
||||
{
|
||||
const char *env;
|
||||
int32_t cnt;
|
||||
|
||||
env = env_get("adbe-tunable");
|
||||
if (env == 0) env = "default";
|
||||
|
||||
for (cnt = 0; cnt < adbe_tuneables_list_size; cnt++) {
|
||||
if (strcmp(env, adbe_tuneables[cnt].name)) continue;
|
||||
|
||||
adbe_tuneables_info = adbe_tuneables + cnt;
|
||||
}
|
||||
if (adbe_tuneables_info == 0) {
|
||||
dprintf(DEBUG_INFO, "Failed to find adbe tunables info, bailing adbe_init()\n");
|
||||
return;
|
||||
}
|
||||
|
||||
rADBE_ACTIVE_SIZE = ADBE_ACTIVE_SIZE_VERTICAL(timing->v_active) | ADBE_ACTIVE_SIZE_HORIZONTAL(timing->h_active);
|
||||
rADBE_FRONT_PORCH = ADBE_FRONT_PORCH_VERTICAL(timing->v_front_porch) | ADBE_FRONT_PORCH_HORIZONTAL(timing->h_front_porch );
|
||||
rADBE_SYNC_PULSE = ADBE_SYNC_PULSE_VERTICAL(timing->v_pulse_width) | ADBE_SYNC_PULSE_HORIZONTAL(timing->h_pulse_width);
|
||||
rADBE_BACK_PORCH = ADBE_BACK_PORCH_VERTICAL(timing->v_back_porch) | ADBE_BACK_PORCH_HORIZONTAL(timing->h_back_porch);
|
||||
|
||||
//rdar://16085315 Errata Samsung’s DSIM_MDRESOL.MainStandby register field description.
|
||||
rADBE_NRT_CTL &= ~ADBE_NRT_CTL_TE_MODE_MASK;
|
||||
rADBE_NRT_CTL |= (ADBE_NRT_CTL_VSYNC_POLARITY(timing->neg_vsync) | ADBE_NRT_CTL_HSYNC_POLARITY(timing->neg_hsync));
|
||||
rADBE_RT_CTL |= ADBE_RT_CTL_FRAME_COUNT_ENABLE;
|
||||
rADBE_NRT_CTL |= ADBE_NRT_CTL_SCAN_SELECT_PROG_CHG;
|
||||
|
||||
#ifdef TARGET_ADBE0_VBLANK_POSITION
|
||||
rADBE_VBLANK_POSITION = TARGET_ADBE0_VBLANK_POSITION;
|
||||
#endif
|
||||
adbe_tuneables_info->adbe0_vblank_clk_gate_wakeup = timing->v_back_porch + timing->v_front_porch + timing->v_pulse_width - 5;
|
||||
|
||||
rADBE_VBLANK_CLK_GATE =
|
||||
(ADBE_VBLANK_CLK_GATE_WAKEUP(adbe_tuneables_info->adbe0_vblank_clk_gate_wakeup) |
|
||||
adbe_tuneables_info->adbe0_vblank_clk_gate_idle);
|
||||
|
||||
//Set AAP
|
||||
rADBE_NRT_CTL |= (adbe_tuneables_info->adbe0_aap_support) ? ADBE_NRT_CTL_AAP_ENABLE: 0;
|
||||
|
||||
// Dither
|
||||
#ifdef WITH_HW_DITHER
|
||||
uint8_t dither_type = DITHER_SPATIO_TEMPORAL;
|
||||
#ifdef TARGET_DITHER_TYPE
|
||||
dither_type = TARGET_DITHER_TYPE;
|
||||
#endif //TARGET_DITHER_TYPE
|
||||
|
||||
//Dithering gets enabled in this block, no need to call into dithering to enable
|
||||
//We need to enable to block to access their corresponding registers
|
||||
switch(dither_type) {
|
||||
case DITHER_SPATIO_TEMPORAL:
|
||||
rADBE_NRT_CTL |= ADBE_NRT_CTL_ST_DITHER_ENABLE;
|
||||
break;
|
||||
case DITHER_BLUE_NOISE:
|
||||
rADBE_NRT_CTL |= ADBE_NRT_CTL_BN_DITHER_ENABLE;
|
||||
break;
|
||||
case DITHER_NONE:
|
||||
default:
|
||||
rADBE_NRT_CTL &= ~(ADBE_NRT_CTL_ST_DITHER_ENABLE | ADBE_NRT_CTL_BN_DITHER_ENABLE);
|
||||
break;
|
||||
}
|
||||
|
||||
dither_init(timing->display_depth);
|
||||
#endif
|
||||
|
||||
rADBE_NRT_CTL |= adbe_tuneables_info->adbe0_tunable_nrt_ctl;
|
||||
|
||||
//Underrun setup
|
||||
rADBE_FIFO_CONFIG = ADBE_FIFO_CONFIG_UNDERRUN_MODE_STICKY | ADBE_FIFO_CONFIG_UNDERRUN_CH0(0x3FF);
|
||||
|
||||
}
|
||||
|
||||
static void adbe_enable_timing_generator_v3_video_mode(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
rADBE_RT_CTL |= ADBE_RT_CTL_VFTG_ENABLE_VID_EN; // Enable VFTG
|
||||
while ((rADBE_RT_CTL & ADBE_RT_CTL_VFTG_STATUS_EN) == 0); // Wait for it to be enabled
|
||||
} else {
|
||||
rADBE_RT_CTL &= ~ADBE_RT_CTL_VFTG_ENABLE_VID_EN; // Disable VFTG
|
||||
while ((rADBE_RT_CTL & ADBE_RT_CTL_VFTG_STATUS_EN) == ADBE_RT_CTL_VFTG_STATUS_EN); // Wait for it to be disabled
|
||||
}
|
||||
}
|
||||
|
||||
static void adbe_enable_timing_generator_v3_command_mode(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
rADBE_RT_CTL |= ADBE_RT_CTL_VFTG_ENABLE_CMD_EN; // Enable VFTG
|
||||
while ((rADBE_RT_CTL & ADBE_RT_CTL_VFTG_STATUS_EN) == 0); // Wait for it to be enabled
|
||||
} else {
|
||||
rADBE_RT_CTL &= ~ADBE_RT_CTL_VFTG_ENABLE_CMD_EN; // Disable VFTG
|
||||
while ((rADBE_RT_CTL & ADBE_RT_CTL_VFTG_STATUS_EN) == ADBE_RT_CTL_VFTG_STATUS_EN); // Wait for it to be disabled
|
||||
}
|
||||
}
|
||||
|
||||
void adbe_enable_timing_generator(bool enable)
|
||||
{
|
||||
#ifdef TARGET_DISP_VIDEO_MODE
|
||||
is_video_mode = TARGET_DISP_VIDEO_MODE;
|
||||
#endif //TARGET_DISP_VIDEO_MODE
|
||||
|
||||
if (is_video_mode) {
|
||||
rADBE_RT_CTL |= (ADBE_RT_CTL_UPDATE_ENABLE_TIMING_READY | ADBE_RT_CTL_UPDATE_REQ_TIMING_NOSYNC);
|
||||
adbe_enable_timing_generator_v3_video_mode(enable);
|
||||
} else {
|
||||
rADBE_NRT_CTL |= ADBE_NRT_CTL_TE_MODE_POS | ADBE_NRT_CTL_VFTG_MODE_COMMAND | ADBE_NRT_CTL_TE_ENABLE_SEL_SW;
|
||||
rADBE_RT_CTL |= (ADBE_RT_CTL_UPDATE_ENABLE_TIMING_READY | ADBE_RT_CTL_UPDATE_REQ_TIMING_NOSYNC);
|
||||
adbe_enable_timing_generator_v3_command_mode(enable);
|
||||
}
|
||||
}
|
||||
|
||||
bool adbe_get_enable_timing_generator(void)
|
||||
{
|
||||
#ifdef TARGET_DISP_VIDEO_MODE
|
||||
is_video_mode = TARGET_DISP_VIDEO_MODE;
|
||||
#endif //TARGET_DISP_VIDEO_MODE
|
||||
|
||||
if (is_video_mode) {
|
||||
return ((rADBE_RT_CTL & ADBE_RT_CTL_VFTG_ENABLE_VID_EN) == (uint32_t)ADBE_RT_CTL_VFTG_ENABLE_VID_EN);
|
||||
} else {
|
||||
return ((rADBE_RT_CTL & ADBE_RT_CTL_VFTG_ENABLE_CMD_EN) == (uint32_t)ADBE_RT_CTL_VFTG_ENABLE_CMD_EN);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_BACKEND_H
|
||||
#define __APPLE_DISPLAY_BACKEND_H
|
||||
|
||||
void adbe_enable_clocks(bool enable);
|
||||
void adbe_init(struct display_timing *timing);
|
||||
void adbe_enable_timing_generator(bool enable);
|
||||
bool adbe_get_enable_timing_generator(void);
|
||||
void adbe_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl);
|
||||
|
||||
#endif /* __APPLE_DISPLAY_BACKEND_H */
|
||||
@@ -0,0 +1,27 @@
|
||||
# Copyright (C) 2012-2014 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DISPLAYPIPE_BASE_ADDR=ADBE_DISPLAYPIPE_BASE_ADDR \
|
||||
WITH_DBE_ADBE=1 \
|
||||
ADBE_VERSION=$(ADBE_VERSION)
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/adbe.o
|
||||
|
||||
ifeq ($(ADBE_VERSION),)
|
||||
$(error "ADBE_VERSION not set")
|
||||
else
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/adbe_v$(ADBE_VERSION).o
|
||||
endif
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
Reference in new issue
Block a user