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@@ -0,0 +1,325 @@
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/*
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* Copyright (C) 2009-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include "adfe_regs.h"
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#include <debug.h>
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#include <drivers/display.h>
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#include <lib/env.h>
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#include <lib/paint.h>
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#include <platform.h>
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#include <platform/chipid.h>
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#include <platform/clocks.h>
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#include <platform/int.h>
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#include <platform/memmap.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/hwisr.h>
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#include <sys.h>
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#include <sys/task.h>
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#include <drivers/adfe/adfe.h>
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/* Display Tunables structures */
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struct adfe_v1_tuneable {
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char *name;
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uint32_t disp_dpcclkcntl[2];
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uint32_t disp_dpbclklvl_clock_off_level[2];
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uint32_t disp_dpbclklvl_clock_on_level[2];
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uint32_t disp_dpusrcstrd[2];
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uint32_t disp_dpcqoscnfg[2];
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uint32_t disp_dpbqoslvl_med_watermark[2];
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uint32_t disp_dpbqoslvl_high_watermark[2];
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uint32_t disp_dpureqcfg[2];
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uint32_t disp_dpvreqcfg[2];
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uint32_t disp_dpvsrcstrd[2];
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uint32_t disp_dpcwbstrd[2];
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};
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#include <platform/soc/display.h>
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#ifndef DISP_VERSION
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#error DISP_VERSION undefined
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#endif
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static struct adfe_v1_tuneable *adfe_tuneables_info;
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static const int32_t adfe_tuneables_list_size = sizeof(adfe_tuneables) / sizeof(struct adfe_v1_tuneable);
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static void adfe_irq_handler(void *arg)
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{
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int which = (int)arg;
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dprintf(DEBUG_INFO, "adfe_irq_handler: DPCIRQ(%d) is 0x%x -- attempting to clear\n", which, rDPCIRQ);
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rDPCIRQ = rDPCIRQ;
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}
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void adfe_init(struct display_timing *timing)
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{
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const char *env;
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int32_t cnt;
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env = env_get("adfe-tunables");
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if (env == 0) env = "default";
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for (cnt = 0; cnt < adfe_tuneables_list_size; cnt++) {
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if (strcmp(env, adfe_tuneables[cnt].name)) continue;
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adfe_tuneables_info = adfe_tuneables + cnt;
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}
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if (adfe_tuneables_info == 0) {
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dprintf(DEBUG_INFO, "Failed to find adfe tunables info, bailing adfe_init()\n");
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return;
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}
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adfe_enable_error_handler();
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#if DISP_VERSION < 5
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// Turn on AutoMode
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rDPCPFDMA |= DPCPFDMA_AUTOMODE;
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// Set FIFO DMA Burst Size to 2 Words
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rDPCPFDMA = (rDPCPFDMA & ~DPCPFDMA_BURSTSIZE_MASK) | DPCPFDMA_BURSTSIZE_2WORDS;
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// Set FIFO DMA Water Mark to 0x400
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rDPCPFDMA = (rDPCPFDMA & ~DPCPFDMA_WATERMARK_MASK) | DPCPFDMA_WATERMARK(0x400);
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#else
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// Turn on AutoMode
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rDPCPFMODE = DPCPFMODE_AUTOEN;
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#endif
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// Set screen size
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rDPCSIZE = (timing->h_active << 16) | (timing->v_active << 0);
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// Set the blend layer clock gating on level based on which adfe
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#ifdef DISP0_BASE_ADDR
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if (DISPLAYPIPE_BASE_ADDR == DISP0_BASE_ADDR) {
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rDPBCLKLVL =
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adfe_tuneables_info->disp_dpbclklvl_clock_off_level[0] |
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adfe_tuneables_info->disp_dpbclklvl_clock_on_level[0];
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} else
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#endif
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#ifdef DISP1_BASE_ADDR
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if (DISPLAYPIPE_BASE_ADDR == DISP1_BASE_ADDR) {
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rDPBCLKLVL =
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adfe_tuneables_info->disp_dpbclklvl_clock_off_level[1] |
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adfe_tuneables_info->disp_dpbclklvl_clock_on_level[1];
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} else
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#endif
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panic("adfe_init: unsupported adfe_base_addr: %p", (void *)DISPLAYPIPE_BASE_ADDR);
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#if (DISP_VERSION < 3)
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// Set blend layer panic level to 0x90
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rDPBPANLVL = 0x90;
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// Enable memory panic for blender with 5000 cycle delay
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rDPCPANCNFG = DPCPANCNFG_PANENAB | DPCPANCNFG_PANBENAB | DPCPANCNFG_PANTIMER(5000);
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#else
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#ifdef DISP0_BASE_ADDR
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if (DISPLAYPIPE_BASE_ADDR == DISP0_BASE_ADDR) {
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// Set the blend QOS level
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rDPBQOSLVL =
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adfe_tuneables_info->disp_dpbqoslvl_med_watermark[0] |
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adfe_tuneables_info->disp_dpbqoslvl_high_watermark[0];
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// Enable memory panic
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rDPCQOSCNFG = adfe_tuneables_info->disp_dpcqoscnfg[0];
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} else
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#endif
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#ifdef DISP1_BASE_ADDR
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if (DISPLAYPIPE_BASE_ADDR == DISP1_BASE_ADDR) {
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// Set the blend QOS level
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rDPBQOSLVL =
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adfe_tuneables_info->disp_dpbqoslvl_med_watermark[1] |
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adfe_tuneables_info->disp_dpbqoslvl_high_watermark[1];
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// Enable memory panic
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rDPCQOSCNFG = adfe_tuneables_info->disp_dpcqoscnfg[1];
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} else
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#endif
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panic("adfe_init: unsupported adfe_base_addr: %p", (void *)DISPLAYPIPE_BASE_ADDR);
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// Set the CSC to pass through
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rDPBCSCCOEFR(0) = 0x1000;
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rDPBCSCCOEFG(1) = 0x1000;
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rDPBCSCCOEFB(2) = 0x1000;
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#endif
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#if 0
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// Enable clock gating but not in U0, U1 or V
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rDPCCLKCNTL = DPCCLKCNTL_GATEENAB;
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#endif
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#if (DISP_VERSION > 4)
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uint32_t i;
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#ifdef DISP0_BASE_ADDR
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if (DISPLAYPIPE_BASE_ADDR == DISP0_BASE_ADDR) {
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for (i = 0; i < 2; i ++) {
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rDPCWBSTRD(i) = adfe_tuneables_info->disp_dpcwbstrd[0];
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rDPUSRCSTRD(i) = adfe_tuneables_info->disp_dpusrcstrd[0];
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rDPUREQCFG(i) = (rDPUREQCFG(i) & DPUREQCFG_CACHEHINT_MASK) | adfe_tuneables_info->disp_dpureqcfg[0];
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}
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for (i = 0; i < 3; i ++) {
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rDPVREQCFG(i) = (rDPVREQCFG(i) & DPVREQCFG_CACHEHINT_MASK) | adfe_tuneables_info->disp_dpvreqcfg[0];
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rDPVSRCSTRD(i) = adfe_tuneables_info->disp_dpvsrcstrd[0];
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}
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rDPCCLKCNTL = adfe_tuneables_info->disp_dpcclkcntl[0];
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} else
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#endif
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#ifdef DISP1_BASE_ADDR
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if (DISPLAYPIPE_BASE_ADDR == DISP1_BASE_ADDR) {
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for (i = 0; i < 2; i ++) {
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rDPCWBSTRD(i) = adfe_tuneables_info->disp_dpcwbstrd[1];
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rDPUSRCSTRD(i) = adfe_tuneables_info->disp_dpusrcstrd[1];
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rDPUREQCFG(i) = (rDPUREQCFG(i) & DPUREQCFG_CACHEHINT_MASK) | adfe_tuneables_info->disp_dpureqcfg[1];
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}
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for (i = 0; i < 3; i ++) {
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rDPVREQCFG(i) = (rDPVREQCFG(i) & DPVREQCFG_CACHEHINT_MASK) | adfe_tuneables_info->disp_dpvreqcfg[1];
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rDPVSRCSTRD(i) = adfe_tuneables_info->disp_dpvsrcstrd[1];
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}
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rDPCCLKCNTL = adfe_tuneables_info->disp_dpcclkcntl[1];
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} else
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#endif
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panic("adfe_init: unsupported adfe_base_addr: %p", (void *)DISPLAYPIPE_BASE_ADDR);
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#endif
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// Set the blend pipe underrun color to red
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rDPBUNDRCNFG = (2 << 30) | (0x3FF << 20);
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}
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void adfe_set_ui_layer(u_int32_t layer, enum colorspace color, struct plane *plane0, struct plane *plane1,
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u_int32_t width, u_int32_t height)
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{
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uint32_t adfe_color;
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addr_t base;
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if (layer > 1) return;
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RELEASE_ASSERT(plane0 != NULL);
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base = (addr_t)(plane0->fb_virt);
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switch (color) {
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case CS_RGB565 :
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adfe_color = 4;
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break;
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case CS_RGB888 :
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adfe_color = 0;
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break;
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default:
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panic("unsupported color 0x%x", color);
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return;
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}
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// Set adfe color, no swap and linear frame buffer
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rDPUSRCFMT(layer) = (adfe_color << 8) | (0 << 4) | (1 << 0);
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// Set base address of this layer (lower 32 bits, in case of 64 bits address)
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rDPUSRCBASE(layer) = (uint32_t)(base);
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// Set stride bytes
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uint32_t rmw = rDPUSRCSTRD(layer);
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rmw &= ~DPUSRCSTRD_SRCSTRIDE_MASK;
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rmw |= (plane0->stride & DPUSRCSTRD_SRCSTRIDE_MASK);
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rDPUSRCSTRD(layer) = rmw;
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#if (DISP_VERSION >= 3)
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// Set the source scale region geometry
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rDPUSRCXY(layer) = 0;
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rDPUSRCWH(layer) = (width << 16) | (height << 0);
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// Set the destination frame geometry
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rDPUDSTXY(layer) = 0;
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rDPUDSTWH(layer) = (width << 16) | (height << 0);
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// Enable source active region 0
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rDPUSRCRGN(layer) = (1 << 0);
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#if (DISP_VERSION < 5)
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// No MMU for UI requests
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// This should not be done on DISP_VERSION >= 5, as it clears
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// HighAddr.
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rDPUMMUCNTL(layer) = 0;
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#endif
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// No scaling (init=0,0 step=1.0,1.0)
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rDPUDDAINITX(layer) = 0;
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rDPUDDAINITY(layer) = 0;
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rDPUDDASTEPX(layer) = 0x100000;
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rDPUDDASTEPY(layer) = 0x100000;
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#endif
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#if (DISP_VERSION > 4)
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rDPUMMUCNTL(layer) = ((base >> 32) & 0xf) << 4;
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#endif
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// Set first region for the requested window
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rDPUSRCSTRXY(layer, 0) = (0 << 16) | (0 << 0);
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rDPUSRCENDXY(layer, 0) = (width << 16) | (height << 0);
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// Set blend layer 1 to pass through layer 1
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rDPBLAY1CNFG = (0xFF << 24) | (0xFF << 16) | (2 << 8) | (2 << 0);
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#if (DISP_VERSION < 3)
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// Set first region enabled
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rDPUSRCRGNENAB(layer) = (1 << 0);
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// Set ui layer fifo on / off levels to 0x20 / 0x60
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rDPUCLKLVL(layer) = (0x20 << 16) | (0x60 << 0);
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// Set ui layer panic level to 0x20
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rDPUPANLVL(layer) = (0x20 << 0);
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#endif
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}
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void adfe_enable_error_handler(void)
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{
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#if (DISP_VERSION < 5)
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// Error handling not implemented before version 5.
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#else
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rDPCIRQENAB |= DPCIRQ_MSTRERR;
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install_int_handler(INT_DISP0, adfe_irq_handler, 0);
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unmask_int(INT_DISP0);
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#endif
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}
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void adfe_disable_error_handler(void)
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{
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#if (DISP_VERSION < 5)
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#else
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rDPCIRQENAB &= ~DPCIRQ_MSTRERR;
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mask_int(INT_DISP0);
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#endif
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}
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void adfe_set_background_color(u_int32_t color)
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{
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rDPBBACKCOLOR = color;
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}
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void adfe_activate_window(void)
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{
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u_int32_t layer = 0;
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if (layer > 1) return;
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// Enable the requested layer
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rDPCENAB |= (1 << (layer + 8));
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#if (DISP_VERSION > 4)
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// Enable VBI, its needed for AutoMode
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rDPCENAB |= (1 << 0);
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#endif
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}
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bool adfe_get_enable(void)
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{
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#if (DISP_VERSION < 5)
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return (rDPCPFDMA & DPCPFDMA_AUTOMODE) != 0;
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#else
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return (rDPCIRQENAB & DPCIRQ_MSTRERR) != 0;
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#endif
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}
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@@ -0,0 +1,172 @@
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/*
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* Copyright (C) 2009-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
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#ifndef __APPLE_DISPLAYPIPE_H
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#define __APPLE_DISPLAYPIPE_H
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#include <platform/soc/hwregbase.h>
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#define rDPCVERSION (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1018))
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#define rDPCSTATE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x101C))
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#define rDPCGO (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1020))
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#define rDPCRESTART (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1024))
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#define rDPCIRQENAB (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1028))
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#define DPCIRQ_MSTRERR (1<<11)
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#define rDPCIRQ (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x102C))
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#define rDPCSIZE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1030))
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#define rDPCFRMCNT (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1034))
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#define rDPCENAB (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1038))
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#if DISP_VERSION < 5
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#define rDPCPFTOP (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x103C))
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#endif
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#define rDPCPFSIZE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1040))
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#define rDPCPFSTAT (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1044))
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#define rDPCPFHEAD (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1048))
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#if DISP_VERSION < 5
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#define rDPCPFDMA (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104C))
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#define DPCPFDMA_AUTOMODE (1 << 4)
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#define DPCPFDMA_BURSTSIZE_1WORD (0 << 8)
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#define DPCPFDMA_BURSTSIZE_2WORDS (1 << 8)
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#define DPCPFDMA_BURSTSIZE_4WORDS (2 << 8)
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#define DPCPFDMA_BURSTSIZE_8WORDS (3 << 8)
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#define DPCPFDMA_BURSTSIZE_16WORDS (4 << 8)
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#define DPCPFDMA_BURSTSIZE_MASK (7 << 8)
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#define DPCPFDMA_WATERMARK(n) ((n) << 16)
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#define DPCPFDMA_WATERMARK_MASK (0x7FF << 16)
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#else
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#define rDPCPFMODE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104C))
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#define DPCPFMODE_WBEN (1 << 1)
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#define DPCPFMODE_AUTOEN (1 << 0)
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#endif
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#define rDPCPFFLUSH (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1050))
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#define rDPCCLKCNTL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1054))
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#define DPCCLKCNTL_FLOOR(n) ((n & 0xFFFF) << 16)
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#define DPCCLKCNTL_PIPE_ENABLE (1 << 12)
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#define DPCCLKCNTL_LB_ENABLE (1 << 8)
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#define DPCCLKCNTL_V_ENABLE (1 << 4)
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#define DPCCLKCNTL_GATEENAB (1 << 0)
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#define rDPCMEMACC (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1058))
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#if (DISP_VERSION < 3)
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#define rDPCPANCNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x105C))
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#define DPCPANCNFG_PANENAB (1 << 0)
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#define DPCPANCNFG_PANU0ENAB (1 << 8)
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#define DPCPANCNFG_PANU1ENAB (1 << 9)
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#define DPCPANCNFG_PANVENAB (1 << 10)
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#define DPCPANCNFG_PANBENAB (1 << 11)
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#define DPCPANCNFG_PANTIMER(n) ((n) << 16)
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#define DPCPANCNFG_PANTIMER_MASK (0xFFFF << 16)
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#else
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#define rDPCQOSCNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x105C))
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#define DPCQOSCNFG_QOS_ENABLE (1 << 0)
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||||
#define DPCQOSCNFG_UIFIFO_ENABLE (1 << 1)
|
||||
#define DPCQOSCNFG_VIDFIFO_ENABLE (1 << 2)
|
||||
#if (DISP_VERSION < 4)
|
||||
#define DPCQOSCNFG_QOS_OPTIMISTIC (1 << 3)
|
||||
#else
|
||||
#define DPCQOSCNFG_QOS_OPTIMISTIC (1 << 4)
|
||||
#endif
|
||||
#define DPCQOSCNFG_PIPE_ENABLE (1 << 8)
|
||||
#define DPCQOSCNFG_QOS_TIMER(n) ((n) << 16)
|
||||
#endif
|
||||
|
||||
#if (DISP_VERSION > 4)
|
||||
#define rDPCWBSTRD(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x4 * (n)) + 0x1068))
|
||||
#define DPCWBSTRD_DSTBURST_1BLOCK (0 << 0)
|
||||
#define DPCWBSTRD_DSTBURST_2BLOCKS (1 << 0)
|
||||
#define DPCWBSTRD_DSTBURST_4BLOCKS (2 << 0)
|
||||
#define DPCWBSTRD_DSTBURST_8BLOCKS (3 << 0)
|
||||
#define DPCWBSTRD_DSTBURST_MASK (3 << 0)
|
||||
#define DPCWBSTRD_DSTSTRIDE_MASK (~0x3F)
|
||||
#endif
|
||||
|
||||
#define rDPBBACKCOLOR (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x203C))
|
||||
#define rDPBLAY1CNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2040))
|
||||
#define rDPBLAY2CNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2044))
|
||||
#define rDPBLAY3CNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2048))
|
||||
#define rDPBCRCENAB (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x204C))
|
||||
#define rDPBCRCDATA (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2050))
|
||||
#define rDPBCRCSNAP (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2054))
|
||||
#define rDPBOUTSIZE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2058))
|
||||
#define rDPBCLKLVL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x205C))
|
||||
#define DPBCLKLVL_OFFLVL(n) ((n) << 0)
|
||||
#define DPBCLKLVL_ONLVL(n) ((n) << 16)
|
||||
#define rDPBUNDRCNFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2064))
|
||||
#if (DISP_VERSION < 3)
|
||||
#define rDPBPANLVL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2060))
|
||||
#else
|
||||
#define rDPBQOSLVL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2060))
|
||||
#define DPBQOSLVL_MED_WATERMARK(n) ((n) << 0)
|
||||
#define DPBQOSLVL_HIGH_WATERMARK(n) ((n) << 16)
|
||||
#define rDPBCSCCOEFR(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x4 * (n)) + 0x2068))
|
||||
#define rDPBCSCCOEFG(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x4 * (n)) + 0x2074))
|
||||
#define rDPBCSCCOEFB(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x4 * (n)) + 0x2080))
|
||||
#define rDPBCSCCOFFR (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x208C))
|
||||
#define rDPBCSCCOFFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2090))
|
||||
#define rDPBCSCCOFFB (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2094))
|
||||
#endif
|
||||
|
||||
#if (DISP_VERSION > 4)
|
||||
#define rDPVREQCFG(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x4 * (n)) + 0x3050))
|
||||
#define DPVREQCFG_REQ_CNT(_n) ((_n) & 0xFF)
|
||||
#define DPVREQCFG_CACHEHINT_MASK (7 << 8)
|
||||
#endif
|
||||
|
||||
#define rDPVSRCSTRD(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x4 * (n)) + 0x3088))
|
||||
#define DPVSRCSTRD_SRCBURST_1BLOCK (0 << 0)
|
||||
#define DPVSRCSTRD_SRCBURST_2BLOCKS (1 << 0)
|
||||
#define DPVSRCSTRD_SRCBURST_4BLOCKS (2 << 0)
|
||||
#define DPVSRCSTRD_SRCBURST_8BLOCKS (3 << 0)
|
||||
#define DPVSRCSTRD_SRCBURST_MASK (3 << 0)
|
||||
#define DPVSRCSTRD_SRCSTRIDE_MASK (~0x3F)
|
||||
|
||||
#if (DISP_VERSION > 4)
|
||||
#define rDPUREQCFG(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x403C))
|
||||
#define DPUREQCFG_REQ_CNT(_n) ((_n) & 0xFF)
|
||||
#define DPUREQCFG_CACHEHINT_MASK (7 << 8)
|
||||
#endif
|
||||
#define rDPUSRCFMT(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4040))
|
||||
#define rDPUSRCBASE(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4044))
|
||||
#define rDPUSRCSTRD(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4048))
|
||||
#define DPUSRCSTRD_SRCBURST_1BLOCK (0 << 0)
|
||||
#define DPUSRCSTRD_SRCBURST_2BLOCKS (1 << 0)
|
||||
#define DPUSRCSTRD_SRCBURST_4BLOCKS (2 << 0)
|
||||
#define DPUSRCSTRD_SRCBURST_8BLOCKS (3 << 0)
|
||||
#define DPUSRCSTRD_SRCBURST_MASK (3 << 0)
|
||||
#define DPUSRCSTRD_SRCSTRIDE_MASK (~0x3F)
|
||||
#if (DISP_VERSION < 3)
|
||||
#define rDPUSRCRGNENAB(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x404C))
|
||||
#define rDPUOUTSIZE(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4070))
|
||||
#define rDPUCLKLVL(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4074))
|
||||
#define rDPUPANLVL(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4078))
|
||||
#define rDPUSRCSTRXY(n, r) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4050 + (4 * (r))))
|
||||
#define rDPUSRCENDXY(n, r) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4060 + (4 * (r))))
|
||||
#else
|
||||
#define rDPUSRCXY(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x404C))
|
||||
#define rDPUSRCWH(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4050))
|
||||
#define rDPUDSTXY(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4054))
|
||||
#define rDPUDSTWH(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4058))
|
||||
#define rDPUSRCRGN(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x405C))
|
||||
#define rDPUSRCSTRXY(n, r) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4060 + (4 * (r))))
|
||||
#define rDPUSRCENDXY(n, r) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4070 + (4 * (r))))
|
||||
#define rDPUDDAINITX(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4080))
|
||||
#define rDPUDDAINITY(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4084))
|
||||
#define rDPUDDASTEPX(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4088))
|
||||
#define rDPUDDASTEPY(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x408C))
|
||||
#define rDPUMMUCNTL(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + (0x1000 * (n)) + 0x4090))
|
||||
#endif
|
||||
|
||||
#define rDPCPERFCNTL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x6008))
|
||||
#define rDPCPERFSTAT (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x600C))
|
||||
#define rDPCPERFCNFG(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x6010 + (4 * (n))))
|
||||
#define rDPCPERFDATA(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x6020 + (4 * (n))))
|
||||
#define rDPCPERFSNAP(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x6030 + (4 * (n))))
|
||||
|
||||
#endif /* ! __APPLE_DISPLAYPIPE_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_FRONTEND_H
|
||||
#define __APPLE_DISPLAY_FRONTEND_H
|
||||
|
||||
void adfe_init(struct display_timing *timing);
|
||||
void adfe_set_ui_layer(u_int32_t pixel_pipe, enum colorspace color, struct plane *plane0, struct plane *plane1, u_int32_t width, u_int32_t height);
|
||||
void adfe_enable_error_handler(void);
|
||||
void adfe_disable_error_handler(void);
|
||||
void adfe_set_background_color(u_int32_t color);
|
||||
void adfe_activate_window(void);
|
||||
bool adfe_get_enable(void);
|
||||
|
||||
#endif /* __APPLE_DISPLAY_FRONTEND_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (C) 2009-2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_DFE_ADFE=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/adfe.o
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
Reference in new issue
Block a user