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/*
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* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include "adfe_v2_regs.h"
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#include <debug.h>
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#include <drivers/display.h>
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#include <lib/env.h>
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#include <lib/paint.h>
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#include <platform.h>
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#include <platform/chipid.h>
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#include <platform/clocks.h>
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#include <platform/int.h>
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#include <platform/memmap.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/hwisr.h>
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#include <sys.h>
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#include <sys/task.h>
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#include <drivers/adfe_v2/adfe.h>
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#if TARGET_USES_GP_CM || TARGET_USES_BLEND_CM
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#include <target/display_gamma_tables.h>
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#endif //TARGET_USES_GP_CM || TARGET_USES_BLEND_CM
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#if WITH_SYSCFG
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#include <lib/syscfg.h>
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#endif
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#if WITH_DEVICETREE
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#include <lib/devicetree.h>
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#endif
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struct adfe_v2_tuneable {
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char *name;
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uint32_t disp_dpcclkcntl;
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uint32_t disp_dpcclklvl_clock_on_level;
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uint32_t disp_dpcclklvl_clock_off_level;
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uint32_t disp_dpcqoscfg;
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uint32_t disp_dpcqosylvl_yellow_off;
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uint32_t disp_dpcqosylvl_yellow_on;
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uint32_t disp_dpcqosrlvl_red_off;
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uint32_t disp_dpcqosrlvl_red_on;
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uint32_t disp_dpclinkdown;
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uint32_t disp_dpgpreqaggr;
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uint32_t disp_dpcafclkgate; //ADP_VERSION > 1
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uint32_t disp_dpcenab;
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};
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#include <platform/soc/display.h>
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#ifndef ADP_VERSION
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#error ADP_VERSION undefined
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#endif
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static void adfe_set_pixel_pipe_plane(u_int32_t pixel_pipe, u_int32_t plane_num, struct plane *plane);
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static void adfe_gp_gamut_adjustment(u_int32_t pixel_pipe);
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static void adfe_blend_gamut_adjustment(void);
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static uint8_t display_pipe;
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static uint8_t gen_pixel_pipe = 0;
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static struct adfe_v2_tuneable *adfe_tuneables_info;
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static const int32_t adfe_tuneables_list_size = sizeof(adfe_tuneables) / sizeof(struct adfe_v2_tuneable);
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static void adfe_irq_handler(void *arg)
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{
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int which = (int)arg;
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dprintf(DEBUG_INFO, "adfe_irq_handler: ADPCIRQ(%d) is 0x%x -- attempting to clear\n", which, rADPCIRQ);
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rADPCIRQ = rADPCIRQ;
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}
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void adfe_init(struct display_timing *timing)
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{
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const char *env;
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int32_t cnt;
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env = env_get("adfe-tunables");
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if (env == 0) env = "default";
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for (cnt = 0; cnt < adfe_tuneables_list_size; cnt++) {
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if (strcmp(env, adfe_tuneables[cnt].name)) continue;
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adfe_tuneables_info = adfe_tuneables + cnt;
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}
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if (adfe_tuneables_info == 0) {
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panic("Failed to find adfe tunables info, bailing adfe_init()\n");
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}
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display_pipe = 0;
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gen_pixel_pipe = 0;
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#ifdef DISP1_BASE_ADDR
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if (DISPLAYPIPE_BASE_ADDR == DISP1_BASE_ADDR) {
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display_pipe = 1;
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gen_pixel_pipe = 0;
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}
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#endif //DISP1_BASE_ADDR
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adfe_enable_error_handler();
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// Turn on AutoMode
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rADPCPFMODE = ADPCPFMODE_AUTOEN | ADPCPFMODE_VBIEN;
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// Set screen size
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rADPCFRAMESIZE = (timing->h_active << 16) | (timing->v_active << 0);
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// Set the pipes clock gating on level (generic to both pipes)
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rADPCCLKLVL = adfe_tuneables_info->disp_dpcclklvl_clock_off_level |
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adfe_tuneables_info->disp_dpcclklvl_clock_on_level;
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// Set the Memory QOS configuration
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rADPCQOSCFG = adfe_tuneables_info->disp_dpcqoscfg;
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//set output FIFO QOS Yellow level
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rADPCQOSYLVL = adfe_tuneables_info->disp_dpcqosylvl_yellow_on |
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adfe_tuneables_info->disp_dpcqosylvl_yellow_off;
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//set output FIFO QOS Red level
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rADPCQOSRLVL = adfe_tuneables_info->disp_dpcqosrlvl_red_on |
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adfe_tuneables_info->disp_dpcqosrlvl_red_off;
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rADPCCLKCNTL = adfe_tuneables_info->disp_dpcclkcntl;
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rADPCLINKDOWN = adfe_tuneables_info->disp_dpclinkdown;
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// Register added in Capri..
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#if ADP_VERSION > 1
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rADPCAFCLKGATE = adfe_tuneables_info->disp_dpcafclkgate;
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#endif
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// Disable CSC
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rADPCCRCCTRL = 0;
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}
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void adfe_set_axis_flip(uint32_t pixel_pipe, bool flipX, bool flipY)
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{
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rADPGPSRCFMT(pixel_pipe) |= ((!!flipX) << 2) | ((!!flipY) << 1);
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}
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// Algorithm provided by display team to do fixed point rounding.
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static uint64_t fixed_to_fixed( uint64_t in, int inprec, int outprec )
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{
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long long sval = *((long long *) &in);
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bool neg = sval < 0;
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if( neg ) sval = -sval;
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if( outprec < inprec ) {
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sval = ((sval >> (inprec - outprec - 1)) + 1) >> 1;
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} else {
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sval <<= outprec - inprec;
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}
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if( neg ) sval = -sval;
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return *((uint64_t *) &sval);
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}
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/*
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* The ADP has 2 Generic Pixel Pipes. These pipes process pixels from memory before entering the Blend Unit.
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* A Plane is a single contigous location in memory containing pixel information
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* No scaling of any component is required (i.e. DDAInitX/DDAInitY are equal to SrcX/SrcY, and all DDA steps are equal to 1).
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* The Scale Region is equal to the Destination Region.
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* All pixels in the scale region are also in an Active Region (ARGB formats only).
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* 2DSN is disabled (YCbCr 4:4:4 formats only).
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*/
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void adfe_set_ui_layer(u_int32_t pixel_pipe, enum colorspace color, struct plane *plane0, struct plane *plane1,
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u_int32_t width, u_int32_t height)
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{
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uint8_t num_planes;
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uint8_t pixel_size, pixel_fmt;
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uint8_t is_ARGB;
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uint32_t reg = 0;
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if (pixel_pipe > 1) return;
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switch(color) {
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case CS_RGB565 :
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is_ARGB = true;
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pixel_size = 2;
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pixel_fmt = 2;
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num_planes = 1;
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break;
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case CS_RGB888 :
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is_ARGB = true;
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pixel_size = 1;
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pixel_fmt = 1;
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num_planes = 1;
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break;
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case CS_ARGB8101010 :
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is_ARGB = true;
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pixel_size = 3;
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pixel_fmt = 0;
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num_planes = 2;
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break;
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default:
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return;
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}
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RELEASE_ASSERT(plane0 != NULL);
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if (num_planes > 1) RELEASE_ASSERT(plane1 != NULL);
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#if defined(__arm64__)
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rADPSMMU_BYPASS_ADDR = (((((addr_t)plane0->fb_virt) >> 32) & 0xF) << 8);
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#endif
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rADPSMMU_DIAG_BOGUS_ACCESS = 0x20ffff;
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rADPDART_DIAG_CONFIG = 0x100;
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rADPDART_DIAG_BOGUS_ACCESS = 0x20ffff;
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rADPDART_FETCH_REQ_CONFIG = 0xe0303;
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// Set displaypixel_pipe color, no swap and linear frame buffer
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reg = rADPGPSRCFMT(pixel_pipe);
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//clean up the fields we are about to set
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reg &= ~((0x3 << 26) | (0x3 << 24) | (1 << 22) | (1 << 21) | (1 << 20) | (0x1f << 4) | (1 << 0));
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reg |= (pixel_fmt << 26) | (pixel_size << 24) | ((num_planes - 1 ) << 22) | (is_ARGB << 21) | (0 << 4) | (1 << 0);
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rADPGPSRCFMT(pixel_pipe) = reg;
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adfe_set_pixel_pipe_plane(pixel_pipe, 0, plane0);
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if (num_planes > 1) {
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adfe_set_pixel_pipe_plane(pixel_pipe, 1, plane1);
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}
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// Enable source active region 0
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rADPGPSRCCFG(pixel_pipe) = (1 << 0);
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// Set the destination frame geometry
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rADPGPDSTXY(pixel_pipe) = 0;
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rADPGPDSTWH(pixel_pipe) = (width << 16) | (height << 0);
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//No Scale Mode
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rADPGPCFG(pixel_pipe) = ADPGPCFG_NO_SCALE;
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//Dithering off
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rADPGPNOISECFG(pixel_pipe) = 0;
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//No color Space Conversion
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rADPGPCSCCFG(pixel_pipe)= ADPGPCSCCFG_CSC_BYPASS;
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// No Color Management
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rADPGPCMCFG(pixel_pipe)= ADPGPCMCFG_CM_BYPASS;
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//Bypass Color space conversion
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rADPBCSCCFG = ADPBCSCCFG_CSCBYPASS;
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adfe_gp_gamut_adjustment(pixel_pipe);
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// Bypass Blend Color Management
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rADPBCMCFG = ADPBCMCFG_CMBYPASS;
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//Tunable
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rADPGPREQAGGR(pixel_pipe, 0) = adfe_tuneables_info->disp_dpgpreqaggr;
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rADPGPREQAGGR(pixel_pipe, 1) = adfe_tuneables_info->disp_dpgpreqaggr;
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//No Need for Blend
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#define BLEND_BYPASS 1
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#if BLEND_BYPASS
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rADPBCFG = ADPBCFG_BLEND_BYPASS;
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#endif //BLEND_BYPASS
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rADPBLAYCFG(pixel_pipe) = (1 << 4) | (pixel_pipe << 0);
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rADPBLAYCFG(1-pixel_pipe) = (0 << 4) | ((1-pixel_pipe) << 0);
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//rADPBBACKCOLOR = 0xf;
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adfe_blend_gamut_adjustment();
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}
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static void adfe_set_pixel_pipe_plane(u_int32_t pixel_pipe, u_int32_t plane_num, struct plane *plane)
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{
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// Set base address of this pixel_pipe (lower 32 bits, in case of 64 bits address)
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rADPGPSRCBASE(pixel_pipe, plane_num) = (uint32_t)plane->fb_virt;
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// Set burst size and stride bytes
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rADPGPSRCSTRD(pixel_pipe, plane_num) = plane->stride;
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// Set the source scale region geometry
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rADPGPSRCXY(pixel_pipe, plane_num) = 0;
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rADPGPSRCWH(pixel_pipe, plane_num) = (plane->width << 16) | (plane->height << 0);
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//Note that if the pipe is being used in No Scale or Scaler Bypass mode DdaInitX must equal SrcX
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rADPGPDDAINITX(pixel_pipe, plane_num) = 0;
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rADPGPDDASTEPX(pixel_pipe, plane_num) = 0x100000;
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//Note that if the pipe is being used in No Scale or Scaler Bypass mode DdaInitY must equal SrcY
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rADPGPDDAINITY(pixel_pipe, plane_num) = 0;
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rADPGPDDASTEPY(pixel_pipe, plane_num) = 0x100000;
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// Set first region for the requested window
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rADPGPSRCACTXY(pixel_pipe, plane_num) = (0 << 16) | (0 << 0);
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rADPGPSRCACTWH(pixel_pipe, plane_num) = (plane->width << 16) | (plane->height << 0);
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}
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void adfe_enable_error_handler(void)
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{
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rADPCIRQENAB |= ADPCIRQ_OUTUNDERIRQ;
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install_int_handler(INT_DISP0, adfe_irq_handler, 0);
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unmask_int(INT_DISP0);
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}
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void adfe_disable_error_handler(void)
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{
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rADPCIRQENAB &= ~ADPCIRQ_OUTUNDERIRQ;
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mask_int(INT_DISP0);
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}
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void adfe_set_background_color(u_int32_t color)
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{
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rADPBBACKCOLOR = color;
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}
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void adfe_activate_window(void)
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{
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if (gen_pixel_pipe > 1) return;
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//Set SID to bypass due to
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//<rdar://problem/13098516> SMMU Configuration Timing
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// Enable the requested generic pixel pipe
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rADPCENAB = adfe_tuneables_info->disp_dpcenab | ADPCENAB_SIDSEL_BYPASS | (1 << (gen_pixel_pipe * 4));
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}
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bool adfe_get_enable(void)
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{
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return (rADPCIRQENAB & ADPCIRQ_OUTUNDERIRQ) != 0;
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}
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static void adfe_blend_gamut_adjustment(void)
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{
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#if TARGET_USES_BLEND_CM
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#if WITH_SYSCFG
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struct primary_calibration_matrix {
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uint32_t version;
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uint32_t matrix[3][3];
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};
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struct primary_calibration_matrix pcm;
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if (syscfgCopyDataForTag('DPCl', (u_int8_t *)&pcm, sizeof(pcm)) > 0) {
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int row, col;
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//Program degamma LUT
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for (row = 0; row < ADP_CM_DEGAMMA_PAIRED_LUT_SIZE; row++) {
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rADPBDEGAMMATABLE(row) = target_blend_degamma_tables[row];
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}
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//Program Linear Degamma
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rADPBDEGAMMALINEAR = target_blend_degamma_tables[row];
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for(row = 0; row < 3; row ++) {
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for(col = 0; col < 3; col++) {
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// Convert from 8.24 to 4.12
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rADPBCMCOEF(row, col) = (uint32_t)(fixed_to_fixed( pcm.matrix[row][col], 24, 12 ) & 0xFFFF);
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}
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}
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for (row = 0; row < ADP_CM_ENGAMMA_PAIRED_LUT_SIZE; row++) {
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rADPBGAMMATABLE_R(row) = target_blend_engamma_tables[row];
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rADPBGAMMATABLE_G(row) = target_blend_engamma_tables[row];
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rADPBGAMMATABLE_B(row) = target_blend_engamma_tables[row];
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}
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rADPBGAMMALINEAR_R = target_blend_engamma_tables[row];
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rADPBGAMMALINEAR_G = target_blend_engamma_tables[row];
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rADPBGAMMALINEAR_B = target_blend_engamma_tables[row];
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// Turn off Blend Color Management Bypass
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rADPBCMCFG &= ~ADPBCMCFG_CMBYPASS;
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}
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#endif
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#endif
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}
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static void adfe_gp_gamut_adjustment(u_int32_t pixel_pipe)
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{
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#if TARGET_USES_GP_CM
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int col;
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int row;
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//Program degamma LUT
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for (row = 0; row < ADP_CM_DEGAMMA_PAIRED_LUT_SIZE; row++) {
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rADPGPDEGAMMATABLE(pixel_pipe, row) = target_gp_degamma_tables[row];
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}
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//Program Linear Degamma
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rADPGPDEGAMMALINEAR(pixel_pipe) = target_gp_degamma_tables[row];
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for(row = 0; row < 3; row ++ ) {
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for(col = 0; col < 3; col ++ ) {
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rADPGPCMCOEF(pixel_pipe, row, col) = target_gp_csc_matrix[row][col];
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}
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}
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for (row = 0; row < ADP_CM_ENGAMMA_PAIRED_LUT_SIZE; row++) {
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rADPGPGAMMATABLE(pixel_pipe, row) = target_gp_engamma_tables[row];
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}
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rADPGPGAMMALINEAR(pixel_pipe) = target_gp_engamma_tables[row];
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//Unbypass the gamut adjustment block
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rADPGPCMCFG(pixel_pipe) &= ~ADPGPCMCFG_CM_BYPASS;
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#endif //TARGET_USES_GP_CM
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}
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@@ -0,0 +1,206 @@
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/*
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||||
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
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||||
#ifndef __APPLE_DISPLAY_FRONTEND_REGS_H
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#define __APPLE_DISPLAY_FRONTEND_REGS_H
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#include <platform/soc/hwregbase.h>
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//General control registers
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#define rADPCSPARE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1000))
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#define rADPCVERSION (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1018))
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#define rADPCSTATE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x101c))
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#define rADPCGO (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1020))
|
||||
#define rADPCRESTART (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1024))
|
||||
#define rADPCIRQENAB (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1028))
|
||||
#define ADPCIRQ_WBPARTIRQ (1 << 14)
|
||||
#define ADPCIRQ_WBCMPLIRQ (1 << 13)
|
||||
#define ADPCIRQ_WRERRIRQ (1 << 12)
|
||||
#define ADPCIRQ_RDERRIRQ (1 << 1)
|
||||
#define ADPCIRQ_PFPROCIRQ (1 << 10)
|
||||
#define ADPCIRQ_PFOVERIRQ (1 << 9)
|
||||
#define ADPCIRQ_PFHDRIRQ (1 << 8)
|
||||
#define ADPCIRQ_PFEMPTYIRQ (1 << 7)
|
||||
#define ADPCIRQ_PFALIGNIRQ (1 << 6)
|
||||
#define ADPCIRQ_PFREPEATIRQ (1 << 5)
|
||||
#define ADPCIRQ_PFSYNCIRQ (1 << 4)
|
||||
#define ADPCIRQ_PFMISSIRQ (1 << 3)
|
||||
#define ADPCIRQ_PFUNDERIRQ (1 << 2)
|
||||
#define ADPCIRQ_OUTUNDERIRQ (1 << 1)
|
||||
#define ADPCIRQ_VBIIRQ (1 << 0)
|
||||
#define rADPCIRQ (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x102c))
|
||||
#define rADPCFRAMESIZE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1030))
|
||||
#define rADPCFRMCNT (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1034))
|
||||
#define rADPCENAB (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1038))
|
||||
#define ADPCENAB_IDEAL_ARB_ENAB (1 << 16)
|
||||
#define ADPCENAB_SIDSEL_BYPASS (1 << 12)
|
||||
#define rADPCPFSIZE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x103c))
|
||||
#define rADPCPFSTAT (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1040))
|
||||
#define rADPCPFHEAD (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1044))
|
||||
#define rADPCPFMODE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1048))
|
||||
#define ADPCPFMODE_AUTOEN (1 << 0)
|
||||
#define ADPCPFMODE_VBIEN (1 << 4)
|
||||
#define rADPCPFFLUSH (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104c))
|
||||
#define rADPCCLKCNTL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1050))
|
||||
#define ADPCCLKCNTL_FLOOR(n) ((n) << 16)
|
||||
#define ADPCCLKCNTL_PIPE_ENABLE (1 << 8)
|
||||
#define ADPCCLKCNTL_LB_ENABLE (1 << 4)
|
||||
#define ADPCCLKCNTL_PIO_GATE_ENABLE (1 << 3)
|
||||
#define ADPCCLKCNTL_STAT_GATE_ENABLE (1 << 2)
|
||||
#define ADPCCLKCNTL_EXT_GATE_ENABLE (1 << 1)
|
||||
#define ADPCCLKCNTL_DYN_GATE_ENABLE (1 << 0)
|
||||
#define rADPCCLKLVL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1054))
|
||||
#define ADPCCLKLVL_ONLVL(n) ((n) << 16)
|
||||
#define ADPCCLKLVL_OFFLVL(n) ((n) << 0)
|
||||
#define rADPCQOSCFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1058))
|
||||
#define ADPCQOSCFG_QOS_TIMER(n) ((n) << 16)
|
||||
#define ADPCQOSCFG_PIPE_ENABLE (1 << 8)
|
||||
#define ADPCQOSCFG_MINLVL_ENABLE (1 << 6)
|
||||
#define ADPCQOSCFG_MON_MODE (1 << 5)
|
||||
#define ADPCQOSCFG_MON_ENABLE (1 << 4)
|
||||
#define ADPCQOSCFG_QOS_ENABLE (1 << 0)
|
||||
#define rADPCQOSYLVL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x105c))
|
||||
#define ADPCQOSYLVL_YELLOW_OFF(n) ((n) << 16)
|
||||
#define ADPCQOSYLVL_YELLOW_ON(n) ((n) << 0)
|
||||
#define rADPCQOSRLVL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1060))
|
||||
#define ADPCQOSRLVL_RED_OFF(n) ((n) << 16)
|
||||
#define ADPCQOSRLVL_RED_ON(n) ((n) << 0)
|
||||
#define rADPCQOSGSNAP (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1064))
|
||||
#define rADPCQOSYSNAP (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1068))
|
||||
#define rADPCQOSRSNAP (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x106c))
|
||||
#define rADPCQOSMINLVLSNAP (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1070))
|
||||
#define rADPCCRCCTRL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1074))
|
||||
#define rADPCLINKDOWN (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1078))
|
||||
#define ADPCLINKDOWN_TEARDOWNNOSCL (1 << 8)
|
||||
#define ADPCLINKDOWN_TEARDOWNAGGR (1 << 4)
|
||||
#define ADPCLINKDOWN_TEARDOWNEN (1 << 0)
|
||||
#if ADP_VERSION > 1
|
||||
#define rADPCAFCLKGATE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x107C))
|
||||
#define ADPAFIDLECOUNT(n) ((n) << 16)
|
||||
#define ADPAFDYNCLKGATEEN (1 << 0)
|
||||
#endif
|
||||
#define rADPCPFTOP(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x10c0 + (4 * (n))))
|
||||
|
||||
//Blend Unit registers
|
||||
#define rADPBSPARE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2000))
|
||||
#define rADPBCFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2020))
|
||||
#define ADPBCFG_BLEND_BYPASS (1 << 0)
|
||||
#define rADPBBACKCOLOR (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2024))
|
||||
#define rADPBLAYCFG(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2028 + (4 * (n))))
|
||||
#define rADPBCRCDATA (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2030))
|
||||
#define rADPBCSCCFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2034))
|
||||
#define ADPBCSCCFG_CSCBYPASS (1 << 0)
|
||||
#define rADPBCSCINOFF(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2038 + (4 * (n))))
|
||||
#define rADPBCSCCOEF(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2044 + (12 * (p)) + (4 * (n))))
|
||||
#define rADPBCSCOUTOFF(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2068 + (4 * (n))))
|
||||
#define rADPBCMCFG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2074))
|
||||
#define ADPBCMCFG_CMBYPASS (1 << 0)
|
||||
#define rADPBDEGAMMALINEAR (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2078))
|
||||
#define rADPBCMCOEF(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x207c + (12 * (p)) + (4 * (n))))
|
||||
#define rADPBGAMMALINEAR (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x20a0))
|
||||
#define rADPBGAMMALINEAR_R (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x20a0))
|
||||
#define rADPBGAMMALINEAR_G (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x20a4))
|
||||
#define rADPBGAMMALINEAR_B (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x20a8))
|
||||
#define rADPBOUTFIFODEPTH (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x20ac))
|
||||
#define rADPBDEGAMMATABLE(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2200 + (4 * (n))))
|
||||
#define rADPBGAMMATABLE(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2800 + (4 * (n))))
|
||||
#define rADPBGAMMATABLE_R(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x2800 + (4 * (n))))
|
||||
#define rADPBGAMMATABLE_G(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x3000 + (4 * (n))))
|
||||
#define rADPBGAMMATABLE_B(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x3800 + (4 * (n))))
|
||||
|
||||
//Generic Pipe registers
|
||||
#define rADPGPSPARE(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4000 + ((p) * 0x2000)))
|
||||
#define rADPGPCFG(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4020 + ((p) * 0x2000)))
|
||||
#define ADPGPCFG_SCALE_BYPASS (1 << 4)
|
||||
#define ADPGPCFG_NO_SCALE (1 << 0)
|
||||
#define rADPGPREQAGGR(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4024 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define ADPGPREQARRG_CACHEHINT_MASK (0x0F0000)
|
||||
#define ADPGPREQAGGR_CACHEHINT(n) ((n) << 16)
|
||||
#define ADPGPREQAGGR_REQAGGRTHRESH(n) ((n) << 4)
|
||||
#define ADPGPREQARRG_OPPORTUNISMENAB (1 << 1)
|
||||
#define ADPGPREQAGGR_REQAGGRENAB (1 << 0)
|
||||
#define rADPGPSRCFMT(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x402c + ((p) * 0x2000)))
|
||||
#define rADPGPSRCBASE(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4030 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPSRCSTRD(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4038 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPSRCXY(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4040 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPSRCWH(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4048 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPDSTXY(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4050 + ((p) * 0x2000)))
|
||||
#define rADPGPDSTWH(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4054 + ((p) * 0x2000)))
|
||||
#define rADPGPTBEDGEALPHA(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4058 + ((p) * 0x2000)))
|
||||
#define rADPGPLREDGEALPHA(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x405c + ((p) * 0x2000)))
|
||||
#define rADPGPTCEDGEALPHA(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4060 + ((p) * 0x2000)))
|
||||
#define rADPGPBCEDGEALPHA(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4064 + ((p) * 0x2000)))
|
||||
#define rADPGPSRCCFG(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4068 + ((p) * 0x2000)))
|
||||
#define rADPGPSRCACTXY(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x406c + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPSRCACTWH(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x407c + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPNOISECFG(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x408c + ((p) * 0x2000)))
|
||||
#define rADPGPNOISELFSR(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4090 + ((p) * 0x2000)))
|
||||
#define rADPGPDDAINITX(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4094 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPDDASTEPX(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x409c + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPDDAINITY(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40a4 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPDDASTEPY(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40ac + ((p) * 0x2000) + (4 * (n))))
|
||||
|
||||
#define rADPGPCSCCFG(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40b4 + ((p) * 0x2000)))
|
||||
#define ADPGPCSCCFG_CSC_BYPASS (1 << 0)
|
||||
#define rADPGPCSCINOFF(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40b8 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPCSCCOEF(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40c4 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPCSCOUTOFF(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40e8 + ((p) * 0x2000) + (4 * (n))))
|
||||
|
||||
#define rADPGPCMCFG(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40f4 + ((p) * 0x2000)))
|
||||
#define ADPGPCMCFG_CM_BYPASS (1 << 0)
|
||||
#define rADPGPDEGAMMALINEAR(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40f8 + ((p) * 0x2000)))
|
||||
#define rADPGPCMCOEF(p, r, c) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x40fc + ((p) * 0x2000) + ((r) * 0xc) + (4 * (c))))
|
||||
|
||||
#define rADPGPGAMMALINEAR(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4120 + ((p) * 0x2000)))
|
||||
#define rADPGPCRCCTRL(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4124 + ((p) * 0x2000)))
|
||||
#define rADPGPCRCDATA(p) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4128 + ((p) * 0x2000)))
|
||||
#define rADPGPINVDDASTEPX(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x412c + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPDEGAMMATABLE(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4200 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPGAMMATABLE(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x4800 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPCOEFX(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x5000 + ((p) * 0x2000) + (4 * (n))))
|
||||
#define rADPGPCOEFY(p, n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x5800 + ((p) * 0x2000) + (4 * (n))))
|
||||
|
||||
//DP Noise RAM Registers
|
||||
#define rADPNOISEARRAY(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x8000 + (4 * (n)))
|
||||
|
||||
//DP Write Back Registers
|
||||
#define rADPWBSPARE (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9000))
|
||||
#define rADPWBBASE(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9020 + (4 * (n))))
|
||||
#define rADPWBSTRD(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9028 + (4 * (n))))
|
||||
#define rADPWBCNTL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9030))
|
||||
#define rADPWBCHROMADOWN (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9034))
|
||||
#define rADPWBLINECNT(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9038 + (4 * (n))))
|
||||
#define rADP_DITHER_SKEW0 (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9040))
|
||||
#define rADP_DITHER_SKEW1 (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9044))
|
||||
#define rADP_DITHER_SKEW2 (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x9048))
|
||||
#define rADP_DITHER_KERNEL (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x904c))
|
||||
|
||||
//SMMU Registers
|
||||
#define rADPSMMU_CONFIG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x10000c))
|
||||
#define rADPSMMU_ERR_STATUS (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100010))
|
||||
#define rADPSMMU_ERR_AXI_REQ0 (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100014))
|
||||
#define rADPSMMU_ERR_AXI_REQ1 (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100018))
|
||||
#define rADPSMMU_ERR_ADDRESS (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x10001c))
|
||||
#define rADPSMMU_DIAG_CONFIG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100020))
|
||||
#define rADPSMMU_DIAG_BOGUS_ACCESS (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100024))
|
||||
#define rADPSMMU_BYPASS_ADDR (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x10002c))
|
||||
#define rADPSMMU_ERR_STTIDX (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100030))
|
||||
#define rADPSMMU_REQ_SCOREBOARD(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x100080 + ((n) * 4))
|
||||
#define rADPSMMU_ACK_SCOREBOARD(n) (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x1000c0 + ((n) * 4))
|
||||
#define rADPSMMU_PERF_CONFIG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x101000))
|
||||
#define rADPSMMU_CTR (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x101004))
|
||||
#define rADPSMMU_STT_PA_DATA (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x102000))
|
||||
|
||||
//DART Registers
|
||||
#define rADPDART_DIAG_CONFIG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104020))
|
||||
#define rADPDART_DIAG_BOGUS_ACCESS (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104024))
|
||||
#define rADPDART_FETCH_REQ_CONFIG (*(volatile u_int32_t *)(DISPLAYPIPE_BASE_ADDR + 0x104030))
|
||||
|
||||
#endif /* ! __APPLE_DISPLAY_FRONTEND_REGS_H */
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_DISPLAY_FRONTEND_H
|
||||
#define __APPLE_DISPLAY_FRONTEND_H
|
||||
|
||||
void adfe_init(struct display_timing *timing);
|
||||
void adfe_set_ui_layer(u_int32_t pixel_pipe, enum colorspace color, struct plane *plane0, struct plane *plane1, u_int32_t width, u_int32_t height);
|
||||
void adfe_enable_error_handler(void);
|
||||
void adfe_disable_error_handler(void);
|
||||
void adfe_set_background_color(u_int32_t color);
|
||||
void adfe_activate_window(void);
|
||||
bool adfe_get_enable(void);
|
||||
void adfe_set_axis_flip(uint32_t pixel_pipe, bool flipX, bool flipY);
|
||||
|
||||
#endif /* __APPLE_DISPLAY_FRONTEND_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_DFE_ADFE_V2=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/adfe_v2.o
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
Reference in new issue
Block a user