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/*
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* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include "iboot/amp_v3_shim.h"
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///////////////////////////////////////////////////////////////////////////////
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////// Global functions
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///////////////////////////////////////////////////////////////////////////////
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void amc_phy_preinit(void)
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{
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uint32_t ch;
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for (ch = 0; ch < AMC_NUM_CHANNELS; ch++) {
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CSR_WRITE(rAMP_DLLUPDTCTRL(AMP_DQ0, ch), 0x00017307);
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CSR_WRITE(rAMP_DLLUPDTCTRL(AMP_DQ1, ch), 0x00017307);
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CSR_WRITE(rAMP_DLLUPDTCTRL(AMP_CA, ch), 0x00017307);
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}
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}
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void amc_phy_init(bool resume)
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{
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uint32_t ch, f;
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#if !SUPPORT_FPGA
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uint32_t rd, dq;
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#endif
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for (ch = 0; ch < AMC_NUM_CHANNELS; ch++) {
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CSR_WRITE(rAMP_AMPEN(AMP_CA, ch), 1);
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CSR_WRITE(rAMP_AMPEN(AMP_DQ0, ch), 1);
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CSR_WRITE(rAMP_AMPEN(AMP_DQ1, ch), 1);
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#if !SUPPORT_FPGA
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CSR_WRITE(rAMP_DQDQSDS(AMP_DQ0, ch), amc_phy_params.dqdqsds);
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CSR_WRITE(rAMP_DQDQSDS(AMP_DQ1, ch), amc_phy_params.dqdqsds);
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CSR_WRITE(rAMP_NONDQDS(ch), amc_phy_params.nondqds);
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for (f = 0; f < AMP_FREQUENCY_SLOTS; f++) {
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CSR_WRITE(rAMP_DIFFMODE_FREQ(AMP_DQ0, ch, f), 0x00000121);
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CSR_WRITE(rAMP_DIFFMODE_FREQ(AMP_DQ1, ch, f), 0x00000121);
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}
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for (rd = 0; rd < AMP_MAX_RD; rd++) {
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for (dq = 0; dq < AMP_MAX_DQ; dq++) {
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CSR_WRITE(rAMP_RDDQDESKEW_CTRL(AMP_DQ0, ch, rd, dq), 0x00000006);
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CSR_WRITE(rAMP_RDDQDESKEW_CTRL(AMP_DQ1, ch, rd, dq), 0x00000006);
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}
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}
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CSR_WRITE(rAMP_DLLLOCKTIM(AMP_CA, ch), 0x000d0013);
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CSR_WRITE(rAMP_DLLLOCKTIM(AMP_DQ0, ch), 0x000d0013);
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CSR_WRITE(rAMP_DLLLOCKTIM(AMP_DQ1, ch), 0x000d0013);
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#endif
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for (f = 0; f < AMP_FREQUENCY_SLOTS; f++) {
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CSR_WRITE(rAMP_CAOUTDLLSCL_FREQ(ch, f), amc_phy_params.freq[f].caoutdllscl);
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CSR_WRITE(rAMP_DQSINDLLSCL_FREQ(AMP_DQ0, ch, f), amc_phy_params.freq[f].dqsindllscl);
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CSR_WRITE(rAMP_DQSINDLLSCL_FREQ(AMP_DQ1, ch, f), amc_phy_params.freq[f].dqsindllscl);
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CSR_WRITE(rAMP_RDCAPCFG_FREQ(AMP_DQ0, ch, f), amc_phy_params.freq[f].rdcapcfg);
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CSR_WRITE(rAMP_RDCAPCFG_FREQ(AMP_DQ1, ch, f), amc_phy_params.freq[f].rdcapcfg);
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CSR_WRITE(rAMP_DQODTVREF_F(AMP_DQ0, ch, f), 0x00000080);
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CSR_WRITE(rAMP_DQODTVREF_F(AMP_DQ1, ch, f), 0x00000080);
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}
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#if !SUPPORT_FPGA
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CSR_WRITE(rAMP_DLLUPDTCTRL(AMP_CA, ch), 0x00017507);
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CSR_WRITE(rAMP_DLLUPDTCTRL(AMP_DQ0, ch), 0x00017507);
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CSR_WRITE(rAMP_DLLUPDTCTRL(AMP_DQ1, ch), 0x00017507);
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CSR_WRITE(rAMP_IMPAUTOCAL(AMP_DQ0, ch), 0x00010000);
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CSR_WRITE(rAMP_IMPAUTOCAL(AMP_DQ1, ch), 0x00010000);
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CSR_WRITE(rAMP_IMPAUTOCAL(AMP_CA, ch), 0x00010000);
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CSR_WRITE(rAMP_DLLUPDTINTVL(AMP_CA, ch), 0x10200020);
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CSR_WRITE(rAMP_DLLUPDTINTVL(AMP_DQ0, ch), 0x10200020);
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CSR_WRITE(rAMP_DLLUPDTINTVL(AMP_DQ1, ch), 0x10200020);
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CSR_WRITE(rAMP_DLLEN(AMP_CA, ch), 0x00000100);
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CSR_WRITE(rAMP_DLLEN(AMP_DQ0, ch), 0x00000100);
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CSR_WRITE(rAMP_DLLEN(AMP_DQ1, ch), 0x00000100);
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CSR_WRITE(rAMP_DLLEN(AMP_CA, ch), 0x00000101);
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CSR_WRITE(rAMP_DLLEN(AMP_DQ0, ch), 0x00000101);
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CSR_WRITE(rAMP_DLLEN(AMP_DQ1, ch), 0x00000101);
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CSR_WRITE(rAMP_DLLEN(AMP_CA, ch), 0x00000100);
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CSR_WRITE(rAMP_DLLEN(AMP_DQ0, ch), 0x00000100);
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CSR_WRITE(rAMP_DLLEN(AMP_DQ1, ch), 0x00000100);
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amc_phy_run_dll_update(ch);
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CSR_WRITE(rAMP_IMPCALCMD(AMP_CA, ch), 0x00000101);
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CSR_WRITE(rAMP_IMPCALCMD(AMP_DQ0, ch), 0x00000101);
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CSR_WRITE(rAMP_IMPCALCMD(AMP_DQ1, ch), 0x00000101);
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while (CSR_READ(rAMP_IMPCALCMD(AMP_CA, ch)) & 0x1) {}
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while (CSR_READ(rAMP_IMPCALCMD(AMP_DQ0, ch)) & 0x1) {}
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while (CSR_READ(rAMP_IMPCALCMD(AMP_DQ1, ch)) & 0x1) {}
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#endif
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CSR_WRITE(rAMP_AMPINIT(AMP_CA, ch), 0x00000001);
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CSR_WRITE(rAMP_AMPINIT(AMP_DQ0, ch), 0x00000001);
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CSR_WRITE(rAMP_AMPINIT(AMP_DQ1, ch), 0x00000001);
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}
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}
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void amc_phy_run_dll_update(uint8_t ch)
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{
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CSR_WRITE(rAMP_DLLUPDTCMD(AMP_CA, ch), 0x00000001);
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CSR_WRITE(rAMP_DLLUPDTCMD(AMP_DQ0, ch), 0x00000001);
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CSR_WRITE(rAMP_DLLUPDTCMD(AMP_DQ1, ch), 0x00000001);
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while ((CSR_READ(rAMP_DLLUPDTCMD(AMP_CA, ch)) & 0x1)) ;
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while ((CSR_READ(rAMP_DLLUPDTCMD(AMP_DQ0, ch)) & 0x1)) ;
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while ((CSR_READ(rAMP_DLLUPDTCMD(AMP_DQ1, ch)) & 0x1)) ;
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}
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// <rdar://problem/15810647>: workaround to avoid memory read failure when switching from boot speed (f = 3) to normal speed (f = 0)
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void amc_phy_pre_normal_speed_enable()
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{
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uint8_t ch, f;
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for (ch = 0; ch < AMC_NUM_CHANNELS; ch++) {
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for (f = 1; f < AMP_FREQUENCY_SLOTS; f++) {
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CSR_WRITE(rAMP_CAOUTDLLSCL_FREQ(ch, f), amc_phy_params.freq[0].caoutdllscl);
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CSR_WRITE(rAMP_DQSINDLLSCL_FREQ(AMP_DQ0, ch, f), amc_phy_params.freq[0].dqsindllscl);
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CSR_WRITE(rAMP_DQSINDLLSCL_FREQ(AMP_DQ1, ch, f), amc_phy_params.freq[0].dqsindllscl);
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}
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#if !SUPPORT_FPGA
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amc_phy_run_dll_update(ch);
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#endif
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}
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}
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void amc_phy_finalize()
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{
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uint8_t ch;
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for (ch = 0; ch < AMC_NUM_CHANNELS; ch++) {
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CSR_WRITE(rAMP_AMPCLK(AMP_CA, ch), amc_phy_params.ampclk);
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CSR_WRITE(rAMP_AMPCLK(AMP_DQ0, ch), amc_phy_params.ampclk);
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CSR_WRITE(rAMP_AMPCLK(AMP_DQ1, ch), amc_phy_params.ampclk);
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}
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}
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void amc_phy_bypass_prep(int step)
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{
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}
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void amc_phy_restore_calibration_values(bool resume)
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{
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#if !SUPPORT_FPGA
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#ifndef AMP_CALIBRATION_SKIP
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// Restore offsets from PMU
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if (resume)
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calibration_save_restore_regs(CALIB_RESTORE, AMC_NUM_CHANNELS);
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#endif
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#endif
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}
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// Perform CA, RDDQ, and WRLVL calibration
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void amc_phy_calibration_ca_rddq_cal(bool resume)
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{
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#ifndef AMP_CALIBRATION_SKIP
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if (!resume)
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calibration_ca_rddq_wrlvl(resume);
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#endif
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}
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void amc_phy_calibration_wrdq_cal(bool resume)
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{
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#ifndef AMP_CALIBRATION_SKIP
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if (!resume)
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calibration_wrdq_rddq(resume);
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#endif
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}
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Load diff
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include "amp_v3_shim.h"
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// This array will hold the contents of memory that will be used for dq calibration
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// static uint8_t dqcal_saved_data[AMC_NUM_RANKS][sizeof(DQ_PRBS7_PATTERNS) * AMC_NUM_CHANNELS]__aligned(32);
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static void shim_save_restore_memory_region(uint32_t save_or_restore);
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///////////////////////////////////////////////////////////////////////////////
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////// Local functions
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///////////////////////////////////////////////////////////////////////////////
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// Before starting dq calibration, saves the contents of dram region that will be written to with calibration patterns.
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// After calibration is complete, restores the contents back to DRAM.
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static void shim_save_restore_memory_region(uint32_t save_or_restore)
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{
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}
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///////////////////////////////////////////////////////////////////////////////
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////// Global functions
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///////////////////////////////////////////////////////////////////////////////
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void shim_init_calibration_params(struct amp_calibration_params *cfg_params)
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{
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// Set the number of channels and ranks on this target
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cfg_params->num_channels = AMC_NUM_CHANNELS;
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cfg_params->num_ranks = AMC_NUM_RANKS;
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// Fiji A0 has a 1 to 1 deskew to sdll step ratio
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if((platform_get_chip_id() == 0x7000) && (platform_get_chip_revision() == CHIP_REVISION_A0)) {
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cfg_params->sdll_scale = 1;
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cfg_params->deskew_scale = 1;
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}
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}
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void shim_configure_pre_ca(void)
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{
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amc_calibration_start(true);
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}
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void shim_enable_rddqcal(bool enable)
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{
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amc_enable_rddqcal(enable);
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}
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void shim_configure_post_wrlvl(struct amp_calibration_params *cfg_params)
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{
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amc_calibration_start(false);
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}
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void shim_configure_pre_wrdq(bool resume)
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{
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amc_calibration_start(true);
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// ok to keep PSQWQCTL0 and PSQWQCTL1 at their value setup for wrdqcal even for the rddqcal that follows
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amc_wrdqcal_start(true);
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}
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void shim_configure_post_prbs_rddq(struct amp_calibration_params *cfg_params)
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{
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amc_wrdqcal_start(false);
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amc_calibration_start(false);
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// Save off the CA, WrLvl, Rddq, and Wrdq offsets to PMU
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if (!(cfg_params->resume))
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calibration_save_restore_regs(CALIB_SAVE, cfg_params->num_channels);
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}
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void shim_mrcmd_to_ch_rnk(uint8_t rw, uint8_t channel, uint8_t rank, int32_t reg, uintptr_t val)
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{
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amc_mrcmd_to_ch_rnk((amc_mrcmd_op_t) rw, channel, rank, reg, val);
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}
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uint64_t shim_compute_dram_addr(uint32_t ch, uint32_t rnk, uint32_t bank, uint32_t row, uint32_t col)
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{
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return amc_get_uncached_dram_virt_addr(ch, rnk, bank, row, col);
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}
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uint32_t shim_get_consecutive_bytes_perchnrnk(void)
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{
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// query AMC for how many consecutive bytes before channel interleaving
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return amc_get_consecutive_bytes_perchnrnk();
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}
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void shim_store_memory_calibration(void *cal_values, uint32_t cal_size)
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{
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if (power_store_memory_calibration(cal_values, cal_size) == 0)
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panic("Unable to save memory calibration values to PMU nvram\n");
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}
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void shim_load_memory_calibration(void *cal_values, uint32_t cal_size)
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{
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if (power_load_memory_calibration(cal_values, cal_size) == 0)
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panic("Unable to load memory calibration values from PMU nvram\n");
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}
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@@ -0,0 +1,69 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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||||
*/
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#ifndef _AMP_T7000_SHIM_H
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#define _AMP_T7000_SHIM_H
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#include <debug.h>
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#include <sys/menu.h>
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#include <drivers/amc/amc.h>
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#include <drivers/amc/amc_phy.h>
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#include <drivers/dram.h>
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#include <drivers/miu.h>
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#include <drivers/power.h>
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#include <platform.h>
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#include <platform/chipid.h>
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#include <sys.h>
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#include <platform/soc/hwregbase.h>
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#include "amp_v3.h"
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#include "amp_v3_calibration.h"
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#define AMP_MAX_RD (2) // 4 bytes are split across 2 DQ PHYs with 2 bytes each
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#define AMP_MAX_DQ (8)
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#define shim_panic(...) do { calibration_dump_results(SELECT_CAL_ALL, true); panic(__VA_ARGS__); } while(0)
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#define shim_printf(...) dprintf(DEBUG_CRITICAL, __VA_ARGS__)
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#define CSR_READ(x) *(volatile u_int32_t *) x
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#define CSR_WRITE(x, y) *(volatile u_int32_t *) x = y
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// <rdar://problem/13899661>
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// "word" for DV requires +1, so for iBoot, should subtract 1 before adding to mem_base
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#define MEM_WRITE(mem_base, data, word) *(uint32_t *)(mem_base + ((word-1) << 2)) = data
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#define MEM_READ(mem_base, word) *(uint32_t *)(mem_base + ((word-1) << 2))
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void shim_init_calibration_params(struct amp_calibration_params *cfg_params);
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void shim_configure_pre_ca(void);
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void shim_enable_rddqcal(bool enable);
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void shim_configure_post_wrlvl(struct amp_calibration_params *cfg_params);
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void shim_configure_pre_wrdq(bool resume);
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void shim_configure_post_prbs_rddq(struct amp_calibration_params *cfg_params);
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void shim_mrcmd_to_ch_rnk(uint8_t rw, uint8_t channel, uint8_t rank, int32_t reg, uintptr_t val);
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uint64_t shim_compute_dram_addr(uint32_t ch, uint32_t rnk, uint32_t bank, uint32_t row, uint32_t col);
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uint32_t shim_get_consecutive_bytes_perchnrnk(void);
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void shim_store_memory_calibration(void *cal_values, uint32_t cal_size);
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void shim_load_memory_calibration(void *cal_values, uint32_t cal_size);
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struct amp_per_freq {
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uint32_t caoutdllscl;
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uint32_t dqsindllscl;
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uint32_t rdcapcfg;
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};
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struct amp_params {
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struct amp_per_freq freq[AMP_FREQUENCY_SLOTS];
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uint32_t dqdqsds;
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uint32_t nondqds;
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uint32_t ampclk;
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};
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#include <platform/ampconfig.h>
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#endif /* _AMP_T7000_SHIM_H */
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@@ -0,0 +1,114 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
|
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*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef _AMP_T7000_H
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#define _AMP_T7000_H
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#define AMP_FREQUENCY_SLOTS (4)
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/* _t: type, DQ0, DQ1, or CA */
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||||
/* _c: channel, 0 or 1 */
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||||
#define AMP_DQ0 (0)
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#define AMP_DQ1 (1)
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#define AMP_CA (2)
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||||
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#define rAMP_AMPEN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x000)
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#define rAMP_AMPCLK(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x004)
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#define rAMP_AMPINIT(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x008)
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||||
#define rAMP_AMPVER(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x00C)
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||||
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||||
#define rAMP_IMPCODE(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x080)
|
||||
#define rAMP_IMPOVRRD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x084)
|
||||
#define rAMP_IMPAUTOCAL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x088)
|
||||
#define rAMP_IMPCALPHYUPDT(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x08C)
|
||||
#define rAMP_IMPCALCMD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x090)
|
||||
#define rAMP_DRAMSIGDLY(_t,_c,_n) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x094 + ((_n) * 4))
|
||||
#define rAMP_NONDQDS(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x098)
|
||||
#define rAMP_DQDQSDS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x09C)
|
||||
#define rAMP_DIFFMODE_FREQ(_t,_c,_f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x0A0 + ((_f) * 4))
|
||||
#define rAMP_DQFLTCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x0B0)
|
||||
|
||||
#define rAMP_RDCAPCFG_FREQ(_t,_c,_f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x100 + ((_f) * 4))
|
||||
#define rAMP_DQSPDENALWYSON(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x110)
|
||||
#define rAMP_DQSPDRES(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x114)
|
||||
#define rAMP_RDFIFOPTRSTS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x118)
|
||||
#define rAMP_CALDQMSK(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x11C)
|
||||
#define rAMP_CALPATCFG(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x120 - ((_t >> 1) * 0x10))
|
||||
#define rAMP_DQTRNCFG(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x124 - ((_t >> 1) * 0x10))
|
||||
#define rAMP_DQTRNCMD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x128 - ((_t >> 1) * 0x10))
|
||||
#define rAMP_DQTRNSTS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x12C - ((_t >> 1) * 0x10))
|
||||
|
||||
#define rAMP_DLLEN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x180)
|
||||
#define rAMP_DLLUPDTCMD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x184)
|
||||
#define rAMP_MDLLOVRRD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x188 + ((_t >> 1) * 4))
|
||||
#define rAMP_MDLLCODE(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x18C - ((_t >> 1) * 4))
|
||||
#define rAMP_DLLLOCKTIM(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x190)
|
||||
#define rAMP_DLLLOCKCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x194)
|
||||
#define rAMP_DLLUPDTINTVL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x198)
|
||||
#define rAMP_DLLUPDTCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x19C)
|
||||
#define rAMP_DLLSTS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x1A0)
|
||||
#define rAMP_DQSINDLLSCL_FREQ(_t,_c,_f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x1B8 + ((_f) * 4))
|
||||
#define rAMP_CAOUTDLLSCL_FREQ(_c,_f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x1B8 + ((_f) * 4))
|
||||
// <rdar://problem/13919568>
|
||||
#define rAMP_TESTMODE(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x200 + ((_t >> 1) * 0x180))
|
||||
|
||||
#define rAMP_WRDQDESKEW_CTRL(_t,_c,_r,_d) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x400 + ((_r)*0x28) + ((_d)*4))
|
||||
#define rAMP_WRDQSDESKEW_CTRL(_t,_c,_r) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x420 + ((_r)*0x28))
|
||||
#define rAMP_WRDMDESKEW_CTRL(_t,_c,_b) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x424 + ((_b)*0x28))
|
||||
#define rAMP_RDDQDESKEW_CTRL(_t,_c,_r,_d) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x450 + ((_r)*0x28) + ((_d)*4))
|
||||
#define rAMP_RDDQSDESKEW_CTRL(_t,_c,_r) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x470 + ((_r)*0x28))
|
||||
#define rAMP_RDDMDESKEW_CTRL(_t,_c,_r) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x474 + ((_r)*0x28))
|
||||
|
||||
#define rAMP_CADESKEW_CTRL(_c,_d) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x500 + ((_d)*4))
|
||||
#define rAMP_CSDESKEW_CTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x528)
|
||||
#define rAMP_CKEDESKEW_CTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x52C)
|
||||
#define rAMP_CKDESKEW_CTRL(_c,_d) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x530 + ((_d)*4))
|
||||
|
||||
#define rAMP_DQSDLLCTRL_WR(_t,_c,_b) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x600 + ((_b)*0x08))
|
||||
#define rAMP_DQSDLLCTRL_RD(_t,_c,_b) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x610 + ((_b)*0x08))
|
||||
#define rAMP_DQWRLVLTIM(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x700)
|
||||
#define rAMP_DQWRLVLDLYCHAINCTRL(_t,_c,_b) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x704 + ((_b)*0x04))
|
||||
#define rAMP_DQWRLVLSDLLCODE(_t,_c,_b) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x70C + ((_b)*0x04))
|
||||
#define rAMP_DQWRLVLRUN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x714)
|
||||
#define rAMP_DQWRLVLDATA(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x718)
|
||||
|
||||
#define rAMP_CASDLLCTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x700)
|
||||
#define rAMP_CAWRLVLSDLLCODE(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x800)
|
||||
#define rAMP_CAWRLVLCLKDLYSEL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x804)
|
||||
|
||||
#define rAMP_CACALCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x800 + ((_t >> 1) * 0x100))
|
||||
#define rAMP_CACALMASK(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x804)
|
||||
#define rAMP_CACALCABYTESEL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x808)
|
||||
#define rAMP_CACALCAMAP0(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x80C)
|
||||
#define rAMP_CACALCAMAP1(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x810)
|
||||
#define rAMP_CACALCAMAP2(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x814)
|
||||
#define rAMP_CACALPAT(_t,_c,_p) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x818 + ((_t >> 1) * 0xEC) + ((_p)*0x04))
|
||||
#define rAMP_CACALRUN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x838 + ((_t >> 1) * 0xEC))
|
||||
#define rAMP_CACALRESULT(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x83C)
|
||||
|
||||
#define rAMP_DQCALCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x900)
|
||||
#define rAMP_DQCALRUN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x908)
|
||||
#define rAMP_DQCALRESULT(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0x90C)
|
||||
|
||||
#define rAMP_DQODTVREF_F(_t,_c,_f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQCA_SPACING) + 0xB00 + ((_f)*0x04))
|
||||
|
||||
#define rAMP_CAPHYUPDTREQ(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0xB00)
|
||||
#define rAMP_CAPHYUPDTSTATUS(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0xB04)
|
||||
|
||||
// Some bit definitions
|
||||
#define CACALRUN_CACALMODE (1 << 16)
|
||||
#define CACALRUN_RUNCACAL (1 << 0)
|
||||
#define TESTMODE_FORCECKELOW (1 << 8)
|
||||
|
||||
#define SIGN_BIT_POS (6)
|
||||
|
||||
#define AMP_MAX_RANKS_PER_CHAN (2)
|
||||
|
||||
#endif /* _AMP_T7000_H */
|
||||
@@ -0,0 +1,132 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __AMP_V3_CALIBRATION_H
|
||||
#define __AMP_V3_CALIBRATION_H
|
||||
|
||||
#define AMP_DQ_PER_CHAN 2
|
||||
|
||||
#define AMP_MAX_PATTERNS 8
|
||||
|
||||
#define CALIB_SAVE 0
|
||||
#define CALIB_RESTORE 1
|
||||
#define CALIB_PMU_BYTES 400
|
||||
// Each register is saved as 1 byte in the array. We will save 1 offset per bit, where offset = SDLL + deskew.
|
||||
// Number of bytes to save per channel = 10 CA bit offsets + 1 CK/CKE/CS deskew + 5 WrLvl SDLLs
|
||||
// + 32 RDDQ deskews + 32 WRDQ deskews = 80
|
||||
#define CALIB_NUM_BYTES_TO_SAVE (AMC_NUM_CHANNELS * (80))
|
||||
|
||||
#define CA_NUM_BITS 10
|
||||
#define CA_ALL_BITS ((1 << CA_NUM_BITS) - 1)
|
||||
#define CA_NUM_PATTERNS 64
|
||||
// <rdar://problem/13821643>
|
||||
#define DELIMIT_POS_ADJ_CASDLL 6
|
||||
#define DELIMIT_POS_ADJ_WRDQSDLL 6
|
||||
|
||||
#define CSBIT (CA_NUM_BITS)
|
||||
#define CKBIT (CA_NUM_BITS + 1)
|
||||
#define CKEBIT (CA_NUM_BITS + 2)
|
||||
#define CASDLLBIT (CA_NUM_BITS + 3)
|
||||
|
||||
#define CACAL_MAX_SWLOOPS (8)
|
||||
|
||||
#define MR_READ 0
|
||||
#define MR_WRITE 1
|
||||
|
||||
#define MR2 0x02
|
||||
#define MR5 0x05
|
||||
#define MR41 0x29
|
||||
#define MR42 0x2A
|
||||
#define MR48 0x30
|
||||
|
||||
#define MIN_ENDPT 0
|
||||
#define MAX_ENDPT 1
|
||||
|
||||
/* defines for conversion between sdll and deskew steps */
|
||||
#define DIRECTION_DESKEW_TO_SDLL 0
|
||||
#define DIRECTION_SDLL_TO_DESKEW 1
|
||||
|
||||
#define CA_MAX_DESKEW_OFFSET 29
|
||||
#define MAX_DESKEW_PROGRAMMED 31
|
||||
#define MAX_SDLL_VAL 63
|
||||
#define MIN_SDLL_VAL 24
|
||||
#define FINER_STEP_SZ 1
|
||||
#define COARSE_STEP_SZ 4
|
||||
#define SOLID_PASS_DETECT 8
|
||||
#define DLLVAL_BITS 0x7F
|
||||
#define DESKEW_CTRL_BITS 0x1F
|
||||
#define SDLL_NUM_BITS 7
|
||||
#define DESKEW_NUM_BITS 5
|
||||
#define RD_LATENCY_ENCODE 26
|
||||
|
||||
// maximum possible loops in the hw
|
||||
#define RDDQ_LOOPCNT 63
|
||||
#define DQ_NUM_BYTES 4
|
||||
#define DQ_NUM_BYTES_PER_DQ 2
|
||||
#define DQ_NUM_BITS_PER_BYTE 8
|
||||
#define DQ_TOTAL_BITS (DQ_NUM_BYTES * DQ_NUM_BITS_PER_BYTE)
|
||||
#define DQ_MAX_DESKEW_PER_BIT 29
|
||||
#define MAX_CAWRLVL_CODE 127
|
||||
#define MAX_DQWRLVL_CODE 127
|
||||
#define DQ_NUM_PATTERNS 128
|
||||
// The number of bytes below is consecutive for a given ch, rnk, bank, and row (interleaving starts after these bytes)
|
||||
//#define DQ_CONSECUTIVE_BYTES_PER_CHRNK 256
|
||||
#define DQ_BYTES_PER_COL 4 // That makes for 64 consecutive columns (or words)
|
||||
// the bank and row numbers where patterns will be written
|
||||
#define DQ_ROW 0
|
||||
#define DQ_BANK 0
|
||||
#define DQ_ADDR_RANK_BIT 16 // RIBI2 addressing for dual rank devices
|
||||
|
||||
// Calibration operation selection
|
||||
#define SELECT_CACAL 0x1
|
||||
#define SELECT_WRLVLCAL 0x2
|
||||
#define SELECT_RDDQCAL 0x4
|
||||
#define SELECT_WRDQCAL 0x8
|
||||
#define SELECT_RDDQCAL2 0x10
|
||||
#define SELECT_CAL_ALL (SELECT_RDDQCAL2 | SELECT_WRDQCAL | SELECT_RDDQCAL | SELECT_WRLVLCAL | SELECT_CACAL)
|
||||
|
||||
// This defintion is put here for non-iBoot compilation environments
|
||||
#ifndef __abs
|
||||
#define __abs(x) (((x) < 0) ? -(x) : (x))
|
||||
#endif
|
||||
|
||||
// Macros to change format between signed integer value and offset with sign and magnitude
|
||||
#define INT_TO_OFFSET(val) ((((val < 0) ? 1 : 0) << SIGN_BIT_POS) | __abs(val))
|
||||
#define OFFSET_TO_INT(val) ((val & ~(1 << SIGN_BIT_POS)) * ((val & (1 << SIGN_BIT_POS)) ? -1 : 1))
|
||||
|
||||
void calibration_ca_rddq_wrlvl(bool resume);
|
||||
void calibration_wrdq_rddq(bool resume);
|
||||
void calibration_save_restore_regs(uint32_t save_or_restore, uint32_t channels);
|
||||
void calibration_dump_results(uint32_t operations, bool dump_passing_points);
|
||||
|
||||
struct amp_calibration_params {
|
||||
uint32_t num_channels;
|
||||
uint32_t num_ranks;
|
||||
bool resume;
|
||||
uint32_t cacalib_hw_loops;
|
||||
uint32_t cacalib_sw_loops;
|
||||
|
||||
/*
|
||||
* Starting with Fiji B0, 1 deskew step is ~22% bigger than 1 sdll step.
|
||||
* Fiji B0 / Capri B0 should define deskew_scale to 100 and sdll_scale to 122 (or some combo of numbers that indicates 22% increase),
|
||||
* while Fiji A0 should define 1 and 1.
|
||||
*/
|
||||
int32_t sdll_scale;
|
||||
int32_t deskew_scale;
|
||||
|
||||
// SEG specific flags
|
||||
bool dv_params_valid; // DV flag
|
||||
bool dv_randomize; // flag to be used by DV to randomize some register values for DV purposes
|
||||
uint32_t dbg_calib_mode; // flag to be used by SEG to skip calibration operations for debug purposes
|
||||
};
|
||||
|
||||
|
||||
#endif /* ! __AMP_V3_CALIBRATION_H */
|
||||
@@ -0,0 +1,22 @@
|
||||
# Copyright (C) 2010-2013 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += WITH_HW_AMP=1
|
||||
|
||||
# Set ENV_IBOOT for calibration code that is shared with SEG
|
||||
OPTIONS += ENV_IBOOT
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/amp_v3.o \
|
||||
$(LOCAL_DIR)/iboot/amp_v3_shim.o \
|
||||
$(LOCAL_DIR)/amp_v3_calibration.o
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
Reference in new issue
Block a user