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/*
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* Copyright (C) 2011-2014 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <lib/devicetree.h>
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#include <platform.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/usbconfig.h>
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#include <platform/soc/chipid.h>
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#include <sys.h>
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#include "ausb.h"
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// USB Widget related constants
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#if !AUSB_USB20PHY_ONLY_VERSION
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#if APPLICATION_IBOOT && (PRODUCT_IBOOT || PRODUCT_IBEC)
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static const uint32_t high_addr_bits = (1 << 8) | ((SDRAM_BASE >> 32) & 0xf);
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#elif APPLICATION_SECUREROM || (APPLICATION_IBOOT && WITH_DFU_MODE)
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static const uint32_t high_addr_bits = (1 << 8) | ((SRAM_BASE >> 32) & 0xf);
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#else
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#error Not Supported
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#endif
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#endif
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///////////////////////////////////////////////////////////
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//
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// USB PHY Control
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//
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///////////////////////////////////////////////////////////
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static bool usbphy_powered;
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void usbphy_power_up(void)
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{
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if (usbphy_powered)
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return;
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clock_gate(CLK_USB, true);
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clock_gate(CLK_USBCTLREG, true);
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clock_gate(CLK_USB_OTG, true);
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#if !AUSB_USB20PHY_ONLY_VERSION
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// Set the USB OTG Widget register
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rAUSB_WIDGET_OTG_ADDR = high_addr_bits;
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#endif
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// * expects SIDDQ and VBUSVLDEXTSEL set to 1 out of reset.
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// * program tuning values
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rAUSB_USB20PHY_CFG0 = USBPHY_OTGTUNE0;
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#if defined(USBPHY_OTGTUNE1)
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rAUSB_USB20PHY_CFG1 = USBPHY_OTGTUNE1;
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#endif
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// <rdar://problem/15495710> ECO_216: Add register control to FSEL of USB PiCOPHY to get better jitter performance
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// The bit USB20PHY_CFG1::PLLBTUNE needs to be set for Fiji revisions > A0 and all Capri revisions
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#if defined(SUB_PLATFORM_T7000) || defined(SUB_PLATFORM_T7001)
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rAUSB_USB20PHY_CFG1 |= (1 << 2);
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#endif
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// <rdar://problem/16373379> Fiji >= B1 and Capri >= A1 need to adjust USB20PHY_CFG1:PLLITUNE
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#if defined(SUB_PLATFORM_T7000)
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if(platform_get_chip_revision() >= CHIP_REVISION_B1)
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rAUSB_USB20PHY_CFG1 |= (2 << 4);
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#endif
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#if defined(SUB_PLATFORM_T7001)
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if(platform_get_chip_revision() >= CHIP_REVISION_A1)
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rAUSB_USB20PHY_CFG1 |= (2 << 4);
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#endif
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// Maui A0/A1 uses different tunable than >= B0
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#if defined(SUB_PLATFORM_S8000)
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if(platform_get_chip_revision() <= CHIP_REVISION_A1)
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rAUSB_USB20PHY_CFG0 = USBPHY_OTGTUNE0_AX;
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#endif
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// * assert PHY_RESET
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rAUSB_USB20PHY_CTL |= (1 << 0);
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// * clear analog power-down (SIDDQ) and otg-block power-down bits
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rAUSB_USB20PHY_CTL &= ~((1 << 3) | (1 << 2));
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// * wait 10us delay
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spin(10);
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// * de-assert PHY_RESET
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rAUSB_USB20PHY_CTL &= ~(1 << 0);
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// * wait 1000us delay: This wait for PLL to be locked after POR.
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spin(1000);
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usbphy_powered = true;
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}
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void usbphy_enable_pullup(void)
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{
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if (!usbphy_powered)
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return;
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// Enable D+ PU
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rAUSB_USB20PHY_OTGSIG |= (1 << 1);
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}
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void usbphy_power_down(void)
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{
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if (!usbphy_powered)
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return;
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// * Assert PHY_RESET
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rAUSB_USB20PHY_CTL |= (1 << 0);
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// * disable D+ PU
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rAUSB_USB20PHY_OTGSIG &= ~(1 << 1);
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// * wait 10us delay
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spin(10);
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// * De-assert PHY_RESET
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rAUSB_USB20PHY_CTL &= ~(1 << 0);
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// * wait 1000us delay: This wait for PLL to be locked after POR.
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spin(1000);
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// * set analog and otg block power down bits
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rAUSB_USB20PHY_CTL |= ((1 << 3) | (1 << 2));
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clock_gate(CLK_USB_OTG, false);
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clock_gate(CLK_USBCTLREG, false);
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clock_gate(CLK_USB, false);
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usbphy_powered = false;
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}
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bool usbphy_is_cable_connected(void)
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{
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bool connected;
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if (!usbphy_powered) {
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clock_gate(CLK_USB, true);
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clock_gate(CLK_USBCTLREG, true);
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}
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connected = (rAUSB_USB20PHY_OTGSIG & (1 << 8)) != 0;
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if (!usbphy_powered) {
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clock_gate(CLK_USBCTLREG, false);
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clock_gate(CLK_USB, false);
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}
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return connected;
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}
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bool usbphy_set_dpdm_monitor(int select)
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{
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// XXX IBOOT64_TODO
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return false;
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}
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#if WITH_DEVICETREE
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void update_devicetree_property(DTNode *node, char * propName, uint32_t value, bool doOR)
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{
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void *propData;
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uint32_t propSize;
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if (FindProperty(node, &propName, &propData, &propSize)) {
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if (propSize >= sizeof(uint32_t)) {
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if(doOR) {
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*(uint32_t *)propData |= value;
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}
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else {
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*(uint32_t *)propData = value;
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}
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}
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}
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}
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void usbphy_update_device_tree(DTNode *node)
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{
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uint32_t phy_tuning_val;
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phy_tuning_val = 0;
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#ifdef USBPHY_UOTGTUNE
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phy_tuning_val = USBPHY_UOTGTUNE;
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#endif
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// Fill in the phy-tuning-val property
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update_devicetree_property(node, "phy-tuning-val", phy_tuning_val, false);
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// <rdar://problem/15495710> ECO_216: Add register control to FSEL of USB PiCOPHY to get better jitter performance
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// The bit USB20PHY_CFG1::PLLBTUNE needs to be set for Fiji revisions > A0 and all Capri revisions
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#if defined(SUB_PLATFORM_T7000) || defined(SUB_PLATFORM_T7001)
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update_devicetree_property(node, "cfg1-device", (1 << 2), true);
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update_devicetree_property(node, "cfg1-host", (1 << 2), true);
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#endif
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// <rdar://problem/16373379> Fiji >= B1 and Capri >= A1 need to adjust USB20PHY_CFG1:PLLITUNE
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#if defined(SUB_PLATFORM_T7000)
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if(platform_get_chip_revision() >= CHIP_REVISION_B1) {
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update_devicetree_property(node, "cfg1-device", (2 << 4), true);
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update_devicetree_property(node, "cfg1-host", (2 << 4), true);
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}
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#endif
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#if defined(SUB_PLATFORM_T7001)
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if(platform_get_chip_revision() >= CHIP_REVISION_A1) {
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update_devicetree_property(node, "cfg1-device", (2 << 4), true);
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update_devicetree_property(node, "cfg1-host", (2 << 4), true);
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}
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#endif
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// Maui A0/A1 uses different tunable than >= B0
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#if defined(SUB_PLATFORM_S8000)
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if(platform_get_chip_revision() <= CHIP_REVISION_A1) {
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update_devicetree_property(node, "cfg0-device", USBPHY_OTGTUNE0_AX, false);
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}
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#endif
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}
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#endif
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///////////////////////////////////////////////////////////
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//
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// USB Widgets Control
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//
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///////////////////////////////////////////////////////////
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#if !AUSB_USB20PHY_ONLY_VERSION
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void ausb_setup_widgets()
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{
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clock_gate(CLK_USB, true);
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// USB_CTL clock should be enabled
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rAUSB_WIDGET_OTG_ADDR = high_addr_bits;
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rAUSB_WIDGET_OHCI0_ADDR = high_addr_bits;
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// Only if EHCI is NOT capable of 64 bit addressing ...
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#if (USBEHCI_ADDR_EXT_WIDGET_EN == 1)
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rAUSB_WIDGET_EHCI0_ADDR = high_addr_bits;
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rAUSB_WIDGET_EHCI1_ADDR = high_addr_bits;
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#endif
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clock_gate(CLK_USB, false);
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}
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#endif
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@@ -0,0 +1,46 @@
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/*
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* Copyright (C) 2011-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __AUSB_H
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#define __AUSB_H
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#include <platform/soc/hwregbase.h>
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#define rAUSB_USB20PHY_CTL (*(volatile uint32_t *)(AUSB_CTL_REG_BASE_ADDR + AUSB_CTL_USB20PHY_REG_OFFSET + 0x00))
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#define rAUSB_USB20PHY_OTGSIG (*(volatile uint32_t *)(AUSB_CTL_REG_BASE_ADDR + AUSB_CTL_USB20PHY_REG_OFFSET + 0x04))
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#define rAUSB_USB20PHY_CFG0 (*(volatile uint32_t *)(AUSB_CTL_REG_BASE_ADDR + AUSB_CTL_USB20PHY_REG_OFFSET + 0x08))
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#define rAUSB_USB20PHY_CFG1 (*(volatile uint32_t *)(AUSB_CTL_REG_BASE_ADDR + AUSB_CTL_USB20PHY_REG_OFFSET + 0x0C))
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#define rAUSB_USB20PHY_BATCTL (*(volatile uint32_t *)(AUSB_CTL_REG_BASE_ADDR + AUSB_CTL_USB20PHY_REG_OFFSET + 0x10))
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#define rAUSB_USB20PHY_TEST (*(volatile uint32_t *)(AUSB_CTL_REG_BASE_ADDR + AUSB_CTL_USB20PHY_REG_OFFSET + 0x1C))
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#if !AUSB_USB20PHY_ONLY_VERSION
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#define rAUSB_WIDGET_OTG_QOS (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x14))
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#define rAUSB_WIDGET_OTG_CACHE (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x18))
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#define rAUSB_WIDGET_OTG_ADDR (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x1C))
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#define rAUSB_WIDGET_EHCI0_QOS (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x34))
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#define rAUSB_WIDGET_EHCI0_CACHE (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x38))
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#define rAUSB_WIDGET_EHCI0_ADDR (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x3C))
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#define rAUSB_WIDGET_OHCI0_QOS (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x54))
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#define rAUSB_WIDGET_OHCI0_CACHE (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x58))
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#define rAUSB_WIDGET_OHCI0_ADDR (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x5C))
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#define rAUSB_WIDGET_EHCI1_QOS (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x74))
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#define rAUSB_WIDGET_EHCI1_CACHE (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x78))
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#define rAUSB_WIDGET_EHCI1_ADDR (*(volatile uint32_t *)(AUSB_PL301_WIDGET_BASE_ADDR + 0x7C))
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#endif
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// Errata bits
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enum
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{
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ERRATA_PHY_JITTER_IMPROVEMENT = 1
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};
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#endif /* __AUSB_H */
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@@ -0,0 +1,16 @@
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# Copyright (C) 2011 Apple Inc. All rights reserved.
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#
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# This document is the property of Apple Inc.
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# It is considered confidential and proprietary.
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#
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# This document may not be reproduced or transmitted in any form,
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# in whole or in part, without the express written permission of
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# Apple Inc.
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#
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LOCAL_DIR := $(GET_LOCAL_DIR)
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OPTIONS += \
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WITH_HW_USBPHY=1
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ALL_OBJS += \
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$(LOCAL_DIR)/ausb.o
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