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@@ -0,0 +1,369 @@
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/*
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* Copyright (C) 2012-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <arch/arm/arm.h>
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#include <drivers/dart.h>
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#include <platform/soc/hwregbase.h>
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#include <sys.h>
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#include "dart_regs.h"
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#if DART_PAGE_SIZE != DART_TT_PGSIZE
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#error "The generic header's idea of the page size doesn't agree with this driver"
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#endif
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typedef uint64_t dart_ent;
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typedef struct dart_l2_tt {
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dart_ent *tt_base;
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uintptr_t tt_phys;
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dart_ent *l3_tt_bases[DART_TTE_PGENTRIES];
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} dart_l2_tt_t;
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typedef struct dart {
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uintptr_t regs;
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dart_l2_tt_t *l2_tts[DART_NUM_TTBR];
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dart_iovm_addr_t addr_mask;
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} dart_t;
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dart_t darts[NUM_DARTS];
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static void *alloc_tt_page(void)
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{
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void *result;
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result = memalign(DART_TT_PGSIZE, DART_TT_PGSIZE);
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bzero(result, DART_TT_PGSIZE);
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return result;
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}
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static void flush_tlb(dart_t *dart)
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{
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arm_memory_barrier();
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// Flush SID 0
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rDART_TLB_OP(dart->regs) = DART_TLB_OP_FLUSH | DART_TLB_OP_SID_MASK0;
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while(rDART_TLB_OP(dart->regs) & DART_TLB_OP_BUSY)
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;
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}
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// Clear out any L3 entries in the DART so that nothing is mapped into IO virtual
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// space. Don't clear out the mappings at the L2 level, just at L3. The DART
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// doesn't support block mappings, so L2 entries can never cause a mapping
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// without a subsequent L3 entry.
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static void clear_mappings(dart_t *dart)
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{
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unsigned int i, j;
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dart_l2_tt_t *l2_tt;
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dart_ent *l3_tt_base;
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for (i = 0; i < DART_NUM_TTBR; i++) {
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l2_tt = dart->l2_tts[i];
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if (l2_tt == NULL)
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continue;
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for (j = 0; j < DART_TTE_PGENTRIES; j++) {
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l3_tt_base = l2_tt->l3_tt_bases[j];
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if (l3_tt_base != NULL)
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memset(l3_tt_base, 0, DART_TT_PGSIZE);
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}
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}
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}
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void dart_init(unsigned int dart_id)
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{
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dart_t *dart;
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uint32_t reg;
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ASSERT(dart_id < NUM_DARTS);
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dart = &darts[dart_id];
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switch (dart_id)
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{
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#ifdef DART0_BASE_ADDR
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case 0:
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dart->regs = DART0_BASE_ADDR;
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dart->addr_mask = DART0_ADDR_MASK;
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break;
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#endif
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#ifdef DART1_BASE_ADDR
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case 1:
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dart->regs = DART1_BASE_ADDR;
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dart->addr_mask = DART1_ADDR_MASK;
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break;
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#endif
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#ifdef DART2_BASE_ADDR
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case 2:
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dart->regs = DART2_BASE_ADDR;
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dart->addr_mask = DART2_ADDR_MASK;
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break;
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#endif
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#ifdef DART3_BASE_ADDR
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case 3:
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dart->regs = DART3_BASE_ADDR;
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dart->addr_mask = DART3_ADDR_MASK;
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break;
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#endif
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default:
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panic("Unknown DART index %d", dart_id);
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break;
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}
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// If the DART has previously been initialized, we need to clear out all mappings
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// This will be a quick no-op if the DART hasn't been initialized
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clear_mappings(dart);
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// If for some reason translation gets disabled, bypass to an invalid
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// address instead of DRAM
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rDART_BYPASS_ADDR(dart->regs) = 0;
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rDART_DIAG_BOGUS_ACCESS(dart->regs) = ERR_REFLECTION_BASE_ADDR >> 12;
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// Tunables
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rDART_DIAG_CONFIG(dart->regs) |= DART_DIAG_CONFIG_PTE_FETCH_PROMOTE_QOS;
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reg = rDART_FETCH_REQ_CONFIG(dart->regs);
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reg &= ~DART_FETCH_REQ_CONFIG_STE(0xf);
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reg |= DART_FETCH_REQ_CONFIG_STE(0x3);
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reg &= ~DART_FETCH_REQ_CONFIG_PTE(0xf);
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reg |= DART_FETCH_REQ_CONFIG_PTE(0x3);
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reg &= ~DART_FETCH_REQ_CONFIG_PTE_PREFETCH(0xf);
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reg |= DART_FETCH_REQ_CONFIG_PTE_PREFETCH(0xe);
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rDART_FETCH_REQ_CONFIG(dart->regs) = reg;
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// Restore TTBRs if we were previously enabled, otherwise initialize
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// all the TTBRs to 0
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dart_enable_translation(dart_id);
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// Enable translation and exceptions for SID 0
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rDART_CONFIG(dart->regs) = 0x80;
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}
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/* Disables all TTBRs and flushes the TLB, but leaves translation enabled. This will
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* make sure that all translation attempts result in an error. If we disabled translation,
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* all translation attempts would go to the bypass address, which is not what we want */
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void dart_disable_translation(unsigned int dart_id)
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{
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dart_t *dart;
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int i;
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ASSERT(dart_id < NUM_DARTS);
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dart = &darts[dart_id];
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for (i = 0; i < DART_NUM_TTBR; i++)
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rDART_TTBR(dart->regs, i) = 0;
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flush_tlb(dart);
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}
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/* Re-enables mappings that were previously created with dart_map_page_range by reprogramming
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* the DART's TTBRs with the previously created translation tables */
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void dart_enable_translation(unsigned int dart_id)
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{
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uint32_t i;
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uint32_t ttbr;
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dart_t *dart;
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dart_l2_tt_t *l2_tt;
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ASSERT(dart_id < NUM_DARTS);
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dart = &darts[dart_id];
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for (i = 0; i < DART_NUM_TTBR; i++) {
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l2_tt = dart->l2_tts[i];
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if (l2_tt == NULL) {
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ttbr = 0;
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} else {
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ttbr = (l2_tt->tt_phys >> DART_TTBR_SHIFT) | DART_TTBR_VALID;
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}
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rDART_TTBR(dart->regs, i) = ttbr;
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}
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flush_tlb(dart);
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}
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void dart_map_page_range(unsigned int dart_id, uintptr_t paddr, dart_iovm_addr_t vaddr, uint32_t pages, bool write_protect)
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{
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uint32_t ttbr;
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uint32_t i;
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dart_iovm_addr_t page_vaddr;
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uintptr_t page_paddr;
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dart_ent ent;
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dart_t *dart;
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ASSERT(dart_id < NUM_DARTS);
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dart = &darts[dart_id];
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ASSERT((vaddr & DART_TT_L3_OFFMASK) == 0);
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ASSERT((paddr & DART_TT_L3_OFFMASK) == 0);
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page_vaddr = vaddr & dart->addr_mask;
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page_paddr = paddr;
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dprintf(DEBUG_SPEW, "dart%d: mapped 0x%04x pages at iovm 0x%08x to phys %p\n", dart_id, pages, vaddr, (void *)paddr);
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for (i = 0; i < pages; i++) {
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uint32_t l1_index = (page_vaddr & DART_TT_L1_INDEX_MASK) >> DART_TT_L1_SHIFT;
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uint32_t l2_index = (page_vaddr & DART_TT_L2_INDEX_MASK) >> DART_TT_L2_SHIFT;
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uint32_t l3_index = (page_vaddr & DART_TT_L3_INDEX_MASK) >> DART_TT_L3_SHIFT;
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dart_l2_tt_t *l2_tt;
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dart_ent *l3_tt;
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if (dart->l2_tts[l1_index] == NULL) {
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dart_ent *new_tt;
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uintptr_t new_tt_phys;
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new_tt = alloc_tt_page();
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new_tt_phys = mem_static_map_physical((uintptr_t)new_tt);
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dart->l2_tts[l1_index] = calloc(1, sizeof(dart_l2_tt_t));
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dart->l2_tts[l1_index]->tt_base = new_tt;
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dart->l2_tts[l1_index]->tt_phys = new_tt_phys;
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ttbr = (new_tt_phys >> DART_TTBR_SHIFT) | DART_TTBR_VALID;
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rDART_TTBR(dart->regs, l1_index) = ttbr;
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}
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l2_tt = dart->l2_tts[l1_index];
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if (l2_tt->l3_tt_bases[l2_index] == NULL) {
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dart_ent *new_tt = alloc_tt_page();
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l2_tt->l3_tt_bases[l2_index] = new_tt;
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ent = ((uintptr_t)mem_static_map_physical((uintptr_t)new_tt)) | DART_TTE_TABLE | DART_TTE_VALID;
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l2_tt->tt_base[l2_index] = ent;
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}
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l3_tt = l2_tt->l3_tt_bases[l2_index];
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RELEASE_ASSERT(l3_tt[l3_index] == 0);
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ent = page_paddr | DART_PTE_WRPROT(write_protect) | DART_PTE_TYPE_VALID;
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l3_tt[l3_index] = ent;
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page_vaddr += DART_TT_L3_SIZE;
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page_paddr += DART_TT_L3_SIZE;
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}
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flush_tlb(dart);
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}
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void dart_unmap_page_range(unsigned int dart_id, dart_iovm_addr_t vaddr, uint32_t pages)
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{
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uint32_t i;
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dart_iovm_addr_t page_vaddr;
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dart_t *dart;
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ASSERT(dart_id < NUM_DARTS);
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dart = &darts[dart_id];
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ASSERT((vaddr & DART_TT_L3_OFFMASK) == 0);
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dprintf(DEBUG_SPEW, "dart%d: unmapped 0x%04x pages at iovm 0x%08x\n", dart_id, pages, vaddr);
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page_vaddr = vaddr & dart->addr_mask;
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for (i = 0; i < pages; i++) {
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uint32_t l1_index = (page_vaddr & DART_TT_L1_INDEX_MASK) >> DART_TT_L1_SHIFT;
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uint32_t l2_index = (page_vaddr & DART_TT_L2_INDEX_MASK) >> DART_TT_L2_SHIFT;
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uint32_t l3_index = (page_vaddr & DART_TT_L3_INDEX_MASK) >> DART_TT_L3_SHIFT;
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dart_l2_tt_t *l2_tt;
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dart_ent *l3_tt;
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l2_tt = dart->l2_tts[l1_index];
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RELEASE_ASSERT(l2_tt != NULL);
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l3_tt = l2_tt->l3_tt_bases[l2_index];
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RELEASE_ASSERT(l3_tt != NULL);
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l3_tt[l3_index] = 0;
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page_vaddr += DART_TT_L3_SIZE;
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}
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flush_tlb(dart);
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}
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void dart_write_protect_page_range(unsigned int dart_id, dart_iovm_addr_t vaddr, uint32_t pages, bool write_protect)
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{
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uint32_t i;
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dart_iovm_addr_t page_vaddr;
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dart_ent ent;
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dart_t *dart;
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ASSERT(dart_id < NUM_DARTS);
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dart = &darts[dart_id];
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ASSERT((vaddr & DART_TT_L3_OFFMASK) == 0);
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page_vaddr = vaddr;
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for (i = 0; i < pages; i++) {
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uint32_t l1_index = (page_vaddr & DART_TT_L1_INDEX_MASK) >> DART_TT_L1_SHIFT;
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uint32_t l2_index = (page_vaddr & DART_TT_L2_INDEX_MASK) >> DART_TT_L2_SHIFT;
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uint32_t l3_index = (page_vaddr & DART_TT_L3_INDEX_MASK) >> DART_TT_L3_SHIFT;
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dart_l2_tt_t *l2_tt;
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dart_ent *l3_tt;
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l2_tt = dart->l2_tts[l1_index];
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RELEASE_ASSERT(l2_tt != NULL);
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l3_tt = l2_tt->l3_tt_bases[l2_index];
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RELEASE_ASSERT(l3_tt != NULL);
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ent = l3_tt[l3_index];
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ent &= DART_PTE_PAGE_MASK;
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ent |= DART_PTE_WRPROT(write_protect);
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l3_tt[l3_index] = ent;
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page_vaddr += DART_TT_L3_SIZE;
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}
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flush_tlb(dart);
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}
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// Verifies that all mappings have been removed from the DART. This is used
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// to verify that drivers aren't leaking mappings, as leaked mappings could
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// lead to a security hole
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void dart_assert_unmapped(unsigned int dart_id)
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{
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dart_t *dart;
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unsigned int i, j, k;
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dart_l2_tt_t *l2_tt;
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dart_ent *l3_tt_base;
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ASSERT(dart_id < NUM_DARTS);
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dart = &darts[dart_id];
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for (i = 0; i < DART_NUM_TTBR; i++) {
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// If the driver isn't tracking an L2 table under the given TTBR,
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// then, the TTBR needs to be 0
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l2_tt = dart->l2_tts[i];
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if (l2_tt == NULL) {
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RELEASE_ASSERT(rDART_TTBR(dart->regs, i) == 0);
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continue;
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}
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// For each L2 table, verify each entry is either 0 or points
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// to an L3 table filled with 0s
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for (j = 0; j < DART_TTE_PGENTRIES; j++) {
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l3_tt_base = l2_tt->l3_tt_bases[j];
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if (l3_tt_base != NULL) {
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for (k = 0; k < DART_TTE_PGENTRIES; k++) {
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RELEASE_ASSERT(l3_tt_base[k] == 0);
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}
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} else {
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RELEASE_ASSERT(l2_tt->tt_base[j] == 0);
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}
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}
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}
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}
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@@ -0,0 +1,117 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
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#ifndef DART_REGS_H
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#define DART_REGS_H
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#define DART_TT_PGSIZE 4096
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#define DART_TTE_SHIFT 3
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#define DART_TTE_PGENTRIES (DART_TT_PGSIZE >> DART_TTE_SHIFT)
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#define DART_TTE_VALID (1 << 0)
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#define DART_TTE_TABLE (1 << 1)
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#define DART_NUM_TTBR 4
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#define DART_NUM_SID 4
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#define rDART_TLB_OP(base) (*(volatile uint32_t *)((base) + 0x00))
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#define rDART_CONFIG(base) (*(volatile uint32_t *)((base) + 0x0c))
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#define rDART_DIAG_CONFIG(base) (*(volatile uint32_t *)((base) + 0x20))
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#define rDART_DIAG_BOGUS_ACCESS(base) (*(volatile uint32_t *)((base) + 0x24))
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#define rDART_BYPASS_ADDR(base) (*(volatile uint32_t *)((base) + 0x2c))
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#define rDART_FETCH_REQ_CONFIG(base) (*(volatile uint32_t *)((base) + 0x30))
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#define rDART_TTBR(base, idx) (*(volatile uint32_t *)((base) + 0x40 + 4 * (idx)))
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#define DART_TLB_OP_FLUSH (2)
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#define DART_TLB_OP_BUSY (1 << 3)
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#define DART_TLB_OP_SID_MASK0 (1 << 8)
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#define DART_TLB_OP_SID_MASK1 (1 << 9)
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#define DART_TLB_OP_SID_MASK2 (1 << 10)
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#define DART_TLB_OP_SID_MASK3 (1 << 11)
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#define DART_DIAG_CONFIG_PTE_FETCH_PROMOTE_QOS (1 << 8)
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#define DART_FETCH_REQ_CONFIG_STE(x) (((x) & 0xf) << 0)
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#define DART_FETCH_REQ_CONFIG_PTE(x) (((x) & 0xf) << 8)
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#define DART_FETCH_REQ_CONFIG_PTE_PREFETCH(x) (((x) & 0xf) << 16)
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#define DART_TTBR_VALID (1 << 31)
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#define DART_TTBR_SHIFT (12)
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/*
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* L1 Translation table (stored in registers)
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||||
*
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||||
* There are DART_NUM_TTBR entries in the L1 table
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||||
* DART_NUM_TTBR entries of 1GB (2^30) of address space.
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||||
*/
|
||||
#define DART_TT_L1_SIZE 0x0000000040000000ULL /* size of area covered by a tte */
|
||||
#define DART_TT_L1_OFFMASK 0x000000003fffffffULL /* offset within an L2 entry */
|
||||
#define DART_TT_L1_SHIFT 30
|
||||
#define DART_TT_L1_INDEX_MASK 0x0000000070000000ULL /* mask for getting index in L1 table from virtual address */
|
||||
|
||||
/*
|
||||
* L2 Translation table
|
||||
*
|
||||
* Each translation table is 4KB
|
||||
* 512 64-bit entries of 2MB (2^21) of address space.
|
||||
*/
|
||||
|
||||
#define DART_TT_L2_SIZE 0x0000000000200000ULL /* size of area covered by a tte */
|
||||
#define DART_TT_L2_OFFMASK 0x00000000001fffffULL /* offset within an L2 entry */
|
||||
#define DART_TT_L2_SHIFT 21 /* page descriptor shift */
|
||||
#define DART_TT_L2_INDEX_MASK 0x000000003fe00000ULL /* mask for getting index in L2 table from virtual address */
|
||||
|
||||
/*
|
||||
* L3 Translation table
|
||||
*
|
||||
* Each translation table is 4KB
|
||||
* 512 64-bit entries of 4KB (2^12) of address space.
|
||||
*/
|
||||
|
||||
#define DART_TT_L3_SIZE 0x0000000000001000ULL /* size of area covered by a tte */
|
||||
#define DART_TT_L3_OFFMASK 0x0000000000000fffULL /* offset within L3 PTE */
|
||||
#define DART_TT_L3_SHIFT 12 /* page descriptor shift */
|
||||
#define DART_TT_L3_INDEX_MASK 0x00000000001ff000ULL /* mask for page descriptor index */
|
||||
|
||||
/*
|
||||
* L3 Page table entries
|
||||
*
|
||||
* The following page table entry types are possible:
|
||||
*
|
||||
* fault page entry
|
||||
* 63 2 0
|
||||
* +------------------------------+--+
|
||||
* | ignored |00|
|
||||
* +------------------------------+--+
|
||||
*
|
||||
*
|
||||
* 63 52 51 36 35 12 11 8 7 6 2 1 0
|
||||
* +-----+------+----------------------+-----+-+-----+-+-+
|
||||
* | ign | zero | OutputAddress[35:12] | ign |W| ign |1|V|
|
||||
* +-----+------+----------------------+-----+-+-----+-+-+
|
||||
*
|
||||
* where:
|
||||
* 'W' Write orotect bit
|
||||
* 'V' Valid bit
|
||||
*/
|
||||
|
||||
#define DART_PTE_SHIFT 3
|
||||
#define DART_PTE_PGENTRIES (DART_TT_PGSIZE >> DART_PTE_SHIFT)
|
||||
|
||||
#define DART_PTE_EMPTY 0x0000000000000000ULL /* unasigned - invalid entry */
|
||||
|
||||
#define DART_PTE_TYPE_VALID 0x0000000000000003ULL /* valid L3 entry: includes bit #1 (counterintuitively) */
|
||||
|
||||
#define DART_PTE_PAGE_MASK 0x0000FFFFFFFFF000ULL /* mask for 4KB page */
|
||||
#define DART_PTE_PAGE_SHIFT 12 /* page shift for 4KB page */
|
||||
|
||||
#define DART_PTE_WRPROT(enable) ((enable) ? (1 << 7) : 0) /* write protect */
|
||||
|
||||
#endif // DART_REGS_H
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_DART=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/dart.o
|
||||
Reference in new issue
Block a user