cdnutter/iBoot
Archived
1
0 Fork 0
Code Issues Packages Projects Releases Wiki Activity

first and last commit

Browse Source
This commit is contained in:
Chris Nutter committed 2023-07-08 13:03:17 -07:00
commit 1bf4efd552
2612 files changed
+636500
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

drivers/apple/dcs/dcs.c
+542
View File
@@ -0,0 +1,542 @@
/*
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/*
* Driver for the LPDDR4 compatible DRAM Control Subsystem (DCS) block
*/
#include <debug.h>
#include <sys/menu.h>
#include <drivers/dcs/dcs_init_lib.h>
#include <drivers/dram.h>
#include <drivers/power.h>
#include <drivers/miu.h>
#include <lib/env.h>
#include <platform.h>
#include <platform/soc/hwclocks.h>
#include <platform/chipid.h>
#include <platform/memmap.h>
#include <platform/timer.h>
#include <sys.h>
#include <string.h>
void mcu_late_init(void)
{
}
uint32_t density_to_Gb(int density)
{
switch (density) {
case JEDEC_LPDDR4_DENSITY_4Gb:
return 4;
case JEDEC_LPDDR4_DENSITY_6Gb:
return 6;
case JEDEC_LPDDR4_DENSITY_8Gb:
return 8;
case JEDEC_LPDDR4_DENSITY_12Gb:
return 12;
case JEDEC_LPDDR4_DENSITY_16Gb:
return 16;
case JEDEC_LPDDR4_DENSITY_24Gb:
return 24;
case JEDEC_LPDDR4_DENSITY_32Gb:
return 32;
default:
panic("unknown LPDDR4 density %d", density);
}
}
static struct dcs_memory_device_info _dcs_device_info;
static bool _dcs_device_info_inited;
const struct dcs_memory_device_info *dcs_get_memory_device_info(void)
{
// if memory is not inited, device info is unknown, spin here ...
if (false == _dcs_device_info_inited)
panic("DCS Memory Device Info grab has jumped the gun");
return ((const struct dcs_memory_device_info *)&_dcs_device_info);
}
// Returns memory size per amcc block
uint64_t dcs_get_memory_size(void)
{
// if memory is not inited, density is unknown, spin here ...
if (false == _dcs_device_info_inited)
panic("DCS Memory Size grab has jumped the gun");
// device density (in MBytes) * ( / 2 due to x16 lpddr4 devices) * num of channels * num of ranks
return (density_to_Gb(_dcs_device_info.density) * (1024 / 8 / 2) * DCS_NUM_CHANNELS * DCS_NUM_RANKS);
}
uint32_t dcs_get_memory_info(void)
{
uint8_t config_id = 0;
// Read device info: vendor, revision, and configuration info
// Configuration info: device width, device type, device density
// We are assuming all of our devices are identical
dcs_mrcmd(MR_READ, 1, 1, 0x5, (uintptr_t)&_dcs_device_info.vendor_id);
dcs_mrcmd(MR_READ, 1, 1, 0x6, (uintptr_t)&_dcs_device_info.rev_id);
dcs_mrcmd(MR_READ, 1, 1, 0x7, (uintptr_t)&_dcs_device_info.rev_id2);
dcs_mrcmd(MR_READ, 1, 1, 0x8, (uintptr_t)&config_id);
if ((_dcs_device_info.vendor_id == 0) || (config_id == 0))
panic("failed to read vendor-id/config-id, vid:%08x, config:%08x, rev:%08x\n",
_dcs_device_info.vendor_id, config_id, _dcs_device_info.rev_id);
_dcs_device_info.width = (32 >> ((config_id >> JEDEC_MR8_WIDTH_SHIFT) & JEDEC_MR8_WIDTH_MASK)) >> 3;
_dcs_device_info.density = ((config_id >> JEDEC_MR8_DENSITY_SHIFT) & JEDEC_MR8_DENSITY_MASK);
_dcs_device_info.type = ((config_id >> JEDEC_MR8_TYPE_SHIFT) & JEDEC_MR8_TYPE_MASK);
_dcs_device_info_inited = true;
uint32_t device_size_Gbits = density_to_Gb(_dcs_device_info.density);
uint32_t total_size_Mbytes = dcs_get_memory_size();
dprintf(DEBUG_INFO, "sdram vendor id:0x%02x rev id:0x%02x rev id2:%02x\n",
_dcs_device_info.vendor_id, _dcs_device_info.rev_id, _dcs_device_info.rev_id2);
dprintf(DEBUG_INFO, "sdram config: width %d/%d Gbit/type %d\n", _dcs_device_info.width << 3,
device_size_Gbits, _dcs_device_info.type);
// Check against Hardware Register Min/Max
if (total_size_Mbytes < 128 || total_size_Mbytes > (16 * 1024) )
panic("unsupported DRAM density: %d Gbit (with Chan==%d x Rank==%d yields %d MB)",
device_size_Gbits, DCS_NUM_CHANNELS, DCS_NUM_RANKS, total_size_Mbytes);
return 0;
}
//================================================================================
void dcs_change_freq(uint32_t freq_bin)
{
// Change the MCU Clk Frequency to the new Frequency
dbgprintf(DCS_DBG_FREQ, "Changing Frequency to Bin %d\n", freq_bin);
// Make the actual Change by sending the appropriate message to the PMGR
uint32_t perf_level = (freq_bin == 0)? kPerformanceMemoryFull:
(freq_bin == 1)? kPerformanceMemoryMid:
(freq_bin == 3)? kPerformanceMemoryLow:
DCS_NONVAL;
if (perf_level == DCS_NONVAL) {
shim_panic("Unsupported Frequency Bin Request: %d\n", freq_bin);
}
clocks_set_performance(perf_level);
}
//================================================================================
void dcs_store_memory_calibration(void *cal_values, uint32_t cal_size)
{
// Save the calibration array to PMU nvram
#if 0
if (power_store_memory_calibration(cal_values, cal_size) == 0)
shim_panic("Unable to save memory calibration values to PMU nvram\n");
#endif
}
void dcs_load_memory_calibration(void *cal_values, uint32_t cal_size)
{
// Retrieve calibration array from PMU nvram
#if 0
if (power_load_memory_calibration(cal_values, cal_size) == 0)
shim_panic("Unable to load memory calibration values from PMU nvram\n");
#endif
}
// To dump calibration results from iBoot menu command
static int dump_mem_calibration_info(int argc, struct cmd_arg *args)
{
dcs_init_debug_enable(DCS_DBG_CAL);
debug_level_dcs = DEBUG_CRITICAL;
calibration_cfg_params_init(false, DCS_NUM_CHANNELS, DCS_NUM_RANKS);
calibration_dump_results(SELECT_CAL_ALL, false);
return 0;
}
MENU_COMMAND_DEBUG(memcal_info, dump_mem_calibration_info, "Prints memory calibration results", NULL);
//================================================================================
////////////////////////////////////////////////////////////
//
// DCS Init Sequence
// Incorporates these specs from SEG
// Maui: Init_A1.html dated Mar 2, 2015, Init_B0.html dated May 20, 2015, Init_B0_1200.html dated June 2, 2015, Init_1200.html dated Oct 29, 2015
// Elba: Init.html dated March 04, 2016, Init_A0.html dated July 14 15, 2015
// s8003: Init_A0.html dated May 20, 2015, Init_A0_1200.html dated June 17, 2015, Init_1200.html dated Oct 29, 2015
// M8: Init.html dated Apr 2, 2015
// Cayman: Init.html dated Feb 18, 2015
////////////////////////////////////////////////////////////
int32_t dcs_init(dcs_boottype_t boot_type)
{
uint32_t num_dcs = DCS_NUM_CHANNELS;
uint32_t num_rnk = DCS_NUM_RANKS;
dcs_config_params_t *param_table;
#ifndef DCS_RUN_AT_50MHZ
volatile uint32_t *cal_results_save_addr = (volatile uint32_t *) MEMORY_CALIB_SAVE_BASE_ADDR;
#if DCS_DO_CALIBRATION
struct amp_calibration_params *cal_cfg = NULL;
#endif // #if DCS_DO_CALIBRATION
#endif // #ifndef DCS_RUN_AT_50MHZ
dprintf(DEBUG_INFO, "dcs_init() ... !\n");
// Config our boot type and note the ChipID/Rev
if (!dcs_init_config(boot_type, platform_get_chip_id(), platform_get_chip_revision(),
num_dcs, num_rnk)) {
panic("DCS Init Config is NOT RIGHT");
}
dcs_init_debug_enable(DCS_DBG_OVERVIEW);
dcs_init_debug_enable(DCS_DBG_MILESTONE);
// dcs_init_debug_enable(DCS_DBG_REG_ACCESS);
// dcs_init_debug_enable(DCS_DBG_CHAN_DETAIL);
// dcs_init_debug_enable(DCS_DBG_SPIN);
// dcs_init_debug_enable(DCS_DBG_MR_READ);
// dcs_init_debug_enable(DCS_DBG_CAL);
dcs_init_debug_enable(DCS_DBG_CAL_MILESTONE);
dcs_init_debug_enable(DCS_DBG_FREQ);
// Initialize the DCS Parameter Table (uses platform-specific callout)
param_table = dcs_init_param_table();
// <rdar://problem/22429659> Maui/Malta/Elba: Reset DRAM during panic reboot in LLB to avoid problems with init sequence
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003 || SUB_PLATFORM_S8001
#if WITH_HW_POWER
int result;
uint8_t boot_stage;
// If we rebooted to save panic log, try resetting the DRAM to reset the FSP on the DRAM
result = power_get_nvram(kPowerNVRAMiBootErrorStageKey, &boot_stage);
// if we properly read the PMU NVRAM and it says we are booting to save panic log ...
if(result == 0 && boot_stage == kPowerNVRAMiBootStagePanicSave) {
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 0);
// Leave reset asserted for 200 us
delay_for_us(200);
dcs_reg_write_all_chan(rDCS_AMP_DRAM_RESETN(AMP_CA), 1);
// Wait 2 ms before starting mem init sequence
delay_for_us(2000);
}
#endif
#endif
//================================================================================
// Step 0: AMC Prolog
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 0, "Prolog");
dcs_init_Prolog();
//================================================================================
// Step 1: AMC Initial Configuration
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 1, "Initial AMC Config");
dcs_init_AMC_Initial_Config();
//================================================================================
// Step 2: AMP Initial Configuration
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 2, "AMP Initial Config");
dcs_init_AMP_Initial_Config();
//================================================================================
// Step 3: Self-Refresh Exit
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 3, "Self-Refresh Exit");
dcs_init_Self_Refresh_Exit_a();
if (izColdBoot && !izFPGA) {
// Change MCU Clk --> 50Mz
dcs_change_freq(3);
// Wait 5 us after Switch to 50MHz to avoid race condition
dcs_spin(5, "after 50MHz\n");
}
dcs_init_Self_Refresh_Exit_b();
//================================================================================
// Step 4: DRAM Reset, ZQ Calibration & Configuration (cold boot only)
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 4, "ZQ Calibration & Configuration");
dcs_init_ZQ_Cal_Cfg();
//================================================================================
// Step 5: Topology-specific configuration
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 5, "Memory Topology Config");
dcs_init_AddrCfg_Cfg();
dcs_get_memory_info();
uint32_t total_size_Mbytes = dcs_get_memory_size();
dcs_init_TotalSize_Cfg(total_size_Mbytes);
// DRAM vendor-specific workarounds
dcs_dram_workarounds(boot_type);
//================================================================================
// Step 6: Prepare for switch from boot-clock speed to normal operation speed
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 6, "Reenable_AMC_Scheduler");
dcs_init_Reenable_AMC_Scheduler();
#if DCS_RUN_AT_50MHZ
dprintf(DEBUG_CRITICAL, "DCS Init: memory frequency fixed to 50 MHz\n");
#else
#if DCS_DO_CALIBRATION
cal_cfg = calibration_cfg_params_init(izResume, num_dcs, num_rnk);
// Override the chip_id and chip_rev default values with actual values
cal_cfg->chip_id = platform_get_chip_id();
cal_cfg->chip_rev = platform_get_chip_revision();
// Coarse CS training disabled on Maui A0/A1
if(cal_cfg->chip_id == 0x8000 && cal_cfg->chip_rev < CHIP_REVISION_B0)
cal_cfg->disable_coarse_cs_training = true;
cal_cfg->clk_period_bin0 = param_table->freq[0].clk_period;
cal_cfg->clk_period_bin1 = param_table->freq[1].clk_period;
// Note if we will use Widest-Eye for calculating Optimal Vref
if (dcs_init_variant_enable(0) & DCS_VARIANT_VREF_USES_WIDEST) {
cal_cfg->opt_vref_mode = DCS_CAL_OPT_VREF_MODE_WIDEST;
}
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: Config Init'd\n");
#endif
// Only perform steps 7-10 if frequequency bucket 1 is supported
if(param_table->supported_freqs & DCS_FREQ(1)) {
//================================================================================
// Step 7: Setup registers for CA calibration for bucket 1
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 7, "CA Calibration Setup--800MHz");
dcs_init_CA_Cal_Setup_Freq1();
//================================================================================
// Step 8: AMP Dynamic CA Vref Timing Calibration at Vmin 800MHz
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 8, "CA Vref Calibration--800MHz, Vmin");
#if DCS_DO_CALIBRATION
// Use these values for 800MHz
cal_cfg->RL = 16;
cal_cfg->WL = 12;
// We will be calibrating for @800MHz (FreqBin 1)
cal_cfg->freq_bin = 1;
if (izColdBoot) {
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d CA Cal\n", cal_cfg->freq_bin);
calibrate_ca();
} else {
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d Cal Regs Restore\n", cal_cfg->freq_bin);
// Restore Calibration Parameters from PMU
calibration_save_restore_ca_wrlvl_regs(CALIB_RESTORE, num_dcs, cal_cfg->freq_bin);
}
#else
dbgprintf(DCS_DBG_MILESTONE, "DCS is Skipping Calibration, per Build Config\n");
#endif
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 8, "Post CA Vref Calibration");
dcs_init_CA_Cal_Freq1();
//================================================================================
// Step 9: Setup registers for DQ calibration for bucket 1
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 9, "DQ Calibration Setup--800MHz");
dcs_init_DQ_Cal_Setup_Freq1_a();
// Change MCU Clk --> bucket 1
if(!izFPGA)
dcs_change_freq(1);
dcs_init_DQ_Cal_Setup_Freq1_b();
//================================================================================
// Step 10: PHY write DQ calibration
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 10, "Wr DQ Cal--800MHz");
#if DCS_DO_CALIBRATION
if (izColdBoot) {
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d WrLvl\n", cal_cfg->freq_bin);
calibrate_wrlvl();
dcs_init_post_wrlvl();
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d Cal Regs Save\n", cal_cfg->freq_bin);
// Save Calibration Parameters (so far) to Memory Stash
calibration_save_restore_ca_wrlvl_regs(CALIB_SAVE, num_dcs, cal_cfg->freq_bin);
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d RdDQ Cal\n", cal_cfg->freq_bin);
calibrate_rddq();
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d WrDQ Cal\n", cal_cfg->freq_bin);
calibrate_wrdq();
}
#else
dbgprintf(DCS_DBG_MILESTONE, "DCS is Skipping Calibration, per Build Config\n");
#endif
dcs_init_wrdq_skew();
cal_results_save_addr = dcs_save_calibration_results(cal_results_save_addr, DCS_FREQ(1));
} // if(param_table->supported_freqs & DCS_FREQ1) {
//================================================================================
// Step 11: Setup registers for CA calibration for bucket 0
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 11, "CA Vref Calibration Setup--1200MHz");
dcs_init_CA_Cal_Setup_Freq0();
//================================================================================
// Step 12: AMP Dynamic CA Timing Calibration
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 12, "CA Vref Calibration--1200MHz, Vnom");
#if DCS_DO_CALIBRATION
if(param_table->freq[0].clk_period == CLK_PERIOD_1600) {
// Use these values for 1600MHz
cal_cfg->RL = 28;
cal_cfg->WL = 14;
} else if(param_table->freq[0].clk_period == CLK_PERIOD_800) {
// Use these values for 800MHz
cal_cfg->RL = 14;
cal_cfg->WL = 12;
} else {
// Use these values for 1200MHz
cal_cfg->RL = 24;
cal_cfg->WL = 12;
}
// We will be calibrating for FreqBin 0
cal_cfg->freq_bin = 0;
if (izColdBoot) {
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d CA Cal\n", cal_cfg->freq_bin);
calibrate_ca();
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003
dcs_dram_workarounds_step12();
#endif
}
#else
dbgprintf(DCS_DBG_MILESTONE, "DCS is Skipping Calibration, per Build Config\n");
#endif
//================================================================================
// Step 13: Setup registers for DQ calibration for bucket 0
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 13, "DQ Calibration Setup--1200MHz");
dcs_init_DQ_Cal_Setup_Freq0_a();
// Change MCU Clk --> bucket 0
if(!izFPGA)
dcs_change_freq(0);
dcs_init_DQ_Cal_Setup_Freq0_b();
//================================================================================
// Step 14: AMP Dynamic DQ Calibration
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 14, "Wr DQ Cal--1200MHz, Vmin");
#if DCS_DO_CALIBRATION
if (izColdBoot) {
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d WrLvl\n", cal_cfg->freq_bin);
calibrate_wrlvl();
dcs_init_post_wrlvl();
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d Cal Regs Save\n", cal_cfg->freq_bin);
// Save Calibration Parameters (all the rest) to Memory Stash & then copy Stash to PMU
calibration_save_restore_ca_wrlvl_regs(CALIB_SAVE, num_dcs, cal_cfg->freq_bin);
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d RdDQ Cal\n", cal_cfg->freq_bin);
calibrate_rddq();
dbgprintf(DCS_DBG_CAL_MILESTONE, "DCS Cal: FreqBin %d WrDQ Cal\n", cal_cfg->freq_bin);
calibrate_wrdq();
// Save off any applicable freq 0 registers
cal_results_save_addr = dcs_save_calibration_results(cal_results_save_addr, DCS_FREQ(0));
}
#else
dbgprintf(DCS_DBG_MILESTONE, "DCS is Skipping Calibration, per Build Config\n");
#endif
#endif // #if DCS_RUN_AT_50MHZ ... #else
//================================================================================
// Step 15: Setup Registers for Boot
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 15, "Setup Registers for Boot");
dcs_init_Reg_for_Boot();
//================================================================================
// Step 16: Enable Other Features
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 16, "Enable Other Features");
dcs_init_MoreFeatures();
//================================================================================
// Step 17: Enable Fast Critical Word Forwarding Feature
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 17, "Fast Critical Word Forwarding");
dcs_init_Fast_Critical_Word_Forwarding();
//================================================================================
// Step 18: Enable Power- and Clock-Gating Features; Config MCC and Global Timers
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 18, "Gating and Global Timers");
dcs_init_Gating_Global_Timers();
//================================================================================
// Step 19: ODTS read & set interval for periodic MR4 on-die Temp sensor reading
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Step %2d: %s\n", 19, "ODTS & Die Temp");
dcs_init_ODTS();
// rdar://problem/23244578, <rdar://problem/23355941>: Allow zqctimer value to be saved at this point to reconfig sequence
#if SUB_PLATFORM_S8000 || SUB_PLATFORM_S8003 || SUB_PLATFORM_S8001
#ifndef DCS_RUN_AT_50MHZ
cal_results_save_addr = dcs_save_calibration_results(cal_results_save_addr, 0);
#endif
#endif
//================================================================================
// Program tunables at the end
//================================================================================
dbgprintf(DCS_DBG_MILESTONE, "DCS Init Tunables\n");
dcs_init_apply_tunables();
//================================================================================
// Restore clock frequency to bucket 1 if it is supported
//================================================================================
if(!izFPGA)
if(param_table->supported_freqs & DCS_FREQ(1))
dcs_change_freq(1);
// cache memory info for later
platform_set_memory_info_with_revids(_dcs_device_info.vendor_id, dcs_get_memory_size(), _dcs_device_info.rev_id, _dcs_device_info.rev_id2);
dbgprintf(DCS_DBG_MILESTONE, "DCS Init DONE!!\n");
return 0;
}
//================================================================================
drivers/apple/dcs/dcs_calibration.c
+5070
View File
File diff suppressed because it is too large. Load diff
drivers/apple/dcs/dcs_calibration_v2.c
+5106
View File
File diff suppressed because it is too large. Load diff
drivers/apple/dcs/dcs_init_lib.c
+403
View File
@@ -0,0 +1,403 @@
/*
* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
/*
* Init Sequence Library for use in:
* Driver for the LPDDR4 compatible DRAM Control Subsystem (DCS) block
*/
/*
Summary of Steps from the Spec (Spreadsheet)
+ (Aa) Steps 0,1,2,3a [need to identify parameterization]
+ (Ab) Step 3b [PMGR: set Freq to 50MHz & delay-wait]
+ (Ac) Steps 3c,4,5 [need to identify parameterization]
+ (B) Step 6 [Change Clk Speed]
+ (C) Step 7 [include delay-wait from early Step 8]
+ (D) Step 8a [Cal: CA 800MHz Vmin]
+ (E) Step 8b [Write Regs]
+ (F) Step 8c [Cal: CA 800MHz Vmin] (...again? should it be CS?)
+ (G) Step 8d [Write Regs]
+ (H) Step 9 [Write Regs]
+ (I) Step 10 [Cal: WrLvl, RdDq, WrDq 800MHz Vmin]
+ (J) Step 11 [Write Regs]
+ (K) Step 12 [Cal: CA 1200MHz Vnom]
+ (L) Step 13 [Write Regs]
+ (M) Step 14 [Cal: WrLvl, RdDq, WrDq 1200MHz Vmin]
+ (N) Steps 15,16,17,18,19,20 [need to identify parameterization]
Between these steps there is possibly a need/desire for:
- Frequency Changes (PMGR)
- PMU save/restore
- debug messages
- register dumps (DV, SiVal)
- anything else!
CONFIG Table:
Compile-Time Known:
Type of Execution Environment CoreOS, DV, SiVal
Type of Target SoC, FPGA, Palladium
ChipID 0x8000, 0x8001, etc.
Revision A0, B0, B1, etc.
Num DCS 4, 8, etc. (Derived...!)
Variant Flags Work-arounds, RADAR Ref., et al.
(Config Info know at Compile time can be subject to #if)
Run-Time Known:
Type of Init ColdBoot, AOP_DDR, AOP_AWAKE
Debug Flags Low-Level, Milestone, et al.
RegValue Table
Much like today's: various values for various registers
Sensitive to ChipID (also Target type?)
(Internal static alloc (Complete Table Fill-in within Init function):
Fill in Values (per ChipID/Rev & Target-type)
return pointer to caller
(Allows customization by caller before use)
TODO:
- Convert to using SPDS for register names, et al
*/
//================================================================================
// API Definitions
#include <drivers/dcs/dcs_init_lib.h>
dcs_config_t dcs_cfg;
extern dcs_config_params_t dcs_params;
#if izIBOOT
int debug_level_dcs = DEBUG_SPEW;
#endif
//================================================================================
// Configure the Library for use for the current Boot Type, Chip Type, etc.
//================================================================================
bool dcs_init_config(dcs_boottype_t boot_type, uint32_t chipID, uint32_t chipRev,
uint32_t num_dcs, uint32_t num_rank)
{
dcs_cfg.valid = false;
// TODO: Get a little noisy about failures in this function
// Validate that Build Environment is one that we support
if (!(izIBOOT || izSIVAL || izDV || izPERTOS)) {
return false;
}
// Validate that Target Type is one that we support
if (!(izSOC || izFPGA || izPAL))
return false;
dcs_cfg.boot_type = boot_type;
// Validate that the Boot Type is one that we support
if (!(izColdBoot || izResume || izAOP_DDR || izAOP_Awake))
return false;
// Validate that we can support the requested number of channels/ranks
if ((num_dcs > DCS_NUM_CHANNELS) || (num_rank > DCS_NUM_RANKS))
return false;
#if izIBOOT
// Validate the Chip ID provided against the actual (only for iBoot)
if (chipID != platform_get_chip_id())
return false;
#endif
dcs_cfg.chipID = chipID;
dcs_cfg.chipRev = chipRev;
dcs_cfg.num_dcs = num_dcs;
dcs_cfg.num_rank = num_rank;
dcs_cfg.debugBitz = DCS_DBG_DEFAULT; // Default include Overview
dcs_cfg.variantBitz = DCS_VARIANT_NONE; // Default: No variant flags enabled
#if 1 // Very useful indicator that we have built this library correctly
dbgprintf(DCS_DBG_OVERVIEW, "DCS Init Lib Built for: "
#if izIBOOT
"iBoot "
#endif
#if izSIVAL
"SiVal "
#endif
#if izDV
"DV "
#endif
#if izPERTOS
"PERTOS "
#endif
#if izSOC
"SOC"
#endif
#if izFPGA
"FPGA"
#endif
#if izPAL
"PAL"
#endif
"\n");
#endif
dbgprintf(DCS_DBG_OVERVIEW,
"DCS Init [%s Build] for ChipID==0x%04x chipRev %c%c (#DCS==%d, #Rank==%d) [%s] using %s\n",
(izIBOOT)? "iBoot":(izSIVAL)? "SiVal":(izDV)? "DV":(izPERTOS)? "PERTOS":"??Build??",
chipID, ((chipRev >> 4) & 0xF) + 'A', ((chipRev >> 0) & 0xF) + '0',
dcs_cfg.num_dcs, dcs_cfg.num_rank,
(izSOC)? "SoC":(izFPGA)? "FPGA":(izPAL)? "Palladium":"??Target??",
(izColdBoot)? "Coldboot":(izResume)? "Resume":(izAOP_DDR)? "AOP_DDR":(izAOP_Awake)? "AOP_Awake":"??BootType??");
// We're good to go!
dcs_cfg.valid = true;
return dcs_cfg.valid;
}
//================================================================================
// Alter the Debug or the Variant Bits, returning the value-before-modifcation
//================================================================================
uint32_t dcs_init_debug_enable(uint32_t bit)
{
uint32_t ret = dcs_cfg.debugBitz;
dcs_cfg.debugBitz |= bit;
return ret;
}
uint32_t dcs_init_debug_disable(uint32_t bit)
{
uint32_t ret = dcs_cfg.debugBitz;
dcs_cfg.debugBitz &= ~bit;
return ret;
}
uint32_t dcs_init_variant_enable(uint32_t bit)
{
uint32_t ret = dcs_cfg.variantBitz;
dcs_cfg.variantBitz |= bit;
return ret;
}
uint32_t dcs_init_variant_disable(uint32_t bit)
{
uint32_t ret = dcs_cfg.variantBitz;
dcs_cfg.variantBitz &= ~bit;
return ret;
}
//================================================================================
// Set up the Config Parameter Table (specifc to Platform, using target type)
//================================================================================
dcs_config_params_t *dcs_init_param_table(void)
{
// Call (platform-specific) function to initialize values to be used during DCS Init
dcs_init_config_params(&dcs_params, DCS_TARGET_TYPE);
// Return pointer to the table
// (allows caller to optionally modify values for possible experimentation)
return &dcs_params;
}
//================================================================================
// Basic Register Write/Poll Functions, including MR Cmds
//================================================================================
void dcs_reg_write(uintptr_t reg_addr, uint32_t reg_value)
{
dbgprintf(DCS_DBG_REG_ACCESS, "DCS Init REG(%p) <- 0x%08X (Single-Reg-Write)\n",
(void *)reg_addr, reg_value);
DCS_REG_ACCESS(reg_addr) = reg_value;
}
void dcs_reg_poll(uintptr_t reg_addr, uint32_t mask_value, uint32_t required_value)
{
dbgprintf(DCS_DBG_REG_ACCESS, "DCS Init REG(%p) Poll: Mask (0x%08X) == 0x%08x (Single-Reg-Poll)\n",
(void *)reg_addr, mask_value, required_value);
SPIN_W_TMO_WHILE((DCS_REG_ACCESS(reg_addr) & mask_value) != required_value);
}
void dcs_reg_write_all_chan(uintptr_t reg_addr, uint32_t reg_value)
{
uint32_t channel;
dbgprintf(DCS_DBG_REG_ACCESS, "DCS Init REG(%p) <- 0x%08X (x%d)",
(void *)reg_addr, reg_value, dcs_cfg.num_dcs);
for(channel = 0; channel < dcs_cfg.num_dcs; channel++) {
DCS_REG_ACCESS(reg_addr + (channel * DCS_SPACING)) = reg_value;
dbgprintf(DCS_DBG_CHAN_DETAIL, "%d ", channel);
}
dbgprintf(DCS_DBG_REG_ACCESS, "\n");
}
void dcs_reg_poll_all_chan(uintptr_t reg_addr, uint32_t mask_value, uint32_t required_value)
{
uint32_t channel;
dbgprintf(DCS_DBG_REG_ACCESS, "DCS Init REG(%p) Poll: Mask (0x%08X) == 0x%08x ...",
(void *)reg_addr, mask_value, required_value);
for(channel = 0; channel < dcs_cfg.num_dcs; channel++) {
dbgprintf(DCS_DBG_CHAN_DETAIL, " %d", channel);
SPIN_W_TMO_WHILE((DCS_REG_READ_CH(channel, reg_addr) & mask_value) != required_value);
dbgprintf(DCS_DBG_CHAN_DETAIL, "!");
}
dbgprintf(DCS_DBG_REG_ACCESS, "\n");
}
// To determine whether to use dcs_reg_write_all_chan or dcs_reg_write,
// because regs within a dcs hw block will be duplicated per channel, while those outside the block will not
bool dcs_reg_is_outside_dcs_block(uintptr_t reg_addr)
{
if((reg_addr >= DCS_BASE_ADDR) && (reg_addr < (DCS_BASE_ADDR + DCS_SPACING)))
return false;
return true;
}
// Only send the cmd to specific channel and rank (no poll afterward)
static void dcs_mrcmd_send_specific_ch_rnk(uint32_t cmd, uint8_t channel, uint8_t rank)
{
cmd |= (rank << MRCMD_RANK_SHIFT);
rDCS_MCU_MRINITCMD(channel) = cmd;
}
// Only poll the specific channel and rank (return cmd word)
static uint32_t dcs_mrcmd_poll_specific_ch_rnk(uint32_t cmd, uint8_t channel, uint8_t rank)
{
SPIN_W_TMO_WHILE((cmd = rDCS_MCU_MRINITSTS(channel)) & MRCMD_POLL_BIT);
return cmd;
}
// Only send the cmd to specific channel and rank
static uint32_t dcs_mrcmd_to_specific_ch_rnk(uint32_t cmd, uint8_t channel, uint8_t rank)
{
dcs_mrcmd_send_specific_ch_rnk(cmd, channel, rank);
return dcs_mrcmd_poll_specific_ch_rnk(cmd, channel, rank);
}
// Send the cmd to channel and rank as indicated (used during calibration on H6 and later)
static uint32_t dcs_form_mrcmd_word(dcs_mrcmd_op_t op, int reg, uintptr_t val)
{
uint32_t cmd;
if (op == MR_READ)
cmd = MRCMD_TYPE_READ | (reg << MRCMD_REG_SHIFT);
else if (op == MR_WRITE)
cmd = MRCMD_TYPE_WRITE | (reg << MRCMD_REG_SHIFT) | (((uint32_t)val) << MRCMD_DATA_SHIFT);
// MPC
else
cmd = MRCMD_TYPE_MPC | (reg << MRCMD_REG_SHIFT) | (((uint32_t)val) << MRCMD_DATA_SHIFT);
return cmd;
}
// Send the cmd to channel and rank as indicated (used during calibration on H6 and later)
void dcs_mrcmd_to_ch_rnk(dcs_mrcmd_op_t op, uint8_t channel, uint8_t rank, int reg, uintptr_t val)
{
uint32_t cmd, regval;
uint8_t *buffer = (uint8_t *) val;
cmd = dcs_form_mrcmd_word(op, reg, val);
regval = dcs_mrcmd_to_specific_ch_rnk(cmd, channel, rank);
if (op == MR_READ) {
dbgprintf(DCS_DBG_MR_READ, " [data==0x%02x] ", (regval >> MRCMD_DATA_SHIFT) & 0xff);
*buffer++ = (regval >> MRCMD_DATA_SHIFT) & 0xff;
}
}
void dcs_mrcmd(dcs_mrcmd_op_t op, uint8_t channels, uint8_t ranks, int reg, uintptr_t val)
{
uint8_t ch, r;
uint32_t cmd, regval;
uint8_t *buffer = (uint8_t *) val;
cmd = dcs_form_mrcmd_word(op, reg, val);
dbgprintf(DCS_DBG_REG_ACCESS, "DCS Init MRCMD(0x%08X)[%dx chan][%dx rank]",
cmd, channels, ranks);
dbgprintf(DCS_DBG_CHAN_DETAIL, " SEND: ");
for (ch = 0; ch < channels; ch++) {
for (r = 0; r < ranks; r++) {
dbgprintf(DCS_DBG_CHAN_DETAIL, "->%d%d ", ch, r);
dcs_mrcmd_send_specific_ch_rnk(cmd, ch, r);
}
}
dbgprintf(DCS_DBG_CHAN_DETAIL, " POLL: ");
for (ch = 0; ch < channels; ch++) {
for (r = 0; r < ranks; r++) {
regval = dcs_mrcmd_poll_specific_ch_rnk(cmd, ch, r);
dbgprintf(DCS_DBG_CHAN_DETAIL, "%d%d! ", ch, r);
if (op == MR_READ) {
dbgprintf(DCS_DBG_MR_READ, " [data==0x%02x] ", (regval >> MRCMD_DATA_SHIFT) & 0xff);
*buffer++ = (regval >> MRCMD_DATA_SHIFT) & 0xff;
}
}
}
dbgprintf(DCS_DBG_REG_ACCESS, "\n");
}
//================================================================================
// Utility Functions
//================================================================================
void dcs_spin(uint32_t duration_us, char *reason)
{
if (reason == NULL) reason = "";
dbgprintf(DCS_DBG_SPIN, "DCS Init Spin %d us %s\n", duration_us, reason);
delay_for_us(duration_us);
}
//================================================================================
// Apply Tunables (uses callout that is specifc to Platform)
//================================================================================
void dcs_init_apply_tunables(void)
{
volatile uintptr_t regptr = 0;
uint32_t regval;
uint32_t i,numtune = 0;
const struct dcs_tunable *dcs_tune;
dcs_tune = dcs_init_tunable_table(&numtune);
// Check that we have a table
if ((dcs_tune == NULL) || (numtune == 0))
return;
for (i = 0; i < numtune; i++, dcs_tune++) {
// end of list?
if (dcs_tune->reg == 0)
break;
// Check if we are now looking at a new register
if (dcs_tune->reg != regptr) {
// Write out regval to previous register (if there was one)
if (regptr) {
if(dcs_reg_is_outside_dcs_block(regptr))
dcs_reg_write(regptr, regval);
else
dcs_reg_write_all_chan(regptr, regval);
}
// read in the current register value (READ from CHAN zero, write to ALL CHAN)
regptr = dcs_tune->reg;
regval = *((uint32_t *)regptr);
}
// Modify the regval for the Bits indicated in the Mask
regval &= ~dcs_tune->mask;
regval |= dcs_tune->value;
}
// (Final) Write out regval to previous register (if there was one)
if (regptr) {
if(dcs_reg_is_outside_dcs_block(regptr))
dcs_reg_write(regptr, regval);
else
dcs_reg_write_all_chan(regptr, regval);
}
#if SUB_PLATFORM_S8001
if (dcs_cfg.chipRev < CHIP_REVISION_B0)
{
dcs_reg_write_all_chan(rDCS_MCU_ROWHAM_CTL(1), 0x4A3822D4);
}
#endif
}
drivers/apple/dcs/include/drivers/dcs/dcs.h
+213
View File
@@ -0,0 +1,213 @@
/*
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __DCS_H
#define __DCS_H
#include <sys/types.h>
/* DRAM Control Subsystem (DCS) */
#define DCS_MAX_FREQUENCY_SLOTS 4
#define DCS_NUM_FREQCHNGCTLREGS 6
#define DCS_FREQ(n) (1 << n)
#define EXEC(_instructions) do { _instructions ; } while(0)
#define __abs(x) (((x) < 0) ? -(x) : (x))
typedef enum {
DCS_BOOT_COLDBOOT,
DCS_BOOT_RESUME, // "Classic Resume" is (AOP_DDR | AOP_AWAKE)
DCS_BOOT_AOP_DDR,
DCS_BOOT_AOP_AWAKE,
} dcs_boottype_t;
typedef enum {
MR_READ,
MR_WRITE,
MR_MPC
} dcs_mrcmd_op_t;
struct dcs_per_freq {
uint32_t clk_period;
uint32_t freqchngctl[DCS_NUM_FREQCHNGCTLREGS];
uint32_t freqchngtim;
uint32_t lat;
uint32_t phyrdwrtim;
uint32_t caspch;
uint32_t act;
uint32_t autoref;
uint32_t selfref;
uint32_t pdn;
uint32_t derate;
uint32_t lat2;
uint32_t tat;
uint32_t mifqmaxctrl;
uint32_t nondqdspd;
uint32_t nondqds;
uint32_t cavref;
uint32_t odt_enable;
uint32_t dqds;
uint32_t dqdqsds;
uint32_t dqvref;
uint32_t cadficaltiming;
uint32_t dqdficaltiming;
uint32_t rddqcalwindow;
uint32_t wrdqcalwindow;
uint32_t caoutdllscl;
uint32_t dqsindllscl;
uint32_t rdcapcfg;
uint32_t autoref2;
};
typedef struct dcs_config_params {
uint32_t flags;
uint32_t supported_freqs;
uint32_t num_freqchngctl_regs;
uint32_t spllctrl_vco_1;
uint32_t spllctrl_vco_2;
uint32_t wrdqcalvrefcodecontrol;
uint32_t rddqcalvrefcodecontrol;
uint32_t rwcfg;
uint32_t phyupdatetimers;
uint32_t dllupdtctrl;
uint32_t dllupdtctrl1;
uint32_t pdn1;
uint32_t modereg;
uint32_t modereg1;
uint32_t autoref_params;
uint32_t autoref_params2;
uint32_t pdn;
uint32_t rnkcfg;
uint32_t cackcswkds;
uint32_t dqspdres;
uint32_t casdllupdatectrl;
uint32_t dqsdllupdatectrl;
uint32_t rdsdllctrl_step2;
uint32_t wrdqdqssdllctrl_step2;
uint32_t cawrlvlsdllcode;
uint32_t dlllocktim;
uint32_t dficaltiming;
uint32_t rdwrdqcaltiming_f0;
uint32_t rdwrdqcalseglen_f0;
uint32_t rdwrdqcaltiming_f1;
uint32_t rdwrdqcalseglen_f1;
uint32_t rdwrdqcaltiming_f3;
uint32_t rdwrdqcaltimingctrl1;
uint32_t rdwrdqcaltimingctrl2;
uint32_t rddqcalpatprbs4i;
uint32_t wrdqcalpatprbs4i;
uint32_t maxrddqssdllmulfactor;
uint32_t maxwrdqssdllmulfactor;
uint32_t dllupdtintvl;
uint32_t dcccontrol;
uint32_t dcccal;
uint32_t cbdrivestr;
uint32_t cbioctl;
uint32_t ckdrivestr;
uint32_t ckioctl;
uint32_t b0drivestr;
uint32_t b0ioctl;
uint32_t b0odt;
uint32_t b0odtctrl;
uint64_t b0dyniselasrtime;
uint64_t b0dynisel;
uint64_t b1dynisel;
uint32_t b1drivestr;
uint32_t b1ioctl;
uint32_t b1odt;
uint32_t b1odtctrl;
uint32_t dqs0drivestr;
uint32_t dqs0ioctl;
uint32_t dqs0odt;
uint32_t dqs0odtctrl;
uint32_t dqs0zdetbiasen;
uint32_t dqs1drivestr;
uint32_t dqs1ioctl;
uint32_t dqs1odt;
uint32_t dqs1odtctrl;
uint32_t dqs1zdetbiasen;
uint32_t zcalfsm0;
uint32_t zcalfsm1;
uint32_t spare0;
uint32_t hwrddqcaltvref;
uint32_t hwwrdqcaltvref;
uint32_t arefparam;
uint32_t odtszqc;
uint32_t longsr;
uint32_t freqchngctl_step3;
uint32_t mr3cmd;
uint32_t mr13cmd;
uint32_t addrcfg;
uint32_t aiuprtbaddr;
uint32_t chnldec;
uint32_t arefparam2;
uint32_t mr13cmd_step7;
uint32_t mr3cmd_step7;
uint32_t mr22cmd;
uint32_t mr11cmd;
uint32_t mr13cmd_step9;
uint32_t freqchngctl_step9;
uint32_t dqs0wkpupd;
uint32_t dqs1wkpupd;
uint32_t mr13cmd_step11;
uint32_t mr2cmd_step11;
uint32_t mr1cmd_step11;
uint32_t mr3cmd_step11;
uint32_t mr22cmd_step11;
uint32_t mr11cmd_step11;
uint32_t mr12cmd_step11;
uint32_t mr14cmd_step11;
uint32_t mr13cmd_step13;
uint32_t mr13cmd_step15;
uint32_t freqchngctl_step15;
uint32_t rdsdllctrl_step15;
uint32_t odtszqc2;
uint32_t qbren_step16;
uint32_t qbrparam;
uint32_t qbren;
uint32_t mccgen;
uint32_t caampclk;
uint32_t dqampclk;
uint32_t pwrmngten;
uint32_t odtszqc3;
struct dcs_per_freq freq[DCS_MAX_FREQUENCY_SLOTS];
} dcs_config_params_t;
typedef struct dcs_tunable {
volatile uintptr_t reg;
uint32_t mask;
uint32_t value;
} dcs_tunable_t;
struct dcs_memory_device_info {
uint32_t vendor_id;
uint32_t rev_id;
uint32_t rev_id2;
uint32_t type;
uint32_t width; // Device width in Bytes
uint32_t density; // Device density in MBytes
};
// to write the same value to the register in all channels
void dcs_reg_write_all_chan(uintptr_t reg_addr, uint32_t reg_value);
bool dcs_reg_is_outside_dcs_block(uintptr_t reg_addr);
void dcs_mrcmd(dcs_mrcmd_op_t op, uint8_t channels, uint8_t ranks, int32_t reg, uintptr_t val);
void dcs_enable_slow_boot (bool enable);
void dcs_enable_autorefresh(void);
uint64_t dcs_get_memory_size(void);
const struct dcs_memory_device_info *dcs_get_memory_device_info(void);
volatile uint32_t *dcs_save_calibration_results(volatile uint32_t *save_region, uint32_t freq);
void dcs_restore_calibration_results(volatile uint32_t *save_region);
void dcs_lock_down_mcc(void);
int32_t dcs_init(dcs_boottype_t boot_type);
#endif /* ! __DCS_H */
drivers/apple/dcs/include/drivers/dcs/dcs_cal.h
+233
View File
@@ -0,0 +1,233 @@
/*
* Copyright (C) 2013-2014 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef _DCS_CAL_H
#define _DCS_CAL_H
#define AMP_FREQUENCY_SLOTS (4)
/* _t: type, DQ0, DQ1, or CA */
/* _c: channel, 0 or 1 */
#define AMP_CA (0)
#define AMP_DQ0 (1)
#define AMP_DQ1 (2)
#define rAMP_AMPEN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x000)
#define rAMP_AMPCLK(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x004)
#define rAMP_AMPINIT(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x008)
#define rAMP_AMPVER(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x00C)
#define rAMP_IMPCODE(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x080)
#define rAMP_IMPOVRRD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x084)
#define rAMP_IMPAUTOCAL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x088)
#define rAMP_IMPCALPHYUPDT(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x08C)
#define rAMP_IMPCALCMD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x090)
#define rAMP_DRAMSIGDLY(_t,_c,_n) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x094 + ((_n) * 4))
#define rAMP_NONDQDS(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x098)
#define rAMP_DQDQSDS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x09C)
#define rAMP_DIFFMODE_FREQ(_t,_c,_f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x0A0 + ((_f) * 4))
#define rAMP_DQFLTCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x0B0)
#define rAMP_DQSPDENALWYSON(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x110)
#define rAMP_DQSPDRES(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x114)
#define rAMP_RDFIFOPTRSTS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x118)
#define rAMP_CALDQMSK(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x11C)
#define rAMP_DQTRNCFG(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x124 - ((_t >> 1) * 0x10))
#define rAMP_DQTRNCMD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x128 - ((_t >> 1) * 0x10))
#define rAMP_DQTRNSTS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x12C - ((_t >> 1) * 0x10))
#define rAMP_DLLEN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x180)
#define rAMP_MDLLOVRRD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x188 + ((_t >> 1) * 4))
#define rAMP_DLLLOCKTIM(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x198)
#define rAMP_DLLLOCKCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x19C)
#define rAMP_DLLUPDTINTVL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x1A0)
#define rAMP_DLLUPDTCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x1A4)
#define rAMP_DLLSTS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x1A8)
#define rAMP_DQSINDLLSCL_FREQ(_t,_c,_f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x1C0 + ((_f) * 4))
#define rAMP_CAOUTDLLSCL_FREQ(_c,_f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x1C0 + ((_f) * 4))
// <rdar://problem/13919568>
#define rAMP_TESTMODE(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x200 + ((_t >> 1) * 0x180))
#define rAMP_CKEDESKEW_CTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x52C)
#define rAMP_DQWRLVLDLYCHAINCTRL(_t,_c,_b) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x704 + ((_b)*0x04))
#define rAMP_DQWRLVLRUN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x714)
#define rAMP_DQWRLVLDATA(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x718)
#define rAMP_CACALMASK(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x804)
#define rAMP_CACALCABYTESEL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x808)
#define rAMP_CACALCAMAP0(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x80C)
#define rAMP_CACALCAMAP1(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x810)
#define rAMP_CACALCAMAP2(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x814)
//#define rAMP_CACALRUN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x838 + ((_t >> 1) * 0xEC))
// CP : Maui Change
//#define rAMP_CACALRESULT(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x83C)
#define rAMP_CAPHYUPDTREQ(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0xB00)
#define rAMP_CAPHYUPDTSTATUS(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0xB04)
#define rAMP_DLLUPDTCMD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x18C)
// Some bit definitions
// CP : Maui Change
#define CACALRUN_CACALMODE 1
#define rAMP_CACACALVREF(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x908)
#define rAMP_CACALBITSELECT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x918)
#define CS_TRAINING 0
#define CA_TRAINING 1
#define CS_FINE_TRAINING 2
#define RUN_DLL_UPDT 0
#define CACALRUN_RUNCACALENTRY (1 << 0)
#define CACALRUN_RUNCACALCS (1 << 4)
#define CACALRUN_RUNCACALCA (1 << 8)
#define CACALRUN_RUNCACALEXIT (1 << 12)
#define CACALRUN_RUNCACALVREF (1 << 16)
#define rAMP_CACALRESULT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x91C)
#define rAMP_CACALRUN(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x924)
#define rAMP_CACALCTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x900)
#define rAMP_CACALCTRL2(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x904)
#define rAMP_CACALCTRL3(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x928)
#define rAMP_CACALPAT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x90C)
#define rAMP_CASDLLCTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x700)
#define rAMP_CASDLLCODE(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x704)
#define rAMP_CKSDLLCTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x710)
#define rAMP_CKSDLLCODE(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x714)
#define rAMP_CSSDLLCTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x708)
#define rAMP_CSSDLLCODE(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x70C)
#define rAMP_AMPCACALENTRYCMD(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x910)
#define rAMP_AMPCACALEXITCMD(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x914)
#define rAMP_MDLLCODE(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x194)
#define rAMP_CKDESKEW_CTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x51C)
#define rAMP_CADESKEW_CTRL(_c,_d) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x500 + ((_d)*4))
#define rAMP_CSDESKEW_CTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x518)
#define rAMP_RDWRDQCALLOOPCNT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE20)
#define rAMP_RUNRDDQCAL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE58)
#define rAMP_CALPATCFG(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x110)
#define rAMP_DQSDLLCTRL_RD(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x608)
#define rAMP_DQSDLLCODE_RD(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x60C)
#define rAMP_RDDQDESKEW_CTRL(_b,_c,_d) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x428 + ((_d)*4))
#define rAMP_RDDQSDESKEW_CTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x448)
#define rAMP_RDDMDESKEW_CTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x44C)
#define rAMP_DQCALCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x900)
#define rAMP_DQCALRUN(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE58)
#define rAMP_DQCALRESULT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE5C)
#define rAMP_RDCLKDLYSEL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x618)
#define rAMP_RDDQCALPAT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE2C)
#define rAMP_RdWrDqCalTiming_f0(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE00)
#define rAMP_RdWrDqCalTiming_f1(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE08)
#define rAMP_RdWrDqCalTiming_f2(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE10)
#define rAMP_RdWrDqCalTiming_f3(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE18)
#define rAMP_RdWrDqCalTimingCtrl2(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE28)
#define rAMP_RDDQCALVREF_f0(_t, _c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0xB00)
#define rAMP_RDDQCALVREF_f1(_t, _c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0xB04)
#define rAMP_CAWRLVLSDLLCODE(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x800)
#define rAMP_CAWRLVLENTRYCMD(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xB00)
#define rAMP_CAWRLVLEXITCMD(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xB04)
#define rAMP_CAWRLVLTIM(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xB08)
#define rAMP_CARUNWRLVL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xB0C)
#define rAMP_CAWRLVLRESULT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xB10)
#define rAMP_AMPSDQIOCFG_DQFLTCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0xA4)
#define rAMP_DQWRLVLSDLLCODE(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x704)
#define rAMCX_DRAMCFG_FREQCHNGMRWCNT(_c) (DCS_BASE_ADDR + ((_c)*DCS_SPACING) + 0x44C)
#define rAMCX_DRAMCFG_FREQCHNGCTL0_FREQ0(_c) (DCS_BASE_ADDR + ((_c)*DCS_SPACING) + 0x450)
#define rAMCX_DRAMCFG_FREQCHNGCTL1_FREQ0(_c) (DCS_BASE_ADDR + ((_c)*DCS_SPACING) + 0x454)
#define rAMCX_DRAMCFG_FREQCHNGCTL0_FREQ1(_c) (DCS_BASE_ADDR + ((_c)*DCS_SPACING) + 0x468)
#define rAMCX_DRAMCFG_FREQCHNGCTL1_FREQ1(_c) (DCS_BASE_ADDR + ((_c)*DCS_SPACING) + 0x46C)
#define RUNDESKEWUPD (1 << 8)
#define rAMP_WRDQCALPAT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE30)
#define rAMP_WRDQSDQ_SDLLCTRL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x600)
#define rAMP_WRDQSDQ_SDLLCODE(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x604)
#define rAMP_WRDQ_CAL_RUN(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE60)
#define rAMP_WRDQ_CAL_RESULT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE64)
#define rAMP_WRDQCALVREF(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x908)
#define rAMP_WRDQDESKEW_CTRL(_b,_c,_t) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x400 + ((_t)*4))
#define rAMP_WRDQSDESKEW_CTRL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x420)
#define rAMP_WRDMDESKEW_CTRL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x424)
#define rAMP_CAMDLL_VTSCL_REFCNTL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x1D4)
#define rAMP_RDMDLL_VTSCL_REFCNTL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x1D8)
#define rAMP_WRMDLL_VTSCL_REFCNTL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x1D8)
#define rAMP_RDCAPCFG_FREQ(_c, _b, _f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x100 + ((_f) * 4))
#define rAMP_DQSPDENALWAYSON(_c, _b) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x110)
#if DCS_REG_VERSION == 2
#define rAMPH_CFGH_DQS0_WKPUPD(_c) (AMP_H_BASE_ADDR + ((_c)*AMP_SPACING)+ 0x0C8)
#define rAMPH_CFGH_DQS1_WKPUPD(_c) (AMP_H_BASE_ADDR + ((_c)*AMP_SPACING)+ 0x138)
#define F0_IDLE_ACTIVE_MASK 0xFFFEFFF7
#define F0_IDLE_ACTIVE_OFFSET 16
#define F1_IDLE_ACTIVE_MASK 0xFFFDFFF7
#define F1_IDLE_ACTIVE_OFFSET 17
#define F1_PDPWK_OFFSET 3
#define DESKEW_CODE_MASK 0x3F
#endif // #if DCS_REG_VERSION == 2
#define RUNWRLVLENTRY_OFFSET 0
#define RUNWRLVLDQ_OFFSET 1
#define RUNWRLVLEXIT_OFFSET 3
#define RUNWRLVLLOOPCNT_OFFSET 8
#define RUNWRLVLMASK_OFFSET 16
#define RUNWRLVL_SDLLUPDOVR 8
#define RUNWRLVL_SDLLUPDWRRES 9
#define WRLVL_SDLLCODE_MASK 0xFFFFFF00
#define WRLVLMAX_SDLLCODE_MASK 0xFF00FFFF
#define WRLVL_SDLLCODE_OFFSET 0
#define WRLVLMAX_SDLLCODE_OFFSET 16
#define DQS_IDLE_ACTIVE_MASK 0xFFFFFFEF
#define DQS_IDLE_ACTIVE_OFFSET 4
#define WRLVL_RESULT 0
#define WRLVL_CNT0_OFFSET 8
#define WRLVL_CNT1_OFFSET 16
#define SDLLOFFSET 16
#define RUN_SDLLUPDOVR 1
#define RUN_SDLLUPDWRRES 2
#define WR_DQ_SDLL_OFFSET 16
#define WR_DQS_SDLL_OFFSET 24
#define WR_SDLLUPDOVR 1
#define WR_SDLLUPDWRRES 2
#define WR_ALL_BITS_PASS 0xFFFF
#define WR_ALL_BITS_FAIL 0x0
#define WR_CALIB_RUN 0
#define WR_DQS_SDLL_CODE_OFFSET 8
#define VT_SCL_REF_MASK 0x3FF
#define VT_SCL_REF_BITS 10
#define VT_SCL_OVR_OFFSET 16
#define VT_SCL_REF_UPD_OFFSET 28
#define DQS_PDEN_OFFSET 24
#define DQS_PDEN_MASK 0xFEFFFFFF
#define DQSPDEN_ALWAYSON_OFFSET 0
#define DQSPDEN_ALWAYSON_MASK 0x1
#define MAX_SDLL_OFFSET
#define TESTMODE_FORCECKELOW (1 << 8)
#define SIGN_BIT_POS (6)
#define AMP_MAX_RANKS_PER_CHAN (2)
#endif /* _DCS_CAL_H */
drivers/apple/dcs/include/drivers/dcs/dcs_cal_v2.h
+291
View File
@@ -0,0 +1,291 @@
/*
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef _DCS_CAL_H
#define _DCS_CAL_H
#define AMP_FREQUENCY_SLOTS (4)
/* _t: type, DQ0, DQ1, or CA */
/* _c: channel, 0 or 1 */
#define AMP_CA (0)
#define AMP_DQ0 (1)
#define AMP_DQ1 (2)
#define rAMP_AMPEN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x000)
#define rAMP_AMPCLK(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x004)
#define rAMP_AMPINIT(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x008)
#define rAMP_AMPVER(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x00C)
#define rAMP_IMPCODE(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x080)
#define rAMP_IMPOVRRD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x084)
#define rAMP_IMPAUTOCAL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x088)
#define rAMP_IMPCALPHYUPDT(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x08C)
#define rAMP_IMPCALCMD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x090)
#define rAMP_DRAMSIGDLY(_t,_c,_n) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x094 + ((_n) * 4))
#define rAMP_NONDQDS(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x098)
#define rAMP_DQDQSDS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x09C)
#define rAMP_DIFFMODE_FREQ(_t,_c,_f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x0A0 + ((_f) * 4))
#define rAMP_DQFLTCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x0B0)
#define rAMP_DQSPDENALWYSON(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x110)
#define rAMP_DQSPDRES(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x114)
#define rAMP_RDFIFOPTRSTS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x118)
#define rAMP_CALDQMSK(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x11C)
#define rAMP_DQTRNCFG(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x124 - ((_t >> 1) * 0x10))
#define rAMP_DQTRNCMD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x128 - ((_t >> 1) * 0x10))
#define rAMP_DQTRNSTS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x12C - ((_t >> 1) * 0x10))
#define rAMP_DLLEN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x180)
#define rAMP_MDLLOVRRD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x188 + ((_t >> 1) * 4))
#define rAMP_DLLLOCKTIM(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x198)
#define rAMP_DLLLOCKCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x19C)
#define rAMP_DLLUPDTINTVL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x1A0)
#define rAMP_DLLUPDTCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x1A4)
#define rAMP_DLLSTS(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x1A8)
#define rAMP_DQSINDLLSCL_FREQ(_t,_c,_f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x1C0 + ((_f) * 4))
#define rAMP_CAOUTDLLSCL_FREQ(_c,_f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x1C0 + ((_f) * 4))
// <rdar://problem/13919568>
#define rAMP_TESTMODE(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x200 + ((_t >> 1) * 0x180))
#define rAMP_CKEDESKEW_CTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0x52C)
#define rAMP_DQWRLVLDLYCHAINCTRL(_t,_c,_b) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x704 + ((_b)*0x04))
#define rAMP_DQWRLVLRUN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x714)
#define rAMP_DQWRLVLDATA(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x718)
#define rAMP_CACALMASK(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x804)
#define rAMP_CACALCABYTESEL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x808)
#define rAMP_CACALCAMAP0(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x80C)
#define rAMP_CACALCAMAP1(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x810)
#define rAMP_CACALCAMAP2(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x814)
//#define rAMP_CACALRUN(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x838 + ((_t >> 1) * 0xEC))
// CP : Maui Change
//#define rAMP_CACALRESULT(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x83C)
#define rAMP_CAPHYUPDTREQ(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0xB00)
#define rAMP_CAPHYUPDTSTATUS(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + AMP_CA_SPACING + 0xB04)
#define rAMP_DLLUPDTCMD(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x18C)
// Some bit definitions
// CP : Maui Change
#define CACALRUN_CACALMODE 1
#define rAMP_CACACALVREF(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x908)
#define rAMP_CACALBITSELECT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x918)
#define CS_TRAINING 0
#define CA_TRAINING 1
#define CS_FINE_TRAINING 2
#define RUN_DLL_UPDT 0
#define CACALRUN_RUNCACALENTRY (1 << 0)
#define CACALRUN_RUNCACALCS (1 << 4)
#define CACALRUN_RUNCACALCA (1 << 8)
#define CACALRUN_RUNCACALEXIT (1 << 12)
#define CACALRUN_RUNCACALVREF (1 << 16)
#define rAMP_CACALRESULT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x91C)
#define rAMP_CACALRUN(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x924)
#define rAMP_CACALCTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x900)
#define rAMP_CACALCTRL2(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x904)
#define rAMP_CACALCTRL3(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x928)
#define rAMP_CACALPAT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x90C)
#define rAMP_CASDLLCTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x700)
#define rAMP_CASDLLCODE(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x704)
#define rAMP_CKSDLLCTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x710)
#define rAMP_CKSDLLCODE(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x714)
#define rAMP_CSSDLLCTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x708)
#define rAMP_CSSDLLCODE(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x70C)
#define rAMP_AMPCACALENTRYCMD(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x910)
#define rAMP_AMPCACALEXITCMD(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x914)
#define rAMP_MDLLCODE(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t)*AMP_DQ_SPACING) + 0x194)
#define rAMP_CKDESKEW_CTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x51C)
#define rAMP_CADESKEW_CTRL(_c,_d) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x500 + ((_d)*4))
#define rAMP_CSDESKEW_CTRL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x518)
#define rAMP_RDWRDQCALLOOPCNT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE20)
#define rAMP_RUNRDDQCAL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE58)
#define rAMP_CALPATCFG(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x110)
#define rAMP_DQSDLLCTRL_RD(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x608)
#define rAMP_DQSDLLCODE_RD(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x60C)
#define rAMP_RDDQDESKEW_CTRL(_b,_c,_d) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x428 + ((_d)*4))
#define rAMP_RDDQSDESKEW_CTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x448)
#define rAMP_RDDMDESKEW_CTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x44C)
#define rAMP_DQCALCTRL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x900)
#define rAMP_DQCALRUN(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE58)
#define rAMP_DQCALRESULT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE5C)
#define rAMP_RDCLKDLYSEL(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x618)
#define rAMP_RDDQCALPAT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE2C)
#define rAMP_RdWrDqCalTiming_f0(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE00)
#define rAMP_RdWrDqCalTiming_f1(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE08)
#define rAMP_RdWrDqCalTiming_f2(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE10)
#define rAMP_RdWrDqCalTiming_f3(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE18)
#define rAMP_RdWrDqCalTimingCtrl2(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE28)
#define rAMP_RDDQCALVREF_f0(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xD10)
#define rAMP_RDDQCALVREF_f1(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xD14)
#define rAMP_DQCAL_BURSTLEN_MODE(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xF10)
#define rAMP_CAWRLVLSDLLCODE(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x800)
#define rAMP_CAWRLVLENTRYCMD(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xB00)
#define rAMP_CAWRLVLEXITCMD(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xB04)
#define rAMP_CAWRLVLTIM(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xB08)
#define rAMP_CARUNWRLVL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xB0C)
#define rAMP_CAWRLVLRESULT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xB10)
#define rAMPH_CFGH_DQS0_WKPUPD(_c) (AMP_H_BASE_ADDR + ((_c)*AMP_SPACING)+ 0x0C8)
#define rAMPH_CFGH_DQS1_WKPUPD(_c) (AMP_H_BASE_ADDR + ((_c)*AMP_SPACING)+ 0x138)
#define rAMPH_CFGH_CABIST_BISTRDFIFOCTRL(_c) (AMP_H_BASE_ADDR + ((_c)*AMP_SPACING)+ 0x164)
#define rAMP_CACALPATSEED_0(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x92C)
#define rAMP_CACALPATSEED_1(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x930)
#define rAMP_DQWRLVLSDLLCODE(_t,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_t + 1)*AMP_DQ_SPACING) + 0x704)
#define rAMCX_DRAMCFG_FREQCHNGMRWCNT(_c) (DCS_BASE_ADDR + ((_c)*DCS_SPACING) + 0x44C)
#define rAMCX_DRAMCFG_FREQCHNGCTL0_FREQ0(_c) (DCS_BASE_ADDR + ((_c)*DCS_SPACING) + 0x450)
#define rAMCX_DRAMCFG_FREQCHNGCTL1_FREQ0(_c) (DCS_BASE_ADDR + ((_c)*DCS_SPACING) + 0x454)
#define rAMCX_DRAMCFG_FREQCHNGCTL0_FREQ1(_c) (DCS_BASE_ADDR + ((_c)*DCS_SPACING) + 0x468)
#define rAMCX_DRAMCFG_FREQCHNGCTL1_FREQ1(_c) (DCS_BASE_ADDR + ((_c)*DCS_SPACING) + 0x46C)
#define RUNDESKEWUPD (1 << 8)
#define rAMP_WRDQCALPAT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE30)
#define rAMP_WRDQSDQ_SDLLCTRL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x600)
#define rAMP_WRDQSDQ_SDLLCODE(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x604)
#define rAMP_WRDQ_CAL_RUN(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE60)
#define rAMP_WRDQ_CAL_RESULT(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xE64)
#define rAMP_WRDQCALVREF(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x908)
#define rAMP_WRDQDESKEW_CTRL(_b,_c,_t) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x400 + ((_t)*4))
#define rAMP_WRDQSDESKEW_CTRL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x420)
#define rAMP_WRDMDESKEW_CTRL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x424)
#define rAMP_CAMDLL_VTSCL_REFCNTL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x1D4)
#define rAMP_RDMDLL_VTSCL_REFCNTL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x1D8)
#define rAMP_WRMDLL_VTSCL_REFCNTL(_b,_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x1D8)
#define rAMP_RDCAPCFG_FREQ(_c, _b, _f) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x100 + ((_f) * 4))
#define rAMP_DQSPDENALWAYSON(_c, _b) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + ((_b + 1)*AMP_DQ_SPACING) + 0x110)
#define rAMP_CALPATPRBS7_0(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xEA0)
#define rAMP_CALPATPRBS7_1(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xEA4)
#define rAMP_CALPATPRBS7_2(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xEA8)
#define rAMP_CALPATPRBS7_3(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xEAC)
#define rAMP_CACALPATSEED_0(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x92C)
#define rAMP_CACALPATSEED_1(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x930)
#define rAMP_WRDQCALPATSEED_B0_0(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xEB4)
#define rAMP_WRDQCALPATSEED_B0_1(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xEB8)
#define rAMP_WRDQCALPATSEED_B0_2(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xEBC)
#define rAMP_WRDQCALPATSEED_B1_0(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xEC0)
#define rAMP_WRDQCALPATSEED_B1_1(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xEC4)
#define rAMP_WRDQCALPATSEED_B1_2(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xEC8)
#define rAMP_WRDQCAL_NC_CONVERSION_THRESHOLD_F0(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xED0)
#define rAMP_WRDQCAL_NC_CONVERSION_THRESHOLD_F1(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xED4)
#define rAMP_WRDQCALVREFCODECONTROL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xF20)
#define rAMP_WRDQCALVREFCODESTATUS(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xF24)
#define rAMP_RDDQCALVREFCODECONTROL(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xF18)
#define rAMP_RDDQCALVREFCODESTATUS(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0xF1C)
#define rAMP_CA_IMPCALCMD(_c) (AMP_BASE_ADDR + ((_c)*AMP_SPACING) + 0x094)
#define RUNIMPCAL_OFFSET 0
#define RUNIMPCAL_MASK 0xFFFFFFFE
#define RUNWRLVLENTRY_OFFSET 0
#define RUNWRLVLDQ_OFFSET 1
#define RUNWRLVLEXIT_OFFSET 3
#define RUNWRLVLLOOPCNT_OFFSET 8
#define RUNWRLVLMASK_OFFSET 16
#define RUNWRLVL_SDLLUPDOVR 8
#define RUNWRLVL_SDLLUPDWRRES 9
#define WRLVL_SDLLCODE_MASK 0xFFFFFF00
#define WRLVLMAX_SDLLCODE_MASK 0xFF00FFFF
#define WRLVL_SDLLCODE_OFFSET 0
#define WRLVLMAX_SDLLCODE_OFFSET 16
#define DQS_IDLE_ACTIVE_MASK 0xFFFFFFEF
#define DQS_IDLE_ACTIVE_OFFSET 4
#define RUNRDDQCAL_WRFIFO_MASK 0xFFFFEFFF
#define RUNRDDQCAL_WRFIFO_OFFSET 12
#define HALF_CLK_OVRVAL_MASK 0xFFFFF3FF
#define HALF_CLK_OVRVAL_OFFSET 10
#define NC_THRESHOLD0_OFFSET 0
#define NC_THRESHOLD1_OFFSET 8
#define NC_THRESHOLD_MASK 0x3F
#define WRLVL_RESULT 0
#define WRDQ_VREF_F1_OFFSET 8
#define WRDQ_VREF_F0_OFFSET 0
#define WRDQ_VREF_F1_MASK 0xFFFF00FF
#define WRDQ_VREF_F0_MASK 0xFFFFFF00
#define RDDQ_VREF_F1_OFFSET 8
#define RDDQ_VREF_F0_OFFSET 0
#define RDDQ_VREF_F1_MASK 0xFFFF00FF
#define RDDQ_VREF_F0_MASK 0xFFFFFF00
#define WRLVL_CNT0_OFFSET 8
#define WRLVL_CNT1_OFFSET 16
#define SDLLOFFSET 16
#define RUN_SDLLUPDOVR 1
#define RUN_SDLLUPDWRRES 2
#define WR_DQ_SDLL_OFFSET 16
#define WR_DQS_SDLL_OFFSET 24
#define WR_SDLLUPDOVR 1
#define WR_SDLLUPDWRRES 2
#define WR_ALL_BITS_PASS 0xFFFF
#define WR_ALL_BITS_FAIL 0x0
#define WR_CALIB_RUN 0
#define WR_DQS_SDLL_CODE_OFFSET 8
#define VT_SCL_REF_MASK 0x3FF
#define VT_SCL_REF_BITS 10
#define VT_SCL_OVR_OFFSET 16
#define VT_SCL_REF_UPD_OFFSET 28
#define DQS_PDEN_OFFSET 24
#define DQS_PDEN_MASK 0xFEFFFFFF
#define DQSPDEN_ALWAYSON_OFFSET 0
#define DQSPDEN_ALWAYSON_MASK 0x1
#define DESKEW_CODE_MASK 0x3F
#define RDDQCAL_BURSTLEN_MODE_MASK 0xFFFFFFFE
#define RDDQCAL_BURSTLEN_MODE_OFFSET 0
#define F0_IDLE_ACTIVE_MASK 0xFFFEFFFF
#define F0_IDLE_ACTIVE_OFFSET 16
#define F1_IDLE_ACTIVE_MASK 0xFFFDFFFF
#define F1_IDLE_ACTIVE_OFFSET 17
#define F3_IDLE_ACTIVE_MASK 0xFFF7FFFF
#define F3_IDLE_ACTIVE_OFFSET 19
#define F0_WEAK_PD_MASK 0xFFFFFFFD
#define F0_WEAK_PD_OFFSET 1
#define F1_WEAK_PD_MASK 0xFFFFFFF7
#define F1_WEAK_PD_OFFSET 3
#define F3_WEAK_PD_MASK 0xFFFFFF7F
#define F3_WEAK_PD_OFFSET 7
#define CACAL_DQS_PULSE_CNT_OFFSET 16
#define CACAL_DQS_PULSE_WIDTH_OFFSET 20
#define BIST_RDFIFO_RESET_MASK 0xFFFFFFFD
#define BIST_RDFIFO_RESET_OFFSET 1
#define MAX_SDLL_OFFSET
#define TESTMODE_FORCECKELOW (1 << 8)
#define SIGN_BIT_POS (6)
#define AMP_MAX_RANKS_PER_CHAN (2)
#endif /* _DCS_CAL_H */
drivers/apple/dcs/include/drivers/dcs/dcs_calibration.h
+271
View File
@@ -0,0 +1,271 @@
/*
* Copyright (C) 2012-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __DCS_CALIBRATION_H
#define __DCS_CALIBRATION_H
#ifdef ENV_IBOOT
// Calibration registers
#if DCS_REG_VERSION < 3
#include <drivers/dcs/dcs_cal.h>
#else
#include <drivers/dcs/dcs_cal_v2.h>
#endif
#endif
// Chip rev definitions for non-iBoot environments
#ifndef ENV_IBOOT
#define CHIP_REVISION_A0 0x00
#define CHIP_REVISION_A1 0x01
#define CHIP_REVISION_B0 0x10
#define CHIP_REVISION_B1 0x11
#define CHIP_REVISION_C0 0x20
#define CHIP_REVISION_C1 0x21
#endif
#define AMP_DQ_PER_CHAN 2
#define AMP_MAX_PATTERNS 8
#define CALIB_SAVE 0
#define CALIB_RESTORE 1
#define CALIB_PMU_BYTES 400
// 1 CASDLL (8 bits), 1 CKSDLL (8 bits), 1 CSSDLL (8 bits), 6 CA bit deskews (6 bits * 6), CK/CS deskew (6 bits * 2), 3 WrLvl SDLLs (8 bits * 3)
// WRDQ SDLLs (2 * 8 bits), WRDQS SDLLs (2 * 8 bits), WR DQ deskew (2 * 8 * 6 bits), WR DQS deskew ( 2 * 6 bits), WR DM deskew (2 * 6 bits)
// 3 WrLvl SDLLs (8 bits * 3) after WRDQ calibration
// RD SDLLs (2 * 8 bits), RD deskew (2 * 8 * 6 bits), RD DMI deskew (2 * 6 bits)
// Optimal Vref for CA, RD & WR for bins 0 & 1 (3 * 2 * 6 bits)
// VT scaling refence codes for CA, RD and WR for both DQ splits ( 3 * 2 * 10 bits)
// Total bits per channel = 24 +36 + 12 + 24 + 16 + 16 + 96 + 12 + 12 + 24 + 16 + 96 + 12 + 36 + 60 = 492 bits
// TODO: Recalculate this (somehow! --> better: sizeof(struct) )
#define CALIB_NUM_BYTES_TO_SAVE (DCS_NUM_CHANNELS * (62))
// CP Changed
#define CA_NUM_BITS 6
#define CA_ALL_BITS ((1 << CA_NUM_BITS) - 1)
#if DCS_REG_VERSION < 3
#define CA_NUM_VREF_F0 10
#define RDDQ_NUM_VREF_F0 10
#define CA_NUM_VREF_F1 21
#define RDDQ_NUM_VREF_F1 26
#define CA_NUM_VREF_MAX ((CA_NUM_VREF_F0 > CA_NUM_VREF_F1) ? CA_NUM_VREF_F0 : CA_NUM_VREF_F1)
#define RDDQ_NUM_VREF_MAX ((RDDQ_NUM_VREF_F0 > RDDQ_NUM_VREF_F1) ? RDDQ_NUM_VREF_F0 : RDDQ_NUM_VREF_F1)
#else
#define CA_NUM_VREF 10
#define RDDQ_NUM_VREF 10
#endif // #if DCS_REG_VERSION < 3
#define WRDQ_NUM_VREF 10
#define CA_NUM_PATTERNS 64
// <rdar://problem/13821643>
#define DELIMIT_POS_ADJ_CASDLL 6
#define DELIMIT_POS_ADJ_WRDQSDLL 6
#define MR_READ 0
#define MR_WRITE 1
#define MR0 0x0
#define MR2 0x02
#define MR5 0x05
#define MR12 0x0C
#define MR13 0x0D
#define MR14 0x0E
#define MR15 0x0F
#define MR20 0x14
#define MR32 0x20
#define MR40 0x28
#define MR41 0x29
#define MR42 0x2A
#define MR48 0x30
#define MIN_ENDPT 0
#define MAX_ENDPT 1
#if DCS_REG_VERSION == 1
#define MAX_DESKEW_PROGRAMMED 31
#define MAX_SDLL_VAL 203
#else
#define MAX_DESKEW_PROGRAMMED 55
#if DCS_REG_VERSION == 2
#define MAX_SDLL_VAL 248
#else
#define MAX_SDLL_VAL 204
#endif // #if DCS_REG_VERSION == 2
#endif // #if DCS_REG_VERSION == 1
#define MIN_SDLL_VAL 0
#define FINER_STEP_SZ 1
#define COARSE_STEP_SZ 4
#define SOLID_PASS_DETECT 8
#define SOLID_PASS_ZONE_DETECT 4
#define SOLID_FAIL 2
#define DLLVAL_BITS 0xFF
#define DESKEW_CTRL_BITS 0x3F
#define SDLL_NUM_BITS 8
#define DESKEW_NUM_BITS 6
#define CA_WRDQ_VREF_CTRL_BITS 0x7F
#define CA_WRDQ_VREF_NUM_BITS 7
#define RDDQ_VREF_CTRL_BITS 0xFF
#define RDDQ_VREF_NUM_BITS 8
#define RD_LATENCY_ENCODE 26
#define MAX_DQWRLVL_CODE 127
#define DQ_NUM_PATTERNS 128
// The number of bytes below is consecutive for a given ch, rnk, bank, and row (interleaving starts after these bytes)
//#define DQ_CONSECUTIVE_BYTES_PER_CHRNK 256
#define DQ_BYTES_PER_COL 4 // That makes for 64 consecutive columns (or words)
// the bank and row numbers where patterns will be written
#define DQ_ROW 0
#define DQ_BANK 0
#define DQ_ADDR_RANK_BIT 16 // RIBI2 addressing for dual rank devices
// Calibration operation selection
#define SELECT_CACAL 0x1
#define SELECT_WRLVLCAL 0x2
#define SELECT_RDDQCAL 0x4
#define SELECT_WRDQCAL 0x8
#define SELECT_CAL_ALL 0xF
// This defintion is put here for non-iBoot compilation environments
#ifndef __abs
#define __abs(x) (((x) < 0) ? -(x) : (x))
#endif
#if DCS_REG_VERSION < 2
#define DQ_MAX_DESKEW_PER_BIT 47
#else
#define DQ_MAX_DESKEW_PER_BIT 55
#endif
// maximum possible loops in the hw
#define RDDQ_LOOPCNT 16
#define DQ_NUM_BYTES 2
#define DQ_NUM_BYTES_PER_DQ 1
#define DQ_NUM_BITS_PER_BYTE 8
#define DQ_TOTAL_BITS (DQ_NUM_BYTES * DQ_NUM_BITS_PER_BYTE)
#define DMI_TOTAL_BITS 2
#define DMI_NUM_BITS_PER_BYTE 1
#if DCS_REG_VERSION == 2
#define MAX_CAWRLVL_CODE 52
#else
#define MAX_CAWRLVL_CODE 47
#endif // #if DCS_REG_VERSION == 2
#define CLK_PERIOD_NUMER (1000000)
#define CLK_PERIOD_OF(_freq_in_mhz) (CLK_PERIOD_NUMER / (_freq_in_mhz))
#define CLK_PERIOD_1600 CLK_PERIOD_OF(1600) // 625
#define CLK_PERIOD_1200 CLK_PERIOD_OF(1200) // 833
#define CLK_PERIOD_800 CLK_PERIOD_OF(800) // 1250
void calibration_ca_rddq_wrlvl(bool resume);
void calibration_wrdq_rddq(bool resume);
void calibration_save_restore_ca_wrlvl_regs(uint32_t save_or_restore, uint32_t channels, bool freq_bin);
void calibration_dump_results(uint32_t operations, bool dump_passing_window);
struct amp_calibration_params {
uint32_t chip_id;
uint32_t chip_rev;
uint32_t num_channels;
uint32_t num_channels_runCalib;
uint32_t num_ranks;
uint32_t clk_period_bin0;
uint32_t clk_period_bin1;
#if DCS_REG_VERSION < 3
uint32_t ca_num_vref_f0;
uint32_t rddq_num_vref_f0;
uint32_t ca_num_vref_f1;
uint32_t rddq_num_vref_f1;
#else
uint32_t ca_num_vref;
uint32_t rddq_num_vref;
#endif // #if DCS_REG_VERSION < 3
uint32_t wrdq_num_vref;
bool wrdq_apply_NC_algorithm;
#if DCS_REG_VERSION < 3
uint32_t ca_vref_values_f0[CA_NUM_VREF_F0];
uint32_t rddq_vref_values_f0[RDDQ_NUM_VREF_F0];
uint32_t ca_vref_values_f1[CA_NUM_VREF_F1];
uint32_t rddq_vref_values_f1[RDDQ_NUM_VREF_F1];
#else
uint32_t ca_vref_values[CA_NUM_VREF];
uint32_t rddq_vref_values[RDDQ_NUM_VREF];
#endif
uint32_t wrdq_vref_values[WRDQ_NUM_VREF];
bool resume;
bool disable_coarse_cs_training;
uint32_t opt_vref_mode; // Use CoM or "Widest Span" method?
uint32_t cacalib_hw_loops;
uint32_t cacalib_sw_loops;
uint32_t cacalib_dqs_pulse_cnt;
uint32_t cacalib_dqs_pulse_width;
uint32_t rddq_cal_loopcnt;
uint32_t wrdq_cal_loopcnt;
uint32_t rddq_legacy_mode;
uint32_t wrdq_legacy_mode;
uint32_t cacal_bit_sel[8];
uint32_t cacal_rd_byte_sel;
uint32_t ca_prbs4_pattern;
uint32_t prbs7_pattern_0;
uint32_t prbs7_pattern_1;
uint32_t prbs7_pattern_2;
uint32_t prbs7_pattern_3;
uint32_t ca_prbs_seed_bit[CA_NUM_BITS];
uint32_t wrdq_prbs_seed[DQ_NUM_BYTES][DQ_NUM_BITS_PER_BYTE + DMI_NUM_BITS_PER_BYTE];
uint32_t ca_invert_mask;
uint32_t CsStopCycleCnt;
uint32_t CsActiveCycleCnt;
uint32_t tADR, tMRD, tCAENT, tVREF_LONG, tCKELCK, tCKCKEH, tDSTrain;
uint32_t tWLO;
uint32_t tWLMRD;
uint32_t tWLDQSEN;
uint32_t tDQSCKE;
uint32_t tCKEHCMD;
uint32_t WrLvlDqsPulseCnt;
int freq_bin;
int RL;
int WL;
// SEG specific flags
bool dv_params_valid; // DV flag
bool dv_randomize; // flag to be used by DV to randomize some register values for DV purposes
uint32_t dbg_calib_mode; // flag to be used by SEG to skip calibration operations for debug purposes
};
#define DCS_CAL_OPT_VREF_MODE_WIDEST 0
#define DCS_CAL_OPT_VREF_MODE_COM 1
////////////////////////////////////////////////////////////////////////////////////////////////////////
// API Functions
////////////////////////////////////////////////////////////////////////////////////////////////////////
struct amp_calibration_params *calibration_cfg_params_init(int bootMode, int numChans, int numRanksPerChn);
void calibrate_ca(void);
void calibrate_wrlvl(void);
void calibrate_wrdq(void);
void calibrate_rddq(void);
////////////////////////////////////////////////////////////////////////////////////////////////////////
#endif /* ! __DCS_CALIBRATION_H */
////////////////////////////////////////////////////////////////////////////////////////////////////////
drivers/apple/dcs/include/drivers/dcs/dcs_init_lib.h
+331
View File
@@ -0,0 +1,331 @@
/*
* Copyright (C) 2014-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef __DCS_INIT_LIB_H
#define __DCS_INIT_LIB_H
/* DRAM Control Subsystem (DCS) Initialization Library API Definitions */
//================================================================================
// Build (Environment) Type: iBoot, SiVal, DV, PE-RTOS
//================================================================================
#define DCS_BUILD_ENV_IBOOT (0)
#define DCS_BUILD_ENV_SIVAL (1)
#define DCS_BUILD_ENV_DV (2)
#define DCS_BUILD_ENV_PERTOS (3)
#define izIBOOT (DCS_BUILD_ENV_TYPE == DCS_BUILD_ENV_IBOOT)
#define izSIVAL (DCS_BUILD_ENV_TYPE == DCS_BUILD_ENV_SIVAL)
#define izDV (DCS_BUILD_ENV_TYPE == DCS_BUILD_ENV_DV)
#define izPERTOS (DCS_BUILD_ENV_TYPE == DCS_BUILD_ENV_PERTOS)
//================================================================================
// Target Type: SoC, FPGA, Palladium
//================================================================================
#define DCS_TARGET_SOC (0)
#define DCS_TARGET_FPGA (1)
#define DCS_TARGET_PALLADIUM (2)
#define izSOC (DCS_TARGET_TYPE == DCS_TARGET_SOC)
#define izFPGA (DCS_TARGET_TYPE == DCS_TARGET_FPGA)
#define izPAL (DCS_TARGET_TYPE == DCS_TARGET_PALLADIUM)
//================================================================================
// What Build Environment?
#ifndef DCS_BUILD_ENV_TYPE
#define DCS_BUILD_ENV_TYPE DCS_BUILD_ENV_IBOOT
#endif
//================================================================================
#if izIBOOT
//================================================================================
#define AMP_H_BASE_ADDR AMPH_BASE_ADDR
#include <sys/types.h>
#include <debug.h>
#include <drivers/dcs/dcs_regs.h>
#include <drivers/dcs/dcs.h>
#include <drivers/dcs/dcs_calibration.h>
#include <drivers/dram.h>
#include <drivers/miu.h>
#include <lib/env.h>
#include <platform.h>
#include <platform/soc/hwclocks.h>
#include <platform/chipid.h>
#include <platform/memmap.h>
#include <platform/timer.h>
#include <sys.h>
#include <string.h>
#define delay_for_us(_us_delay) spin(_us_delay)
extern int debug_level_dcs;
#define do_printf(x...) dprintf(debug_level_dcs, x)
#define dcs_panic(x...) \
EXEC( \
debug_level_dcs = DEBUG_CRITICAL; \
dcs_cfg.debugBitz |= DCS_DBG_CAL; \
calibration_dump_results(SELECT_CAL_ALL, true); \
panic(x); \
)
#if SUPPORT_FPGA
#define DCS_TARGET_TYPE DCS_TARGET_FPGA
#endif
// iBoot gets these definitions via the make command line
// Maximum channels/ranks supported by the target
//#define DCS_NUM_CHANNELS 4
//#define DCS_NUM_RANKS 1
// iBoot gets this definition via the make command line
#ifdef AMP_CALIBRATION_SKIP
#define DCS_DO_CALIBRATION 0
#else
#define DCS_DO_CALIBRATION 1
#endif
//================================================================================
#elif izSIVAL
//================================================================================
#include "drivers/dcs/dcs_sival.h"
//================================================================================
#elif izDV
//================================================================================
//================================================================================
#elif izPERTOS
//================================================================================
//================================================================================
#else // other than iBoot (examples: SiVal, DV, etc.)
//================================================================================
// iBoot has a special version of a tight SpinLoop with Timeout
// Other build environments may use the following simple definition (no Timeout),
// or else provide their own by modifying this definition
#define SPIN_W_TMO_WHILE(__expr) while(__expr)
// iBoot defines this function to delay for N microseconds
// Other build environments may use the following degenerate definition (no delay),
// or else provide their own by modifying this definition
#define delay_for_us(_us_delay) EXEC(;)
// iBoot defines this function to optionally print out debug messages
// Other build environments may use the following simple definition (printf),
// or else provide their own by modifying this definition
#define do_printf(x...) printf(x)
// iBoot defines this function to halt execution and terminate because of a fatal error
// Other build environments may use the following similar definition (panic),
// or else provide their own by modifying this definition
#define dcs_panic(x...) \
EXEC( \
debug_level_dcs = DEBUG_CRITICAL; \
dcs_cfg.debugBitz |= DCS_DBG_CAL; \
calibration_dump_results(SELECT_CAL_ALL, true); \
panic(x); \
)
// iBoot derives this definition from other definitions provided via the make command line
// Other build environments may explicitly define the target type here,
// or use any other desired method
//#define DCS_TARGET_TYPE DCS_TARGET_SOC
//#define DCS_TARGET_TYPE DCS_TARGET_FPGA
//#define DCS_TARGET_TYPE DCS_TARGET_PALLADIUM
// Maximum channels/ranks supported by the target
#define DCS_NUM_CHANNELS 4
#define DCS_NUM_RANKS 1
#define DCS_DO_CALIBRATION 1 // ZERO to Skip Calibration
//================================================================================
#endif
//================================================================================
#ifndef DCS_TARGET_TYPE
#define DCS_TARGET_TYPE DCS_TARGET_SOC
#endif
typedef uint32_t dcs_buildtype_t;
typedef uint32_t dcs_target_t;
#define CACAL_MAX_SWLOOPS 1
//================================================================================
// Config Sturcture
//================================================================================
typedef struct {
bool valid;
dcs_boottype_t boot_type;
uint32_t chipID; // Supported ChipID values listed below
uint32_t chipRev; // A0, B0, B1, etc.
uint32_t num_dcs; // Number of DCS Blocks for this Chip
uint32_t num_rank; // Number of Ranks for the DRAM
uint32_t debugBitz; // Bit Field to control various debug behaviors
uint32_t variantBitz; // Bit Field to control variant behavior (workaround, per RADAR)
} dcs_config_t;
// Supported Chip Revision Codes
#define DCS_CHIP_REV_A0 0x00
#define DCS_CHIP_REV_A1 0x01
#define DCS_CHIP_REV_A2 0x02
#define DCS_CHIP_REV_B0 0x10
#define DCS_CHIP_REV_B1 0x11
#define DCS_CHIP_REV_B2 0x12
#define DCS_CHIP_REV_C0 0x20
#define DCS_CHIP_REV_C1 0x21
#define DCS_CHIP_REV_C2 0x22
//================================================================================
#define BIT_N(_N) (1 << (_N))
// Defined debug Bitz
#define DCS_DBG_NONE 0x00000000
#define DCS_DBG_REG_ACCESS BIT_N(0)
#define DCS_DBG_CHAN_DETAIL BIT_N(1)
#define DCS_DBG_SPIN BIT_N(2)
#define DCS_DBG_MR_READ BIT_N(3)
#define DCS_DBG_MILESTONE BIT_N(4)
#define DCS_DBG_CAL BIT_N(5)
#define DCS_DBG_CAL_MILESTONE BIT_N(6)
#define DCS_DBG_FREQ BIT_N(7)
#define DCS_DBG_OVERVIEW BIT_N(8)
#define DCS_DBG_ASSESS_CONFIG BIT_N(9)
#define DCS_DBG_DEFAULT (DCS_DBG_OVERVIEW | DCS_DBG_ASSESS_CONFIG)
// Defined variant Bitz
#define DCS_VARIANT_NONE 0x00000000
#define DCS_VARIANT_SKIP_MCC BIT_N(0)
#define DCS_VARIANT_VREF_USES_WIDEST BIT_N(1) // Use Widest-Eye Algorithm for Optimal Vref
#define DCS_NONVAL (0xF82BDEAD)
//================================================================================
extern dcs_config_t dcs_cfg;
// extern dcs_config_params_t dcs_params;
#define izColdBoot (dcs_cfg.boot_type == DCS_BOOT_COLDBOOT)
#define izResume (dcs_cfg.boot_type == DCS_BOOT_RESUME)
#define izAOP_DDR (dcs_cfg.boot_type == DCS_BOOT_AOP_DDR)
#define izAOP_Awake (dcs_cfg.boot_type == DCS_BOOT_AOP_AWAKE)
//================================================================================
#define ifbit_printf(_b, _f, x...) EXEC(if ((_b) & (_f)) do_printf(x))
#define dbgprintf(_b, x...) ifbit_printf(_b, dcs_cfg.debugBitz, x)
//================================================================================
// These are used by the Calibration Functions ... provided by dcs_init_lib
// Save SRAM space in iBoot by removing calibration debug printfs
#if izIBOOT
#define shim_printf(x...) do { } while(0)
#else
#define shim_printf(x...) dbgprintf(DCS_DBG_CAL, x)
#endif
#define shim_panic(x...) dcs_panic(x)
#define shim_mrcmd_to_ch_rnk(x...) dcs_mrcmd_to_ch_rnk(x)
//================================================================================
// Callouts Required by this Library.
// Must be Provided externally (build environment, platform, target, etc.)
//================================================================================
void dcs_dram_workarounds(dcs_boottype_t boot_type);
void dcs_dram_workarounds_step12(void);
void dcs_init_config_params(dcs_config_params_t *use_dcs_params, dcs_target_t targtype);
const dcs_tunable_t *dcs_init_tunable_table(uint32_t *table_len);
void dcs_change_freq(uint32_t freq_bin);
void dcs_store_memory_calibration(void *cal_values, uint32_t cal_size);
void dcs_load_memory_calibration(void *cal_values, uint32_t cal_size);
//================================================================================
// These are used by the Calibration Functions ... must be provided by build environment
#define shim_change_freq(_bin) dcs_change_freq(_bin)
#define shim_store_memory_calibration dcs_store_memory_calibration
#define shim_load_memory_calibration dcs_load_memory_calibration
//================================================================================
// API Functions provided by this Library and available for use
//================================================================================
bool dcs_init_config(dcs_boottype_t boot_type, uint32_t chipID, uint32_t chipRev,
uint32_t num_dcs, uint32_t num_rank);
uint32_t dcs_init_debug_enable(uint32_t bit);
uint32_t dcs_init_debug_disable(uint32_t bit);
uint32_t dcs_init_variant_enable(uint32_t bit);
uint32_t dcs_init_variant_disable(uint32_t bit);
dcs_config_params_t *dcs_init_param_table(void);
void dcs_mrcmd_to_ch_rnk(dcs_mrcmd_op_t op, uint8_t channel, uint8_t rank, int reg, uintptr_t val);
void dcs_mrcmd(dcs_mrcmd_op_t op, uint8_t channels, uint8_t ranks, int reg, uintptr_t val);
void dcs_spin(uint32_t duration_us, char *reason);
void dcs_enable_autorefresh(void);
void dcs_init_apply_tunables(void);
// Step 0: AMC Prolog
void dcs_init_Prolog(void);
// Step 1: AMC Initial Configuration
void dcs_init_AMC_Initial_Config(void);
// Step 2: AMP Initial Configuration
void dcs_init_AMP_Initial_Config(void);
// Step 3: Self-Refresh Exit
void dcs_init_Self_Refresh_Exit_a(void);
void dcs_init_Self_Refresh_Exit_b(void);
// Step 4: DRAM Reset, ZQ Calibration & Configuration (cold boot only)
void dcs_init_ZQ_Cal_Cfg(void);
// Step 5a: AddrConfig Configuration
void dcs_init_AddrCfg_Cfg(void);
void dcs_init_TotalSize_Cfg(uint32_t total_size_Mbytes);
// Step 6: Switch from boot-clock speed to normal operation speed
void dcs_init_Reenable_AMC_Scheduler(void);
// Step 7: Setup registers for CA calibration for bucket 1
void dcs_init_CA_Cal_Setup_Freq1(void);
// Step 8: AMP Dynamic CA Vref Timing Calibration at Vmin 800MHz
void dcs_init_CA_Cal_Freq1(void);
// Step 9: Setup registers for DQ calibration for bucket 1
void dcs_init_DQ_Cal_Setup_Freq1_a(void);
void dcs_init_DQ_Cal_Setup_Freq1_b(void);
// Step 10: PHY write DQ calibration
void dcs_init_wrdq_skew(void);
void dcs_init_post_wrlvl(void);
// Step 11: Setup registers for CA calibration for bucket 0
void dcs_init_CA_Cal_Setup_Freq0(void);
// Step 12: AMP Dynamic CA Timing Calibration
// NO PROVIDED FUNCTION
// Step 13: Setup registers for DQ calibration for bucket 0
void dcs_init_DQ_Cal_Setup_Freq0_a(void);
void dcs_init_DQ_Cal_Setup_Freq0_b(void);
// Step 14: AMP Dynamic DQ Calibration
// NO PROVIDED FUNCTION
// Step 15: Setup Registers for Boot
void dcs_init_Reg_for_Boot(void);
// Step 16: Enable Other Features
void dcs_init_MoreFeatures(void);
// Step 17: Enable Fast Critical Word Forwarding Feature
void dcs_init_Fast_Critical_Word_Forwarding(void);
// Step 18: Enable Power- and Clock-Gating Features; Config MCC and Global Timers
void dcs_init_Gating_Global_Timers(void);
// Step 19: ODTS read & set interval for periodic MR4 on-die Temp sensor reading
void dcs_init_ODTS(void);
// <rdar://problem/23244578> Elba: Samsung DRAM workaround: disable hw zqcal
bool shim_apply_samsung_workaround(void);
void dcs_reg_write(uintptr_t reg_addr, uint32_t reg_value);
void dcs_reg_poll(uintptr_t reg_addr, uint32_t mask_value, uint32_t required_value);
void dcs_reg_write_all_chan(uintptr_t reg_addr, uint32_t reg_value);
void dcs_reg_poll_all_chan(uintptr_t reg_addr, uint32_t mask_value, uint32_t required_value);
#endif /* ! __DCS_INIT_LIB_H */
drivers/apple/dcs/include/drivers/dcs/dcs_regs.h
+676
View File
@@ -0,0 +1,676 @@
/*
* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
*
* This document is the property of Apple Inc.
* It is considered confidential and proprietary.
*
* This document may not be reproduced or transmitted in any form,
* in whole or in part, without the express written permission of
* Apple Inc.
*/
#ifndef _DCS_S8000_H
#define _DCS_S8000_H
#include <drivers/dcs/dcs.h>
#include <platform.h>
#include <platform/soc/hwregbase.h>
#include <sys/types.h>
/*
* DCS_REG_VERSION mapping used in iBoot for various platforms
* Maui: 1
* s8003: 2
* Elba: 3
* Cayman: 4
*
* SoCs with "dcsh" block to have bit 4 set
* M8: 0x10
*/
#ifndef DCS_REG_VERSION
#define DCS_REG_VERSION (1)
#endif
#ifndef NUM_AMCCS
#define NUM_AMCCS (1)
#endif
/* Macro to read a register in a particular DCS channel */
#define DCS_REG_ACCESS(reg) (*(volatile uint32_t *)(reg))
#define DCS_REG_READ_CH(_c,reg) DCS_REG_ACCESS((reg) + ((_c)*DCS_SPACING))
// Used by Calibration Code
#define CSR_READ(addr) DCS_REG_ACCESS(addr)
#define CSR_WRITE(addr, val) EXEC(DCS_REG_ACCESS(addr) = val)
#define KAY (1024)
#define MEG (KAY*KAY)
#define DCS_FREQUENCY_SLOTS (4)
#if DCS_REG_VERSION >= 0x10
// PIOWRAP registers
#define rAMC_PIO_ACCESS_CFG (PIO_BASE_ADDR + 0x02C)
// AMCSYS registers
#define rAMC_AMCEN (AMC_BASE_ADDR + 0x000)
#define rAMC_CLKGATE (AMC_BASE_ADDR + 0x004)
#define rAMC_AIUPRT_RD_CWF (AMC_BASE_ADDR + 0x084)
#define rAMC_AIUPRT_RD_GEN (AMC_BASE_ADDR + 0x088)
#define rAMC_AIUPRTBADDR (AMC_BASE_ADDR + 0x0A0)
#define rAMC_AIUCHNLDEC (AMC_BASE_ADDR + 0x0A4)
#define rAMC_AIUADDRBANKHASH(_n) (AMC_BASE_ADDR + (_n * 4) + 0x0B0)
#define rAMC_AIUCHNLCRD (AMC_BASE_ADDR + 0x100)
#define rAMC_AIUCHNLTM (AMC_BASE_ADDR + 0x104)
#define rAMC_AIURDBRSTLEN (AMC_BASE_ADDR + 0x108)
#define rAMC_AIURDMAXCRD (AMC_BASE_ADDR + 0x10C)
#define rAMC_AIURDMINCRD (AMC_BASE_ADDR + 0x110)
#define rAMC_AIURDREFL (AMC_BASE_ADDR + 0x114)
#define rAMC_AIUWRBRSTLEN (AMC_BASE_ADDR + 0x118)
#define rAMC_AIUWRMAXCRD (AMC_BASE_ADDR + 0x11C)
#define rAMC_AIUWRMINCRD (AMC_BASE_ADDR + 0x120)
#define rAMC_AIUWRREFL (AMC_BASE_ADDR + 0x124)
#define rAMC_AIUCPUSPCREQ (AMC_BASE_ADDR + 0x128)
#define rAMC_AIUGRXSPCREQ (AMC_BASE_ADDR + 0x12C)
#define rAMC_AIUNRTSPCREQ (AMC_BASE_ADDR + 0x130)
#define rAMC_AIURLTSPCREQ (AMC_BASE_ADDR + 0x134)
#define rAMC_AIUWPQSCH (AMC_BASE_ADDR + 0x138)
#define rAMC_AIUTHOTLEN (AMC_BASE_ADDR + 0x13C)
#define rAMC_AIUTHOTLCPUPARAM (AMC_BASE_ADDR + 0x140)
#define rAMC_AIUTHOTLRLTPARAM (AMC_BASE_ADDR + 0x144)
#define rAMC_AIUTHOTLNRTPARAM (AMC_BASE_ADDR + 0x148)
#define rAMC_AIUTHOTLGRXPARAM (AMC_BASE_ADDR + 0x14C)
#define rAMC_AIUPUSHEN (AMC_BASE_ADDR + 0x150)
#define rAMC_AIUTHOTLCPUPARAM2 (AMC_BASE_ADDR + 0x154)
#define rAMC_AIUTHOTLRLTPARAM2 (AMC_BASE_ADDR + 0x158)
#define rAMC_AIUTHOTLNRTPARAM2 (AMC_BASE_ADDR + 0x15C)
#define rAMC_AIUTHOTLGRXPARAM2 (AMC_BASE_ADDR + 0x160)
#define rAMC_AIULLTSCHCTL (AMC_BASE_ADDR + 0x164)
#define rAMC_AIURDMAXCRD2 (AMC_BASE_ADDR + 0x168)
#define rAMC_AIURDMINCRD2 (AMC_BASE_ADDR + 0x16C)
#define rAMC_AIURDREFL2 (AMC_BASE_ADDR + 0x170)
#define rAMC_AIUWRMAXCRD2 (AMC_BASE_ADDR + 0x174)
#define rAMC_AIUWRMINCRD2 (AMC_BASE_ADDR + 0x178)
#define rAMC_AIUWRREFL2 (AMC_BASE_ADDR + 0x17C)
#define rAMC_AIUMEDSPCREQ (AMC_BASE_ADDR + 0x180)
#define rAMC_AIUTHOTLMEDPARAM (AMC_BASE_ADDR + 0x184)
#define rAMC_AIUTHOTLMEDPARAM2 (AMC_BASE_ADDR + 0x188)
#define rAMC_QBREN (AMC_BASE_ADDR + 0x200)
#define rAMC_PSQRQCTL0 (AMC_BASE_ADDR + 0x208)
#define rAMC_PSQRQCTL1 (AMC_BASE_ADDR + 0x20C)
#define rAMC_PSQRQTIMER(_n) (AMC_BASE_ADDR + (_n * 4) + 0x210)
#define rAMC_PSQRQBRST (AMC_BASE_ADDR + 0x21C)
#define rAMC_PSQRQSCHCRD (AMC_BASE_ADDR + 0x220)
#define rAMC_PSQWQCTL1 (AMC_BASE_ADDR + 0x228)
#define rAMC_PSQWQBRST (AMC_BASE_ADDR + 0x230)
#define rAMC_PSQWQSCHCRD (AMC_BASE_ADDR + 0x234)
#define rAMC_MCUQOS (AMC_BASE_ADDR + 0x238)
#define rAMC_MCUQOSLLT (AMC_BASE_ADDR + 0x23C)
#define rAMC_ADDRMAPMODE (AMC_BASE_ADDR + 0x400)
#define rAMC_ADDRCFG (AMC_BASE_ADDR + 0x404)
#define rAMC_PWRMNGTPARAM (AMC_BASE_ADDR + 0x408)
// AMCSYS_AON
#define rAMC_IDLE2BCG_CONTROL (AMC_BASE_ADDR + 0x8014)
// DCSH_AON
#define rDCS_AON_IDLE2BCG_CONTROL (DCS_BASE_ADDR + DCSH_AON_SPACING + 0x004)
#endif // #if DCS_REG_VERSION >= 0x10
#if NUM_AMCCS == 2
/* AMCC0 registers */
#define rAMCC_MCCCHNLDEC_ADDR (AMCC_BASE_ADDR(0) + 0x4A4)
#define rAMCC_MCUCHNHASH_ADDR (AMCC_BASE_ADDR(0) + 0x4A8)
#define rAMCC_DRAMACCCTRL_ADDR (AMCC_BASE_ADDR(0) + 0x4B8)
#define rAMCC_ADDRCFG_ADDR (AMCC_BASE_ADDR(0) + 0x4CC)
#define rAMCC_MCC0QPROPCTRL_ADDR (AMCC_BASE_ADDR(0) + 0x648)
#define rAMCC_MCC1QPROPCTRL_ADDR (AMCC_BASE_ADDR(0) + 0x64C)
#define rAMCC_MCCGEN_ADDR (AMCC_BASE_ADDR(0) + 0x780)
#define rAMCC_MCCCFG_TAG_RD_DIS_ADDR (AMCC_BASE_ADDR(0) + 0x794)
#define rAMCC_MCCPWRONWAYCNTSTATUS_ADDR (AMCC_BASE_ADDR(0) + 0x79C)
#define rAMCC_MCCCHNLDEC DCS_REG_ACCESS(rAMCC_MCCCHNLDEC_ADDR)
#define rAMCC_DRAMACCCTRL DCS_REG_ACCESS(rAMCC_DRAMACCCTRL_ADDR)
#define rAMCC_ADDRCFG DCS_REG_ACCESS(rAMCC_ADDRCFG_ADDR)
#define rAMCC_MCC0QPROPCTRL DCS_REG_ACCESS(rAMCC_MCC0QPROPCTRL_ADDR)
#define rAMCC_MCC1QPROPCTRL DCS_REG_ACCESS(rAMCC_MCC1QPROPCTRL_ADDR)
#define rAMCC_MCCGEN DCS_REG_ACCESS(rAMCC_MCCGEN_ADDR)
#define rAMCC_MCCCFG_TAG_RD_DIS DCS_REG_ACCESS(rAMCC_MCCCFG_TAG_RD_DIS_ADDR)
#define rAMCC_MCCPWRONWAYCNTSTATUS DCS_REG_ACCESS(rAMCC_MCCPWRONWAYCNTSTATUS_ADDR)
/* AMCC1 registers */
#define rAMCC1_MCCCHNLDEC_ADDR (AMCC_BASE_ADDR(1) + 0x4A4)
#define rAMCC1_MCUCHNHASH_ADDR (AMCC_BASE_ADDR(1) + 0x4A8)
#define rAMCC1_DRAMACCCTRL_ADDR (AMCC_BASE_ADDR(1) + 0x4B8)
#define rAMCC1_ADDRCFG_ADDR (AMCC_BASE_ADDR(1) + 0x4CC)
#define rAMCC1_MCC0QPROPCTRL_ADDR (AMCC_BASE_ADDR(1) + 0x648)
#define rAMCC1_MCC1QPROPCTRL_ADDR (AMCC_BASE_ADDR(1) + 0x64C)
#define rAMCC1_MCCGEN_ADDR (AMCC_BASE_ADDR(1) + 0x780)
#define rAMCC1_MCCCFG_TAG_RD_DIS_ADDR (AMCC_BASE_ADDR(1) + 0x794)
#define rAMCC1_MCCPWRONWAYCNTSTATUS_ADDR (AMCC_BASE_ADDR(1) + 0x79C)
#define rAMCC1_MCCCHNLDEC DCS_REG_ACCESS(rAMCC1_MCCCHNLDEC_ADDR)
#define rAMCC1_DRAMACCCTRL DCS_REG_ACCESS(rAMCC1_DRAMACCCTRL_ADDR)
#define rAMCC1_ADDRCFG DCS_REG_ACCESS(rAMCC1_ADDRCFG_ADDR)
#define rAMCC1_MCC0QPROPCTRL DCS_REG_ACCESS(rAMCC1_MCC0QPROPCTRL_ADDR)
#define rAMCC1_MCC1QPROPCTRL DCS_REG_ACCESS(rAMCC1_MCC1QPROPCTRL_ADDR)
#define rAMCC1_MCCGEN DCS_REG_ACCESS(rAMCC1_MCCGEN_ADDR)
#define rAMCC1_MCCCFG_TAG_RD_DIS DCS_REG_ACCESS(rAMCC1_MCCCFG_TAG_RD_DIS_ADDR)
#define rAMCC1_MCCPWRONWAYCNTSTATUS DCS_REG_ACCESS(rAMCC1_MCCPWRONWAYCNTSTATUS_ADDR)
#elif NUM_AMCCS == 1
/* AMCC registers */
#define rAMCC_MCCCHNLDEC_ADDR (AMCC_BASE_ADDR(0) + 0x4A4)
#define rAMCC_DRAMACCCTRL_ADDR (AMCC_BASE_ADDR(0) + 0x4B4)
#define rAMCC_ADDRCFG_ADDR (AMCC_BASE_ADDR(0) + 0x4C8)
#define rAMCC_MCC0QPROPCTRL_ADDR (AMCC_BASE_ADDR(0) + 0x648)
#define rAMCC_MCC1QPROPCTRL_ADDR (AMCC_BASE_ADDR(0) + 0x64C)
#define rAMCC_MCCGEN_ADDR (AMCC_BASE_ADDR(0) + 0x780)
#define rAMCC_MCCCFG_TAG_RD_DIS_ADDR (AMCC_BASE_ADDR(0) + 0x794)
#define rAMCC_MCCPWRONWAYCNTSTATUS_ADDR (AMCC_BASE_ADDR(0) + 0x79C)
#define rAMCC_MCCCHNLDEC DCS_REG_ACCESS(rAMCC_MCCCHNLDEC_ADDR)
#define rAMCC_DRAMACCCTRL DCS_REG_ACCESS(rAMCC_DRAMACCCTRL_ADDR)
#define rAMCC_ADDRCFG DCS_REG_ACCESS(rAMCC_ADDRCFG_ADDR)
#define rAMCC_MCC0QPROPCTRL DCS_REG_ACCESS(rAMCC_MCC0QPROPCTRL_ADDR)
#define rAMCC_MCC1QPROPCTRL DCS_REG_ACCESS(rAMCC_MCC1QPROPCTRL_ADDR)
#define rAMCC_MCCGEN DCS_REG_ACCESS(rAMCC_MCCGEN_ADDR)
#define rAMCC_MCCCFG_TAG_RD_DIS DCS_REG_ACCESS(rAMCC_MCCCFG_TAG_RD_DIS_ADDR)
#define rAMCC_MCCPWRONWAYCNTSTATUS DCS_REG_ACCESS(rAMCC_MCCPWRONWAYCNTSTATUS_ADDR)
#endif // #if NUM_AMCCS == 2
#define AMCC_MCCCFG_TAG_RD_DIS_ADDR(i) (AMCC_BASE_ADDR(i) + 0x794)
#define AMCC_MCCGEN_MCC_RAM_EN (1 << 1)
#define AMCC_MCCGEN_MCC_RAM_EN_LOCK (1 << 16)
#define DCS_NUM_MEG_IN_DRAM_BLK (128)
/* MCU registers */
#define rDCS_MCU_AMCCTRL (DCS_BASE_ADDR + 0x000)
#define rDCS_MCU_CLKGATE (DCS_BASE_ADDR + 0x004)
#define rDCS_MCU_AMCCLKPWRGATE (DCS_BASE_ADDR + 0x010)
#define rDCS_MCU_AMCCLKPWRGATE2 (DCS_BASE_ADDR + 0x014)
#if DCS_REG_VERSION >= 0x10
#define rDCS_MCU_IDLE_EXTEND_CONTROL (DCS_BASE_ADDR + 0x018)
#define rDCS_MCU_DIV_CLK_SELECT (DCS_BASE_ADDR + 0x020)
#endif
#define rDCS_MCU_OPIDLETMR (DCS_BASE_ADDR + 0x180)
#define rDCS_MCU_OPTMRADJEN (DCS_BASE_ADDR + 0x184)
#define rDCS_MCU_OPTMRADJPARAM (DCS_BASE_ADDR + 0x188)
#define rDCS_MCU_MIFNRTAGE (DCS_BASE_ADDR + 0x18C)
#define rDCS_MCU_MIFRTAGE (DCS_BASE_ADDR + 0x190)
#define rDCS_MCU_MIFPCAGE (DCS_BASE_ADDR + 0x194)
#define rDCS_MCU_QBREN (DCS_BASE_ADDR + 0x198)
#define rDCS_MCU_QBRPARAM (DCS_BASE_ADDR + 0x19C)
#if DCS_REG_VERSION >= 0x10
#define rDCS_MCU_QBRPARAM2 (DCS_BASE_ADDR + 0x1A0)
#endif
#define rDCS_MCU_PSQRQCTL0 (DCS_BASE_ADDR + 0x1A4)
#define rDCS_MCU_PSQCPU0LLT_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 0xC) + 0x1A8)
#define rDCS_MCU_PSQCPU1LLT_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 0xC) + 0x1AC)
#define rDCS_MCU_PSQSOCLLT_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 0xC) + 0x1B0)
#define rDCS_MCU_PSQRQTIMER0 (DCS_BASE_ADDR + 0x1D8)
#define rDCS_MCU_PSQRQTIMER1 (DCS_BASE_ADDR + 0x1DC)
#define rDCS_MCU_PSQRQBRST (DCS_BASE_ADDR + 0x1E0)
#define rDCS_MCU_PSQRQSCHCRD (DCS_BASE_ADDR + 0x1E4)
#define rDCS_MCU_PSQWQ_CTL(_n) (DCS_BASE_ADDR + ((_n) * 4) + 0x1E8)
#define rDCS_MCU_PSQWQCTL0 rDCS_MCU_PSQWQ_CTL(0)
#define rDCS_MCU_PSQWQCTL1 rDCS_MCU_PSQWQ_CTL(1)
#define rDCS_MCU_PSQWQCTL2 rDCS_MCU_PSQWQ_CTL(2)
#define rDCS_MCU_PSQWQTHR (DCS_BASE_ADDR + 0x1F4)
#define rDCS_MCU_PSQWQBRST (DCS_BASE_ADDR + 0x1F8)
#define rDCS_MCU_PSQWQSCHCRD (DCS_BASE_ADDR + 0x1FC)
#define rDCS_MCU_QOSLLT (DCS_BASE_ADDR + 0x200)
#define rDCS_MCU_SBQOSUPGCTL (DCS_BASE_ADDR + 0x204)
#define rDCS_MCU_SBQOSUPGISPAIDS (DCS_BASE_ADDR + 0x208)
#define rDCS_MCU_PHYRDWRTIM_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x280)
#define rDCS_MCU_PHYUPDATETIMERS (DCS_BASE_ADDR + 0x300)
#if (DCS_REG_VERSION >= 4 && DCS_REG_VERSION < 0x10)
#define rDCS_MCU_LAT_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x340)
#define rDCS_MCU_CASPCH_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x350)
#define rDCS_MCU_ACT_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x360)
#define rDCS_MCU_AUTOREF_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x370)
#define rDCS_MCU_SELFREF_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x380)
#define rDCS_MCU_PDN (DCS_BASE_ADDR + 0x390)
#define rDCS_MCU_MODEREG (DCS_BASE_ADDR + 0x394)
#define rDCS_MCU_DERATE_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x398)
#define rDCS_MCU_TAT_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x3A8)
#define rDCS_MCU_AUTOREF_PARAMS (DCS_BASE_ADDR + 0x3BC)
#define rDCS_MCU_PDN1 (DCS_BASE_ADDR + 0x3C0)
#define rDCS_MCU_MODEREG1 (DCS_BASE_ADDR + 0x3C4)
#define rDCS_MCU_PDN_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x3C8)
#else
#define rDCS_MCU_LAT_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x380)
#define rDCS_MCU_CASPCH_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x390)
#define rDCS_MCU_ACT_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x3A0)
#define rDCS_MCU_AUTOREF_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x3B0)
#define rDCS_MCU_SELFREF_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x3C0)
#define rDCS_MCU_PDN (DCS_BASE_ADDR + 0x3D0)
#define rDCS_MCU_MODEREG (DCS_BASE_ADDR + 0x3D4)
#define rDCS_MCU_DERATE_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x3D8)
#define rDCS_MCU_TAT_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x3E8)
#define rDCS_MCU_AUTOREF_PARAMS (DCS_BASE_ADDR + 0x3FC)
#endif
#define rDCS_MCU_RWCFG (DCS_BASE_ADDR + 0x400)
#define rDCS_MCU_RNKCFG (DCS_BASE_ADDR + 0x404)
#define rDCS_MCU_AREFEN_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x408)
#define rDCS_MCU_AREFPARAM (DCS_BASE_ADDR + 0x418)
#if (DCS_REG_VERSION >= 4 && DCS_REG_VERSION < 0x10)
#define rDCS_MCU_LONGSR (DCS_BASE_ADDR + 0x420)
#define rDCS_MCU_ODTSZQC (DCS_BASE_ADDR + 0x424)
#define rDCS_MCU_PWRMNGTEN (DCS_BASE_ADDR + 0x428)
#define rDCS_MCU_PWRMNGTPARAM_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x42C)
#define rDCS_MCU_MCPHYUPDTPARAM (DCS_BASE_ADDR + 0x440)
#define rDCS_MCU_READLEVELING (DCS_BASE_ADDR + 0x444)
#define rDCS_MCU_FREQCHNGCTL (DCS_BASE_ADDR + 0x450)
#define rDCS_MCU_FREQCHNGCTL_FREQ(_n,_f) (DCS_BASE_ADDR + ((_n) * 4) + ((_f) * 0x18) + 0x454)
#define rDCS_MCU_FREQCHNGTIM_FREQ(_n) (DCS_BASE_ADDR + ((_n) * 4) + 0x4B4)
#define rDCS_MCU_LS3B_QUIES_CTRL (DCS_BASE_ADDR + 0x838)
#else
#define rDCS_MCU_LONGSR (DCS_BASE_ADDR + 0x41C)
#define rDCS_MCU_ODTSZQC (DCS_BASE_ADDR + 0x420)
#define rDCS_MCU_PWRMNGTEN (DCS_BASE_ADDR + 0x424)
#define rDCS_MCU_PWRMNGTPARAM_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x428)
#define rDCS_MCU_MCPHYUPDTPARAM (DCS_BASE_ADDR + 0x43C)
#define rDCS_MCU_READLEVELING (DCS_BASE_ADDR + 0x440)
#define rDCS_MCU_FREQCHNGCTL (DCS_BASE_ADDR + 0x44C)
#define rDCS_MCU_ROWHAM_CTL(_n) (DCS_BASE_ADDR + ((_n) * 4) + 0x4B0)
#define rDCS_MCU_FREQCHNGCTL_FREQ(_n,_f) (DCS_BASE_ADDR + ((_n) * 4) + ((_f) * 0x18) + 0x450)
#if DCS_REG_VERSION < 3
#define rDCS_MCU_FREQCHNGTIM_FREQ(_n) (DCS_BASE_ADDR + ((_n) * 4) + 0x4C0)
#else
#define rDCS_MCU_FREQCHNGTIM_FREQ(_n) (DCS_BASE_ADDR + ((_n) * 4) + 0x4C4)
#endif // #if DCS_REG_VERSION < 3
#endif // #if (DCS_REG_VERSION >= 4 && DCS_REG_VERSION < 0x10)
#define rDCS_MCU_MRINITCMD_0 (DCS_BASE_ADDR + 0x500)
#define rDCS_MCU_MRINITSTS_0 (DCS_BASE_ADDR + 0x504)
#define rDCS_MCU_INTSTS_0 (DCS_BASE_ADDR + 0x708)
#define rDCS_MCU_MIFQMAXCTRL_FREQ(_f) (DCS_BASE_ADDR + ((_f) * 4) + 0x780)
#define rDCS_MCU_MRINITCMD(_c) DCS_REG_READ_CH(_c,rDCS_MCU_MRINITCMD_0)
#define rDCS_MCU_MRINITSTS(_c) DCS_REG_READ_CH(_c,rDCS_MCU_MRINITSTS_0)
#define rDCS_MCU_INTSTS(_c) DCS_REG_READ_CH(_c,rDCS_MCU_INTSTS_0)
#define MRCMD_POLL_BIT (0x100)
#define MRCMD_RANK_SHIFT (13)
#define MRCMD_CMDTYPE_SHIFT (8)
#define MRCMD_REG_SHIFT (16)
#define MRCMD_DATA_SHIFT (24)
#define MRCMD_TYPE(_h) (((_h) & 0xFF) << MRCMD_CMDTYPE_SHIFT)
#define MRCMD_TYPE_READ MRCMD_TYPE(0x11)
#define MRCMD_TYPE_WRITE MRCMD_TYPE(0x01)
#define MRCMD_TYPE_MPC MRCMD_TYPE(0x41)
/* SPLLCTRL registers */
#define rDCS_SPLLCTRL_MODEREG (DCS_BASE_ADDR + SPLLCTRL_SPACING + 0x000)
#define rDCS_SPLLCTRL_CHARGEPUMP (DCS_BASE_ADDR + SPLLCTRL_SPACING + 0x01C)
#define rDCS_SPLLCTRL_VCO (DCS_BASE_ADDR + SPLLCTRL_SPACING + 0x020)
#define rDCS_SPLLCTRL_LDO (DCS_BASE_ADDR + SPLLCTRL_SPACING + 0x024)
#define rDCS_SPLLCTRL_SPLLPWRDNCFG (DCS_BASE_ADDR + SPLLCTRL_SPACING + 0x05C)
#define rDCS_SPLLCTRL_SPLLDIVCFG (DCS_BASE_ADDR + SPLLCTRL_SPACING + 0x060)
#if DCS_REG_VERSION >= 2
#define rDCS_SPLLCTRL_MDLLPWRDNCFG(_n) (DCS_BASE_ADDR + SPLLCTRL_SPACING + ((_n) * 4) + 0x064)
#endif
#if DCS_REG_VERSION >= 0x10
#define rDCS_SPLLCTRL_RECONFIGSWRESETTRIGGER (DCS_BASE_ADDR + SPLLCTRL_SPACING + 0x074)
#define rDCS_SPLLCTRL_RECONFIGSWRESETCONTROL (DCS_BASE_ADDR + SPLLCTRL_SPACING + 0x078)
#endif
/* AMP registers */
/* _t: type, DQ0, DQ1, or CA */
/* _c: channel, 0 or 1 */
#define AMP_CA (0)
#define AMP_DQ0 (1)
#define AMP_DQ1 (2)
#define DCS_AMP_NUM_PHYS (3)
#define AMP_IFF(__t,_t,_off) (((__t) == (_t))? _off:0)
#define rDCS_AMP_AMPEN(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x000)
#define rDCS_AMP_AMPCLK(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x004)
#define rDCS_AMP_AMPINIT(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x008)
#define rDCS_AMP_DRAM_RESETN(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x00C) // Only for AMPCA
#define rDCS_AMP_AMPVER(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + AMP_IFF(_t,0,4) + 0x00C)
// for AMPCA Only
#define rDCS_AMP_IMPCODE (AMP_BASE_ADDR + 0x080)
#if (DCS_REG_VERSION >= 4 && DCS_REG_VERSION < 0x10)
#define rDCS_AMP_IMPAUTOCAL (AMP_BASE_ADDR + 0x084)
#define rDCS_AMP_IMPCALCONTROL (AMP_BASE_ADDR + 0x088)
#define rDCS_AMP_IMPCALPHYUPDT (AMP_BASE_ADDR + 0x08C)
#define rDCS_AMP_IMPCALCMD (AMP_BASE_ADDR + 0x090)
#else
#define rDCS_AMP_IMPOVRRD (AMP_BASE_ADDR + 0x084)
#define rDCS_AMP_IMPAUTOCAL (AMP_BASE_ADDR + 0x088)
#define rDCS_AMP_IMPCALCONTROL (AMP_BASE_ADDR + 0x08C)
#define rDCS_AMP_IMPCALPHYUPDT (AMP_BASE_ADDR + 0x090)
#define rDCS_AMP_IMPCALCMD (AMP_BASE_ADDR + 0x094)
#define rDCS_AMP_NONDQDSPD_F(_f) (AMP_BASE_ADDR + 0x09C + ((_f) * 4))
#define rDCS_AMP_NONDQDS_F(_f) (AMP_BASE_ADDR + 0x0AC + ((_f) * 4))
#define rDCS_AMP_CACKCSWKPD_F(_f) (AMP_BASE_ADDR + 0x0BC + ((_f) * 4))
#define rDCS_AMP_CACKCSWKDS (AMP_BASE_ADDR + 0x0CC)
#define rDCS_AMP_BISTRXMODE (AMP_BASE_ADDR + 0x0D4)
#endif
#if (DCS_REG_VERSION == 3 || DCS_REG_VERSION >= 0x10)
#define rDCS_AMP_DCCCONTROL (AMP_BASE_ADDR + 0x0DC)
#define rDCS_AMP_DCCTIMER (AMP_BASE_ADDR + 0x0E0)
#define rDCS_AMP_IMPCALCONTROL2 (AMP_BASE_ADDR + 0x0E8)
#if DCS_REG_VERSION >= 0x10
#define rDCS_AMP_IMPCALCONTROL3 (AMP_BASE_ADDR + 0x0EC)
#endif // #if DCS_REG_VERSION >= 0x10
#elif (DCS_REG_VERSION >= 4 && DCS_REG_VERSION < 0x10)
#define rDCS_AMP_DCCCONTROL (AMP_BASE_ADDR + 0x098)
#define rDCS_AMP_DCCTIMER (AMP_BASE_ADDR + 0x09C)
#endif
// For AMPDQn
#define rDCS_AMP_DRAMSIGDLY(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x080 + AMP_IFF(_t,0,0x18))
#define rDCS_AMP_DQDQSDS_F(_t,_f) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x084 + ((_f) * 4))
#define rDCS_AMP_DIFFMODE_FREQ(_t,_f) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x094 + ((_f) * 4))
#define rDCS_AMP_DQFLTCTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x0A4) // For AMPDQn only
#define rDCS_AMP_DCC(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x0A8 + AMP_IFF(_t,0,0x28))
#if DCS_REG_VERSION < 4
#define rDCS_AMP_DQDS_F(_t,_f) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x0AC + ((_f) * 4))
#endif
#define rDCS_AMP_RDCAPCFG_FREQ(_t,_f) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x100 + ((_f) * 4))
#define rDCS_AMP_DQSPDENALWYSON(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x110)
#define rDCS_AMP_DQSPDRES(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x114)
#define rDCS_AMP_RDFIFOPTRSTS(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x118)
#define rDCS_AMP_CALDQMSK(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x11C)
#define rDCS_AMP_CALPATCFG(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x120 - AMP_IFF(_t,0,0x10))
#define rDCS_AMP_DQTRNCFG(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x124 - AMP_IFF(_t,0,0x10))
#define rDCS_AMP_DQTRNCMD(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x128 - AMP_IFF(_t,0,0x10))
#define rDCS_AMP_DQTRNSTS(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x12C - AMP_IFF(_t,0,0x10))
#define rDCS_AMP_DLLEN(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x180)
#define rDCS_AMP_MDLLFREQBINDIS(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x184)
#define rDCS_AMP_MDLLFREQSCALE(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x188)
#define rDCS_AMP_DLLUPDTCMD(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x18C)
#define rDCS_AMP_MDLLOVRRD(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x190 + AMP_IFF(_t,0,4))
#define rDCS_AMP_MDLLCODE(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x194 - AMP_IFF(_t,0,4))
#define rDCS_AMP_DLLLOCKTIM(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x198)
#define rDCS_AMP_DLLLOCKCTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x19C)
#if (DCS_REG_VERSION >= 4 && DCS_REG_VERSION < 0x10)
#define rDCS_AMP_DLLUPDTINTVL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1A0 - AMP_IFF(_t,0,4))
#define rDCS_AMP_DLLUPDTCTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1A4 - AMP_IFF(_t,0,4))
#define rDCS_AMP_CAOUTDLLSCL_FREQ(_f) (AMP_BASE_ADDR + 0x1A4 + ((_f) * 4)) // For AMPCA Only
#define rDCS_AMP_MDLLCODE_CAP_CNTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1BC)
#define rDCS_AMP_MDLL_VTSCALE_CNTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1C0)
#define rDCS_AMP_CAMDLL_VTSCALE_REFCNTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1C4)
#define rDCS_AMP_RDMDLL_VTSCALE_REFCNTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1C8)
#define rDCS_AMP_WRMDLL_VTSCALE_REFCNTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1CC)
#define rDCS_AMP_CA_VTSCALE_FACTOR_STAT(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1D0)
#define rDCS_AMP_RD_VTSCALE_FACTOR_STAT(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1D4)
#define rDCS_AMP_WR_VTSCALE_FACTOR_STAT(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1D8)
#else
#define rDCS_AMP_DLLUPDTINTVL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1A0)
#define rDCS_AMP_DLLUPDTCTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1A4)
#define rDCS_AMP_DQSINDLLSCL_FREQ(_t,_f) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1BC + ((_f) * 4))
#define rDCS_AMP_CAOUTDLLSCL_FREQ(_f) (AMP_BASE_ADDR + 0x1C0 + ((_f) * 4)) // For AMPCA Only
#define rDCS_AMP_MDLLCODE_CAP_CNTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1CC)
#define rDCS_AMP_MDLL_VTSCALE_CNTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1D0)
#define rDCS_AMP_CAMDLL_VTSCALE_REFCNTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1D4)
#define rDCS_AMP_RDMDLL_VTSCALE_REFCNTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1D8)
#define rDCS_AMP_WRMDLL_VTSCALE_REFCNTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1DC)
#define rDCS_AMP_CA_VTSCALE_FACTOR_STAT(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1E0)
#define rDCS_AMP_RD_VTSCALE_FACTOR_STAT(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1E4)
#define rDCS_AMP_WR_VTSCALE_FACTOR_STAT(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x1E8)
#endif
#define rDCS_AMP_TESTMODE(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x200 + AMP_IFF(_t,0,0x180))
// For AMPDQn Only
#define rDCS_AMP_WRDQDESKEW_CTRL(_t,_d) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x400 + ((_d) * 4))
#define rDCS_AMP_WRDQSDESKEW_CTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x420)
#define rDCS_AMP_WRDMDESKEW_CTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x424)
#define rDCS_AMP_RDDQDESKEW_CTRL(_t,_d) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x428 + ((_d) * 4))
#define rDCS_AMP_RDDQSDESKEW_CTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x448)
#define rDCS_AMP_RDDMDESKEW_CTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x44C)
#define rDCS_AMP_WRDQDQSSDLLCTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x600)
#define rDCS_AMP_WRDQDQSSDLLCODE(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x604)
#define rDCS_AMP_RDSDLLCTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x608)
#define rDCS_AMP_RDSDLLCODE(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x60C)
#define rDCS_AMP_RDCAPSDLLCTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x610)
#define rDCS_AMP_RDCAPSDLLCODE(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x614)
#define rDCS_AMP_RDDQSDLL_DLYSEL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x618)
#define rDCS_AMP_SDLL_UPDATE_CNTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x61c + AMP_IFF(_t,0,0xFC))
#define rDCS_AMP_DQSDQ_SKEWCTL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x620)
#define rDCS_AMP_DQSDQ_SKEW(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x624)
#define rDCS_AMP_SDLL_UPDATE_DEFER_EN(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x628 + AMP_IFF(_t,0,0xF4))
#define rDCS_AMP_WRLVL_DLYCHAIN_CTRL(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x700)
#define rDCS_AMP_WRLVL_SDLL_CODE0(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0x704)
// For AMPCA Only
#define rDCS_AMP_CADESKEW_CTRL(_d) (AMP_BASE_ADDR + 0x500 + ((_d) * 4))
#define rDCS_AMP_CSDESKEW_CTRL (AMP_BASE_ADDR + 0x518)
#define rDCS_AMP_CKDESKEW_CTRL (AMP_BASE_ADDR + 0x51C)
#define rDCS_AMP_CASDLLCTRL (AMP_BASE_ADDR + 0x700)
#define rDCS_AMP_CASDLLCODE (AMP_BASE_ADDR + 0x704)
#define rDCS_AMP_CSSDLLCTRL (AMP_BASE_ADDR + 0x708)
#define rDCS_AMP_CSSDLLCODE (AMP_BASE_ADDR + 0x70C)
#define rDCS_AMP_CKSDLLCTRL (AMP_BASE_ADDR + 0x710)
#define rDCS_AMP_CKSDLLCODE (AMP_BASE_ADDR + 0x714)
// Some bit definitions
#define RUNSDLLUPDWRRESULT (1 << 2)
#define SDLLOVRVAL_MASK (0x00FF0000)
#define WRLVLRUNUPDWRRESULT (1 << 9)
#define WRLVLSDLLCODE_MASK (0x000000FF)
#define RUNDESKEWUPD (1 << 8)
#define DESKEWCODE_MASK (0x0000003F)
#define VREFSEL_MASK (0x000000FF)
#define DQSVREFSEL_MASK (0x00FF0000)
#define VTSCALEREFUPDATE (1 << 28)
#define VTSCALEREFSTATUS_MASK (0x000003FF)
#define VTSCALEREFSTATUS_SHIFT (0)
#define VTSCALEREFOVERRIDEVAL_MASK (0x03FF0000)
#define VTSCALEREFOVERRIDEVAL_SHIFT (16)
// #define rDCS_AMP_SDLL_UPDATE_CNTL rDCS_AMP_SDLL_UPDATE_CNTL(0) // 0x718
// #define rDCS_AMP_SDLL_UPDATE_DEFER_EN rDCS_AMP_SDLL_UPDATE_DEFER_EN(0) // 0x71C
#define rDCS_AMP_MCCPWRONWAYCNTCTRL (AMP_BASE_ADDR + 0x798)
#define rDCS_AMP_MCCPWRONWAYCNTSTAT (AMP_BASE_ADDR + 0x79c)
#define rDCS_AMP_MCCALCHINT (AMP_BASE_ADDR + 0x7c8)
#define rDCS_AMP_CAWRLVLSDLLCODE (AMP_BASE_ADDR + 0x800)
#define rDCS_AMP_ODTENABLE_F(_f) (AMP_BASE_ADDR + 0xD00 + ((_f) * 4))
#if (DCS_REG_VERSION >= 4 && DCS_REG_VERSION < 0x10)
#define rDCS_AMP_VREF_F(_t,_f) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0xB00 + AMP_IFF(_t,0,0x200) + ((_f) * 4))
#else
#define rDCS_AMP_VREF_F(_t,_f) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0xB00 + AMP_IFF(_t,0,0x210) + ((_f) * 4))
#endif
#define rDCS_AMPDQ_RDDQSMULFACTOR(_t) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0xD00)
#define rDCS_AMPDQ_DFICALTIMING_F(_t,_f) (AMP_BASE_ADDR + ((_t)*AMP_DQ_SPACING) + 0xD80 + ((_f) * 4))
#define rDCS_AMP_RDWRDQCALTIMING_F(_f) (AMP_BASE_ADDR + 0xE00 + ((_f) * 8))
#define rDCS_AMP_RDWRDQCALSEGLEN_F(_f) (AMP_BASE_ADDR + 0xE04 + ((_f) * 8))
#define rDCS_AMP_HWRDWRDQCALTIMINGCTRL(_n) (AMP_BASE_ADDR + 0xE20 + ((_n) * 4))
#define rDCS_AMP_HWRDDQCALPATPRBS4I (AMP_BASE_ADDR + 0xE2C)
#define rDCS_AMP_HWWRDQCALPATPRBS4I (AMP_BASE_ADDR + 0xE30)
#define rDCS_AMP_HWRDWRDQCALFULLSCANEN (AMP_BASE_ADDR + 0xE34)
#define rDCS_AMP_RDDQCALWINDOW_F(_f) (AMP_BASE_ADDR + 0xE38 + ((_f) * 8))
#define rDCS_AMP_WRDQCALWINDOW_F(_f) (AMP_BASE_ADDR + 0xE3C + ((_f) * 8))
#define rDCS_AMP_DFICALTIMING (AMP_BASE_ADDR + 0xE74)
#define rDCS_AMP_MAXWRDQ_SDLL_MULFACTOR (AMP_BASE_ADDR + 0xE78)
#define rDCS_AMP_MAXRDDQS_SDLL_MULFACTOR (AMP_BASE_ADDR + 0xE7C)
#define rDCS_AMP_MAXWRDQS_SDLL_MULFACTOR (AMP_BASE_ADDR + 0xE80)
#define rDCS_AMPCA_DFICALTIMING_F(_f) (AMP_BASE_ADDR + 0xF80 + ((_f - 1) * 4))
#define rDCS_AMPCA_DFICALTIMING_RDDQCAL2 (AMP_BASE_ADDR + 0xF90 )
#if DCS_REG_VERSION >= 3
#define rDCS_AMP_HWWRDQCALPATPRBS7(_n) (AMP_BASE_ADDR + 0xEA0 + ((_n) * 4))
#define rDCS_AMP_HWWRDQCALPATINVERTMASK (AMP_BASE_ADDR + 0xEB0)
#define rDCS_AMP_HWWRDQCALDYNHALFCLKDLYCTRL (AMP_BASE_ADDR + 0xECC)
#define rDCS_AMP_HWRDDQCALVREFCONTROL (AMP_BASE_ADDR + 0xED8)
#define rDCS_AMP_HWRDDQCALTVREF (AMP_BASE_ADDR + 0xEDC)
#define rDCS_AMP_HWRDDQCALVREFOFFSETCONTROL(_n) (AMP_BASE_ADDR + 0xEE0 + ((_n - 1) * 4))
#define rDCS_AMP_HWWRDQCALVREFCONTROL (AMP_BASE_ADDR + 0xEE8)
#define rDCS_AMP_HWWRDQCALTVREF (AMP_BASE_ADDR + 0xEEC)
#define rDCS_AMP_HWWRDQCALVREFOFFSETCONTROL(_n) (AMP_BASE_ADDR + 0xEF0 + ((_n - 1) * 4))
#define rDCS_AMP_DQCALBURSTLENMODE (AMP_BASE_ADDR + 0xF10)
#define rDCS_AMP_RDDQCALVREFCODECONTROL (AMP_BASE_ADDR + 0xF18)
#define rDCS_AMP_RDDQCALVREFCODESTATUS (AMP_BASE_ADDR + 0xF1C)
#define rDCS_AMP_WRDQCALVREFCODECONTROL (AMP_BASE_ADDR + 0xF20)
#define rDCS_AMP_WRDQCALVREFCODESTATUS (AMP_BASE_ADDR + 0xF24)
#endif
#if DCS_REG_VERSION >= 2
// AMPH
#define rDCS_AMPH_ZCAL_FSM(_n) (AMPH_BASE_ADDR + (_n * 4) + 0x008)
#define rDCS_AMPH_DBG_REG0 (AMPH_BASE_ADDR + 0x024)
#define rDCS_AMPH_CB_DRIVESTR (AMPH_BASE_ADDR + 0x028)
#define rDCS_AMPH_CB_IMPCTL (AMPH_BASE_ADDR + 0x02C)
#define rDCS_AMPH_CB_WKPUPD (AMPH_BASE_ADDR + 0x030)
#define rDCS_AMPH_CB_IOCTL (AMPH_BASE_ADDR + 0x044)
#define rDCS_AMPH_CK_DRIVESTR (AMPH_BASE_ADDR + 0x050)
#define rDCS_AMPH_CK_WKPUPD (AMPH_BASE_ADDR + 0x058)
#define rDCS_AMPH_CK_IOCTL (AMPH_BASE_ADDR + 0x060)
#define rDCS_AMPH_CK_ZDETBIASEN (AMPH_BASE_ADDR + 0x068)
#define rDCS_AMPH_B0_DRIVESTR (AMPH_BASE_ADDR + 0x078)
#define rDCS_AMPH_B0_IMPCTL (AMPH_BASE_ADDR + 0x07C)
#define rDCS_AMPH_B0_WKPUPD (AMPH_BASE_ADDR + 0x080)
#define rDCS_AMPH_B0_DYN_ISEL (AMPH_BASE_ADDR + 0x098)
#define rDCS_AMPH_B0_DYN_ISEL_ASRTIME (AMPH_BASE_ADDR + 0x09C)
#define rDCS_AMPH_B0_IOCTL (AMPH_BASE_ADDR + 0x0A0)
#define rDCS_AMPH_B0_ODT (AMPH_BASE_ADDR + 0x0B0)
#define rDCS_AMPH_B0_ODTCTRL (AMPH_BASE_ADDR + 0x0B4)
#define rDCS_AMPH_DQS0_DRIVESTR (AMPH_BASE_ADDR + 0x0C0)
#define rDCS_AMPH_DQS0_IMPCTL (AMPH_BASE_ADDR + 0x0C4)
#define rDCS_AMPH_DQS0_WKPUPD (AMPH_BASE_ADDR + 0x0C8)
#define rDCS_AMPH_DQS0_DCD_IOCTL (AMPH_BASE_ADDR + 0x0CC)
#define rDCS_AMPH_DQS0_IOCTL (AMPH_BASE_ADDR + 0x0D0)
#define rDCS_AMPH_DQS0_ODT (AMPH_BASE_ADDR + 0x0D8)
#define rDCS_AMPH_DQS0_ZDETBIASEN (AMPH_BASE_ADDR + 0x0DC)
#define rDCS_AMPH_DQS0_ODTCTRL (AMPH_BASE_ADDR + 0x0E0)
#define rDCS_AMPH_B1_DRIVESTR (AMPH_BASE_ADDR + 0x0E8)
#define rDCS_AMPH_B1_IMPCTL (AMPH_BASE_ADDR + 0x0EC)
#define rDCS_AMPH_B1_WKPUPD (AMPH_BASE_ADDR + 0x0F0)
#define rDCS_AMPH_B1_DYN_ISEL (AMPH_BASE_ADDR + 0x108)
#define rDCS_AMPH_B1_IOCTL (AMPH_BASE_ADDR + 0x10C)
#define rDCS_AMPH_B1_ODT (AMPH_BASE_ADDR + 0x11C)
#define rDCS_AMPH_B1_ODTCTRL (AMPH_BASE_ADDR + 0x120)
#define rDCS_AMPH_DQS1_DRIVESTR (AMPH_BASE_ADDR + 0x130)
#define rDCS_AMPH_DQS1_IMPCTL (AMPH_BASE_ADDR + 0x134)
#define rDCS_AMPH_DQS1_WKPUPD (AMPH_BASE_ADDR + 0x138)
#define rDCS_AMPH_DQS1_DCD_IOCTL (AMPH_BASE_ADDR + 0x13C)
#define rDCS_AMPH_DQS1_IOCTL (AMPH_BASE_ADDR + 0x140)
#define rDCS_AMPH_DQS1_ODT (AMPH_BASE_ADDR + 0x148)
#define rDCS_AMPH_DQS1_ODTCTRL (AMPH_BASE_ADDR + 0x14C)
#define rDCS_AMPH_DQS1_ZDETBIASEN (AMPH_BASE_ADDR + 0x150)
#define rDCS_AMPH_DCC_CAL (AMPH_BASE_ADDR + 0x290)
#define rDCS_AMPH_SPARE(_n) (AMPH_BASE_ADDR + (_n * 4) + 0x2FC)
#define rDCS_AMPH_DCC_BYPCA (AMPH_BASE_ADDR + 0x29C)
#define rDCS_AMPH_DCC_BYPCK (AMPH_BASE_ADDR + 0x2A0)
#define rDCS_AMPH_DCC_BYPCS (AMPH_BASE_ADDR + 0x2A4)
#define rDCS_AMPH_DCC_BYPB0 (AMPH_BASE_ADDR + 0x2A8)
#define rDCS_AMPH_DCC_BYPDQS0 (AMPH_BASE_ADDR + 0x2AC)
#define rDCS_AMPH_DCC_BYPB1 (AMPH_BASE_ADDR + 0x2B0)
#define rDCS_AMPH_DCC_BYPDQS1 (AMPH_BASE_ADDR + 0x2B4)
#else
#define rDCS_AMPH_SLC_REG(_n) (AMPH_BASE_ADDR + (_n * 4) + 0x080)
#endif // #if DCS_REG_VERSION >= 2
#define AMP_MAX_RANKS_PER_CHAN (2)
#define DQ_NUM_BITS_PER_BYTE 8
// Global Timer Registers
#define rGLBTIMER_MDLLTIMER (GLBTIMER_BASE_ADDR + 0x000)
#define rGLBTIMER_MDLLVOLTRAMPTIMER (GLBTIMER_BASE_ADDR + 0x004)
#define rGLBTIMER_CTRLUPDMASKTIMER (GLBTIMER_BASE_ADDR + 0x008)
#define rGLBTIMER_IDTTIMER (GLBTIMER_BASE_ADDR + 0x00c)
#define rGLBTIMER_RDCALTIMER (GLBTIMER_BASE_ADDR + 0x010)
#define rGLBTIMER_WRCALTIMER (GLBTIMER_BASE_ADDR + 0x014)
#define rGLBTIMER_ZQCTIMER (GLBTIMER_BASE_ADDR + 0x018)
#if DCS_REG_VERSION >= 0x10
#define rGLBTIMER_FREQCHNG_ACTIVE (GLBTIMER_BASE_ADDR + 0x094)
#endif
#if DCS_REG_VERSION >= 3
#define rGLBTIMER_DCCTIMER (GLBTIMER_BASE_ADDR + 0x01c)
#define rGLBTIMER_PERCAL_FREQCHNGTIMER (GLBTIMER_BASE_ADDR + 0x020)
#define rGLBTIMER_VOLTRAMPTIMER (GLBTIMER_BASE_ADDR + 0x024)
#define rGLBTIMER_IMPCALTIMER (GLBTIMER_BASE_ADDR + 0x028)
#define rGLBTIMER_PERWRCALCFG (GLBTIMER_BASE_ADDR + 0x02c)
#define rGLBTIMER_PERRDCALCFG (GLBTIMER_BASE_ADDR + 0x030)
#define rGLBTIMER_VOLTRAMPCFG (GLBTIMER_BASE_ADDR + 0x034)
#define rGLBTIMER_FREQCHNGCFG (GLBTIMER_BASE_ADDR + 0x038)
#define rGLBTIMER_PMGRWAKEUPCFG (GLBTIMER_BASE_ADDR + 0x03c)
#define rGLBTIMER_FREQBIN3CALCFG (GLBTIMER_BASE_ADDR + 0x040)
#define rGLBTIMER_CHEN (GLBTIMER_BASE_ADDR + 0x044)
#define rGLBTIMER_CAL2PREFREQCHNGDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x048)
#define rGLBTIMER_PREFREQ2ALLBANKDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x050)
#define rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x058)
#define rGLBTIMER_FREQCHNG2PSTCALDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x060)
#define rGLBTIMER_VOLTRAMP2ALLBANKDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x068)
#define rGLBTIMER_ALLBANK2PMGRACKDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x070)
#define rGLBTIMER_PRECALWAITPERIOD (GLBTIMER_BASE_ADDR + 0x078)
#define rGLBTIMER_CALSEG2ALLBANK(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x07C)
#define rGLBTIMER_ALLBANK2CALSEG(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x084)
#define rGLBTIMER_VREFCNTRL (GLBTIMER_BASE_ADDR + 0x08C)
#define rGLBTIMER_PERVREFCALCFG (GLBTIMER_BASE_ADDR + 0x090)
#else
#define rGLBTIMER_PERCAL_FREQCHNGTIMER (GLBTIMER_BASE_ADDR + 0x01c)
#define rGLBTIMER_VOLTRAMPTIMER (GLBTIMER_BASE_ADDR + 0x020)
#define rGLBTIMER_IMPCALTIMER (GLBTIMER_BASE_ADDR + 0x024)
#define rGLBTIMER_PERWRCALCFG (GLBTIMER_BASE_ADDR + 0x028)
#define rGLBTIMER_PERRDCALCFG (GLBTIMER_BASE_ADDR + 0x02c)
#define rGLBTIMER_VOLTRAMPCFG (GLBTIMER_BASE_ADDR + 0x030)
#define rGLBTIMER_FREQCHNGCFG (GLBTIMER_BASE_ADDR + 0x034)
#define rGLBTIMER_PMGRWAKEUPCFG (GLBTIMER_BASE_ADDR + 0x038)
#define rGLBTIMER_FREQBIN3CALCFG (GLBTIMER_BASE_ADDR + 0x03c)
#define rGLBTIMER_CHEN (GLBTIMER_BASE_ADDR + 0x040)
#define rGLBTIMER_CAL2PREFREQCHNGDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x044)
#define rGLBTIMER_PREFREQ2ALLBANKDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x04C)
#define rGLBTIMER_PREFREQCHNG2FREQCHNGDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x054)
#define rGLBTIMER_FREQCHNG2PSTCALDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x05C)
#define rGLBTIMER_VOLTRAMP2ALLBANKDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x064)
#define rGLBTIMER_ALLBANK2PMGRACKDLY(_n) (GLBTIMER_BASE_ADDR + ((_n) * 4) + 0x06C)
#endif // #if DCS_REG_VERSION >= 3
#endif /* _DCS_S8000_H */
drivers/apple/dcs/rules.mk
+27
View File
@@ -0,0 +1,27 @@
# Copyright (C) 2013-2014 Apple Inc. All rights reserved.
#
# This document is the property of Apple Inc.
# It is considered confidential and proprietary.
#
# This document may not be reproduced or transmitted in any form,
# in whole or in part, without the express written permission of
# Apple Inc.
#
LOCAL_DIR := $(GET_LOCAL_DIR)
# Set ENV_IBOOT for calibration code that is shared with SEG
OPTIONS += ENV_IBOOT
ALL_OBJS += \
$(LOCAL_DIR)/dcs.o \
$(LOCAL_DIR)/dcs_init_lib.o
DCS_CAL_LIB_V1_PLATFORMS := s8000 s8003
ifneq ($(filter $(SUB_PLATFORM),$(DCS_CAL_LIB_V1_PLATFORMS)),)
ALL_OBJS += $(LOCAL_DIR)/dcs_calibration.o
else
ALL_OBJS += $(LOCAL_DIR)/dcs_calibration_v2.o
endif
GLOBAL_INCLUDES += $(LOCAL_DIR)/include