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/*
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* Copyright (C) 2009-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <lib/env.h>
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#include <platform/soc/hwregbase.h>
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#include <drivers/dither.h>
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#if DITHER_VERSION == 2
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#include "dither_v2.h"
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#elif DITHER_VERSION == 3
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#include "dither_v3.h"
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#else
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#include "dither_v4.h"
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#endif
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#ifndef DITHER_BASE_ADDR
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#error "DITHER base addr for AppleDither Block is not defined"
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#endif
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static uint8_t dither_type;
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#if DITHER_VERSION == 4
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#ifndef TARGET_DITHER_INBITSREDUCTION
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#define TARGET_DITHER_INBITSREDUCTION 2
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#endif
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#ifndef TARGET_DITHER_EDOUTTOSTINWIDTH
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#define TARGET_DITHER_EDOUTTOSTINWIDTH 3
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#endif
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#ifndef TARGET_DITHER_DITHEROUTWIDTH
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#define TARGET_DITHER_DITHEROUTWIDTH 3
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#endif
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#ifndef TARGET_DITHER_ST_METHOD_MAX
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#define TARGET_DITHER_ST_METHOD_MAX 3
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#endif
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#ifndef TARGET_DITHER_ST_METHOD_POP
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#define TARGET_DITHER_ST_METHOD_POP 0
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#endif
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#ifndef TARGET_DITHER_ST_PHASE
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#define TARGET_DITHER_ST_PHASE 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC0
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#define TARGET_DITHER_ST_SKEWLOC0 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC1
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#define TARGET_DITHER_ST_SKEWLOC1 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC2
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#define TARGET_DITHER_ST_SKEWLOC2 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC3
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#define TARGET_DITHER_ST_SKEWLOC3 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC4
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#define TARGET_DITHER_ST_SKEWLOC4 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC5
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#define TARGET_DITHER_ST_SKEWLOC5 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC6
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#define TARGET_DITHER_ST_SKEWLOC6 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC7
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#define TARGET_DITHER_ST_SKEWLOC7 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC8
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#define TARGET_DITHER_ST_SKEWLOC8 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC9
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#define TARGET_DITHER_ST_SKEWLOC9 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC10
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#define TARGET_DITHER_ST_SKEWLOC10 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC11
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#define TARGET_DITHER_ST_SKEWLOC11 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC12
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#define TARGET_DITHER_ST_SKEWLOC12 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC13
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#define TARGET_DITHER_ST_SKEWLOC13 0
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#endif
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#ifndef TARGET_DITHER_ST_SKEWLOC14
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#define TARGET_DITHER_ST_SKEWLOC14 0
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#endif
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void dither_init(uint32_t display_width, uint32_t display_height, uint32_t display_depth)
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#else
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void dither_init(uint32_t display_depth)
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#endif
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{
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//Fixing the value for now. When the request comes to use a Blue noise, please ask how to make
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//the decision: Based on Target or based on number of dithering bits
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dither_type = DITHER_SPATIO_TEMPORAL;
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#ifdef TARGET_DITHER_TYPE
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dither_type = TARGET_DITHER_TYPE;
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#endif //TARGET_DITHER_TYPE
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#if DITHER_VERSION == 2
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//Number of bits reduced by the dithering algorithm core.
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rDITHER_METHOD = (4 << 4) | ((display_depth <= 18) ? 0x3 : 0x2);
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rDITHER_BOOST_POP = (display_depth <= 18) ? 0x1 : 0x0;
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rDITHER_OUTPUT_WIDTH = (display_depth <=18) ? 0x0 : 0x1;
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#endif
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#if DITHER_VERSION == 3
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switch(dither_type) {
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case DITHER_SPATIO_TEMPORAL:
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dprintf(DEBUG_SPEW, "Spatial_temporal Dither\n");
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//Bypass BN
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//<rdar://problem/11389221> [FPGA DEBUG]: Disabling certains backend blocks via ADBE0:MODE_CTL doesn't disable them
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rDITHER_BN_OP_CFG = (1 << 29);
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rDITHER_ST_METHOD = (0x4 << 4);
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if (display_depth == 24)
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rDITHER_ST_METHOD |= (0x1 << 13) | (0x2 << 0);
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else if (display_depth <= 18)
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rDITHER_ST_METHOD |= (0x1 << 13) | (0x3 << 0);
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else
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panic("unexpected display depth");
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break;
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case DITHER_BLUE_NOISE:
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// Note: If bn_dither_enable is set and st_dither_enable is cleared, the
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// spatio/temporal dither stage must also be disabled internally
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// (see DITHER Register Spec.) by setting SPAT_TEMP_METHOD.mode to 0x4 and
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// SPAT_TEMP_METHOD.depth to 0x0
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dprintf(DEBUG_SPEW, "Blue_noise Dither\n");
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rDITHER_ST_METHOD |= (0x4 << 13);
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rDITHER_ST_METHOD &= ~(0xf); //clear depth
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rDITHER_BN_OP_CFG = 1;
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uint32_t thr_bit;
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switch(display_depth) {
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case 24:
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thr_bit = DITHER_BN_CONST_THR2BIT;
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break;
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case 18:
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thr_bit = DITHER_BN_CONST_THR4BIT;
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rDITHER_BN_OP_CFG |= (0x1 << 24) | (0x1 << 20) | (0x1 << 16);
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break;
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default:
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panic("unexpected display depth");
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}
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rDITHER_BN_CONST = (thr_bit << 16 | thr_bit << 8 | thr_bit << 0);
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break;
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case DITHER_NONE:
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default:
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dprintf(DEBUG_SPEW, "%d is not a supported dithering type. Disabling dithering\n", dither_type);
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//bypassed and clock-gated if both st_dither_enable and bn_dither_enable are
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//cleared
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rDITHER_ST_METHOD = 0;
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rDITHER_BN_OP_CFG = (1 << 29);
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break;
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}
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#endif
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#if DITHER_VERSION == 4
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rDITHER_ACTIVEREGIONSTART = 0 << 16 | 0; //Set active region start
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rDITHER_ACTIVEREGIONSIZE = display_height << 16 | display_width; //Set Active Region
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// Setup for 8-bit panel with VRR
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rDITHER_INBITSREDUCTION = TARGET_DITHER_INBITSREDUCTION;
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rDITHER_EDOUTTOSTINWIDTH = TARGET_DITHER_EDOUTTOSTINWIDTH;
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rDITHER_DITHEROUTWIDTH = TARGET_DITHER_DITHEROUTWIDTH;
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switch(dither_type) {
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case DITHER_SPATIO_TEMPORAL:
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dprintf(DEBUG_SPEW, "Spatial_temporal Dither\n");
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rDITHER_ST_METHOD |= (TARGET_DITHER_ST_METHOD_MAX << 13) | (TARGET_DITHER_ST_METHOD_POP << 8);
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if (display_depth == 24)
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rDITHER_ST_METHOD |= (0x2 << 0);
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else if (display_depth <= 18)
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rDITHER_ST_METHOD |= (0x3 << 0);
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else
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panic("unexpected display depth");
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rDITHER_ST_PHASE = TARGET_DITHER_ST_PHASE;
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rDITHER_ST_SKEWLOC0 = TARGET_DITHER_ST_SKEWLOC0;
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rDITHER_ST_SKEWLOC1 = TARGET_DITHER_ST_SKEWLOC1;
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rDITHER_ST_SKEWLOC2 = TARGET_DITHER_ST_SKEWLOC2;
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rDITHER_ST_SKEWLOC3 = TARGET_DITHER_ST_SKEWLOC3;
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rDITHER_ST_SKEWLOC4 = TARGET_DITHER_ST_SKEWLOC4;
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rDITHER_ST_SKEWLOC5 = TARGET_DITHER_ST_SKEWLOC5;
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rDITHER_ST_SKEWLOC6 = TARGET_DITHER_ST_SKEWLOC6;
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rDITHER_ST_SKEWLOC7 = TARGET_DITHER_ST_SKEWLOC7;
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rDITHER_ST_SKEWLOC8 = TARGET_DITHER_ST_SKEWLOC8;
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rDITHER_ST_SKEWLOC9 = TARGET_DITHER_ST_SKEWLOC9;
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rDITHER_ST_SKEWLOC10 = TARGET_DITHER_ST_SKEWLOC10;
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rDITHER_ST_SKEWLOC11 = TARGET_DITHER_ST_SKEWLOC11;
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rDITHER_ST_SKEWLOC12 = TARGET_DITHER_ST_SKEWLOC12;
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rDITHER_ST_SKEWLOC13 = TARGET_DITHER_ST_SKEWLOC13;
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rDITHER_ST_SKEWLOC14 = TARGET_DITHER_ST_SKEWLOC14;
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rDITHER_ENABLE |= (1 << 1);
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break;
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case DITHER_ERROR_DIFFUSION:
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dprintf(DEBUG_SPEW, "Error Diffusion Dither\n");
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rDITHER_ED_THRESHOLDRED = (8192 << 2);
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rDITHER_ED_THRESHOLDGREEN = (8192 << 2);
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rDITHER_ED_THRESHOLDBLUE = (8192 << 2);
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rDITHER_ENABLE |= (1 << 0);
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break;
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case DITHER_NONE:
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default:
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dprintf(DEBUG_SPEW, "%d is not a supported dithering type. Disabling dithering\n", dither_type);
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//bypassed and clock-gated if both st_dither_enable and bn_dither_enable are
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//cleared
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rDITHER_ST_METHOD = 0;
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break;
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}
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//double buffer registers. force them to update
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rDITHER_UPDATECONTROL = DITHER_UPDATECONTROL_UPDATEENABLETIMING |
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DITHER_UPDATECONTROL_UPDATEREQTIMING ;
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#endif
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}
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void dither_set_enable(bool enable)
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{
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#if DITHER_VERSION == 2
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if (enable) {
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rDITHER_ENABLE = (dither_type == DITHER_SPATIO_TEMPORAL)? (1 << 0) : (1 << 1);
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} else {
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rDITHER_ENABLE = 0;
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}
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#endif
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}
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@@ -0,0 +1,52 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __DITHER_V2_H
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#define __DITHER_V2_H
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#define rDITHER_ENABLE (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0000)) //Enable Dither block
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#define rDITHER_METHOD (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0004)) //Main dithering method setting
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#define rDITHER_VERSION (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0008)) //Block revision number
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#define rDITHER_BOOST_POP (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x000c)) //Bit-popping and bit-boost
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#define rDITHER_OUTPUT_WIDTH (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0010)) //Output bit-width setting
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#define rDITHER_ST_OFFSET (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0014)) //Phase offset for Blue/Red wrt green
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#define rDITHER_ST_SEQUENCE (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0018)) //Phase sequence for over 4 frames
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#define rDITHER_ST_KERNEL0 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x001c)) //Kernel0
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#define rDITHER_ST_KERNEL1 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0020)) //Kernel1
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#define rDITHER_ST_KERNEL2 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0024)) //Kernel2
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#define rDITHER_ST_KERNEL3 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0028)) //Kernel3
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#define rDITHER_ST_KERNEL4 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x002c)) //Kernel4
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#define rDITHER_ST_KERNEL5 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0030)) //Kernel5
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#define rDITHER_ST_KERNEL6 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0034)) //Kernel6
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#define rDITHER_ST_KERNEL7 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0038)) //Kernel7
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#define rDITHER_SKEWLOC0 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x003c)) //Skew location0
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#define rDITHER_SKEWLOC1 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0040)) //Skew location1
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#define rDITHER_SKEWLOC2 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0044)) //Skew location2
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#define rDITHER_SKEWLOC3 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0048)) //Skew location3
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#define rDITHER_SKEWLOC4 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x004c)) //Skew location4
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#define rDITHER_SKEWLOC5 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0050)) //Skew location5
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#define rDITHER_SKEWLOC6 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0054)) //Skew location6
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#define rDITHER_SKEWLOC7 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0058)) //Skew location7
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#define rDITHER_SKEWLOC8 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x005c)) //Skew location8
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#define rDITHER_SKEWLOC9 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0060)) //Skew location9
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#define rDITHER_SKEWLOC10 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0064)) //Skew location10
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#define rDITHER_SKEWLOC11 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0068)) //Skew location11
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#define rDITHER_SKEWLOC12 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x006c)) //Skew location12
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#define rDITHER_SKEWLOC13 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0070)) //Skew location13
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#define rDITHER_SKEWLOC14 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0074)) //Skew location14
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#define rDITHER_REG_UPDATE (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0078)) //Register Update Control
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#define rDITHER_CRC_CON (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x007c)) //CRC Control Register
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#define rDITHER_CRC_R (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0080)) //CRC for R component
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#define rDITHER_CRC_G (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0084)) //CRC for G component
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#define rDITHER_CRC_B (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0088)) //CRC for B component
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#define rDITHER_HACTIVE (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x008c)) //Dither Horizontal Active Width
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#define rDITHER_SPARE (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0090)) //Spare Register
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#endif /* ! __DITHER_V2_H */
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@@ -0,0 +1,54 @@
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/*
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* Copyright (C) 2013 Apple Inc. All rights reserved.
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||||
*
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||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
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#ifndef _DITHER_V3_H
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#define _DITHER_V3_H
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//Space-Temporal Dither Registers
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#define rDITHER_ST_VERSION (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0000)) //Version (major and minor revision number)
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#define rDITHER_ST_METHOD (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0004)) //Dither method setting
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#define rDITHER_ST_PHASE (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0008)) //Sequence of dither matrix rotation phases
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#define rDITHER_ST_KERNEL0 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x000c)) //Kernel bit pattern for input pixel[2:0] == 0
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#define rDITHER_ST_KERNEL1 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0010)) //Kernel bit pattern for input pixel[2:0] == 1
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#define rDITHER_ST_KERNEL2 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0014)) //Kernel bit pattern for input pixel[2:0] == 2
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#define rDITHER_ST_KERNEL3 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0018)) //Kernel bit pattern for input pixel[2:0] == 3
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#define rDITHER_ST_KERNEL4 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x001c)) //Kernel bit pattern for input pixel[2:0] == 4
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#define rDITHER_ST_KERNEL5 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0020)) //Kernel bit pattern for input pixel[2:0] == 5
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#define rDITHER_ST_KERNEL6 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0024)) //Kernel bit pattern for input pixel[2:0] == 6
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#define rDITHER_ST_KERNEL7 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0028)) //Kernel bit pattern for input pixel[2:0] == 7
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#define rDITHER_ST_SKEWLOC0 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x002c)) //Skew location0
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#define rDITHER_ST_SKEWLOC1 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0030)) //Skew location1
|
||||
#define rDITHER_ST_SKEWLOC2 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0034)) //Skew location2
|
||||
#define rDITHER_ST_SKEWLOC3 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0038)) //Skew location3
|
||||
#define rDITHER_ST_SKEWLOC4 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x003c)) //Skew location4
|
||||
#define rDITHER_ST_SKEWLOC5 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0040)) //Skew location5
|
||||
#define rDITHER_ST_SKEWLOC6 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0044)) //Skew location6
|
||||
#define rDITHER_ST_SKEWLOC7 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0048)) //Skew location7
|
||||
#define rDITHER_ST_SKEWLOC8 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x004c)) //Skew location8
|
||||
#define rDITHER_ST_SKEWLOC9 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0050)) //Skew location9
|
||||
#define rDITHER_ST_SKEWLOC10 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0054)) //Skew location10
|
||||
#define rDITHER_ST_SKEWLOC11 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0058)) //Skew location11
|
||||
#define rDITHER_ST_SKEWLOC12 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x005c)) //Skew location12
|
||||
#define rDITHER_ST_SKEWLOC13 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0060)) //Skew location13
|
||||
#define rDITHER_ST_SKEWLOC14 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0064)) //Skew location14
|
||||
#define rDITHER_ST_CRC_CON (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0068)) //CRC Control Register
|
||||
#define rDITHER_ST_CRC_R (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x006c)) //CRC for R component
|
||||
#define rDITHER_ST_CRC_G (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0070)) //CRC for G component
|
||||
#define rDITHER_ST_CRC_B (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0074)) //CRC for B component
|
||||
|
||||
//Blue-noise
|
||||
#define rDITHER_BN_VERSION (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0080)) //Version (major and minor revision number)
|
||||
#define rDITHER_BN_OP_CFG (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0084)) //Configuration of Dither Operation
|
||||
#define rDITHER_BN_CONST (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0088)) //Constant Threshold for Blue Noise Dither
|
||||
#define DITHER_BN_CONST_THR2BIT 0x2
|
||||
#define DITHER_BN_CONST_THR4BIT 0x8
|
||||
#define DITHER_BN_CONST_THR5BIT 0x10
|
||||
|
||||
#endif /* ! _DITHER_V3_H */
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef _DITHER_V4_H
|
||||
#define _DITHER_V4_H
|
||||
|
||||
#define rDITHER_ENABLE (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0000)) //Enable register for pipeline blocks
|
||||
#define rDITHER_UPDATECONTROL (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0004)) //Synchronize LUT and register updates to next vertical blank interval
|
||||
#define DITHER_UPDATECONTROL_UPDATEENABLETIMING (1 << 1)
|
||||
#define DITHER_UPDATECONTROL_UPDATEREQTIMING (1 << 0)
|
||||
|
||||
#define rDITHER_ACTIVEREGIONSTART (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0008)) //Pixel Coordinates of Upper Left Hand of Active Window
|
||||
#define rDITHER_ACTIVEREGIONSIZE (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x000C)) //Width and Height of Active Region
|
||||
#define rDITHER_INBITSREDUCTION (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0010)) //Reduce input pixel width
|
||||
#define rDITHER_EDOUTTOSTINWIDTH (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0014)) //Pixel width between ED and ST
|
||||
#define rDITHER_DITHEROUTWIDTH (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0018)) //Output width of dither pipeline. Unused bits will be 0.
|
||||
|
||||
//ED Dither
|
||||
#define rDITHER_ED_THRESHOLDRED (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0080)) //Per Channel Threshold Registers. This is typically set to equivalent pixel value of .5
|
||||
#define rDITHER_ED_THRESHOLDGREEN (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0084)) //Per Channel Threshold Registers. This is typically set to equivalent pixel value of .5
|
||||
#define rDITHER_ED_THRESHOLDBLUE (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0088)) //Per Channel Threshold Registers. This is typically set to equivalent pixel value of .5
|
||||
|
||||
// XXX - Are these right???
|
||||
#define DITHER_BN_CONST_THR2BIT 0x2
|
||||
#define DITHER_BN_CONST_THR4BIT 0x8
|
||||
#define DITHER_BN_CONST_THR5BIT 0x10
|
||||
|
||||
//Space-Temporal Dither Registers
|
||||
#define rDITHER_ST_METHOD (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0100)) //Dither method setting
|
||||
#define rDITHER_ST_PHASE (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0104)) //Sequence of dither matrix rotation phases
|
||||
#define rDITHER_ST_KERNEL0 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0108)) //Kernel bit pattern for input pixel[2:0] == 0
|
||||
#define rDITHER_ST_KERNEL1 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x010C)) //Kernel bit pattern for input pixel[2:0] == 1
|
||||
#define rDITHER_ST_KERNEL2 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0110)) //Kernel bit pattern for input pixel[2:0] == 2
|
||||
#define rDITHER_ST_KERNEL3 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0114)) //Kernel bit pattern for input pixel[2:0] == 3
|
||||
#define rDITHER_ST_KERNEL4 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0118)) //Kernel bit pattern for input pixel[2:0] == 4
|
||||
#define rDITHER_ST_KERNEL5 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x011C)) //Kernel bit pattern for input pixel[2:0] == 5
|
||||
#define rDITHER_ST_KERNEL6 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0120)) //Kernel bit pattern for input pixel[2:0] == 6
|
||||
#define rDITHER_ST_KERNEL7 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0124)) //Kernel bit pattern for input pixel[2:0] == 7
|
||||
#define rDITHER_ST_SKEWLOC0 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0128)) //Skew location0
|
||||
#define rDITHER_ST_SKEWLOC1 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x012C)) //Skew location1
|
||||
#define rDITHER_ST_SKEWLOC2 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0130)) //Skew location2
|
||||
#define rDITHER_ST_SKEWLOC3 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0134)) //Skew location3
|
||||
#define rDITHER_ST_SKEWLOC4 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0138)) //Skew location4
|
||||
#define rDITHER_ST_SKEWLOC5 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x013C)) //Skew location5
|
||||
#define rDITHER_ST_SKEWLOC6 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0140)) //Skew location6
|
||||
#define rDITHER_ST_SKEWLOC7 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0144)) //Skew location7
|
||||
#define rDITHER_ST_SKEWLOC8 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0148)) //Skew location8
|
||||
#define rDITHER_ST_SKEWLOC9 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x014C)) //Skew location9
|
||||
#define rDITHER_ST_SKEWLOC10 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0150)) //Skew location10
|
||||
#define rDITHER_ST_SKEWLOC11 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0154)) //Skew location11
|
||||
#define rDITHER_ST_SKEWLOC12 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0158)) //Skew location12
|
||||
#define rDITHER_ST_SKEWLOC13 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x015C)) //Skew location13
|
||||
#define rDITHER_ST_SKEWLOC14 (*(volatile u_int32_t *)(DITHER_BASE_ADDR + 0x0160)) //Skew location14
|
||||
|
||||
#endif /* ! _DITHER_V4_H */
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_DITHER=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/dither.o
|
||||
Reference in new issue
Block a user