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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <lib/env.h>
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#include <lib/paint.h>
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#include <lib/syscfg.h>
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#include <drivers/dpb.h>
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#include "dpb.h"
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static void dpb_load_gamma_table(u_int32_t lut_id, u_int32_t *lut_data);
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static void dpb_convert_gamma_tables(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, u_int32_t *mod_red_lut, u_int32_t *mod_green_lut, u_int32_t *mod_blue_lut, struct syscfg_wpcl *wpcl);
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#define DPB_LUT_SIZE_PER_CHANNEL 129
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void dpb_init(void)
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{
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//do not bypass any of the blocks
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//<rdar://problem/13436089> Leave LUT bypass config in default state in DPB::CONTROL_REG
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#ifdef DPB_DETECT_VIB_CONTROL_TUNABLE
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rDPB_DETECT_VBI_CONTROL_REG = DPB_DETECT_VIB_CONTROL_TUNABLE;
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#endif
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}
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bool dpb_get_enable(void)
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{
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return false;
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}
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void dpb_set_enable(bool enable)
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{
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if (enable) {
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rDPB_CONTROL_REG |= DPB_CTRL_ENABLE_CFG;
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} else {
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rDPB_CONTROL_REG &= ~DPB_CTRL_ENABLE_CFG;
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}
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}
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void dpb_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl)
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{
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u_int32_t mod_red_lut[DPB_LUT_SIZE_PER_CHANNEL], mod_green_lut[DPB_LUT_SIZE_PER_CHANNEL], mod_blue_lut[DPB_LUT_SIZE_PER_CHANNEL];
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dpb_convert_gamma_tables(red_lut, green_lut, blue_lut, mod_red_lut, mod_green_lut, mod_blue_lut, wpcl);
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// Load the Gamma Correction Table
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dpb_load_gamma_table(DPB_RED, mod_red_lut);
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dpb_load_gamma_table(DPB_GREEN, mod_green_lut);
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dpb_load_gamma_table(DPB_BLUE, mod_blue_lut);
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// Turn on Gamma Correction
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rDPB_CONTROL_REG |= DPB_CTRL_CGM_ENABLE_CFG;
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// Load the Gamma Correction Table
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dpb_load_gamma_table(DPB_RED, mod_red_lut);
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dpb_load_gamma_table(DPB_GREEN, mod_green_lut);
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dpb_load_gamma_table(DPB_BLUE, mod_blue_lut);
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rDPB_TABLE_CONTROL_REG |= DPB_UPDATE_REGISTERS | DPB_IMMEDIATE_UPDATE | DPB_UPDATE_CGM_GREEN_TABLE | DPB_UPDATE_CGM_RED_TABLE | DPB_UPDATE_CGM_BLUE_TABLE;
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//Wait till HW is cleared
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while ((rDPB_TABLE_CONTROL_REG & DPB_UPDATE_CGM_GREEN_TABLE) && (rDPB_TABLE_CONTROL_REG & DPB_UPDATE_CGM_RED_TABLE) && (rDPB_TABLE_CONTROL_REG & DPB_UPDATE_CGM_BLUE_TABLE));
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// Load the Gamma Correction Table again since the OS reads them (double buffered registers)
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dpb_load_gamma_table(DPB_RED, mod_red_lut);
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dpb_load_gamma_table(DPB_GREEN, mod_green_lut);
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dpb_load_gamma_table(DPB_BLUE, mod_blue_lut);
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}
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static void dpb_load_gamma_table(u_int32_t lut_id, u_int32_t *lut_data)
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{
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u_int32_t cnt;
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u_int32_t lut_size = DPB_LUT_SIZE_PER_CHANNEL;
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volatile u_int32_t * lut_addr;
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switch(lut_id) {
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case DPB_RED:
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lut_addr = &DPB_CGM_RED;
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break;
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case DPB_GREEN:
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lut_addr = &DPB_CGM_GREEN;
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break;
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case DPB_BLUE:
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lut_addr = &DPB_CGM_BLUE;
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break;
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default:
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panic("invalid gamma lut id");
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}
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for (cnt = 0; cnt < lut_size; cnt++, lut_addr++) {
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*lut_addr = lut_data[cnt];
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}
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}
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//Gamma table is passed in the old clcd format, which is not compatible "as is" with dpb HW format.
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// The table provided has the following charasteristics:
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// 1. its values are compressed
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// 2. the layout is linear layout 1..n
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// For H6 , we need the following table charasterictics:
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// 1. decompress
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// 2. layout is bankbased entry = (2N+1) << 16 | 2N
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static void dpb_convert_gamma_tables(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, u_int32_t *mod_red_lut, u_int32_t *mod_green_lut, u_int32_t *mod_blue_lut, struct syscfg_wpcl *wpcl)
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{
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int i, j;
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u_int32_t oddValue, evenValue;
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u_int32_t reg;
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const u_int32_t *orig_luts[3];
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u_int32_t *mod_luts[3];
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uint32_t coeffs[3];
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orig_luts[0] = red_lut;
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orig_luts[1] = green_lut;
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orig_luts[2] = blue_lut;
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mod_luts[0] = mod_red_lut;
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mod_luts[1] = mod_green_lut;
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mod_luts[2] = mod_blue_lut;
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coeffs[0] = wpcl->red;
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coeffs[1] = wpcl->green;
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coeffs[2] = wpcl->blue;
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// For H6, there are 129 10-bit entries on 2 banks, totalling 258:
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// RESERVED1 BANK 1 RESERVED0 BANK 0
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// [31:26] [25:16] [15:10] [9:0]
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// X 1 X 0
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// X 3 X 2
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// ...
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// X 257 X 256
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for (i = 0; i < DPB_LUT_SIZE_PER_CHANNEL; i++)
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{
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for (j = 0; j < 3; j++)
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{
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//extract 2n+1
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oddValue = (2*i+1 >= 257) ? 0 : orig_luts[j][2*i+1];
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//decompress
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oddValue = ((oddValue * coeffs[j]) >> WpCl_Quotation_Denominator) & 0x03FF;
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//extract 2n
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evenValue = orig_luts[j][2*i];
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//decompress
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evenValue = ((evenValue * coeffs[j]) >> WpCl_Quotation_Denominator) & 0x03FF;
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reg = (oddValue << 16) | evenValue;
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mod_luts[j][i] = reg;
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}
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}
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}
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@@ -0,0 +1,117 @@
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/*
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* Copyright (C) 2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __APPLE_DPB_H
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#define __APPLE_DPB_H
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#include <platform/soc/hwregbase.h>
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#ifdef DISP0_DPB_BASE_ADDR
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#define DPB_BASE_ADDR DISP0_DPB_BASE_ADDR
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#endif
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#ifndef DPB_BASE_ADDR
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#error "DPB base addr for AppleDynamicPixelBackligh (DPB) Block is not defined"
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#endif
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#define DPB_RED 0
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#define DPB_GREEN 1
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#define DPB_BLUE 2
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#define rDPB_CONTROL_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0000)) //Main Control Register
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#define DPB_CTRL_CGM_BYPASSCFG (1 << 9)
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#define DPB_CTRL_TMF_BYPASS_CFG (1 << 8)
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#define DPB_CTRL_PMR_BYPASS_CFG (1 << 7)
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#define DPB_CTRL_MIN_PIXEL_MASK_ENABLE_CFG (1 << 6)
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#define DPB_CTRL_CGM_ENABLE_CFG (1 << 5)
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#define DPB_CTRL_PMR_ENABLE_CFG (1 << 4)
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#define DPB_CTRL_LOW_PASS_FILTER_BYPASS_CFG (1 << 3)
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#define DPB_CTRL_SMOOTH_OFF_CFG (1 << 2)
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#define DPB_CTRL_DYNAMIC_TMF_CFG (1 << 1)
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#define DPB_CTRL_ENABLE_CFG (1 << 0)
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#define DPB_CTRL_BCL_ENABLE (1 << 7)
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#define DPB_CTRL_DYNAMIC_BACKLIGHT (1 << 6)
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#define DPB_CTRL_TMF_BYPASS (1 << 5)
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#define DPB_CTRL_MIN_PIXEL_MASK_ENABLE (1 << 4)
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#define DPB_CTRL_TEMPORTAL_FILTER_BYPASS (1 << 3)
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#define DPB_CTRL_SMOOTH_OFF (1 << 2)
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#define DPB_CTRL_DPB_DYNAMIC_TMF (1 << 1)
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#define rDPB_HISTOGRAM_CONTROL_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0004)) //Definition of luminance calculation for histogram
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#define rDPB_WINDOW_UPPER_LEFT_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0008)) //Register defining top and left boundaries of active pixel window
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#define rDPB_WINDOW_BOTTOM_RIGHT_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x000c)) //Register defining bottom and right boundaries of active pixel window
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#define rDPB_LOW_PASS_FILTER_CONTROL_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0010)) //Temporal Filter Control Register 1
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#define rDPB_LOW_PASS_FILTER_CONTROL2_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0014)) //Temporal Filter Control Register 2
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#define rDPB_SLOPE_CONTROL_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0018)) //Slope Control Register
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#define DPB_SLOPEM2_SHIFT (20)
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#define DPB_SLOPEM2_MASK (0x1FF << DPB_SLOPEM2_SHIFT)
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#define rDPB_TABLE_CONTROL_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x001c)) //Synchronize LUT and register updates to next vertical blank interval
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#define DPB_IMMEDIATE_UPDATE (1 << 15)
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#define DPB_DUMP_HISTOGRAM (1 << 14)
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#define DPB_UPDATE_REGISTERS (1 << 13)
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#define DPB_UPDATE_CGM_BLUE_TABLE (1 << 12)
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#define DPB_UPDATE_CGM_GREEN_TABLE (1 << 11)
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#define DPB_UPDATE_CGM_RED_TABLE (1 << 10)
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#define DPB_UPDATE_PMR_BLUE_TABLE (1 << 9)
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#define DPB_UPDATE_PMR_GREEN_TABLE (1 << 8)
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#define DPB_UPDATE_PMR_RED_TABLE (1 << 7)
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#define DPB_UPDATE_ENGAMMA_BLUE_TABLE (1 << 6)
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#define DPB_UPDATE_ENGAMMA_GREEN_TABLE (1 << 5)
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#define DPB_UPDATE_ENGAMMA_RED_TABLE (1 << 4)
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#define DPB_UPDATE_DEGAMMA_BLUE_TABLE (1 << 2)
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#define DPB_UPDATE_DEGAMMA_GREEN_TABLE (1 << 1)
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#define DPB_UPDATE_DEGAMMA_RED_TABLE (1 << 0)
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#define rDPB_DETECT_VBI_CONTROL_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0020)) //Detect VBI Register
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#define rDPB_MAX_SLOPE_CONTROL_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0024)) //Max Slope Control Register
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#define rDPB_SLOPE_STATUS_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0028)) //Slope Status Register
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#define rDPB_HISTOGRAM_BIN_STATUS_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x002c)) //Histogram Bin Status Register
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#define rDPB_HISTOGRAM_PIXEL_CNT_STATUS_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0030)) //Histogram Pixel Count Status Register
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#define rDPB_BACK_LIGHT_LEVEL_STATUS_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0034)) //Backlight Level Status Register
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#define rDPB_FRAME_COUNTER_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0038)) //Frame Counter Register
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#define rDPB_HISTOGRAM_MIN_PIXEL_CNT_STATUS_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x003c)) //Histogram Min Pixel Count Status Register
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#define rDPB_MIN_PIXEL_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0040)) //Minimum Pixel Threshold Register
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#define rDPB_CLIP_PIXEL_CNT_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0044)) //Pixel Count Register
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#define rDPB_MAX_KNEE_POINT_DELTA_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0048)) //Max Kneepoint Delta Register
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#define rDPB_CRC_CONTROL_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x004c)) //CRC Control Register
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#define rDPB_CRC_WINDOW_START_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0050)) //CRC Window Start Register
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#define rDPB_CRC_WINDOW_END_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0054)) //CRC Window End Register
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#define rDPB_CRC0_STATUS_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0058)) //CRC0 Status Register
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#define rDPB_CRC1_STATUS_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x005c)) //CRC1 Status Register (reserved)
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#define rDPB_BACK_LIGHT_CONTROL_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0060)) //Back light control register used to override computed back light value
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#define rDPB_INTERRUPT_CONTROL_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0064)) //DPB Interrupt Control Register
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#define rDPB_INTERRUPT_STATUS_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0068)) //DPB Interrupt Status Register
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#define rDPB_DEGAMMA_KNEE_POINT_STATUS_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x006c)) //Knee Point values in gamma decoded domain
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#define rDPB_DEGAMMA_MAX_BRIGHT_STATUS_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0070)) //Maximum Brightness value in gamma decoded domain
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#define rDPB_VERSION_REG (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0074)) //DPB Version
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//DPB_MEMORY Register
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#define DPB_HISTOGRAM_STATS (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x0400)) // [32][256] Histogram of binned brightness values over one frame
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#define DPB_TMF_RED (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x1000)) // [32][33] Tone Modifier LUT, Red component
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#define DPB_TMF_GREEN (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x1400)) // [32][33] Tone Modifier LUT, Green component
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#define DPB_TMF_BLUE (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x1800)) // [32][33] Tone Modifier LUT, Blue component
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#define DPB_PMR_RED (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x2000)) // [32][129] Pixel Manager LUT, Red component
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#define DPB_PMR_GREEN (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x2400)) // [32][129] Pixel Manager LUT, Green component
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#define DPB_PMR_BLUE (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x2800)) // [32][129] Pixel Manager LUT, Blue component
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#define DPB_CGM_RED (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x3000)) // [32][129] Gamma Correction LUT, Red component
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#define DPB_CGM_GREEN (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x3400)) // [32][129] Gamma Correction LUT, Green component
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#define DPB_CGM_BLUE (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x3800)) // [32][129] Gamma Correction LUT, Blue component
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#define DPB_DEGAMMA_RED (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x4000)) // [32][65] Gamma Decode LUT, Red component
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#define DPB_DEGAMMA_GREEN (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x4400)) // [32][65] Gamma Decode LUT, Green component
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#define DPB_DEGAMMA_BLUE (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x4800)) // [32][65] Gamma Decode LUT, Blue component
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#define DPB_DEGAMMA_SLOPE (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x4c00)) // [32][65] Slope LUT in gamma-decoded domain
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#define DPB_ENGAMMA_RED (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x5000)) // [32][113] Gamma encode LUT, Red component
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#define DPB_ENGAMMA_GREEN (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x5400)) // [32][113] Gamma encode LUT, Green component
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#define DPB_ENGAMMA_BLUE (*(volatile u_int32_t *)(DPB_BASE_ADDR + 0x5800)) // [32][113] Gamma encode LUT, Blue component
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#endif /* ! __APPLE_DPB_H */
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@@ -0,0 +1,17 @@
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# Copyright (C) 2012 Apple Inc. All rights reserved.
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#
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# This document is the property of Apple Inc.
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# It is considered confidential and proprietary.
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#
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# This document may not be reproduced or transmitted in any form,
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# in whole or in part, without the express written permission of
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# Apple Inc.
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#
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LOCAL_DIR := $(GET_LOCAL_DIR)
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OPTIONS += \
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WITH_DPB=1 \
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DPB_VERSION=1
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ALL_OBJS += \
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$(LOCAL_DIR)/dpb.o
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