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// *****************************************************************************
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//
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// File: H2fmi_private.h
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//
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// *****************************************************************************
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//
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// Notes:
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//
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// - register bitfield definitions are only good for creating bitfield in
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// register position; add definitions for extracting value from register
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// position
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//
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// *****************************************************************************
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//
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// Copyright (C) 2008 Apple Computer, Inc. All rights reserved.
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//
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// This document is the property of Apple Computer, Inc.
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// It is considered confidential and proprietary.
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//
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// This document may not be reproduced or transmitted in any form,
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// in whole or in part, without the express written permission of
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// Apple Computer, Inc.
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//
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// *****************************************************************************
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#ifndef _H2FMI_PRIVATE_H_
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#define _H2FMI_PRIVATE_H_
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#include <sys/task.h>
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#include "H2fmi_regs.h"
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// =============================================================================
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// preprocessor platform identification
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// =============================================================================
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#if (defined(APPLICATION_SECUREROM) && APPLICATION_SECUREROM)
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#define H2FMI_BOOTROM true
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#else
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#define H2FMI_BOOTROM false
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#endif
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#if (defined(APPLICATION_EMBEDDEDIOP) && APPLICATION_EMBEDDEDIOP)
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#define H2FMI_IOP true
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#else
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#define H2FMI_IOP false
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#endif
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#if (defined(APPLICATION_IBOOT) && APPLICATION_IBOOT)
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#define H2FMI_IBOOT true
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#else
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#define H2FMI_IBOOT false
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#endif
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// TODO: add EFI platform identification
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// =============================================================================
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// configurable preprocessor compilation control
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// =============================================================================
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// Set H2FMI_DEBUG below to true if you want to build with extra
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// debugging features (default to false).
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#define H2FMI_DEBUG false
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// Set H2FMI_TEST_HOOK below to true if you want to insert tests at the end
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// of FIL_Init in iBoot (default to false).
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#define H2FMI_TEST_HOOK false
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// Set H2FMI_DMA_SYNC_READ and/or H2FMI_DMA_SYNC_WRITE to true in order to
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// force read and/or write operations to only use the synchronous interface
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// to the CDMA. This is a workaround for a problem with async dma that is
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// currently under investigation.
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#define H2FMI_DMA_SYNC_READ false
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#define H2FMI_DMA_SYNC_WRITE false
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// Set H2FMI_WAIT_USING_ISR to true if you want operations to wait for
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// dma and bus events by hooking an interrupt service routine to the
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// FMI interrupt vector; set to false for waiting using register
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// polling with yield (default to true).
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#define H2FMI_WAIT_USING_ISR true
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// =============================================================================
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// fixed preprocessor compilation control
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// =============================================================================
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// Always build SecureROM read-only.
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#if (H2FMI_BOOTROM)
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#define H2FMI_READONLY true
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// Also, EmbeddedIOP builds should always be read/write.
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#elif (H2FMI_IOP)
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#define H2FMI_READONLY false
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// Otherwise, ignore nand driver read-only configuration in iBoot
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// debug builds so that erase/write are available for use in testing
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// read operations.
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#elif (H2FMI_IBOOT && defined(AND_READONLY) && H2FMI_DEBUG)
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#define H2FMI_READONLY false
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// Otherwise, mirror nand driver configuration in iBoot.
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#elif (defined(AND_READONLY))
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#define H2FMI_READONLY true
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#else
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#define H2FMI_READONLY false
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#endif
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// =============================================================================
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// preprocessor constant definitions
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// =============================================================================
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#define H2FMI_META_PER_ENVELOPE 10
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#define H2FMI_BYTES_PER_META 10
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#define H2FMI_MAX_DEVICE 8UL
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#define H2FMI_BYTES_PER_SECTOR 512UL
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#define H2FMI_WORDS_PER_SECTOR (H2FMI_BYTES_PER_SECTOR / sizeof(uint32_t))
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#define H2FMI_BOOT_SECTORS_PER_PAGE 3UL
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#define H2FMI_BOOT_BYTES_PER_PAGE (H2FMI_BYTES_PER_SECTOR * H2FMI_BOOT_SECTORS_PER_PAGE)
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#define H2FMI_DEFAULT_TIMEOUT_MICROS ((utime_t)(2 * 1000 * 1000))
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#define H2FMI_PAGE_TIMEOUT_MICROS ((utime_t)(2 * 1000 * 1000))
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#define H2FMI_NAND_ID_SIZE 5
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// conservative bus timings used for boot and Read Id during init
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#define H2FMI_INIT_READ_CYCLE_NANOS 200
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#define H2FMI_INIT_READ_SETUP_NANOS 100
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#define H2FMI_INIT_READ_HOLD_NANOS 100
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#define H2FMI_INIT_WRITE_CYCLE_NANOS 200
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#define H2FMI_INIT_WRITE_SETUP_NANOS 100
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#define H2FMI_INIT_WRITE_HOLD_NANOS 100
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// =============================================================================
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// type declarations
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// =============================================================================
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typedef uint32_t h2fmi_ce_t;
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typedef uint32_t h2fmi_chipid_t;
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struct _h2fmi_t
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{
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volatile uint32_t* regs;
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uint32_t num_of_ce;
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uint32_t pages_per_block;
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uint32_t sectors_per_page;
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uint32_t bytes_per_spare;
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uint32_t blocks_per_ce;
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uint32_t banks_per_ce;
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uint32_t bytes_per_meta;
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uint32_t if_ctrl;
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uint32_t isr_condition;
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struct task_event dma_data_done_event;
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struct task_event dma_meta_done_event;
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struct task_event isr_event;
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bool initialized;
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};
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typedef struct _h2fmi_t h2fmi_t;
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struct _h2fmi_virt_to_phys_map_t
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{
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uint32_t bus;
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h2fmi_ce_t ce;
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};
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typedef struct _h2fmi_virt_to_phys_map_t h2fmi_virt_to_phys_map_t;
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// =============================================================================
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// general fail macro
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// =============================================================================
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#define h2fmi_fail(b) \
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do { \
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dprintf(DEBUG_CRITICAL, \
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"[FIL:ERR] FAIL -> %s@%d\n", \
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__FILE__, __LINE__); \
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b = false; \
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} while (0)
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// =============================================================================
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// fmi bus selection macros
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//
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// Note: this doesn't scale nicely past two buses
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// =============================================================================
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#define h2fmi_select_by_bus(fmi, sel0, sel1) ((fmi->regs == FMI0) ? sel0 : sel1)
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#define h2fmi_bus_index(fmi) h2fmi_select_by_bus(fmi, 0, 1)
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// =============================================================================
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// dma-related macros
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// =============================================================================
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#define h2fmi_dma_data_chan(fmi) h2fmi_select_by_bus(fmi, DMA_FMI0DATA, DMA_FMI1DATA)
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#define h2fmi_dma_meta_chan(fmi) h2fmi_select_by_bus(fmi, DMA_FMI0CHECK, DMA_FMI1CHECK)
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#define h2fmi_dma_meta_fifo(fmi) ((void*)(((uint32_t)fmi->regs) + FMI_META_FIFO))
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#define h2fmi_dma_data_fifo(fmi) ((void*)(((uint32_t)fmi->regs) + FMI_DATA_BUF))
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// =============================================================================
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// busy wait macro
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//
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// this should only be used for very short waits that should never halt
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// during code sequences where performance matters
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// =============================================================================
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#define h2fmi_busy_wait(fmi, reg, mask, cond) \
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do { \
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uint32_t val; \
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do { \
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val = h2fmi_rd(fmi, reg); \
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} while ((val & (mask)) != (cond)); \
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h2fmi_wr(fmi, reg, (val & ~(mask)) | (~(cond) & (mask))); \
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} while (0)
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// =============================================================================
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// cache operation size macro
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// =============================================================================
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// TODO: refactor this cache line rounding functionality
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#if (H2FMI_IOP)
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#define cache_op_size(buf_size) (((buf_size) + (CPU_CACHELINE_SIZE-1)) & ~(CPU_CACHELINE_SIZE-1))
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#else
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#define cache_op_size(buf_size) buf_size
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#endif
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// =============================================================================
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// nand device command bytes
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// =============================================================================
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#define NAND_CMD__RESET ((uint8_t)0xFF)
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#define NAND_CMD__READ_ID ((uint8_t)0x90)
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#define NAND_CMD__READ_STATUS ((uint8_t)0x70)
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#define NAND_CMD__READ ((uint8_t)0x00)
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#define NAND_CMD__READ_CONFIRM ((uint8_t)0x30)
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#define NAND_CMD__ERASE ((uint8_t)0x60)
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#define NAND_CMD__ERASE_CONFIRM ((uint8_t)0xD0)
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#define NAND_CMD__WRITE ((uint8_t)0x80)
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#define NAND_CMD__WRITE_CONFIRM ((uint8_t)0x10)
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// =============================================================================
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// nand operations timeout specifications
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// =============================================================================
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#define TIMEOUT_MICROSEC_READ ((uint32_t)1000)
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#define TIMEOUT_MICROSEC_WRITE ((uint32_t)5000)
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#define TIMEOUT_MICROSEC_ERASE ((uint32_t)15000)
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// =============================================================================
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// nand operations status specifications
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// =============================================================================
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#define NAND_STATUS__CHIP_STATUS1 ((uint8_t)1 << 0)
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#define NAND_STATUS__CHIP_STATUS1_FAIL ((uint8_t)1 << 0)
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#define NAND_STATUS__CHIP_STATUS1_PASS ((uint8_t)0 << 0)
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#define NAND_STATUS__CHIP_STATUS2 ((uint8_t)1 << 1)
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#define NAND_STATUS__CHIP_STATUS2_FAIL ((uint8_t)1 << 1)
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#define NAND_STATUS__CHIP_STATUS2_PASS ((uint8_t)0 << 1)
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// bits 2-4 are not used
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#define NAND_STATUS__PAGE_BUFFER_RB ((uint8_t)1 << 5)
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#define NAND_STATUS__PAGE_BUFFER_RB_READY ((uint8_t)1 << 5)
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#define NAND_STATUS__PAGE_BUFFER_RB_BUSY ((uint8_t)0 << 5)
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#define NAND_STATUS__DATA_CACHE_RB ((uint8_t)1 << 6)
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#define NAND_STATUS__DATA_CACHE_RB_READY ((uint8_t)1 << 6)
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#define NAND_STATUS__DATA_CACHE_RB_BUSY ((uint8_t)0 << 6)
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#define NAND_STATUS__WRITE_PROTECT ((uint8_t)1 << 7)
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#define NAND_STATUS__WRITE_PROTECT_NOT_PROTECTED ((uint8_t)1 << 7)
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#define NAND_STATUS__WRITE_PROTECT_PROTECTED ((uint8_t)0 << 7)
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// =============================================================================
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// implementation function declarations shared between SecureROM and iBoot
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// =============================================================================
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bool h2fmi_init_minimal(h2fmi_t* fmi, uint32_t interface);
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void h2fmi_ungate(h2fmi_t* fmi);
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void h2fmi_gate(h2fmi_t* fmi);
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void h2fmi_reset(h2fmi_t* fmi);
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void h2fmi_calc_bus_timings(h2fmi_t* fmi, uint32_t min_read_cycle_nanos, uint32_t min_read_setup_nanos, uint32_t min_read_hold_nanos, uint32_t min_write_cycle_nanos, uint32_t min_write_setup_nanos, uint32_t min_write_hold_nanos);
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bool h2fmi_is_chipid_invalid(uint32_t id);
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bool h2fmi_wait_done(h2fmi_t* fmi, uint32_t reg, uint32_t mask, uint32_t bits);
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bool h2fmi_wait_dma_task_pending(h2fmi_t* fmi);
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void h2fmi_clean_ecc(h2fmi_t* fmi);
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void h2fmi_fmc_read_data(h2fmi_t* fmi, uint32_t size, uint8_t* data);
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bool h2fmi_nand_reset(h2fmi_t* fmi, h2fmi_ce_t ce);
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bool h2fmi_nand_read_id(h2fmi_t* fmi, h2fmi_ce_t ce, uint32_t* id);
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bool h2fmi_pio_read_sector(h2fmi_t* fmi, void* buf);
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// =============================================================================
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// implementation function declarations not used by SecureROM
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// =============================================================================
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#if (!H2FMI_BOOTROM)
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bool h2fmi_init_fil(h2fmi_t* fmi, uint32_t interface, void* scratch_buf);
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void h2fmi_init_sys(h2fmi_t* fmi);
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bool h2fmi_erase_blocks(h2fmi_t* fmi, uint32_t ce, uint32_t block, bool* status_failed);
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bool h2fmi_write_page(h2fmi_t* fmi, uint32_t ce, uint32_t page, uint8_t* data_buf, uint8_t* meta_buf, bool* status_failed);
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bool h2fmi_read_page(h2fmi_t* fmi, uint32_t ce, uint32_t page, uint8_t* data_buf, uint8_t* meta_buf, uint8_t* max_corrected, bool* is_clean);
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bool h2fmi_write_multi(h2fmi_t* fmi, uint32_t page_count, uint32_t* chip_enable_array, uint32_t* page_number_array, uint8_t** data_buf_array, uint8_t** meta_buf_array, bool* status_failed);
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bool h2fmi_reset_and_read_chipids(h2fmi_t* fmi, h2fmi_chipid_t* ids);
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bool h2fmi_nand_reset_all(h2fmi_t* fmi);
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void h2fmi_nand_read_chipid(h2fmi_t* fmi, h2fmi_ce_t ce, h2fmi_chipid_t* id);
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uint32_t h2fmi_config_raw_data_format(h2fmi_t* fmi);
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uint32_t h2fmi_config_raw_spare_format(void);
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uint32_t h2fmi_config_page_format(h2fmi_t* fmi);
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void h2fmi_config_page_addr(h2fmi_t* fmi, uint32_t page);
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bool h2fmi_using_16bit_ecc(h2fmi_t* fmi);
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bool h2fmi_read_raw_page(h2fmi_t* fmi, uint32_t ce, uint32_t page, uint8_t* data_buf, uint8_t* spare_buf);
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bool h2fmi_wait_status(h2fmi_t* fmi, uint8_t io_mask, uint8_t io_cond, uint8_t* status);
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void h2fmi_dma_data_done_handler(void* arg);
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void h2fmi_dma_meta_done_handler(void* arg);
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||||
void h2fmiInitVirtToPhysMap(void);
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void h2fmiMapBankToBusAndEnable(uint32_t bank, uint32_t bus, h2fmi_ce_t enable);
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h2fmi_t* h2fmiTranslateBankToBus(uint32_t bank);
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||||
h2fmi_ce_t h2fmiTranslateBankToCe(uint32_t bank);
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||||
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||||
#endif // !H2FMI_BOOTROM
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||||
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||||
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||||
// =============================================================================
|
||||
// implementation function declarations used only for debug during development
|
||||
//
|
||||
// note that these are designed so that the calls will disappear when
|
||||
// not compiling for debug
|
||||
// =============================================================================
|
||||
|
||||
#if (H2FMI_DEBUG)
|
||||
|
||||
bool h2fmi_test_hook(h2fmi_t* fmi);
|
||||
void h2fmi_spew_config(h2fmi_t* fmi);
|
||||
void h2fmi_spew_status_regs(h2fmi_t* fmi, const char* prefix);
|
||||
void h2fmi_spew_fmi_regs(h2fmi_t* fmi, const char* prefix);
|
||||
void h2fmi_spew_fmc_regs(h2fmi_t* fmi, const char* prefix);
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||||
void h2fmi_spew_ecc_regs(h2fmi_t* fmi, const char* prefix);
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||||
void h2fmi_spew_regs(h2fmi_t* fmi, const char* prefix);
|
||||
void h2fmi_spew_buffer(uint8_t* buf, size_t size);
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||||
|
||||
#else
|
||||
|
||||
#define h2fmi_test_hook(fmi_ignored) true
|
||||
#define h2fmi_spew_config(fmi_ignored)
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||||
#define h2fmi_spew_status_regs(fmi_ignored, prefix_ignored)
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||||
#define h2fmi_spew_fmi_regs(fmi_ignored, prefix_ignored)
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||||
#define h2fmi_spew_fmc_regs(fmi_ignored, prefix_ignored)
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||||
#define h2fmi_spew_ecc_regs(fmi_ignored, prefix_ignored)
|
||||
#define h2fmi_spew_regs(fmi_ignored, prefix_ignored)
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||||
#define h2fmi_spew_buffer(buf_ignored, size_ignored)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif // _H2FMI_PRIVATE_H_
|
||||
|
||||
// ********************************** EOF **************************************
|
||||
@@ -0,0 +1,761 @@
|
||||
// *****************************************************************************
|
||||
//
|
||||
// File: H2fmi_regs.h
|
||||
//
|
||||
// *****************************************************************************
|
||||
//
|
||||
// Notes:
|
||||
//
|
||||
// - register bitfield definitions are only good for creating bitfield in
|
||||
// register position
|
||||
//
|
||||
// - consider adding definitions for extracting value from register position
|
||||
//
|
||||
// *****************************************************************************
|
||||
//
|
||||
// Copyright (C) 2008 Apple Computer, Inc. All rights reserved.
|
||||
//
|
||||
// This document is the property of Apple Computer, Inc.
|
||||
// It is considered confidential and proprietary.
|
||||
//
|
||||
// This document may not be reproduced or transmitted in any form,
|
||||
// in whole or in part, without the express written permission of
|
||||
// Apple Computer, Inc.
|
||||
//
|
||||
// *****************************************************************************
|
||||
|
||||
#ifndef _H2FMI_REGS_H_
|
||||
#define _H2FMI_REGS_H_
|
||||
|
||||
#include <sys/types.h>
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
// =============================================================================
|
||||
// preprocessor compilation control
|
||||
// =============================================================================
|
||||
|
||||
// Change the constant below to true if you want to see all FMI
|
||||
// subsystem register writes; note that doing so is likely to change
|
||||
// timing and therefore behavior, so it should be a rare case that you
|
||||
// would ever want to do this.
|
||||
#define H2FMI_TRACE_REG_WRITES false
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// register access macros
|
||||
// =============================================================================
|
||||
|
||||
#define h2fmi_wr(fmi, reg, val) ((fmi)->regs[(reg) >> 2] = (val))
|
||||
#define h2fmi_rd(fmi, reg) ((fmi)->regs[(reg) >> 2])
|
||||
#define h2fmi_rd8(fmi, reg) (((volatile uint8_t*)((fmi)->regs))[reg])
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// register bases and offsets
|
||||
// =============================================================================
|
||||
|
||||
#define FMI0 ((volatile uint32_t*)FMI0_BASE_ADDR)
|
||||
#define FMI1 ((volatile uint32_t*)FMI1_BASE_ADDR)
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define FMI_BA(offset) ((uint32_t)(0x000 + offset))
|
||||
#define FMC_BA(offset) ((uint32_t)(0x400 + offset))
|
||||
#define ECC_BA(offset) ((uint32_t)(0x800 + offset))
|
||||
|
||||
#else
|
||||
|
||||
#define FMI_BA(offset) ((uint32_t)(0x00000 + offset))
|
||||
#define FMC_BA(offset) ((uint32_t)(0x40000 + offset))
|
||||
#define ECC_BA(offset) ((uint32_t)(0x80000 + offset))
|
||||
|
||||
#endif
|
||||
|
||||
#define FMI_CONFIG FMI_BA(0x00)
|
||||
#define FMI_CONTROL FMI_BA(0x04)
|
||||
#define FMI_STATUS FMI_BA(0x08)
|
||||
#define FMI_INT_PEND FMI_BA(0x0C)
|
||||
#define FMI_INT_EN FMI_BA(0x10)
|
||||
#define FMI_DATA_BUF FMI_BA(0x14)
|
||||
#define FMI_META_FIFO FMI_BA(0x18)
|
||||
#define FMI_DEBUG0 FMI_BA(0x1C)
|
||||
#define FMI_DEBUG1 FMI_BA(0x20)
|
||||
#define FMI_DEBUG2 FMI_BA(0x24)
|
||||
#if FMI_VERSION > 2
|
||||
#define FMI_SCRAMBLER_SEED_FIFO FMI_BA(0x3C)
|
||||
#endif
|
||||
|
||||
#if FMI_VERSION > 0
|
||||
|
||||
#define FMI_DEBUG3 FMI_BA(0x28)
|
||||
#define FMI_HW_VERSION FMI_BA(0x30)
|
||||
#define FMI_DATA_SIZE FMI_BA(0x34)
|
||||
|
||||
#endif
|
||||
|
||||
#define FMC_ON FMC_BA(0x00)
|
||||
#define FMC_VER FMC_BA(0x04)
|
||||
#define FMC_IF_CTRL FMC_BA(0x08)
|
||||
#define FMC_CE_CTRL FMC_BA(0x0C)
|
||||
#define FMC_RW_CTRL FMC_BA(0x10)
|
||||
#define FMC_CMD FMC_BA(0x14)
|
||||
#define FMC_ADDR0 FMC_BA(0x18)
|
||||
#define FMC_ADDR1 FMC_BA(0x1C)
|
||||
#define FMC_ADDRNUM FMC_BA(0x20)
|
||||
#define FMC_DATANUM FMC_BA(0x24)
|
||||
#define FMC_UNDEF0 FMC_BA(0x28)
|
||||
#define FMC_UNDEF1 FMC_BA(0x2C)
|
||||
#define FMC_TO_CTRL FMC_BA(0x30)
|
||||
#define FMC_TO_CNT FMC_BA(0x34)
|
||||
#define FMC_UNDEF2 FMC_BA(0x38)
|
||||
#define FMC_UNDEF3 FMC_BA(0x3C)
|
||||
#define FMC_INTMASK FMC_BA(0x40)
|
||||
#define FMC_STATUS FMC_BA(0x44)
|
||||
#define FMC_NAND_STATUS FMC_BA(0x48)
|
||||
#define FMC_RBB_CONFIG FMC_BA(0x4C)
|
||||
#define FMC_LOCK0_L FMC_BA(0x50)
|
||||
#define FMC_LOCK0_H FMC_BA(0x54)
|
||||
#define FMC_LOCK1_L FMC_BA(0x58)
|
||||
#define FMC_LOCK1_H FMC_BA(0x5C)
|
||||
#define FMC_LOCK2_L FMC_BA(0x60)
|
||||
#define FMC_LOCK2_H FMC_BA(0x64)
|
||||
#define FMC_ALARMCMD FMC_BA(0x68)
|
||||
#define FMC_REJECTCMD FMC_BA(0x6C)
|
||||
|
||||
#define ECC_VERSION ECC_BA(0x00)
|
||||
#define ECC_CON0 ECC_BA(0x04)
|
||||
#define ECC_CON1 ECC_BA(0x08)
|
||||
#define ECC_RESULT ECC_BA(0x0C)
|
||||
#define ECC_PND ECC_BA(0x10)
|
||||
#define ECC_MASK ECC_BA(0x14)
|
||||
#define ECC_HISTORY ECC_BA(0x18)
|
||||
#define ECC_CORE_SW_RESET ECC_BA(0x1C)
|
||||
#define ECC_LOC0 ECC_BA(0x20)
|
||||
#define ECC_LOC1 ECC_BA(0x24)
|
||||
#define ECC_LOC2 ECC_BA(0x28)
|
||||
#define ECC_LOC3 ECC_BA(0x2C)
|
||||
#define ECC_LOC4 ECC_BA(0x30)
|
||||
#define ECC_LOC5 ECC_BA(0x34)
|
||||
#define ECC_LOC6 ECC_BA(0x38)
|
||||
#define ECC_UNDEF0 ECC_BA(0x3C)
|
||||
#define ECC_PARITY0 ECC_BA(0x40)
|
||||
#define ECC_PARITY1 ECC_BA(0x44)
|
||||
#define ECC_PARITY2 ECC_BA(0x48)
|
||||
#define ECC_PARITY3 ECC_BA(0x4C)
|
||||
#define ECC_PARITY4 ECC_BA(0x50)
|
||||
#define ECC_PARITY5 ECC_BA(0x54)
|
||||
#define ECC_PARITY6 ECC_BA(0x58)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMI_CONFIG bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define FMI_CONFIG__DMA_BURST(n) (((n) & 0x7) << 17)
|
||||
#define FMI_CONFIG__LBA_MODE(v) (((v) & 0x3) << 15)
|
||||
#define FMI_CONFIG__ECC_MODE(m) (((m) & 0x1) << 14)
|
||||
#define FMI_CONFIG__META_PER_ENVELOPE(n) (((n) & 0x3F) << 8)
|
||||
#define FMI_CONFIG__META_PER_PAGE(n) (((n) & 0x3F) << 2)
|
||||
#define FMI_CONFIG__PAGE_SIZE(n) (((n) & 0x03) << 0)
|
||||
|
||||
#else
|
||||
|
||||
#define FMI_CONFIG__ECC_CORRECTABLE_BITS(m) (((m) & 0x1F) << 3)
|
||||
#define FMI_CONFIG__DMA_BURST(n) (((n) & 0x7) << 0)
|
||||
|
||||
#endif
|
||||
|
||||
#define FMI_CONFIG__DMA_BURST__32_CYCLES FMI_CONFIG__DMA_BURST(5)
|
||||
#define FMI_CONFIG__DMA_BURST__16_CYCLES FMI_CONFIG__DMA_BURST(4)
|
||||
#define FMI_CONFIG__DMA_BURST__8_CYCLES FMI_CONFIG__DMA_BURST(3)
|
||||
#define FMI_CONFIG__DMA_BURST__4_CYCLES FMI_CONFIG__DMA_BURST(2)
|
||||
#define FMI_CONFIG__DMA_BURST__2_CYCLES FMI_CONFIG__DMA_BURST(1)
|
||||
#define FMI_CONFIG__DMA_BURST__1_CYCLES FMI_CONFIG__DMA_BURST(0)
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define FMI_CONFIG__LBA_MODE__NORMAL FMI_CONFIG__LBA_MODE(0)
|
||||
#define FMI_CONFIG__LBA_MODE__BYPASS_ECC FMI_CONFIG__LBA_MODE(1)
|
||||
#define FMI_CONFIG__LBA_MODE__LBA_TYPE_AB FMI_CONFIG__LBA_MODE(2)
|
||||
#define FMI_CONFIG__LBA_MODE__LBA_TYPE_C FMI_CONFIG__LBA_MODE(3)
|
||||
|
||||
#define FMI_CONFIG__ECC_MODE__16BIT FMI_CONFIG__ECC_MODE(1)
|
||||
#define FMI_CONFIG__ECC_MODE__8BIT FMI_CONFIG__ECC_MODE(0)
|
||||
|
||||
#define FMI_CONFIG__PAGE_SIZE__2K FMI_CONFIG__PAGE_SIZE(0)
|
||||
#define FMI_CONFIG__PAGE_SIZE__4K FMI_CONFIG__PAGE_SIZE(1)
|
||||
#define FMI_CONFIG__PAGE_SIZE__8K FMI_CONFIG__PAGE_SIZE(2)
|
||||
#define FMI_CONFIG__PAGE_SIZE__512 FMI_CONFIG__PAGE_SIZE(3)
|
||||
|
||||
#else
|
||||
|
||||
#define FMI_CONFIG__ECC_MAX_CORRECTION FMI_CONFIG__ECC_CORRECTABLE_BITS(30)
|
||||
|
||||
#endif
|
||||
|
||||
#if FMI_VERSION > 2
|
||||
#define FMI_CONFIG__ENABLE_WHITENING (0x1UL << 8)
|
||||
#endif
|
||||
|
||||
#if FMI_VERSION > 3
|
||||
#define FMI_CONFIG__SCRAMBLE_SEED (0x1UL << 14)
|
||||
#endif
|
||||
|
||||
// =============================================================================
|
||||
// FMI_CONTROL bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define FMI_CONTROL__MODE(m) (((m) & 0x3) << 1)
|
||||
#define FMI_CONTROL__START_BIT (0x1UL << 0)
|
||||
|
||||
#define FMI_CONTROL__MODE__IDLE FMI_CONTROL__MODE(0)
|
||||
#define FMI_CONTROL__MODE__READ FMI_CONTROL__MODE(1)
|
||||
#define FMI_CONTROL__MODE__WRITE FMI_CONTROL__MODE(2)
|
||||
#define FMI_CONTROL__MODE__UNDEF FMI_CONTROL__MODE(3)
|
||||
|
||||
#else
|
||||
|
||||
#if FMI_VERSION > 3
|
||||
#define FMI_CONTROL__RESET_SEED (0x1UL << 11)
|
||||
#endif
|
||||
|
||||
#define FMI_CONTROL__BUFFER_1_LOCK(m) (((m) & 0x3) << 5)
|
||||
#define FMI_CONTROL__BUFFER_0_LOCK(m) (((m) & 0x3) << 3)
|
||||
#define FMI_CONTROL__MODE(m) (((m) & 0x3) << 1)
|
||||
#define FMI_CONTROL__START_BIT (0x1UL << 0)
|
||||
|
||||
#define FMI_CONTROL__MODE__IDLE FMI_CONTROL__MODE(0)
|
||||
#define FMI_CONTROL__MODE__READ FMI_CONTROL__MODE(1)
|
||||
#define FMI_CONTROL__MODE__WRITE FMI_CONTROL__MODE(2)
|
||||
#define FMI_CONTROL__MODE__SOFTWARE_RESET FMI_CONTROL__MODE(3)
|
||||
|
||||
#define FMI_CONTROL__BUFFER_0_LOCK_FREE FMI_CONTROL__BUFFER_0_LOCK(0)
|
||||
#define FMI_CONTROL__BUFFER_0_LOCK_DMA FMI_CONTROL__BUFFER_0_LOCK(1)
|
||||
#define FMI_CONTROL__BUFFER_0_LOCK_ECC FMI_CONTROL__BUFFER_0_LOCK(2)
|
||||
#define FMI_CONTROL__BUFFER_0_LOCK_FMC FMI_CONTROL__BUFFER_0_LOCK(3)
|
||||
|
||||
#define FMI_CONTROL_BUFFER_1_LOCK_FREE FMI_CONTROL__BUFFER_1_LOCK(0)
|
||||
#define FMI_CONTROL_BUFFER_1_LOCK_DMA FMI_CONTROL__BUFFER_1_LOCK(1)
|
||||
#define FMI_CONTROL_BUFFER_1_LOCK_ECC FMI_CONTROL__BUFFER_1_LOCK(2)
|
||||
#define FMI_CONTROL_BUFFER_1_LOCK_FMC FMI_CONTROL__BUFFER_1_LOCK(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMI_STATUS bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMI_STATUS__FMC_ACTIVE (0x1UL << 3)
|
||||
#define FMI_STATUS__ECC_ACTIVE (0x1UL << 2)
|
||||
#define FMI_STATUS__DMA_ACTIVE (0x1UL << 1)
|
||||
#define FMI_STATUS__BUS_ACTIVE (0x1UL << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMI_INT_PEND bitfields
|
||||
// =============================================================================
|
||||
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define FMI_INT_PEND__ECC_INTERRUPT (0x1UL << 14)
|
||||
#define FMI_INT_PEND__ECC_READY_BUSY (0x1UL << 13)
|
||||
#define FMI_INT_PEND__ECC_DONE (0x1UL << 12)
|
||||
#define FMI_INT_PEND__FMC_INTERRUPT (0x1UL << 11)
|
||||
#define FMI_INT_PEND__FMC_READY_BUSY (0x1UL << 10)
|
||||
|
||||
#else
|
||||
|
||||
#define FMI_INT_PEND__ECC_INTERRUPT (0x1UL << 21)
|
||||
#define FMI_INT_PEND__ECC_READY_BUSY (0x1UL << 20)
|
||||
#define FMI_INT_PEND__ECC_DONE (0x1UL << 19)
|
||||
#define FMI_INT_PEND__FMC_INTERRUPT (0x1UL << 18)
|
||||
#define FMI_INT_PEND__FMC_READY_BUSY(n) (((n) & 0xFF << 10)
|
||||
|
||||
#endif
|
||||
|
||||
#define FMI_INT_PEND__FMC_TIMEOUT (0x1UL << 9)
|
||||
#define FMI_INT_PEND__FMC_NSRBBDONE (0x1UL << 8)
|
||||
#define FMI_INT_PEND__FMC_NSERR (0x1UL << 7)
|
||||
#define FMI_INT_PEND__FMC_TRANSDONE (0x1UL << 6)
|
||||
#define FMI_INT_PEND__FMC_ADDRESSDONE (0x1UL << 5)
|
||||
#define FMI_INT_PEND__FMC_CMDDONE (0x1UL << 4)
|
||||
#define FMI_INT_PEND__META_FIFO_OVERFLOW (0x1UL << 3)
|
||||
#define FMI_INT_PEND__META_FIFO_UNDERFLOW (0x1UL << 2)
|
||||
#define FMI_INT_PEND__LAST_FMC_DONE (0x1UL << 1)
|
||||
#define FMI_INT_PEND__TRANSACTION_COMPLETE (0x1UL << 0)
|
||||
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMI_INT_EN bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMI_INT_EN__ECC_INTERRUPT (0x1UL << 14)
|
||||
#define FMI_INT_EN__ECC_READY_BUSY (0x1UL << 13)
|
||||
#define FMI_INT_EN__ECC_DONE (0x1UL << 12)
|
||||
#define FMI_INT_EN__FMC_INTERRUPT (0x1UL << 11)
|
||||
#define FMI_INT_EN__FMC_READY_BUSY (0x1UL << 10)
|
||||
#define FMI_INT_EN__FMC_TIMEOUT (0x1UL << 9)
|
||||
#define FMI_INT_EN__FMC_NSRBBDONE (0x1UL << 8)
|
||||
#define FMI_INT_EN__FMC_NSERR (0x1UL << 7)
|
||||
#define FMI_INT_EN__FMC_TRANSDONE (0x1UL << 6)
|
||||
#define FMI_INT_EN__FMC_ADDRESSDONE (0x1UL << 5)
|
||||
#define FMI_INT_EN__FMC_CMDDONE (0x1UL << 4)
|
||||
#define FMI_INT_EN__META_FIFO_OVERFLOW (0x1UL << 3)
|
||||
#define FMI_INT_EN__META_FIFO_UNDERFLOW (0x1UL << 2)
|
||||
#define FMI_INT_EN__LAST_FMC_DONE (0x1UL << 1)
|
||||
#define FMI_INT_EN__TRANSACTION_COMPLETE (0x1UL << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMI_DEBUG0 bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define FMI_DEBUG0__DMA_BLOCK_COUNT(n) (((n) & 0x1F) << 24)
|
||||
#define FMI_DEBUG0__DATA_TC_RECEIVED (0x1UL << 23)
|
||||
#define FMI_DEBUG0__DATA_DMA_DONE (0x1UL << 22)
|
||||
#define FMI_DEBUG0__DMA_DATA_RW_PTR(n) (((n) & 0x7F) << 15)
|
||||
|
||||
#else
|
||||
|
||||
#define FMI_DEBUG0__DMA_SECTOR_COUNT(n) (((n) & 0x7F) << 25)
|
||||
#define FMI_DEBUG0__DATA_TC_RECEIVED (0x1UL << 24)
|
||||
#define FMI_DEBUG0__DMA_WORD_COUNT(n) (((n) & 0x1FF << 15)
|
||||
|
||||
#endif
|
||||
|
||||
#define FMI_DEBUG0__META_BYTE_COUNT(n) (((n) & 0x3F) << 9)
|
||||
#define FMI_DEBUG0__FMC_TASKS_PENDING(n) (((n) & 0x3) << 7)
|
||||
#define FMI_DEBUG0__ECC_TASKS_PENDING(n) (((n) & 0x3) << 5)
|
||||
#define FMI_DEBUG0__DMA_TASKS_PENDING(n) (((n) & 0x3) << 3)
|
||||
#define FMI_DEBUG0__FMC_TARGET_BUFFER(b) (((b) & 0x1) << 2)
|
||||
#define FMI_DEBUG0__ECC_TARGET_BUFFER(b) (((b) & 0x1) << 1)
|
||||
#define FMI_DEBUG0__DMA_TARGET_BUFFER(b) (((b) & 0x1) << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMI_DEBUG1 bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define FMI_DEBUG1__META_TC_RECEIVED (0x1UL << 28)
|
||||
#define FMI_DEBUG1__NEXT_META_LOCATION(n) (((n) & 0x3F) << 22)
|
||||
#define FMI_DEBUG1__FMC_PAGE_DONE (0x1UL << 21)
|
||||
#define FMI_DEBUG1__FMC_BLOCK_COUNT(n) (((n) & 0x1F) << 16)
|
||||
|
||||
#else
|
||||
|
||||
#define FMI_DEBUG1__METADATA_TC_RECEIVED (0x1UL << 27)
|
||||
#define FMI_DEBUG1__METADATA_ADDRESS(n) (((n) & 0x7FF) << 16)
|
||||
|
||||
#endif
|
||||
|
||||
#define FMI_DEBUG1__META_FIFO_LEVEL(n) (((n) & 0x3F) << 10)
|
||||
#define FMI_DEBUG1__META_FIFO_WRITE_PTR(n) (((n) & 0x1F) << 5)
|
||||
#define FMI_DEBUG1__META_FIFO_READ_PTR(n) (((n) & 0x1F) << 0)
|
||||
|
||||
// =============================================================================
|
||||
// FMI_DEBUG2 bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define FMI_DEBUG2__BUFFER_1_META_BYTES(n) (((n) & 0x3F) << 24)
|
||||
#define FMI_DEBUG2__BUFFER_0_META_BYTES(n) (((n) & 0x3F) << 18)
|
||||
#define FMI_DEBUG2__META_BYTES_REMAINING(n) (((n) & 0x3F) << 12)
|
||||
#define FMI_DEBUG2__PAUSED_AHB_ADDRESS(n) (((n) & 0xFF) << 4)
|
||||
#define FMI_DEBUG2__AHB_STATE(n) (((n) & 0x3) << 1)
|
||||
#define FMI_DEBUG2__PAUSED_AHB_BUS (0x1UL << 0)
|
||||
|
||||
#else
|
||||
|
||||
#define FMI_DEBUG2__BUFFER_1_META_BYTES(n) (((n) & 0x3F) << 19)
|
||||
#define FMI_DEBUG2__BUFFER_0_META_BYTES(n) (((n) & 0x3F) << 13)
|
||||
#define FMI_DEBUG2__META_BYTES_REMAINING(n) (((n) & 0x3F) << 7)
|
||||
#define FMI_DEBUG2__DATA_STATE(n) (((n) & 0xF) << 3)
|
||||
#define FMI_DEBUG2__AHB_STATE(n) (((n) & 0x7) << 0)
|
||||
|
||||
#endif
|
||||
|
||||
// =============================================================================
|
||||
// FMI_DEBUG3 bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION > 0
|
||||
|
||||
#define FMI_DEBUG3__PAUSED_AHB_ADDRESS(n) (((n) & 0xFF) << 9)
|
||||
#define FMI_DEBUG3__PAUSE_AHB_BUS (0x1UL << 8)
|
||||
#define FMI_DEBUG3__FMC_PAGE_DONE (0x1UL << 7)
|
||||
#define FMI_DEBUG3__FMC_BLOCK_COUNT(n) (((n) & 0x7F) << 0)
|
||||
|
||||
#endif
|
||||
|
||||
// =============================================================================
|
||||
// FMI_DATA_SIZE bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION > 0
|
||||
|
||||
#define FMI_DATA_SIZE__META_BYTES_PER_ENVELOPE(n) (((n) & 0x3F) << 25)
|
||||
#define FMI_DATA_SIZE__META_BYTES_PER_PAGE(n) (((n) & 0x3F) << 19)
|
||||
#define FMI_DATA_SIZE__BYTES_PER_SECTOR(n) (((n) & 0x7FF) << 8)
|
||||
#define FMI_DATA_SIZE__SECTORS_PER_PAGE(n) (((n) & 0xFF) << 0)
|
||||
|
||||
#endif
|
||||
|
||||
// =============================================================================
|
||||
// FMC_ON bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_ON__SWRST (0x1UL << 8)
|
||||
#define FMC_ON__LOCK_ON (0x1UL << 4)
|
||||
#define FMC_ON__CLKGATING_RDY (0x1UL << 1)
|
||||
#define FMC_ON__ENABLE (0x1UL << 0)
|
||||
#define FMC_ON__DISABLE (!FMC_ON__ENABLE)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_IF_CTRL bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_IF_CTRL__WPB (0x1UL << 21)
|
||||
#define FMC_IF_CTRL__RBBEN (0x1UL << 20)
|
||||
#define FMC_IF_CTRL__DCCYCLE(v) (((v) & 0xF) << 16)
|
||||
#define FMC_IF_CTRL__REB_SETUP(v) (((v) & 0xF) << 12)
|
||||
#define FMC_IF_CTRL__REB_HOLD(v) (((v) & 0xF) << 8)
|
||||
#define FMC_IF_CTRL__WEB_SETUP(v) (((v) & 0xF) << 4)
|
||||
#define FMC_IF_CTRL__WEB_HOLD(v) (((v) & 0xF) << 0)
|
||||
|
||||
#define FMC_IF_CTRL__TIMING_MAX_CLOCKS (0xFUL)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_CE_CTRL bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_CE_CTRL__CE_COUNT (8)
|
||||
#define FMC_CE_CTRL__CEB(n) (0x1UL << ((n) & 0x7))
|
||||
|
||||
#define FMC_CE_CTRL__CEB7 FMC_CE_CTRL__CEB(7)
|
||||
#define FMC_CE_CTRL__CEB6 FMC_CE_CTRL__CEB(6)
|
||||
#define FMC_CE_CTRL__CEB5 FMC_CE_CTRL__CEB(5)
|
||||
#define FMC_CE_CTRL__CEB4 FMC_CE_CTRL__CEB(4)
|
||||
#define FMC_CE_CTRL__CEB3 FMC_CE_CTRL__CEB(3)
|
||||
#define FMC_CE_CTRL__CEB2 FMC_CE_CTRL__CEB(2)
|
||||
#define FMC_CE_CTRL__CEB1 FMC_CE_CTRL__CEB(1)
|
||||
#define FMC_CE_CTRL__CEB0 FMC_CE_CTRL__CEB(0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_RW_CTRL bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_RW_CTRL__REBHOLD (0x1UL << 6)
|
||||
#define FMC_RW_CTRL__WR_MODE (0x1UL << 5)
|
||||
#define FMC_RW_CTRL__RD_MODE (0x1UL << 4)
|
||||
#define FMC_RW_CTRL__ADDR_MODE (0x1UL << 3)
|
||||
#define FMC_RW_CTRL__CMD3_MODE (0x1UL << 2)
|
||||
#define FMC_RW_CTRL__CMD2_MODE (0x1UL << 1)
|
||||
#define FMC_RW_CTRL__CMD1_MODE (0x1UL << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_CMD bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_CMD__CMD3(c) (((c) & 0xFF) << 16)
|
||||
#define FMC_CMD__CMD2(c) (((c) & 0xFF) << 8)
|
||||
#define FMC_CMD__CMD1(c) (((c) & 0xFF) << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_ADDR0 bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_ADDR0__SEQ3(a) (((a) & 0xFF) << 24)
|
||||
#define FMC_ADDR0__SEQ2(a) (((a) & 0xFF) << 16)
|
||||
#define FMC_ADDR0__SEQ1(a) (((a) & 0xFF) << 8)
|
||||
#define FMC_ADDR0__SEQ0(a) (((a) & 0xFF) << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_ADDR1 bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_ADDR1__SEQ7(a) (((a) & 0xFF) << 24)
|
||||
#define FMC_ADDR1__SEQ6(a) (((a) & 0xFF) << 16)
|
||||
#define FMC_ADDR1__SEQ5(a) (((a) & 0xFF) << 8)
|
||||
#define FMC_ADDR1__SEQ4(a) (((a) & 0xFF) << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_ADDRNUM bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_ADDRNUM__NUM(n) (((n) & 0x7) << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_DATANUM bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define FMC_DATANUM__NUM(n) (((n) & 0x3F) << 0)
|
||||
|
||||
#else
|
||||
|
||||
#define FMC_DATANUM__NUM(n) (((n) & 0x3FF) << 0)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_TO_CTRL bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_TO_CTRL__EN (0x1UL << 12)
|
||||
#define FMC_TO_CTRL__DIV(d) (((d) & 0xF) << 8)
|
||||
#define FMC_TO_CTRL__VAL(v) (((v) & 0xFF) << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_TO_CNT bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_TO_CNT__CNT(c) (((c) & 0xFF) << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_INTMASK bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_INTMASK__RBBDONE(n) (0x1UL << (((n) & 0x7) + 8))
|
||||
|
||||
#define FMC_INTMASK__RBBDONE7 FMC_INTMASK__RBBDONE(7)
|
||||
#define FMC_INTMASK__RBBDONE6 FMC_INTMASK__RBBDONE(6)
|
||||
#define FMC_INTMASK__RBBDONE5 FMC_INTMASK__RBBDONE(5)
|
||||
#define FMC_INTMASK__RBBDONE4 FMC_INTMASK__RBBDONE(4)
|
||||
#define FMC_INTMASK__RBBDONE3 FMC_INTMASK__RBBDONE(3)
|
||||
#define FMC_INTMASK__RBBDONE2 FMC_INTMASK__RBBDONE(2)
|
||||
#define FMC_INTMASK__RBBDONE1 FMC_INTMASK__RBBDONE(1)
|
||||
#define FMC_INTMASK__RBBDONE0 FMC_INTMASK__RBBDONE(0)
|
||||
#define FMC_INTMASK__TIMEOUT (0x1UL << 7)
|
||||
#define FMC_INTMASK__NSERR (0x1UL << 6)
|
||||
#define FMC_INTMASK__NSRBBDONE (0x1UL << 5)
|
||||
#define FMC_INTMASK__TRANSDONE (0x1UL << 4)
|
||||
#define FMC_INTMASK__ADDRESSDONE (0x1UL << 3)
|
||||
#define FMC_INTMASK__CMD3DONE (0x1UL << 2)
|
||||
#define FMC_INTMASK__CMD2DONE (0x1UL << 1)
|
||||
#define FMC_INTMASK__CMD1DONE (0x1UL << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_STATUS bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_STATUS__RBBDONE(n) (0x1UL << (((n) & 0x7) + 8))
|
||||
|
||||
#define FMC_STATUS__EMERGENCY2 (0x1UL << 21)
|
||||
#define FMC_STATUS__EMERGENCY01 (0x1UL << 20)
|
||||
#define FMC_STATUS__RDATADIRTY (0x1UL << 16)
|
||||
#define FMC_STATUS__RBBDONE7 FMC_STATUS__RBBDONE(7)
|
||||
#define FMC_STATUS__RBBDONE6 FMC_STATUS__RBBDONE(6)
|
||||
#define FMC_STATUS__RBBDONE5 FMC_STATUS__RBBDONE(5)
|
||||
#define FMC_STATUS__RBBDONE4 FMC_STATUS__RBBDONE(4)
|
||||
#define FMC_STATUS__RBBDONE3 FMC_STATUS__RBBDONE(3)
|
||||
#define FMC_STATUS__RBBDONE2 FMC_STATUS__RBBDONE(2)
|
||||
#define FMC_STATUS__RBBDONE1 FMC_STATUS__RBBDONE(1)
|
||||
#define FMC_STATUS__RBBDONE0 FMC_STATUS__RBBDONE(0)
|
||||
#define FMC_STATUS__TIMEOUT (0x1UL << 7)
|
||||
#define FMC_STATUS__NSERR (0x1UL << 6)
|
||||
#define FMC_STATUS__NSRBBDONE (0x1UL << 5)
|
||||
#define FMC_STATUS__TRANSDONE (0x1UL << 4)
|
||||
#define FMC_STATUS__ADDRESSDONE (0x1UL << 3)
|
||||
#define FMC_STATUS__CMD3DONE (0x1UL << 2)
|
||||
#define FMC_STATUS__CMD2DONE (0x1UL << 1)
|
||||
#define FMC_STATUS__CMD1DONE (0x1UL << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_RBB_CONFIG bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_RBB_CONFIG__POL(v) (((v) & 0xFF) << 8)
|
||||
#define FMC_RBB_CONFIG__POS(v) (((v) & 0xFF) << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_ALARMCMD bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_ALARMCMD__READ1(v) (((v) & 0xFF) << 16)
|
||||
#define FMC_ALARMCMD__PROG1(v) (((v) & 0xFF) << 8)
|
||||
#define FMC_ALARMCMD__ERASE1(v) (((v) & 0xFF) << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// FMC_REJECTCMD bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define FMC_REJECTCMD__READ2(v) (((v) & 0xFF) << 16)
|
||||
#define FMC_REJECTCMD__PROG2(v) (((v) & 0xFF) << 8)
|
||||
#define FMC_REJECTCMD__ERASE2(v) (((v) & 0xFF) << 0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// ECC_CON0 bitfields
|
||||
// =============================================================================
|
||||
|
||||
#define ECC_CON0__START_ENC (0x1UL << 1)
|
||||
#define ECC_CON0__START_DEC (0x1UL << 0)
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define ECC_CON0__META_LENGTH(n) (((n) & 0x1F) << 8)
|
||||
#define ECC_CON0__MODE_SEL(m) (((m) & 0x1) << 2)
|
||||
#define ECC_CON0__MODE_SEL__16BIT ECC_CON0__MODE_SEL(1)
|
||||
#define ECC_CON0__MODE_SEL__8BIT ECC_CON0__MODE_SEL(0)
|
||||
|
||||
#else
|
||||
|
||||
#define ECC_CON0__INFORMATION_LENGTH(n) (((n) & 0x7FF) << 16)
|
||||
#define ECC_CON0__MODE_SEL(m) (((m) & 0x1F) << 4)
|
||||
#define ECC_CON0__MAX_CORRECTION ECC_CON0__MODE_SEL(30)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// ECC_CON1 bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION > 0
|
||||
|
||||
#define ECC_CON1__ALLOWED_STUCK_BIT_IN_FP(n) (((n) & 0x1F) << 16)
|
||||
|
||||
#endif
|
||||
|
||||
#if FMI_VERSION > 2
|
||||
#define ECC_CON1__IMPLICIT_WRITE_MARK (1UL << 31)
|
||||
#endif
|
||||
|
||||
#define ECC_CON1__ERROR_ALERT_LEVEL(n) (((n) & 0x1F) << 8)
|
||||
#define ECC_CON1__INT_ENABLE(b) (((b) & 0x1) << 7)
|
||||
|
||||
#define ECC_CON1__INT_ENABLE__ENABLE ECC_CON1__INT_ENABLE(1)
|
||||
#define ECC_CON1__INT_ENABLE__DISABLE ECC_CON1__INT_ENABLE(0)
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// ECC_RESULT bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define ECC_RESULT__ERROR_CNT(n) (((n) & 0x1F) << 16)
|
||||
#define ECC_RESULT__ERROR_FLAG (0x1UL << 0)
|
||||
|
||||
#else
|
||||
|
||||
#define ECC_RESULT_FIFO__ERROR_CNT(n) (((n) & 0x1F) << 16)
|
||||
#define ECC_RESULT_FIFO__STUCK_BIT_EXCEEDED (0x1UL << 14)
|
||||
#define ECC_RESULT_FIFO__STUCK_BIT_CNT(n) (((n) & 0x3F) << 8)
|
||||
#define ECC_RESULT_FIFO__ALL_FF (0x1UL << 3)
|
||||
#define ECC_RESULT_FIFO__ALL_ZERO (0x1UL << 2)
|
||||
#define ECC_RESULT_FIFO__FREE_PAGE (0x1UL << 1)
|
||||
#define ECC_RESULT_FIFO__UNCORRECTABLE (0x1UL << 0)
|
||||
#define ECC_RESULT_FIFO__RESET_FIFO (0x1UL << 0)
|
||||
|
||||
#endif
|
||||
|
||||
// =============================================================================
|
||||
// ECC_PND bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define ECC_PND__BCH_ALL_FF (0x1UL << 6)
|
||||
#define ECC_PND__SECTOR_ERROR_ALERT (0x1UL << 5)
|
||||
#define ECC_PND__READY_BUSY (0x1UL << 4)
|
||||
#define ECC_PND__UNCORRECTABLE (0x1UL << 3)
|
||||
#define ECC_PND__DEC_DONE (0x1UL << 2)
|
||||
#define ECC_PND__ENC_DONE (0x1UL << 1)
|
||||
#define ECC_PND__ENC_DEC_DONE (0x1UL << 0)
|
||||
|
||||
#else
|
||||
|
||||
#define ECC_PND__MAX_STUCK_BIT_CNT(n) (((n) & 0x3F) << 24)
|
||||
#define ECC_PND__MAX_ERROR_CNT(n) (((n) & 0x1F) << 16)
|
||||
#define ECC_PND__SOME_STUCK_BIT_EXCEEDED (0x1UL << 9)
|
||||
#define ECC_PND__SOME_ALL_FF (0x1UL << 8)
|
||||
#define ECC_PND__SOME_ALL_ZERO (0x1UL << 7)
|
||||
#define ECC_PND__ALL_FREE_PAGE (0x1UL << 6)
|
||||
#define ECC_PND__SOME_ERROR_ALERT (0x1UL << 5)
|
||||
#define ECC_PND__READY_BUSY (0x1UL << 4)
|
||||
#define ECC_PND__UNCORRECTABLE (0x1UL << 3)
|
||||
#define ECC_PND__ENC_DONE (0x1UL << 2) // note swap from 8920
|
||||
#define ECC_PND__DEC_DONE (0x1UL << 1) // note swap from 8920
|
||||
#define ECC_PND__ENC_DEC_DONE (0x1UL << 0)
|
||||
|
||||
#endif
|
||||
|
||||
// =============================================================================
|
||||
// ECC_MASK bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define ECC_MASK__SECTOR_ERR_ALERT_MASK (0x1UL << 5)
|
||||
#define ECC_MASK__UNCORRECTABLE_MASK (0x1UL << 3)
|
||||
#define ECC_MASK__DEC_DONE_MASK (0x1UL << 2)
|
||||
#define ECC_MASK__ENC_DONE_MASK (0x1UL << 1)
|
||||
#define ECC_MASK__ENC_DEC_DONE_MASK (0x1UL << 0)
|
||||
|
||||
#else
|
||||
|
||||
#define ECC_MASK__SOME_STUCK_BIT_EXCEEDED (0x1UL << 9)
|
||||
#define ECC_MASK__SOME_ALL_FF_MASK (0x1UL << 8)
|
||||
#define ECC_MASK__SOME_ALL_ZERO_MASK (0x1UL << 7)
|
||||
#define ECC_MASK__SOME_ERROR_ALERT_MASK (0x1UL << 5)
|
||||
#define ECC_MASK__ANY_UNCORRECTABLE_MASK (0x1UL << 3)
|
||||
#define ECC_MASK__ENC_DONE_MASK (0x1UL << 2) // note swap from 8920
|
||||
#define ECC_MASK__DEC_DONE_MASK (0x1UL << 1) // note swap from 8920
|
||||
#define ECC_MASK__ENC_DEC_DONE_MASK (0x1UL << 0)
|
||||
|
||||
#endif
|
||||
|
||||
// =============================================================================
|
||||
// ECC_HISTORY bitfields
|
||||
// =============================================================================
|
||||
|
||||
#if FMI_VERSION == 0
|
||||
|
||||
#define ECC_HISTORY__ERROR_COUNT_CLEAR (0x1UL << 24)
|
||||
#define ECC_HISTORY__ERROR_COUNT(n) (((n) & 0x1FFF) << 11)
|
||||
#define ECC_HISTORY__DECODING_NUMBER_CLEAR (0x1UL << 10)
|
||||
#define ECC_HISTORY__DECODING_NUMBER(n) (((n) & 0x3FF) << 0)
|
||||
|
||||
#else
|
||||
|
||||
#define ECC_HISTORY__ERROR_COUNT_CLEAR (0x1UL << 26)
|
||||
#define ECC_HISTORY__ERROR_COUNT(n) (((n) & 0x7FFF) << 11)
|
||||
#define ECC_HISTORY__DECODING_NUMBER_CLEAR (0x1UL << 10)
|
||||
#define ECC_HISTORY__DECODING_NUMBER(n) (((n) & 0x3FF) << 0)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif // _H2FMI_REGS_H_
|
||||
|
||||
// ********************************** EOF **************************************
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2008 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += WITH_HW_BOOTROM_NAND=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/H2fmi_bootrom.o
|
||||
Reference in new issue
Block a user