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@@ -0,0 +1,604 @@
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/*
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* Copyright (C) 2007 Apple Inc. All rights reserved.
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* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <lib/libc.h>
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#include <platform.h>
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#include <platform/int.h>
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#include <platform/clocks.h>
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#include <platform/soc/hwclocks.h>
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#include <sys.h>
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#include "aes.h"
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/* aes driver, copy and customize */
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#define AES_MAX_BOUNCE_BUFFER 64
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static volatile u_int32_t gAesIrqDoneFlag = 0;
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static u_int8_t g_bounce_buffer[AES_MAX_BOUNCE_BUFFER] __attribute__ ((aligned (32)));
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static int aes_inited = 0;
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static int key_size_to_bytes(enum aes_key_size size)
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{
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return 16 + (size * 8);
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}
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void aes_init(void)
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{
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dprintf(DEBUG_SPEW,"aes_init()\n");
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clock_gate(CLK_AES, true);
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AES_MODULE_POWER_ON();
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AesInit();
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aes_inited = 1;
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}
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/*! \fn void AesInit(void)
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* \brief power on and initialize AES module
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* \param none
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* \return none
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*/
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u_int32_t AesInit(void)
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{
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gAesIrqDoneFlag = 0;
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/* install_int_handler(INT_AES, Isr_AesHandler, 0); */
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/* unmask_int(INT_AES); */
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rAES_IRQ_MASK = 0x00000000; /** Mask all interrupt source */
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return 0;
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}
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/*! \fn void AesUninit(void)
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* \brief release AES module
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* \param none
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* \return none
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*/
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u_int32_t AesUninit(void)
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{
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gAesIrqDoneFlag = 0;
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AES_MODULE_POWER_OFF();
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//rAES_IRQ_MASK = 0x00000000; /** Mask all interrupt source */
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/* mask_int(INT_AES); */
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// SysResetInterrupt(INT_AES);
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return 0;
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}
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/*! \fn void AesOff(void)
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* \brief Power Off AES module
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* \param none
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* \return
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*/
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void AesOff(void)
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{
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AES_MODULE_POWER_OFF(); /** AES module is disabled and preparation for clock down */
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//while(!(rAES_POWER & 0x02)); /** ready for clock down */
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}
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/*! \fn void _AesSetKeyType(u_int32_t cipherKeyType)
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* \brief power off AES module
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* \param cipherKeyType cipher key type
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* \return none
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*/
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void _AesSetKeyType(enum aes_key_type cipherKeyType)
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{
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rAES_CIPHERKEY_SEL = cipherKeyType;
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#if AES_VERSION > 0
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rAES_COMPLIMENT = ~rAES_CIPHERKEY_SEL;
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#endif
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}
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/*! \fn void _AesSetKey(u_int8_t *pKeyArr)
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* \brief set cipher keys into AES module
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* \param[in] pKeyArr 128-bit Key
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* \return none
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*/
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void _AesSetKey(u_int8_t *pKeyArr)
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{
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/*<<< joe.kang@H1 061212: EVT 2 new code 061212*/
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u_int32_t index;
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u_int32_t uLength;
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volatile u_int32_t * reg;
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if(rAES_CIPHERKEY_SEL == 0) /* 0 is a user defined key */
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{
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switch ((rAES_CFG & 0x30)>>4)
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{
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case 1: // 192 bit
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reg = &rAES_KEY_MM;
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uLength = 6;
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break;
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case 2: // 256 bit
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reg = &rAES_KEY_MX;
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uLength = 8;
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break;
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case 0: // 128 bit
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default:
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reg = &rAES_KEY_X;
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uLength = 4;
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break;
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}
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for(index = 0 ;index < uLength ;index ++)
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{
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#if AES_VERSION > 0
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*(reg + index) = *(u_int32_t *)(pKeyArr + index * 4);
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#else
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*(reg + index) = swap32(*(u_int32_t *)(pKeyArr + index * 4));
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#endif
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}
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}
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}
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/*! \fn void _AesClearKey(void)
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* \brief clear cipher keys into AES module
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* \param[in] void
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* \return none
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*/
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void _AesClearKey(void)
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{
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/*<<< joe.kang@H1 061212: EVT 2 new code 061212*/
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memset ((void *) &rAES_KEY_MX, 0, 32);
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}
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/*! \fn void _AesClearIV(void)
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* \brief clear cipher keys into AES module
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* \param[in] void
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* \return none
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*/
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void _AesClearIV(void)
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{
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/*<<< joe.kang@H1 061212: EVT 2 new code 061212*/
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memset ((void *) &rAES_IV_1, 0, 16);
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}
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/*! \fn void AesSoftwareReset(void)
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* \brief apply software reset to AES module
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* \param none
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* \return none
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*/
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void AesSoftwareReset(void)
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{
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rAES_SWRST = 0x00000001; /** Software Reset for AES */
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rAES_SWRST = 0x00000000; /** No Reset */
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}
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/*! \fn INT32T AesReadyToStart(void);
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* @brief This function set configurations for ready to start AES Engine.
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*
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* @param NONE
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* @return 0 if success. others if failed.
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* @see AesNotifyComplete
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*/
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u_int32_t AesReadyToStart(void)
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{
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/* Set ready to start */
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gAesIrqDoneFlag = 0;
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return 0;
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}
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void AesSetVector(u_int8_t * pLocalIv)
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{
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int index;
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volatile u_int32_t * reg;
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if (pLocalIv == 0)
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{
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rAES_IV_1 = 0;
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rAES_IV_2 = 0;
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rAES_IV_3 = 0;
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rAES_IV_4 = 0;
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}
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else
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{
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/*<<< joe.kang@H1 061212: EVT 2 new code 061212*/
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reg = &rAES_IV_1;
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for(index = 0 ;index < 4 ;index ++)
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{
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#if AES_VERSION > 0
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*(reg + index) = *(u_int32_t *)(pLocalIv + index * 4);
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#else
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*(reg + index) = swap32(*(u_int32_t *)(pLocalIv + index * 4));
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#endif
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}
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}
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return;
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}
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/*! \fn void AesStartEncryption(u_int8_t *destAddr, u_int8_t *srcAddr, u_int32_t size, u_int32_t keyType, u_int32_t *keyArr)
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* \brief encrypt data
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* \param destAddr destination address
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* \param srcAddr source address
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* \param size number of bytes
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* \param[in] keyArr cipher key array
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* \return none
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*/
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void AesStartEncryption(
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u_int8_t *destAddr,
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u_int8_t *srcAddr,
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u_int8_t *cryptoAddr,
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u_int32_t size,
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u_int32_t keyType,
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u_int8_t *keyArr,
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u_int32_t keySize,
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bool bChainingMode,
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u_int32_t srcSize,
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u_int32_t dstSize,
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u_int32_t cryptoSize,
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u_int8_t *pIv)
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{
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/* Ready to start */
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AesReadyToStart();
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AesSoftwareReset();
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AES_MODULE_POWER_ON();
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// rAES_IRQ_MASK = 0x0000000F; /** Unmask all interrupt source */
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_AesSetKeyType(keyType);
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_AesSetKey(keyArr);
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//if(bChainingMode == true)
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//AesSetVector();
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/** aes key size : 128bit, stay in pause state & wait for CPU's action, Encryption */
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rAES_CFG = (0x3<<1);
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AesSetCryption(true);
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AesSetKeySize(keySize);
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AesSetChainingMode(bChainingMode);
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AesSetVector(pIv);
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rAES_XFR_NUM = size; /** Total Transfer Number (number of bytes) */
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rAES_TBUF_START = (u_int32_t)destAddr; /** Start Address of Target Buffer (byte aligned) */
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rAES_TBUF_SIZE = dstSize; /** Size of Taget Buffer (byte aligned) */
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rAES_SBUF_START = (u_int32_t)srcAddr; /** Start Address of Source Buffer (byte aligned) */
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rAES_SBUF_SIZE = srcSize; /** Size of Source Buffer (byte aligned) */
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rAES_CRYPT_START = (u_int32_t)cryptoAddr; /** Starting Address of Encryption in Source Buffer (byte aligned) */
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rAES_CRYPT_SIZE = cryptoSize; /** Size of Encryption (16 byte aligned) */
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gAesIrqDoneFlag = 0;
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_AesStart();
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}
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/*! \fn void AesStartDecryption(u_int8_t *destAddr, u_int8_t *srcAddr, u_int32_t size, u_int32_t keyType, u_int32_t *keyArr)
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* \brief decrypt data
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* \param destAddr destination address
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* \param srcAddr source address
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* \param size number of bytes
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* \param[in] keyArr cipher key array
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* \return none
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*/
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void AesStartDecryption(
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u_int8_t *destAddr,
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u_int8_t *srcAddr,
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u_int8_t *cryptoAddr,
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u_int32_t size,
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u_int32_t keyType,
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u_int8_t *keyArr,
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u_int32_t keySize,
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bool bChainingMode,
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u_int32_t srcSize,
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u_int32_t dstSize,
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u_int32_t cryptoSize,
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u_int8_t *pIv)
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{
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/* Ready to start */
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AesReadyToStart();
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AesSoftwareReset();
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AES_MODULE_POWER_ON();
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_AesSetKeyType(keyType);
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// rAES_IRQ_MASK = 0x0000000F; /** Unmask all interrupt source */
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_AesSetKey(keyArr);
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//if(bChainingMode == true)
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//AesSetVector();
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/** aes key size : 128bit, stay in pause state & wait for CPU's action, Decryption */
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rAES_CFG = (0x3<<1);
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AesSetCryption(false);
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AesSetKeySize(keySize);
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AesSetChainingMode(bChainingMode);
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AesSetVector(pIv);
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rAES_XFR_NUM = size;
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rAES_TBUF_START = (u_int32_t)destAddr; /** Start Address of Target Buffer (number of bytes) */
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rAES_TBUF_SIZE = dstSize; /** Size of Target Buffer (byte aligned) */
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rAES_SBUF_START = (u_int32_t)srcAddr; /** Start Address of Source Buffer (byte aligned) */
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rAES_SBUF_SIZE = srcSize; /** Unmask all interrupt source */
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rAES_CRYPT_START = (u_int32_t)cryptoAddr; /** Starting Address of Decryption in Source Buffer (byte aligned) */
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rAES_CRYPT_SIZE = cryptoSize; /** Size of Decryotion (16 byte aligned) */
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gAesIrqDoneFlag = 0;
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_AesStart();
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}
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/*! \fn void _AesStart(void)
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* \brief start aes
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* \param none
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* \return none
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*/
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void _AesStart(void)
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{
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#if AES_SYNCH_START
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rAES_ENDIAN = (1 << 1); // Set Synch-Start bit
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#else
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rAES_COMMAND = CMD_AES_START; // Set Asynch-Start bit
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#endif
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}
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/*! \fn u_int32_t AesGetIrqStatus(void)
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* \brief Get IRQ status return
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* \param none
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* \return none
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*/
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u_int32_t
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AesGetIrqStatus(void)
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{
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return rAES_IRQ;
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}
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/*! \fn void AesGetIrqStatus(u_int32_t status)
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* \brief Set IRQ status return
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* \param IRQ status
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* \return none
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*/
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void AesSetIrqStatus(u_int32_t status)
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{
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rAES_IRQ = status;
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}
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/*! \fn INT32T AesNotifyComplete(void);
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* @remark This function must be implemented by apple. SAMSUNG just offer
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* a reference code.
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*
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* @brief Nofity AES operation complete.
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* @param NONE
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* @return @c 0 if success. @c -1 if failed.
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* @see AesWaitForComplete, AesReadyToStart
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*/
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u_int32_t AesNotifyComplete(void)
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{
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gAesIrqDoneFlag = 1;
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return 0;
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}
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/*! \fn INT32T AesWaitForComplete(void);
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* \remark This function must be implemented by apple. SAMSUNG just offer
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* a reference code.
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* \brief Wait until AES operation complete.
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* \param NONE
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* \return @c 0 if success. @c -1 if failed.
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* \see AesNotifyComplete
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*/
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u_int32_t
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AesWaitForComplete(void)
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{
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/* polling until AES I/O complete */
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//while(gAesIrqDoneFlag == 0);
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while( 0 == (rAES_IRQ & 0xf) ) ;
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#if AES_SYNCH_START
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/* synch zeroes XFR_NUM - must wait to avoid racing */
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while( 0 != rAES_XFR_NUM ) ;
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#endif
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/*<<< joe.kang@H1 061212: EVT 2 new code 061212*/
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_AesClearKey();
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_AesClearIV();
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// clear all pending IRQs
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rAES_IRQ = 0xf;
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return 0;
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}
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/*! \fn void Isr_AesHandler(void)
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* \brief interrupt service routine
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* \param none
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* \return none
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*/
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void Isr_AesHandler(void *arg)
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{
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u_int32_t status;
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status = rAES_IRQ;
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dprintf(DEBUG_SPEW,"aes_int: status 0x%x\n", status);
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#if 0
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/* check the status */
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if(status & AES_IRQ_XFR_DONE_BIT)
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{
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gAesIrqDoneFlag = 1;
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}
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if(status & AES_IRQ_TBUF_FULL_BIT)
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{
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g_pRomGlobals->gAesIrqDoneFlag = 1;
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}
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if(status & AES_IRQ_SBUF_EMPTY_BIT)
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{
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;
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}
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if(status & AES_IRQ_ILLEGAL_OP_BIT)
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{
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;
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}
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#endif
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/* clear status register */
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rAES_IRQ = status;
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/* Notify to the module pended */
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if (AesNotifyComplete() != 0)
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{
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panic("AesNotifyComplete() return !0");
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}
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}
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/*! \fn void AesSetKeySize(void)
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* \brief set key size
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* \param none
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* \return none
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*/
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void AesSetKeySize(enum aes_key_size keysize)
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{
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||||
u_int32_t rdata;
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u_int32_t wmask;
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u_int32_t wdata;
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wmask = (3<<4);
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rdata = rAES_CFG & (~wmask);
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wdata = rdata | (keysize<<4);
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rAES_CFG = wdata;
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}
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/*! \fn void AesSetChainingMode(void)
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* \brief select chaining Mode
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||||
* \param none
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||||
* \return none
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||||
*/
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||||
void AesSetChainingMode(bool bFlag)
|
||||
{
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||||
u_int32_t rdata;
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||||
u_int32_t wmask;
|
||||
u_int32_t wdata;
|
||||
|
||||
wmask = (1<<3);
|
||||
rdata = rAES_CFG & (~wmask);
|
||||
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||||
wdata = rdata | (bFlag<<3);
|
||||
rAES_CFG = wdata;
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||||
}
|
||||
/*! \fn void AesSetCryption(void)
|
||||
* \brief select cryption mode
|
||||
* \param none
|
||||
* \return none
|
||||
*/
|
||||
void AesSetCryption(bool bFlag)
|
||||
{
|
||||
/**
|
||||
* bFlag 0: decryption / 1: encryption
|
||||
*/
|
||||
u_int32_t rdata;
|
||||
u_int32_t wmask;
|
||||
u_int32_t wdata;
|
||||
|
||||
wmask = (1<<0);
|
||||
rdata = rAES_CFG & (~wmask);
|
||||
|
||||
wdata = rdata | (bFlag<<0);
|
||||
rAES_CFG = wdata;
|
||||
}
|
||||
|
||||
bool
|
||||
AesGetCryption(void)
|
||||
{
|
||||
bool result;
|
||||
|
||||
result = (bool)(rAES_CFG & 0x01);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/*!
|
||||
*/
|
||||
void
|
||||
AesSetCommand(u_int32_t cmd)
|
||||
{
|
||||
rAES_COMMAND = cmd;
|
||||
}
|
||||
|
||||
/*!
|
||||
*/
|
||||
void
|
||||
AesSetSourceConfig(u_int32_t addr, u_int32_t size)
|
||||
{
|
||||
rAES_SBUF_START = addr;
|
||||
|
||||
if(size != 0xffffffff)
|
||||
{
|
||||
rAES_SBUF_SIZE = size;
|
||||
}
|
||||
}
|
||||
/*!
|
||||
*/
|
||||
void
|
||||
AesSetCryptConfig(u_int32_t addr, u_int32_t size)
|
||||
{
|
||||
rAES_CRYPT_START = addr;
|
||||
|
||||
if(size != 0xffffffff)
|
||||
{
|
||||
rAES_CRYPT_SIZE = size;
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
AES_CBC_DecryptInPlace(u_int8_t * pAddr, u_int32_t u32Len, u_int32_t keyType, u_int8_t * pKey, u_int8_t * pIv)
|
||||
{
|
||||
u_int8_t *addr = pAddr;
|
||||
|
||||
aes_init();
|
||||
|
||||
if ( AES_MAX_BOUNCE_BUFFER >= u32Len ) {
|
||||
memcpy( g_bounce_buffer, pAddr, u32Len );
|
||||
addr = g_bounce_buffer;
|
||||
}
|
||||
|
||||
platform_cache_operation(CACHE_CLEAN | CACHE_INVALIDATE, 0, 0);
|
||||
AesStartDecryption((u_int8_t *)addr, (u_int8_t *)addr, (u_int8_t *)addr, u32Len, keyType, pKey, 0, 1, u32Len, u32Len, u32Len, pIv);
|
||||
AesWaitForComplete();
|
||||
|
||||
if ( AES_MAX_BOUNCE_BUFFER >= u32Len ) {
|
||||
memcpy( pAddr, addr, u32Len );
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
bool
|
||||
AES_CBC_EncryptInPlace(u_int8_t * pAddr, u_int32_t u32Len, u_int32_t keyType, u_int8_t * pKey, u_int8_t * pIv)
|
||||
{
|
||||
u_int8_t *addr = pAddr;
|
||||
|
||||
aes_init();
|
||||
|
||||
if ( AES_MAX_BOUNCE_BUFFER >= u32Len ) {
|
||||
memcpy( g_bounce_buffer, pAddr, u32Len );
|
||||
addr = g_bounce_buffer;
|
||||
}
|
||||
|
||||
platform_cache_operation(CACHE_CLEAN | CACHE_INVALIDATE, 0, 0);
|
||||
AesStartEncryption((u_int8_t *)addr, (u_int8_t *)addr, (u_int8_t *)addr, u32Len, keyType, pKey, 0, 1, u32Len, u32Len, u32Len, pIv);
|
||||
AesWaitForComplete();
|
||||
|
||||
if ( AES_MAX_BOUNCE_BUFFER >= u32Len ) {
|
||||
memcpy( pAddr, addr, u32Len );
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Computer, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _SAMSUNG_AES_H
|
||||
#define _SAMSUNG_AES_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <sys/types.h>
|
||||
#include <drivers/aes.h>
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
#define rAES_POWER (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x00))
|
||||
#define rAES_COMMAND (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x04))
|
||||
#define rAES_SWRST (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x08))
|
||||
#define rAES_IRQ (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x0C))
|
||||
#define rAES_IRQ_MASK (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x10))
|
||||
#define rAES_CFG (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x14))
|
||||
#define rAES_XFR_NUM (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x18))
|
||||
#define rAES_XFR_CNT (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x1C))
|
||||
#define rAES_TBUF_START (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x20))
|
||||
#define rAES_TBUF_SIZE (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x24))
|
||||
#define rAES_SBUF_START (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x28))
|
||||
#define rAES_SBUF_SIZE (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x2C))
|
||||
#define rAES_CRYPT_START (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x30))
|
||||
#define rAES_CRYPT_SIZE (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x34))
|
||||
#define rAES_CADDR_TBUF (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x38))
|
||||
#define rAES_CADDR_SBUF (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x3C))
|
||||
#define rAES_XFR_STATUS (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x40))
|
||||
#define rBUS_FIFO_STATUS (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x44))
|
||||
#define rAES_FIFO_STATUS (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x48))
|
||||
#define rAES_KEY_MX (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x4C))
|
||||
#define rAES_KEY_MH (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x50))
|
||||
#define rAES_KEY_MM (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x54))
|
||||
#define rAES_KEY_ML (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x58))
|
||||
#define rAES_KEY_X (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x5C))
|
||||
#define rAES_KEY_H (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x60))
|
||||
#define rAES_KEY_M (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x64))
|
||||
#define rAES_KEY_L (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x68))
|
||||
#define rAES_CIPHERKEY_SEL (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x6C))
|
||||
#define rAES_ENDIAN (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x70))
|
||||
#define rAES_IV_1 (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x74))
|
||||
#define rAES_IV_2 (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x78))
|
||||
#define rAES_IV_3 (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x7C))
|
||||
#define rAES_IV_4 (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x80))
|
||||
#define rAES_COMPLIMENT (*(volatile u_int32_t *)(AES_BASE_ADDR + 0x88))
|
||||
|
||||
#define CMD_AES_STOP 0 //Command Stop (Pause)
|
||||
#define CMD_AES_START 1 //Command Start (only available in idle state)
|
||||
#define CMD_AES_ABORT 2 //Command Abort
|
||||
#define CMD_AES_CONTINUE 3 //Command Continue (only available in pause state)
|
||||
|
||||
#define AES_KEY_TYPE_USER_DEFINE 0
|
||||
#define AES_KEY_TYPE_GLOBAL_ID 1
|
||||
#define AES_KEY_TYPE_USER_ID 2
|
||||
|
||||
#define AES_IRQ_XFR_DONE_BIT (1<<0)
|
||||
#define AES_IRQ_TBUF_FULL_BIT (1<<1)
|
||||
#define AES_IRQ_SBUF_EMPTY_BIT (1<<2)
|
||||
#define AES_IRQ_ILLEGAL_OP_BIT (1<<3)
|
||||
|
||||
#define AES_MODULE_POWER_ON() rAES_POWER = 0x00000001
|
||||
#define AES_MODULE_POWER_OFF() rAES_POWER = 0x00000000
|
||||
|
||||
/**
|
||||
* AES KEY SIZE
|
||||
*/
|
||||
enum aes_key_size {
|
||||
_AES_KEY_SIZE_128 = 0,
|
||||
_AES_KEY_SIZE_192,
|
||||
_AES_KEY_SIZE_256,
|
||||
|
||||
_AES_KEY_SIZE_MAX
|
||||
};
|
||||
|
||||
|
||||
#define AES_MODE_ECB 0 /*Electronic Codebook*/
|
||||
#define AES_MODE_CBC 1 /*Cipher Block Chaining*/
|
||||
|
||||
u_int32_t AesInit(void);
|
||||
u_int32_t AesUninit(void);
|
||||
u_int32_t AesWaitForComplete(void);
|
||||
|
||||
void AesSetKeySize(enum aes_key_size keysize);
|
||||
void AesSetChainingMode(bool bFlag);
|
||||
void AesSetCryption(bool bFlag);
|
||||
|
||||
void _AesStart(void);
|
||||
|
||||
__END_DECLS
|
||||
|
||||
#endif /* ! _SAMSUNG_AES_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_OLD_AES=1
|
||||
|
||||
MODULES += \
|
||||
drivers/aes
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/aes.o
|
||||
@@ -0,0 +1,101 @@
|
||||
/*
|
||||
* Test/debug code to mess with the arm7
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/menu.h>
|
||||
#include <lib/env.h>
|
||||
#include <lib/heap.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/memmap.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/soc/arm7m.h>
|
||||
#include <target/gpiodef.h>
|
||||
|
||||
#if WITH_MENU
|
||||
#if DEBUG_BUILD
|
||||
|
||||
#define ARM7M_ALIGN (1 << 12)
|
||||
#define ARM7M_ALIGN_MASK (ARM7M_ALIGN - 1)
|
||||
|
||||
int do_arm7_go(int argc, struct cmd_arg *args)
|
||||
{
|
||||
addr_t addr;
|
||||
|
||||
addr = env_get_uint("loadaddr", DEFAULT_LOAD_ADDRESS);
|
||||
|
||||
if (addr & ARM7M_ALIGN_MASK) {
|
||||
dprintf(DEBUG_CRITICAL, "load address not on a page boundary, cannot remap\n");
|
||||
return(-1);
|
||||
}
|
||||
dprintf(DEBUG_INFO, "configuring ARM7M for image @ 0x%08x\n", addr);
|
||||
|
||||
/* clock on */
|
||||
clock_gate(CLK_ISP, true);
|
||||
clock_gate(CLK_MSVDX, true);
|
||||
clock_gate(CLK_ARM7, true);
|
||||
clock_reset_device(CLK_ARM7);
|
||||
|
||||
/* turn the arm7m off and reset it */
|
||||
rARM7M_CTRL = 0;
|
||||
rARM7M_CTRL = ARM7M_CTRL_RESET;
|
||||
|
||||
/* set up translation */
|
||||
rARM7M_AT_BASE = addr;
|
||||
rARM7M_AT_RANGE = 0x03ff0000; /* give the ARM7 1MiB of DDR */
|
||||
|
||||
/* start */
|
||||
rARM7M_CTRL = ARM7M_CTRL_ENABLE;
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
MENU_COMMAND_DEBUG(arm7_go, do_arm7_go, "start ARM7M with a downloaded image", NULL);
|
||||
|
||||
int do_arm7_stop(int argc, struct cmd_arg *args)
|
||||
{
|
||||
|
||||
/* turn the arm7m off and reset it */
|
||||
rARM7M_CTRL = 0;
|
||||
rARM7M_CTRL = ARM7M_CTRL_RESET;
|
||||
|
||||
/* clock off */
|
||||
clock_gate(CLK_ARM7, false);
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
MENU_COMMAND_DEBUG(arm7_stop, do_arm7_stop, "stop the arm7", NULL);
|
||||
|
||||
#ifdef GPIO_ARM7_DEBUG
|
||||
|
||||
int do_arm7_jtag_select(int argc, struct cmd_arg *args)
|
||||
{
|
||||
#if (GPIO_ARM7_DEBUG_ARM7 >= 0)
|
||||
gpio_configure_out(GPIO_ARM7_DEBUG, GPIO_ARM7_DEBUG_ARM7);
|
||||
#else
|
||||
gpio_configure_in(GPIO_ARM7_DEBUG);
|
||||
#endif
|
||||
return(0);
|
||||
}
|
||||
|
||||
MENU_COMMAND_DEVELOPMENT(arm7_jtag, do_arm7_jtag_select, "switch JTAG from Cortex to ARM7M", NULL);
|
||||
|
||||
int do_cortex_jtag_select(int argc, struct cmd_arg *args)
|
||||
{
|
||||
#if (GPIO_ARM7_DEBUG_CORTEX >= 0)
|
||||
gpio_configure_out(GPIO_ARM7_DEBUG, GPIO_ARM7_DEBUG_CORTEX);
|
||||
#else
|
||||
gpio_configure_in(GPIO_ARM7_DEBUG);
|
||||
#endif
|
||||
return(0);
|
||||
}
|
||||
|
||||
MENU_COMMAND_DEVELOPMENT(cortex_jtag, do_cortex_jtag_select, "switch JTAG from ARM7M to Cortex", NULL);
|
||||
|
||||
#endif /* GPIO_ARM7_DEBUG */
|
||||
|
||||
#endif /* DEBUG_BUILD */
|
||||
#endif /* WITH_MENU */
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
ALL_OBJS += ${LOCAL_DIR}/arm7.o
|
||||
|
||||
OPTIONS += WITH_ARM7_DEBUG=1
|
||||
@@ -0,0 +1,173 @@
|
||||
/*
|
||||
* Copyright (C) 2007-2009 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/arm7m/arm7m.h>
|
||||
#include <platform.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/int.h>
|
||||
#include <platform/soc/arm7m.h>
|
||||
#include <platform/soc/hwisr.h>
|
||||
#include <sys.h>
|
||||
#include <sys/boot.h>
|
||||
#include <sys/callout.h>
|
||||
#include <sys/task.h>
|
||||
|
||||
/*
|
||||
* Early init is done every time the ARM7 starts.
|
||||
*/
|
||||
int
|
||||
arm7m_init(void)
|
||||
{
|
||||
|
||||
/*
|
||||
* Cache starts off. Invalidate and then turn it on.
|
||||
*/
|
||||
rARM7M_CACHE_INV = 1;
|
||||
rARM7M_CACHE_ON = ARM7M_CACHE_ON_ENABLE;
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Halt waiting for an interrupt.
|
||||
*/
|
||||
void
|
||||
arm7m_halt(void)
|
||||
{
|
||||
/* XXX need to avoid doing this until cache operations are complete */
|
||||
rARM7M_SLEEP = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Cache control
|
||||
*/
|
||||
void
|
||||
arm7m_cache_operation(int operation, void *address, u_int32_t length)
|
||||
{
|
||||
uint32_t actual_base, lines;
|
||||
|
||||
if (length == 0) {
|
||||
/*
|
||||
* To perform whole-cache operations, we have to turn the cache off.
|
||||
*
|
||||
* Since this introduces both a coherency risk and also since our use
|
||||
* of the hardware needs to be exclusive, we disable interrupts.
|
||||
*/
|
||||
enter_critical_section();
|
||||
rARM7M_CACHE_ON = 0;
|
||||
|
||||
if (operation & CACHE_CLEAN)
|
||||
rARM7M_CACHE_SYNC = 0;
|
||||
if (operation & CACHE_INVALIDATE)
|
||||
rARM7M_CACHE_INV = 0;
|
||||
|
||||
/* on the panic path, leave the cache off */
|
||||
if (!(operation & CACHE_PANIC))
|
||||
rARM7M_CACHE_ON = ARM7M_CACHE_ON_ENABLE;
|
||||
|
||||
exit_critical_section();
|
||||
} else {
|
||||
actual_base = (uint32_t)address;
|
||||
ASSERT((actual_base & ARM7M_CACHE_LINE_MASK) == actual_base);
|
||||
ASSERT((length % ARM7M_CACHE_LINE_SIZE) == 0);
|
||||
|
||||
lines = length >> ARM7M_CACHE_LINE_SHIFT;
|
||||
ASSERT(lines > 0);
|
||||
|
||||
/*
|
||||
* Disable interrupts to prevent re-entrance from an interrupt
|
||||
* handler.
|
||||
*/
|
||||
enter_critical_section();
|
||||
for (;;) {
|
||||
rARM7M_CLINE_ADDR = actual_base;
|
||||
if (operation & CACHE_CLEAN)
|
||||
rARM7M_CLINE_SYNC = 0;
|
||||
if (operation & CACHE_INVALIDATE)
|
||||
rARM7M_CLINE_INV = 0;
|
||||
if (--lines < 1)
|
||||
break;
|
||||
actual_base += ARM7M_CACHE_LINE_SIZE;
|
||||
}
|
||||
exit_critical_section();
|
||||
}
|
||||
}
|
||||
|
||||
#if SUPPORT_SLEEP
|
||||
static struct task *sleeping_task;
|
||||
extern u_int32_t arch_sleep_magic;
|
||||
|
||||
void
|
||||
platform_sleep(void)
|
||||
{
|
||||
/*
|
||||
* Disable interrupts; this is matched by the
|
||||
* exit_critical_section call in interrupt_init on the wake
|
||||
* path.
|
||||
*/
|
||||
enter_critical_section();
|
||||
|
||||
/* we are the sleeping task */
|
||||
sleeping_task = task_get_current_task();
|
||||
|
||||
/* fool the upcoming test on the sleep path */
|
||||
arch_sleep_magic = SLEEP_MAGIC_NOT_ASLEEP;
|
||||
|
||||
/* save our current context - on wake we will return from this call */
|
||||
arch_task_context_switch(&sleeping_task->arch, &sleeping_task->arch);
|
||||
|
||||
/* if we are on the wake path, go back */
|
||||
if (SLEEP_MAGIC_WAKEY_WAKEY == arch_sleep_magic)
|
||||
return;
|
||||
|
||||
/* flip the switch and wait for us to go to sleep */
|
||||
arch_sleep_magic = SLEEP_MAGIC_WAKEY_WAKEY;
|
||||
|
||||
/* disable and flush the cache, since we're about to be turned off */
|
||||
rARM7M_CACHE_ON = 0;
|
||||
rARM7M_CACHE_SYNC = 0;
|
||||
|
||||
/* XXX really need to know how long the cache operation will take to complete */
|
||||
for (;;) {
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
platform_wakeup(void)
|
||||
{
|
||||
/*
|
||||
* Cache starts off. Invalidate and then turn it on.
|
||||
*/
|
||||
rARM7M_CACHE_INV = 1;
|
||||
rARM7M_CACHE_ON = ARM7M_CACHE_ON_ENABLE;
|
||||
|
||||
/*
|
||||
* The VIC init is sleep/wake friendly - note this unmasks
|
||||
* interrupts that were unmasked at sleep time, so handlers
|
||||
* must be ready (or interrupt sources should be masked before
|
||||
* sleep).
|
||||
*
|
||||
* This call also exits the critical section that was entered
|
||||
* in platform_sleep (current_task has not changed).
|
||||
*/
|
||||
interrupt_init();
|
||||
|
||||
/* kick the callout system to re-evaluate deadlines */
|
||||
callout_reset_deadline();
|
||||
|
||||
/* and switch back to the context that went to sleep */
|
||||
arch_task_context_restore(&sleeping_task->arch);
|
||||
|
||||
panic("arch_task_context_restore didn't");
|
||||
}
|
||||
#endif /* SUPPORT_SLEEP */
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ARM7M_H
|
||||
#define __ARM7M_H
|
||||
|
||||
#include <sys/types.h>
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
extern int arm7m_init(void);
|
||||
extern void arm7m_halt(void);
|
||||
extern void arm7m_cache_operation(int operation, void *address, u_int32_t length);
|
||||
|
||||
__END_DECLS
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
ALL_OBJS += ${LOCAL_DIR}/arm7m.o
|
||||
|
||||
GLOBAL_INCLUDES += ${LOCAL_DIR}/include
|
||||
@@ -0,0 +1,178 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/display.h>
|
||||
#include <lib/paint.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <drivers/dither.h>
|
||||
|
||||
#include "clcd_regs.h"
|
||||
|
||||
#ifndef CLCD_VERSION
|
||||
#error CLCD_VERSION undefined
|
||||
#endif
|
||||
|
||||
static void clcd_load_gamma_table(u_int32_t lut_id, u_int32_t *lut_data, uint32_t coeff);
|
||||
|
||||
void clcd_enable_clocks(bool enable)
|
||||
{
|
||||
int device;
|
||||
|
||||
if (CLCD_DISPLAYPIPE_BASE_ADDR == DISP0_BASE_ADDR)
|
||||
device = CLK_DISP0;
|
||||
else
|
||||
device = CLK_DISP1;
|
||||
|
||||
// Enable/disable displaypipe and clcd clocks
|
||||
if (enable) {
|
||||
clock_gate(device, true);
|
||||
clock_gate(CLK_CLCD, true);
|
||||
}
|
||||
else {
|
||||
clock_gate(CLK_CLCD, false);
|
||||
clock_gate(device, false);
|
||||
}
|
||||
}
|
||||
|
||||
void clcd_init(struct display_timing *timing)
|
||||
{
|
||||
rCLCD_STATUS = (1 << 8); // Reset CLCD
|
||||
while (rCLCD_STATUS & (1 << 8)); // Wait for reset complete...
|
||||
spin(1); // ... and wait some more: <rdar://problem/6090842>
|
||||
|
||||
// Enable sync enable
|
||||
rCLCD_STATUS = (1 << 2);
|
||||
|
||||
// Bypass and clock gate MIE
|
||||
rCLCD_CFG = (1 << 1) | (1 << 0);
|
||||
|
||||
|
||||
#if DITHER_VERSION == 1
|
||||
rCLCD_DITH_CFG = (1 << 31) | (1 << 0);
|
||||
|
||||
// Set dithering constants
|
||||
rCLCD_DITH_CONST = (2 << 16) | (4 << 8) | (8 << 0);
|
||||
|
||||
if (timing->display_depth <= 18) {
|
||||
#if CLCD_DITHER_BASE_ADDR
|
||||
rCLCD_DITHER_METHOD = (4 << 4) | (2 << 0);
|
||||
rCLCD_DITHER_ENABLE = 1;
|
||||
#else
|
||||
rCLCD_DITH_CFG |= (1 << 24) | (1 << 20) | (1 << 16);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if DITHER_VERSION == 2
|
||||
//Need to force the bypass dithering in the clcd block
|
||||
rCLCD_DITH_CFG = (1 << 31) | (1 << 29) | (1 << 0);
|
||||
rCLCD_DITH_CONST = 0;
|
||||
|
||||
dither_init(timing->display_depth);
|
||||
dither_set_enable(true);
|
||||
#endif
|
||||
|
||||
rCLCD_OTF_CON1 = 0;
|
||||
rCLCD_OTF_CON2 = (timing->neg_vclk << 3) | (timing->neg_hsync << 2) | (timing->neg_vsync << 1) | (timing->neg_vden << 0);
|
||||
|
||||
rCLCD_OTF_TCON1 = (CLCD_OTF_TCON1_VSPP |
|
||||
CLCD_OTF_TCON1_VBPD(timing->v_back_porch) |
|
||||
CLCD_OTF_TCON1_VFPD(timing->v_front_porch) |
|
||||
CLCD_OTF_TCON1_VSPW(timing->v_pulse_width));
|
||||
#if defined(TARGET_CLCD_VSPP) && (TARGET_CLCD_VSPP == 0)
|
||||
rCLCD_OTF_TCON1 &= ~CLCD_OTF_TCON1_VSPP;
|
||||
#endif
|
||||
rCLCD_OTF_TCON2 = (CLCD_OTF_TCON2_HBPD(timing->h_back_porch) |
|
||||
CLCD_OTF_TCON2_HFPD(timing->h_front_porch) |
|
||||
CLCD_OTF_TCON2_HSPW(timing->h_pulse_width));
|
||||
rCLCD_OTF_TCON3 = (CLCD_OTF_TCON3_HOZVAL(timing->h_active) |
|
||||
CLCD_OTF_TCON3_LINEVAL(timing->v_active));
|
||||
}
|
||||
|
||||
bool clcd_get_enable_timing_generator(void)
|
||||
{
|
||||
return ((rCLCD_OTF_CON1 & 1) == 1);
|
||||
}
|
||||
|
||||
void clcd_enable_timing_generator(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
rCLCD_OTF_CON1 |= 1; // Turn OTF on
|
||||
}
|
||||
else {
|
||||
rCLCD_OTF_CON1 &= ~1; // Turn off OTF
|
||||
while ((rCLCD_OTF_CON1 & (1 << 1)) == 0); // Wait for OTF off
|
||||
}
|
||||
}
|
||||
|
||||
void clcd_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl)
|
||||
{
|
||||
RELEASE_ASSERT(red_lut != NULL);
|
||||
RELEASE_ASSERT(green_lut != NULL);
|
||||
RELEASE_ASSERT(blue_lut != NULL);
|
||||
RELEASE_ASSERT(wpcl != NULL);
|
||||
|
||||
// Load the Gamma Correction Table
|
||||
clcd_load_gamma_table(CLCD_GM_COR_RED, red_lut, wpcl->red);
|
||||
clcd_load_gamma_table(CLCD_GM_COR_GREEN, green_lut, wpcl->green);
|
||||
clcd_load_gamma_table(CLCD_GM_COR_BLUE, blue_lut, wpcl->blue);
|
||||
|
||||
#if CLCD_VERSION >= 1
|
||||
// Swap to the new Gamma Correction Table
|
||||
rCLCD_GM_CON = CLCD_GM_CON_GM_CO_TBL_UPDATED;
|
||||
|
||||
// Wait for the swap to complete
|
||||
while ((rCLCD_GM_CON & CLCD_GM_CON_GM_CO_TBL_UPDATED) != 0);
|
||||
|
||||
// Load the Alternate Gamma Correction Table
|
||||
clcd_load_gamma_table(CLCD_GM_COR_RED, red_lut, wpcl->red);
|
||||
clcd_load_gamma_table(CLCD_GM_COR_GREEN, green_lut, wpcl->green);
|
||||
clcd_load_gamma_table(CLCD_GM_COR_BLUE, blue_lut, wpcl->blue);
|
||||
#endif
|
||||
|
||||
// Turn on Gamma Correction
|
||||
rCLCD_GM_CON = CLCD_GM_CON_GM_CO_ENABLE;
|
||||
}
|
||||
|
||||
static void clcd_load_gamma_table(u_int32_t lut_id, u_int32_t *lut_data, uint32_t coeff)
|
||||
{
|
||||
u_int32_t cnt;
|
||||
u_int32_t lut_size = (lut_id == CLCD_GM_ENC) ? 225 : 256;
|
||||
u_int32_t lut_value, lut_value2;
|
||||
|
||||
rCLCD_GM_TBL_ACC_CON = (1 << 16) | (lut_id << 12) | (0 << 0);
|
||||
|
||||
for (cnt = 0; cnt < lut_size; cnt++) {
|
||||
lut_value = lut_data[cnt];
|
||||
|
||||
switch (lut_id) {
|
||||
case CLCD_GM_DEC_RED :
|
||||
case CLCD_GM_DEC_GREEN :
|
||||
case CLCD_GM_DEC_BLUE :
|
||||
break;
|
||||
|
||||
case CLCD_GM_COR_RED :
|
||||
case CLCD_GM_COR_GREEN :
|
||||
case CLCD_GM_COR_BLUE :
|
||||
lut_value2 = (lut_data[cnt + 1] * coeff) >> WpCl_Quotation_Denominator;
|
||||
lut_value = (lut_value * coeff) >> WpCl_Quotation_Denominator;
|
||||
lut_value = ((lut_value << 10) & 0x000FFC00) | (lut_value2 & 0x000003FF);
|
||||
break;
|
||||
|
||||
case CLCD_GM_ENC :
|
||||
break;
|
||||
}
|
||||
|
||||
rCLCD_GM_TBL_WDATA = (1 << 31) | lut_value;
|
||||
}
|
||||
|
||||
rCLCD_GM_TBL_ACC_CON = 0;
|
||||
}
|
||||
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __SAMSUNG_CLCD_REGS_H
|
||||
#define __SAMSUNG_CLCD_REGS_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rCLCD_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0000))
|
||||
#define rCLCD_CFG (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0004))
|
||||
#define rCLCD_INT_EN (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0008))
|
||||
#define rCLCD_INT_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x000C))
|
||||
#define rCLCD_VER (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0010))
|
||||
#define rCLCD_DITH_CFG (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0014))
|
||||
#define rCLCD_DITH_CONST (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0018))
|
||||
#define rCLCD_DPHSYNC_CTRL (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0020))
|
||||
#define rCLCD_DPVSYNC_CTRL (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0024))
|
||||
#define rCLCD_GM_CON (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x002C))
|
||||
#define CLCD_GM_CON_GM_CO_ENABLE (1 << 0)
|
||||
#define CLCD_GM_CON_GM_CO_TBL_UPDATED (1 << 6)
|
||||
#define rCLCD_GM_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0030))
|
||||
#define rCLCD_GM_TBL_ACC_CON (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0034))
|
||||
#define CLCD_GM_OFF (0)
|
||||
#define CLCD_GM_DEC_RED (1)
|
||||
#define CLCD_GM_DEC_GREEN (2)
|
||||
#define CLCD_GM_DEC_BLUE (3)
|
||||
#define CLCD_GM_COR_RED (4)
|
||||
#define CLCD_GM_COR_GREEN (5)
|
||||
#define CLCD_GM_COR_BLUE (6)
|
||||
#define CLCD_GM_ENC (7)
|
||||
#define rCLCD_GM_TBL_WDATA (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0038))
|
||||
#define rCLCD_GM_TBL_RDATA (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x003C))
|
||||
#define rCLCD_OTF_CON1 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0050))
|
||||
#define rCLCD_OTF_CON2 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0054))
|
||||
#define rCLCD_OTF_TCON1 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0058))
|
||||
#if (DISP_VERSION < 3)
|
||||
#define CLCD_OTF_TCON1_VSPP (1 << 24)
|
||||
#define CLCD_OTF_TCON1_VBPD(_l) (((_l)-1) << 16)
|
||||
#define CLCD_OTF_TCON1_VFPD(_l) (((_l)-1) << 8)
|
||||
#define CLCD_OTF_TCON1_VSPW(_l) (((_l)-1) << 0)
|
||||
#else
|
||||
#define CLCD_OTF_TCON1_VSPP (1 << 30)
|
||||
#define CLCD_OTF_TCON1_VBPD(_l) (((_l)-1) << 20)
|
||||
#define CLCD_OTF_TCON1_VFPD(_l) (((_l)-1) << 10)
|
||||
#define CLCD_OTF_TCON1_VSPW(_l) (((_l)-1) << 0)
|
||||
#endif
|
||||
#define rCLCD_OTF_TCON2 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x005C))
|
||||
#if (DISP_VERSION < 4)
|
||||
#define CLCD_OTF_TCON2_HBPD(_p) (((_p)-1) << 16)
|
||||
#define CLCD_OTF_TCON2_HFPD(_p) (((_p)-1) << 8)
|
||||
#define CLCD_OTF_TCON2_HSPW(_p) (((_p)-1) << 0)
|
||||
#else
|
||||
#define CLCD_OTF_TCON2_HBPD(_p) (((_p)-1) << 20)
|
||||
#define CLCD_OTF_TCON2_HFPD(_p) (((_p)-1) << 10)
|
||||
#define CLCD_OTF_TCON2_HSPW(_p) (((_p)-1) << 0)
|
||||
#endif
|
||||
#define rCLCD_OTF_TCON3 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0060))
|
||||
#define CLCD_OTF_TCON3_HOZVAL(_p) (((_p)-1) << 16)
|
||||
#define CLCD_OTF_TCON3_LINEVAL(_p) (((_p)-1) << 0)
|
||||
#define rCLCD_OTF_INT_EN (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0064))
|
||||
#define rCLCD_OTF_INT_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0068))
|
||||
#define rCLCD_MIE_SAT_CON (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0074))
|
||||
|
||||
#define rCLCD_DITHER_ENABLE (*(volatile u_int32_t *)(CLCD_DITHER_BASE_ADDR + 0x0000))
|
||||
#define rCLCD_DITHER_METHOD (*(volatile u_int32_t *)(CLCD_DITHER_BASE_ADDR + 0x0004))
|
||||
|
||||
#endif /* __SAMSUNG_CLCD_REGS_H */
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2012, 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __SAMSUNG_CLCD_V2_H
|
||||
#define __SAMSUNG_CLCD_V2_H
|
||||
|
||||
void clcd_enable_clocks(bool enable);
|
||||
void clcd_init(struct display_timing *timing);
|
||||
bool clcd_get_enable_timing_generator(void);
|
||||
void clcd_enable_timing_generator(bool enable);
|
||||
void clcd_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl);
|
||||
|
||||
#endif /* __SAMSUNG_CLCD_V2_H */
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DISPLAYPIPE_BASE_ADDR=CLCD_DISPLAYPIPE_BASE_ADDR \
|
||||
WITH_DBE_CLCD=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/clcd.o
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_DISPLAYPORT_H
|
||||
#define DRIVER_DISPLAYPORT_H 1
|
||||
|
||||
#include <drivers/display.h>
|
||||
#include <drivers/displayAV.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t mode : 4; // 3:0
|
||||
uint32_t type : 4; // 7:4
|
||||
uint32_t min_link_rate : 8; // 15:8
|
||||
uint32_t max_link_rate : 8; // 23:16
|
||||
uint32_t lanes : 4; // 27:24
|
||||
uint32_t ssc : 1; // 28
|
||||
uint32_t alpm : 1; // 29
|
||||
uint32_t vrr_enable : 1; // 30
|
||||
uint32_t vrr_on : 1; // 31
|
||||
} dp_t;
|
||||
|
||||
#endif //DRIVER_DISPLAYPORT_H
|
||||
@@ -0,0 +1,912 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
// Registers for Display Port General Control
|
||||
#define DPTX_DP_TX_VERSION 0x0010
|
||||
|
||||
#define DPTX_FUNC_EN_1 0x0018
|
||||
|
||||
#define DPTX_FUNC_EN_1_VIDCAP (0x1<<6)
|
||||
#define DPTX_FUNC_EN_1_VIDFIF0 (0x1<<5)
|
||||
#define DPTX_FUNC_EN_1_AUDFIF0 (0x1<<4)
|
||||
#define DPTX_FUNC_EN_1_AUDCAP (0x1<<3)
|
||||
#define DPTX_FUNC_EN_1_HDCP (0x1<<2)
|
||||
#define DPTX_FUNC_EN_1_SW_ALL (0x1<<0)
|
||||
|
||||
#define DPTX_FUNC_EN_2 0x001C
|
||||
#define DPTX_FUNC_EN_2_SSC (0x1<<7)
|
||||
#define DPTX_FUNC_EN_2_AUX (0x1<<2)
|
||||
#define DPTX_FUNC_EN_2_SERDES_FIFO (0x1<<1)
|
||||
#define DPTX_FUNC_EN_2_LS_CLK_DOMAIN (0x1<<0)
|
||||
|
||||
#define DPTX_VIDEO_CTL_1 0x0020
|
||||
#define DPTX_VIDEO_CTL_1_VIDEO_EN_SHIFT (7)
|
||||
#define DPTX_VIDEO_CTL_1_VIDEO_EN (0x1<<DPTX_VIDEO_CTL_1_VIDEO_EN_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_1_VIDEO_MUTE_SHIFT (6)
|
||||
#define DPTX_VIDEO_CTL_1_VIDEO_MUTE (0x1<<DPTX_VIDEO_CTL_1_VIDEO_MUTE_SHIFT)
|
||||
|
||||
#define DPTX_VIDEO_CTL_2 0x0024
|
||||
#define DPTX_VIDEO_CTL_2_IN_D_RANGE_SHIFT (7)
|
||||
#define DPTX_VIDEO_CTL_2_IN_D_RANGE_MASK (0x1<<DPTX_VIDEO_CTL_2_IN_D_RANGE_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_2_IN_D_RANGE_VESA (0x0<<DPTX_VIDEO_CTL_2_IN_D_RANGE_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_2_IN_D_RANGE_CEA (0x1<<DPTX_VIDEO_CTL_2_IN_D_RANGE_SHIFT)
|
||||
|
||||
#define DPTX_VIDEO_CTL_2_IN_BPC_SHIFT (4)
|
||||
#define DPTX_VIDEO_CTL_2_IN_BPC_MASK (0x3<<DPTX_VIDEO_CTL_2_IN_BPC_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_2_IN_BPC_12BIT (0x3<<DPTX_VIDEO_CTL_2_IN_BPC_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_2_IN_BPC_10BIT (0x2<<DPTX_VIDEO_CTL_2_IN_BPC_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_2_IN_BPC_8BIT (0x1<<DPTX_VIDEO_CTL_2_IN_BPC_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_2_IN_BPC_6BIT (0x0<<DPTX_VIDEO_CTL_2_IN_BPC_SHIFT)
|
||||
|
||||
#define DPTX_VIDEO_CTL_2_IN_COLOR_F_SHIFT (0)
|
||||
#define DPTX_VIDEO_CTL_2_IN_COLOR_F_MASK (0x3<<DPTX_VIDEO_CTL_2_IN_COLOR_F_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_2_IN_COLOR_F_YCbCr444 (0x2<<DPTX_VIDEO_CTL_2_IN_COLOR_F_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_2_IN_COLOR_F_YCbCr22 (0x1<<DPTX_VIDEO_CTL_2_IN_COLOR_F_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_2_IN_COLOR_F_RGB (0x0<<DPTX_VIDEO_CTL_2_IN_COLOR_F_SHIFT)
|
||||
|
||||
#define DPTX_VIDEO_CTL_3 0x0028
|
||||
#define DPTX_VIDEO_CTL_3_IN_YC_COEFFI_SHIFT (7)
|
||||
#define DPTX_VIDEO_CTL_3_IN_YC_COEFFI_MASK (0x1<<DPTX_VIDEO_CTL_3_IN_YC_COEFFI_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_3_IN_YC_COEFFI_ITU709 (0x1<<DPTX_VIDEO_CTL_3_IN_YC_COEFFI_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_3_IN_YC_COEFFI_ITU601 (0x0<<DPTX_VIDEO_CTL_3_IN_YC_COEFFI_SHIFT)
|
||||
|
||||
#define DPTX_VIDEO_CTL_4 0x002C
|
||||
#define DPTX_VIDEO_CTL_4_BIST_EN (0x1<<3)
|
||||
|
||||
#define DPTX_VIDEO_CTL_4_BIST_WIDTH_SHIFT (2)
|
||||
#define DPTX_VIDEO_CTL_4_BIST_WIDTH_MASK (0x1<<DPTX_VIDEO_CTL_4_BIST_WIDTH_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_4_BIST_WIDTH_64 (0x1<<DPTX_VIDEO_CTL_4_BIST_WIDTH_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_4_BIST_WIDTH_32 (0x0<<DPTX_VIDEO_CTL_4_BIST_WIDTH_SHIFT)
|
||||
|
||||
#define DPTX_VIDEO_CTL_4_BIST_TYPE_SHIFT (0)
|
||||
#define DPTX_VIDEO_CTL_4_BIST_TYPE_MASK (0x3<<DPTX_VIDEO_CTL_4_BIST_TYPE_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_4_BIST_TYPE_COLOR_BAR (0x0<<DPTX_VIDEO_CTL_4_BIST_TYPE_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_4_BIST_TYPE_W_G_B_BAR (0x1<<DPTX_VIDEO_CTL_4_BIST_TYPE_SHIFT)
|
||||
#define DPTX_VIDEO_CTL_4_BIST_TYPE_MOBILE_WHITE (0x2<<DPTX_VIDEO_CTL_4_BIST_TYPE_SHIFT)
|
||||
|
||||
#define DPTX_VIDEO_CTL_8 0x003C
|
||||
#define DPTX_VIDEO_CTL_10 0x0044
|
||||
#define DPTX_VIDEO_CTL_10_F_SEL (0x1<<4)
|
||||
|
||||
#define DPTX_VIDEO_CTL_10_SLAVE_I_SCAN_CFG (0x1<<2)
|
||||
#define DPTX_VIDEO_CTL_10_VSYNC_P_CFG (0x1<<1)
|
||||
#define DPTX_VIDEO_CTL_10_HSYNC_P_CFG (0x1<<0)
|
||||
|
||||
#define DPTX_TOTAL_LINE_CFG_L 0x0048
|
||||
#define DPTX_TOTAL_LINE_CFG_H 0x004C
|
||||
#define DPTX_ACTIVE_LINE_CFG_L 0x0050
|
||||
#define DPTX_ACTIVE_LINE_CFG_H 0x0054
|
||||
#define DPTX_V_F_PORCH_CFG 0x0058
|
||||
#define DPTX_V_SYNC_WIDTH_CFG 0x005C
|
||||
#define DPTX_V_B_PORCH_CFG 0x0060
|
||||
#define DPTX_TOTAL_PIXEL_CFG_L 0x0064
|
||||
#define DPTX_TOTAL_PIXEL_CFG_H 0x0068
|
||||
#define DPTX_ACTIVE_PIXEL_CFG_L 0x006C
|
||||
#define DPTX_ACTIVE_PIXEL_CFG_H 0x0070
|
||||
#define DPTX_H_F_PORCH_CFG_L 0x0074
|
||||
#define DPTX_H_F_PORCH_CFG_H 0x0078
|
||||
#define DPTX_H_SYNC_CFG_L 0x007C
|
||||
#define DPTX_H_SYNC_CFG_H 0x0080
|
||||
#define DPTX_H_B_PORCH_CFG_L 0x0084
|
||||
#define DPTX_H_B_PORCH_CFG_H 0x0088
|
||||
#define DPTX_VIDEO_STATUS 0x008C
|
||||
#define DPTX_TOTAL_LINE_STA_L 0x0090
|
||||
#define DPTX_TOTAL_LINE_STA_H 0x0094
|
||||
#define DPTX_ACTIVE_LINE_STA_L 0x0098
|
||||
#define DPTX_ACTIVE_LINE_STA_H 0x009C
|
||||
#define DPTX_V_F_PORCH_STA 0x00A0
|
||||
#define DPTX_V_SYNC_STA 0x00A4
|
||||
#define DPTX_V_B_PORCH_STA 0x00A8
|
||||
#define DPTX_TOTAL_PIXEL_STA_L 0x00AC
|
||||
#define DPTX_TOTAL_PIXEL_STA_H 0x00B0
|
||||
#define DPTX_ACTIVE_PIXEL_STA_L 0x00B4
|
||||
#define DPTX_ACTIVE_PIXEL_STA_H 0x00B8
|
||||
#define DPTX_H_F_PORCH_STA_L 0x00BC
|
||||
#define DPTX_H_F_PORCH_STA_H 0x00C0
|
||||
#define DPTX_H_SYNC_STA_L 0x00C4
|
||||
#define DPTX_H_SYNC_STA_H 0x00C8
|
||||
#define DPTX_H_B_PORCH_STA_L 0x00CC
|
||||
#define DPTX_H_B_PORCH_STA_H 0x00D0
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_SPDIF_AUDIO_CTL_0 0x00D8
|
||||
#define DPTX_BF_C_AUD_SPDIF_EN (0x1<<7) //Not Touched: For Audio Slave mode
|
||||
#define DPTX_BF_C_FORCE_SPDIF_DET (0x1<<2) //Not Touched: Test Purpose Only
|
||||
#define DPTX_BF_P_SPDIF_PARITY_CTRL (0x1<<1) //Not Touched: Test Purpose Only
|
||||
#define DPTX_BF_P_SPDIF_CLK_DET_RESET_BYPASS (0x1<<0) //Not Touched: Diffculty of MF code
|
||||
|
||||
#define DPTX_DP_AUDIO_CTL_1 0x00DC
|
||||
#define DPTX_SPDIF_AUDIO_STA_0 0x00E0
|
||||
#define DPTX_SPDIF_AUDIO_STA_1 0x00E4
|
||||
#define DPTX_SPDIF_ERR_THRD 0x00E8
|
||||
#define DPTX_SPDIF_ERR_CNT 0x00EC
|
||||
#define DPTX_AUDIO_BIST_CTL 0x00F0
|
||||
#define DPTX_AUD_FREQ_CNT_1 0x00F4
|
||||
#define DPTX_AUD_FREQ_CNT_2 0x00F8
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_AVI_DB1 0x01D0
|
||||
#define DPTX_AVI_DB2 0x01D4
|
||||
#define DPTX_AVI_DB3 0x01D8
|
||||
#define DPTX_AVI_DB4 0x01DC
|
||||
#define DPTX_AVI_DB5 0x01E0
|
||||
#define DPTX_AVI_DB6 0x01E4
|
||||
#define DPTX_AVI_DB7 0x01E8
|
||||
#define DPTX_AVI_DB8 0x01EC
|
||||
#define DPTX_AVI_DB9 0x01F0
|
||||
#define DPTX_AVI_DB10 0x01F4
|
||||
#define DPTX_AVI_DB11 0x01F8
|
||||
#define DPTX_AVI_DB12 0x01FC
|
||||
#define DPTX_AVI_DB13 0x0200
|
||||
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_AUDIO_DB1 0x021C
|
||||
#define DPTX_AUDIO_DB2 0x0220
|
||||
#define DPTX_AUDIO_DB3 0x0224
|
||||
#define DPTX_AUDIO_DB4 0x0228
|
||||
#define DPTX_AUDIO_DB5 0x022C
|
||||
#define DPTX_AUDIO_DB6 0x0230
|
||||
#define DPTX_AUDIO_DB7 0x0234
|
||||
#define DPTX_AUDIO_DB8 0x0238
|
||||
#define DPTX_AUDIO_DB9 0x023C
|
||||
#define DPTX_AUDIO_DB10 0x0240
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_IF_TYPE 0x0244
|
||||
|
||||
#define DPTX_IF_PKT_DB1 0x0254
|
||||
#define DPTX_IF_PKT_DB2 0x0258
|
||||
#define DPTX_IF_PKT_DB3 0x025C
|
||||
#define DPTX_IF_PKT_DB4 0x0260
|
||||
#define DPTX_IF_PKT_DB5 0x0264
|
||||
#define DPTX_IF_PKT_DB6 0x0268
|
||||
#define DPTX_IF_PKT_DB7 0x026C
|
||||
#define DPTX_IF_PKT_DB8 0x0270
|
||||
#define DPTX_IF_PKT_DB9 0x0274
|
||||
#define DPTX_IF_PKT_DB10 0x0278
|
||||
#define DPTX_IF_PKT_DB11 0x027C
|
||||
#define DPTX_IF_PKT_DB12 0x0280
|
||||
#define DPTX_IF_PKT_DB13 0x0284
|
||||
#define DPTX_IF_PKT_DB14 0x0288
|
||||
#define DPTX_IF_PKT_DB15 0x028C
|
||||
#define DPTX_IF_PKT_DB16 0x0290
|
||||
#define DPTX_IF_PKT_DB17 0x0294
|
||||
#define DPTX_IF_PKT_DB18 0x0298
|
||||
#define DPTX_IF_PKT_DB19 0x029C
|
||||
#define DPTX_IF_PKT_DB20 0x02A0
|
||||
#define DPTX_IF_PKT_DB21 0x02A4
|
||||
#define DPTX_IF_PKT_DB22 0x02A8
|
||||
#define DPTX_IF_PKT_DB23 0x02AC
|
||||
#define DPTX_IF_PKT_DB24 0x02B0
|
||||
#define DPTX_IF_PKT_DB25 0x02B4
|
||||
|
||||
#define DPTX_MPEG_DB1 0x02D0
|
||||
#define DPTX_MPEG_DB2 0x02D4
|
||||
#define DPTX_MPEG_DB3 0x02D8
|
||||
#define DPTX_MPEG_DB4 0x02DC
|
||||
#define DPTX_MPEG_DB5 0x02E0
|
||||
#define DPTX_MPEG_DB6 0x02E4
|
||||
#define DPTX_MPEG_DB7 0x02E8
|
||||
#define DPTX_MPEG_DB8 0x02EC
|
||||
#define DPTX_MPEG_DB9 0x02F0
|
||||
#define DPTX_MPEG_DB10 0x02F4
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_AUDIO_BIST_CH_STA1 0x0340
|
||||
#define DPTX_AUDIO_BIST_CH_STA2 0x0344
|
||||
#define DPTX_AUDIO_BIST_CH_STA3 0x0348
|
||||
#define DPTX_AUDIO_BIST_CH_STA4 0x034C
|
||||
#define DPTX_AUDIO_BIST_CH_STA5 0x0350
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_LANE_MAP 0x035C
|
||||
#define DPTX_LANE_MAP_LANE1_SHIFT 2
|
||||
#define DPTX_LANE_MAP_LANE0_SHIFT 0
|
||||
|
||||
|
||||
#define DPTX_ANALOG_CTL_1 0x0370
|
||||
#if DISPLAYPORT_VERSION >= 3
|
||||
#define DPTX_ANALOG_CTL_1_SEL_BG (1<<6)
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_ANALOG_CTL_1_TX_TERM_CTL_SHIFT 4
|
||||
#define DPTX_ANALOG_CTL_1_TX_TERM_CTL_73_OHM_VALUE 0
|
||||
#define DPTX_ANALOG_CTL_1_TX_TERM_CTL_50_OHM_VALUE 1
|
||||
#define DPTX_ANALOG_CTL_1_TX_TERM_CTL_61_OHM_VALUE 2
|
||||
#define DPTX_ANALOG_CTL_1_TX_TERM_CTL_45_OHM_VALUE 3
|
||||
|
||||
#define DPTX_ANALOG_CTL_1_TX_SWING_INC_30PER (1<<3)
|
||||
|
||||
#define DPTX_ANALOG_CTL_1_TEST_BIT_MASK (0x7)
|
||||
#define DPTX_ANALOG_CTL_1_TEST_BIT_SHIFT (0)
|
||||
|
||||
#define DPTX_ANALOG_CTL_2 0x0374
|
||||
#define DPTX_ANALOG_CTL_2_SEL_CLK_24M (1<<3)
|
||||
|
||||
#define DPTX_ANALOG_CTL_2_TX_DVDD_BIT_MASK (0x7)
|
||||
#define DPTX_ANALOG_CTL_2_TX_DVDD_BIT_SHIFT (0)
|
||||
#define DPTX_ANALOG_CTL_2_TX_DVDD_BIT_DVDD (0<<DPTX_ANALOG_CTL_2_TX_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_2_TX_DVDD_BIT_0_875V (1<<DPTX_ANALOG_CTL_2_TX_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_2_TX_DVDD_BIT_0_9375V (2<<DPTX_ANALOG_CTL_2_TX_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_2_TX_DVDD_BIT_1_000V (3<<DPTX_ANALOG_CTL_2_TX_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_2_TX_DVDD_BIT_1_0625V (4<<DPTX_ANALOG_CTL_2_TX_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_2_TX_DVDD_BIT_1_125V (5<<DPTX_ANALOG_CTL_2_TX_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_2_TX_DVDD_BIT_1_1875V (6<<DPTX_ANALOG_CTL_2_TX_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_2_TX_DVDD_BIT_1_250V (7<<DPTX_ANALOG_CTL_2_TX_DVDD_BIT_SHIFT)
|
||||
|
||||
#define DPTX_ANALOG_CTL_3 0x0378
|
||||
#define DPTX_ANALOG_CTL_3_VCO_BIT_SHIFT (0)
|
||||
#define DPTX_ANALOG_CTL_3_VCO_000uA (0x00<<DPTX_ANALOG_CTL_3_VCO_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_VCO_200uA (0x01<<DPTX_ANALOG_CTL_3_VCO_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_VCO_300uA (0x02<<DPTX_ANALOG_CTL_3_VCO_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_VCO_400uA (0x03<<DPTX_ANALOG_CTL_3_VCO_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_VCO_500uA (0x04<<DPTX_ANALOG_CTL_3_VCO_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_VCO_600uA (0x05<<DPTX_ANALOG_CTL_3_VCO_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_VCO_700uA (0x06<<DPTX_ANALOG_CTL_3_VCO_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_VCO_900uA (0x07<<DPTX_ANALOG_CTL_3_VCO_BIT_SHIFT)
|
||||
|
||||
#define DPTX_ANALOG_CTL_3_SEL_CUR_SHIFT (3)
|
||||
#define DPTX_ANALOG_CTL_3_SEL_CUR_LPP_LC_AVG (0x00<<DPTX_ANALOG_CTL_3_SEL_CUR_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_SEL_CUR_LC (0x01<<DPTX_ANALOG_CTL_3_SEL_CUR_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_SEL_CUR_LPP (0x02<<DPTX_ANALOG_CTL_3_SEL_CUR_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_SEL_CUR_LPP_LC (0x03<<DPTX_ANALOG_CTL_3_SEL_CUR_SHIFT)
|
||||
|
||||
#define DPTX_ANALOG_CTL_3_DRIVE_DVDD_BIT_SHIFT (5)
|
||||
#define DPTX_ANALOG_CTL_3_DRIVE_DVDD (0x00<<DPTX_ANALOG_CTL_3_DRIVE_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_DRIVE_0_8750V (0x01<<DPTX_ANALOG_CTL_3_DRIVE_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_DRIVE_0_9375V (0x02<<DPTX_ANALOG_CTL_3_DRIVE_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_DRIVE_1_1000V (0x03<<DPTX_ANALOG_CTL_3_DRIVE_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_DRIVE_1_0625V (0x04<<DPTX_ANALOG_CTL_3_DRIVE_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_DRIVE_1_1250V (0x05<<DPTX_ANALOG_CTL_3_DRIVE_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_DRIVE_1_1875V (0x06<<DPTX_ANALOG_CTL_3_DRIVE_DVDD_BIT_SHIFT)
|
||||
#define DPTX_ANALOG_CTL_3_DRIVE_1_2500V (0x07<<DPTX_ANALOG_CTL_3_DRIVE_DVDD_BIT_SHIFT)
|
||||
|
||||
|
||||
#define DPTX_PLL_FILTER_CTL_1 0x037C
|
||||
#define DPTX_PLL_FILTER_CTL_1_PD_RING_OSC_PWR_DWN (0x1<<6)
|
||||
|
||||
#define DPTX_PLL_FILTER_CTL_1_AUX_TERM_CTL_SHIFT (4)
|
||||
#define DPTX_PLL_FILTER_CTL_1_AUX_TERM_CTL_200_OHM (0x0<<DPTX_PLL_FILTER_CTL_1_AUX_TERM_CTL_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_1_AUX_TERM_CTL_102_OHM (0x1<<DPTX_PLL_FILTER_CTL_1_AUX_TERM_CTL_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_1_AUX_TERM_CTL_69_OHM (0x2<<DPTX_PLL_FILTER_CTL_1_AUX_TERM_CTL_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_1_AUX_TERM_CTL_52_OHM (0x3<<DPTX_PLL_FILTER_CTL_1_AUX_TERM_CTL_SHIFT)
|
||||
|
||||
#define DPTX_PLL_FILTER_CTL_1_TX_CUR_MULT_SHIFT (2)
|
||||
#define DPTX_PLL_FILTER_CTL_1_TX_CUR_MULT_1 (0x0<<DPTX_PLL_FILTER_CTL_1_TX_CUR_MULT_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_1_TX_CUR_MULT_2 (0x1<<DPTX_PLL_FILTER_CTL_1_TX_CUR_MULT_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_1_TX_CUR_MULT_3 (0x2<<DPTX_PLL_FILTER_CTL_1_TX_CUR_MULT_SHIFT)
|
||||
|
||||
#define DPTX_PLL_FILTER_CTL_1_TX_CUR_SHIFT (0)
|
||||
#define DPTX_PLL_FILTER_CTL_1_TX_CUR_1mA (0x0<<DPTX_PLL_FILTER_CTL_1_TX_CUR_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_1_TX_CUR_2mA (0x1<<DPTX_PLL_FILTER_CTL_1_TX_CUR_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_1_TX_CUR_3mA (0x2<<DPTX_PLL_FILTER_CTL_1_TX_CUR_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_1_TX_CUR_4mA (0x3<<DPTX_PLL_FILTER_CTL_1_TX_CUR_SHIFT)
|
||||
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_PLL_FILTER_CTL_2 0x0380
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH1_AMP_SHIFT (4)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH1_AMP_NEG_120mV (0x0<<DPTX_PLL_FILTER_CTL_2_CH1_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH1_AMP_NEG_80mV (0x1<<DPTX_PLL_FILTER_CTL_2_CH1_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH1_AMP_NEG_40mV (0x2<<DPTX_PLL_FILTER_CTL_2_CH1_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH1_AMP_0mV (0x3<<DPTX_PLL_FILTER_CTL_2_CH1_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH1_AMP_40mV (0x4<<DPTX_PLL_FILTER_CTL_2_CH1_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH1_AMP_80mV (0x5<<DPTX_PLL_FILTER_CTL_2_CH1_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH1_AMP_120mV (0x6<<DPTX_PLL_FILTER_CTL_2_CH1_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH1_AMP_160mV (0x7<<DPTX_PLL_FILTER_CTL_2_CH1_AMP_SHIFT)
|
||||
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH0_AMP_SHIFT (0)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH0_AMP_NEG_120mV (0x0<<DPTX_PLL_FILTER_CTL_2_CH0_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH0_AMP_NEG_80mV (0x1<<DPTX_PLL_FILTER_CTL_2_CH0_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH0_AMP_NEG_40mV (0x2<<DPTX_PLL_FILTER_CTL_2_CH0_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH0_AMP_0mV (0x3<<DPTX_PLL_FILTER_CTL_2_CH0_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH0_AMP_40mV (0x4<<DPTX_PLL_FILTER_CTL_2_CH0_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH0_AMP_80mV (0x5<<DPTX_PLL_FILTER_CTL_2_CH0_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH0_AMP_120mV (0x6<<DPTX_PLL_FILTER_CTL_2_CH0_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH0_AMP_160mV (0x7<<DPTX_PLL_FILTER_CTL_2_CH0_AMP_SHIFT)
|
||||
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH0_AMP_SHIFT (0)
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_AUX_HW_RETRY_CTL 0x0390
|
||||
|
||||
#define DPTX_AUX_HW_RETRY_BIT_PERIOD_DELAY_SHIFT (8)
|
||||
#define DPTX_AUX_HW_RETRY_BIT_PERIOD_DELAY_MASK (0x7)
|
||||
|
||||
#define DPTX_AUX_HW_RETRY_INTERVAL_SHIFT (3)
|
||||
#define DPTX_AUX_HW_RETRY_INTERVAL_600us (0x00<<DPTX_AUX_HW_RETRY_INTERVAL_SHIFT)
|
||||
#define DPTX_AUX_HW_RETRY_INTERVAL_800us (0x01<<DPTX_AUX_HW_RETRY_INTERVAL_SHIFT)
|
||||
#define DPTX_AUX_HW_RETRY_INTERVAL_1000us (0x02<<DPTX_AUX_HW_RETRY_INTERVAL_SHIFT)
|
||||
#define DPTX_AUX_HW_RETRY_INTERVAL_1800us (0x03<<DPTX_AUX_HW_RETRY_INTERVAL_SHIFT)
|
||||
|
||||
#define DPTX_AUX_HW_RETRY_COUNT_SHIFT (0)
|
||||
#define DPTX_AUX_HW_RETRY_COUNT_MASK (0x7)
|
||||
|
||||
#define DPTX_INT_STATE 0x03C0
|
||||
#define DPTX_COMMON_INT_STA_1 0x03C4
|
||||
#define DPTX_COMMON_INT_1_VSYNC_DET (0x1<<7)
|
||||
#define DPTX_COMMON_INT_1_PLL_LCK_CHG (0x1<<6)
|
||||
#define DPTX_COMMON_INT_1_SPDIF_ERR (0x1<<5)
|
||||
#define DPTX_COMMON_INT_1_SPDIF_UNSTBL (0x1<<4)
|
||||
#define DPTX_COMMON_INT_1_VID_FMT_CHG (0x1<<3)
|
||||
#define DPTX_COMMON_INT_1_AUD_CLK_CHG (0x1<<2)
|
||||
#define DPTX_COMMON_INT_1_VID_CLK_CHG (0x1<<1)
|
||||
#define DPTX_COMMON_INT_1_VSW_INT (0x1<<0)
|
||||
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_COMMON_INT_STA_2 0x03C8
|
||||
#define DPTX_COMMON_INT_2_HDCP_CHG (0x1<<6)
|
||||
#define DPTX_COMMON_INT_2_HW_BKSV_RDY (0x1<<3)
|
||||
#define DPTX_COMMON_INT_2_HW_SHA_DONE (0x1<<2)
|
||||
#define DPTX_COMMON_INT_2_HW_AUTH_CHG (0x1<<1)
|
||||
#define DPTX_COMMON_INT_2_HW_AUTH_DONE (0x1<<0)
|
||||
|
||||
#define DPTX_COMMON_INT_STA_3 0x03CC
|
||||
#define DPTX_COMMON_INT_3_AFIFO_UNDER (0x1<<7)
|
||||
#define DPTX_COMMON_INT_3_AFIFO_OVER (0x1<<6)
|
||||
#define DPTX_COMMON_INT_3_R0_CHK (0x1<<5)
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_COMMON_INT_STA_4 0x03D0
|
||||
#define DPTX_COMMON_INT_4_SPDIF_BI_PHASE_ERR (0x1<<5)
|
||||
#define DPTX_COMMON_INT_4_HP_CHG (0x1<<2)
|
||||
#define DPTX_COMMON_INT_4_HPD_LOST (0x1<<1)
|
||||
#define DPTX_COMMON_INT_4_PLUG (0x1<<0)
|
||||
|
||||
#define DPTX_DP_INT_STA 0x03DC
|
||||
#define DPTX_DP_INT_STA_INT_HPD (0x1<<6)
|
||||
#define DPTX_DP_INT_STA_HW_LINK_TR_FIN (0x1<<5)
|
||||
#define DPTX_DP_INT_STA_RPLY_RCV (0x1<<1)
|
||||
#define DPTX_DP_INT_STA_AUX_ERR (0x1<<0)
|
||||
|
||||
#define DPTX_COMMON_INT_MASK_1 0x03E0
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_COMMON_INT_MASK_2 0x03E4
|
||||
#define DPTX_COMMON_INT_MASK_3 0x03E8
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_COMMON_INT_MASK_4 0x03EC
|
||||
|
||||
#define DPTX_DP_INT_STA_MASK 0x03F8
|
||||
#define DPTX_INT_CTL 0x03FC
|
||||
#define DPTX_INT_SET_SOFT_INT (1<<2)
|
||||
#define DPTX_INT_POLARITY_HIGH (1<<0)
|
||||
|
||||
// Registers for HDCP Function
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_HDCP_STA 0x0400
|
||||
#define DPTX_HDCP_STA_BKSV_VALID (0x1<<3)
|
||||
#define DPTX_HDCP_STA_ENCRYPT (0x1<<2)
|
||||
#define DPTX_HDCP_STA_HW_AUTHEN_PASS (0x1<<1)
|
||||
#define DPTX_HDCP_STA_AKSV_VALID (0x1<<0)
|
||||
|
||||
#define DPTX_HDCP_CTL_0 0x0404
|
||||
#define DPTX_HDCP_CTL_0_SW_STORE_AN (0x1<<7)
|
||||
#define DPTX_HDCP_CTL_0_SW_RX_REPEATER (0x1<<6)
|
||||
#define DPTX_HDCP_CTL_0_HW_RE_AUTHEN (0x1<<5)
|
||||
#define DPTX_HDCP_CTL_0_SW_AUTH_OK (0x1<<4)
|
||||
#define DPTX_HDCP_CTL_0_HW_AUTH_EN (0x1<<3)
|
||||
#define DPTX_HDCP_CTL_0_HDCP_ENC_EN (0x1<<2)
|
||||
#define DPTX_HDCP_CTL_0_HW_1ST_PART_ATHENTICATION_EN (0x1<<1)
|
||||
#define DPTX_HDCP_CTL_0_HW_2ND_PART_ATHENTICATION_EN (0x1<<0)
|
||||
|
||||
#define DPTX_AKSV0 0x0414
|
||||
#define DPTX_AKSV1 0x0418
|
||||
#define DPTX_AKSV2 0x041C
|
||||
#define DPTX_AKSV3 0x0420
|
||||
#define DPTX_AKSV4 0x0424
|
||||
#define DPTX_AN0 0x0428
|
||||
#define DPTX_AN1 0x042C
|
||||
#define DPTX_AN2 0x0430
|
||||
#define DPTX_AN3 0x0434
|
||||
#define DPTX_AN4 0x0438
|
||||
#define DPTX_AN5 0x043C
|
||||
#define DPTX_AN6 0x0440
|
||||
#define DPTX_AN7 0x0444
|
||||
#define DPTX_BKSV0 0x0448
|
||||
#define DPTX_BKSV1 0x044C
|
||||
#define DPTX_BKSV2 0x0450
|
||||
#define DPTX_BKSV3 0x0454
|
||||
#define DPTX_BKSV4 0x0458
|
||||
#define DPTX_RI0 0x045C
|
||||
#define DPTX_RI1 0x0460
|
||||
#define DPTX_RX_CAPS 0x0468
|
||||
#define DPTX_RX_BSTATUS_0 0x046C
|
||||
#define DPTX_RX_BSTATUS_1 0x0470
|
||||
#define DPTX_SKIP_RPT_ZERO_DEV 0x0474
|
||||
#define DPTX_HDCP_KEY_STA 0x0478
|
||||
#define DPTX_HDCP_KEY_CMD 0x047C
|
||||
#define DPTX_SPSRAM_CFG_1 0x0488
|
||||
#define DPTX_SPSRAM_CFG_1_KEY_MODE (0x1<<6)
|
||||
#define DPTX_SPSRAM_CFG_1_SRAM_RW_DONE (0x1<<5)
|
||||
#define DPTX_SPSRAM_CFG_1_SRAM_WRITE_EN (0x1<<2)
|
||||
#define DPTX_SPSRAM_CFG_1_SRAM_READ_EN (0x1<<1)
|
||||
#define DPTX_SPSRAM_CFG_1_SRAM_ADDR8 (0x1<<0)
|
||||
|
||||
#define DPTX_SPSRAM_CFG_2 0x048C
|
||||
#define DPTX_RW_ROM_ADDR 0x0490
|
||||
#define DPTX_RD_DATA 0x0494
|
||||
#define DPTX_W_DATA 0x0498
|
||||
#define DPTX_HDCP_FRAME_NUM 0x04A4
|
||||
#define DPTX_HDCP_VID_0 0x04A8
|
||||
#define DPTX_HDCP_VID_1 0x04AC
|
||||
#define DPTX_HDCP_VID_2 0x04B0
|
||||
#define DPTX_HDCP_AM0_0 0x04C0
|
||||
#define DPTX_HDCP_AM0_1 0x04C4
|
||||
#define DPTX_HDCP_AM0_2 0x04C8
|
||||
#define DPTX_HDCP_AM0_3 0x04CC
|
||||
#define DPTX_HDCP_AM0_4 0x04D0
|
||||
#define DPTX_HDCP_AM0_5 0x04D4
|
||||
#define DPTX_HDCP_AM0_6 0x04D8
|
||||
#define DPTX_HDCP_AM0_7 0x04DC
|
||||
#define DPTX_WRITE_AKSV_WAIT 0x0500
|
||||
#define DPTX_LINK_CHK_TIMER 0x0504
|
||||
#define DPTX_RPTR_RDY_TIMER 0x0508
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
//Registers for Display Port Functions
|
||||
#define DPTX_SYS_CTL_1 0x0600
|
||||
#define DPTX_SYS_CTL_1_DET_STA (1<<2)
|
||||
|
||||
|
||||
#define DPTX_SYS_CTL_2 0x0604
|
||||
#define DPTX_SYS_CTL_2_STRM_CHG_STA (1<<2)
|
||||
|
||||
#define DPTX_SYS_CTL_3 0x0608
|
||||
#define DPTX_SYS_CTL_3_HPD_STATUS (0x1<<6)
|
||||
#define DPTX_SYS_CTL_3_F_HPD (0x1<<5)
|
||||
#define DPTX_SYS_CTL_3_HPD_CTRL (0x1<<4)
|
||||
#define DPTX_SYS_CTL_3_HDCP_RDY (0x1<<3)
|
||||
#define DPTX_SYS_CTL_3_STRM_VALID (0x1<<2)
|
||||
#define DPTX_SYS_CTL_3_F_VALID (0x1<<1)
|
||||
#define DPTX_SYS_CTL_3_VALID_CTRL (0x1<<0)
|
||||
|
||||
|
||||
#define DPTX_SYS_CTL_4 0x060c
|
||||
#define DPTX_SYS_CTL_4_FIX_M_AUD (0x1<<4)
|
||||
#define DPTX_SYS_CTL_4_ENHANCED (0x1<<3)
|
||||
#define DPTX_SYS_CTL_4_FIX_M_VID (0x1<<2)
|
||||
|
||||
#define DPTX_DP_VID_CTL 0x0610
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_DP_AUD_CTL 0x0618
|
||||
#define DPTX_BF_C_DP_AUDIO_EN (0x1<<0)
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_PKT_SEND_CTL 0x0640
|
||||
#define DPTX_BF_C_AUDIO_INFO_UP (0x1<<7)
|
||||
#define DPTX_BF_C_AVI_UP (0x1<<6)
|
||||
#define DPTX_BF_C_MPEG_UP (0x1<<5)
|
||||
#define DPTX_BF_C_IF_UP (0x1<<4)
|
||||
#define DPTX_BF_C_AUDIO_INFOR_EN (0x1<<3)
|
||||
#define DPTX_BF_C_AVI_EN (0x1<<2)
|
||||
#define DPTX_BF_C_MPEG_EN (0x1<<1)
|
||||
#define DPTX_BF_C_IF_EN (0x1<<0)
|
||||
|
||||
#define DPTX_DP_HDCP_CTL 0x0648
|
||||
#define DPTX_DP_HDCP_CTL_HW_HDCP_INT (0x1<<0)
|
||||
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_SPDIF_PHASE1_CTL_0 0x0650
|
||||
#define DPTX_SPDIF_PHASE1_CTL_1 0x0654
|
||||
#define DPTX_SPDIF_PHASE2_CTL_0 0x0658
|
||||
#define DPTX_SPDIF_PHASE2_CTL_1 0x065C
|
||||
#define DPTX_SPDIF_PHASE3_CTL_0 0x0660
|
||||
#define DPTX_SPDIF_PHASE3_CTL_1 0x0664
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_LINK_BW_SET 0x0680
|
||||
#define DPTX_LANE_COUNT_SET 0x0684
|
||||
#define DPTX_DP_TRAINING_PTRN_SET 0x0688
|
||||
#define DPTX_DP_TRAINING_PTRN_SET_SCRM_EDP (1<<9)
|
||||
#define DPTX_DP_TRAINING_PTRN_SET_SCRM_DIS (1<<5)
|
||||
|
||||
#define DPTX_DP_TRAINING_PTRN_SET_LQ_SHIFT 2
|
||||
#define DPTX_DP_TRAINING_PTRN_SET_SW_SHIFT 0
|
||||
|
||||
#define DPTX_DP_TRAINING_PTRN_SET_SW_MASK 0x3
|
||||
|
||||
#define DPTX_DP_LN0_LINK_TRAINING_CTL 0x068C
|
||||
#define DPTX_DP_LN1_LINK_TRAINING_CTL 0x0690
|
||||
#define DPTX_DP_LN2_LINK_TRAINING_CTL 0x0694
|
||||
#define DPTX_DP_LN3_LINK_TRAINING_CTL 0x0698
|
||||
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_FINE_ADJ_PRE_EMPHASIS_SHIFT (6)
|
||||
|
||||
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_MAX_PRE_REACH (1<<5)
|
||||
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_PRE_SET_SHIFT (3)
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_PRE_SET_MASK (0x3 << DPTX_DP_LN_LINK_TRAINING_CTL_PRE_SET_SHIFT)
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_PRE_SET_9_5dB (3<<DPTX_DP_LN_LINK_TRAINING_CTL_PRE_SET_SHIFT)
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_PRE_SET_6_0dB (2<<DPTX_DP_LN_LINK_TRAINING_CTL_PRE_SET_SHIFT)
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_PRE_SET_3_5dB (1<<DPTX_DP_LN_LINK_TRAINING_CTL_PRE_SET_SHIFT)
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_PRE_SET_0dB (0<<DPTX_DP_LN_LINK_TRAINING_CTL_PRE_SET_SHIFT)
|
||||
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_MAX_DRV_REACH (1<<2)
|
||||
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_DRV_SET_SHIFT (0)
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_DRV_SET_MASK (0x3 << DPTX_DP_LN_LINK_TRAINING_CTL_DRV_SET_SHIFT)
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_DRV_SET_1200mV (3<<DPTX_DP_LN_LINK_TRAINING_CTL_DRV_SET_SHIFT)
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_DRV_SET_800mV (2<<DPTX_DP_LN_LINK_TRAINING_CTL_DRV_SET_SHIFT)
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_DRV_SET_600mV (1<<DPTX_DP_LN_LINK_TRAINING_CTL_DRV_SET_SHIFT)
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_DRV_SET_400mV (0<<DPTX_DP_LN_LINK_TRAINING_CTL_DRV_SET_SHIFT)
|
||||
#else //DISPLAYPORT_VERSION
|
||||
#define LOW_POWER_MODE 1
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_PC2_SHIFT 16
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_PRE_EMP_SHIFT 8
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_SWING_SHIFT 0
|
||||
#define DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(_pc2, _pre_emph, _swing) \
|
||||
((_pc2 << DPTX_DP_LN_LINK_TRAINING_CTL_PC2_SHIFT) | (_pre_emph << DPTX_DP_LN_LINK_TRAINING_CTL_PRE_EMP_SHIFT) | (_swing << DPTX_DP_LN_LINK_TRAINING_CTL_SWING_SHIFT))
|
||||
|
||||
//Table 5_ Low Swing Mode when SEL_LOWPOWER is 1
|
||||
#define CHX_SWING_150mV_PRE_EMP1_0dB_PRE_EMP2_0dB DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x0, 0x1e)
|
||||
#define CHX_SWING_200mV_PRE_EMP1_0dB_PRE_EMP2_0dB DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x0, 0x28)
|
||||
#define CHX_SWING_250mV_PRE_EMP1_0dB_PRE_EMP2_0dB DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x0, 0x32)
|
||||
#define CHX_SWING_300mV_PRE_EMP1_0dB_PRE_EMP2_0dB DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x0, 0x3c)
|
||||
#define CHX_SWING_150mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0xf, 0x26)
|
||||
#define CHX_SWING_200mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x14, 0x32)
|
||||
#define CHX_SWING_250mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x19, 0x3f)
|
||||
#define CHX_SWING_300mV_PRE_EMP1_6dB_PRE_EMP2_0dB DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x1e, 0x4b)
|
||||
//Table 6_ Post Cursor 0
|
||||
#define CHX_SWING_400mV_PRE_EMP1_0dB_PRE_EMP2_0dB_PC0 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x0, 0x50)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_0dB_PRE_EMP2_0dB_PC0 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x0, 0x78)
|
||||
#define CHX_SWING_800mV_PRE_EMP1_0dB_PRE_EMP2_0dB_PC0 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x0, 0xa0)
|
||||
#define CHX_SWING_1200mV_PRE_EMP1_0dB_PRE_EMP2_0dB_PC0 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x0, 0xf0)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB_PC0 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x28, 0x64)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB_PC0 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x3c, 0x96)
|
||||
#define CHX_SWING_800mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB_PC0 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x50, 0xc8)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_6dB_PRE_EMP2_0dB_PC0 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x50, 0x78)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_6dB_PRE_EMP2_0dB_PC0 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0x78, 0xb4)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_9_5dB_PRE_EMP2_0dB_PC0 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x0, 0xa0, 0xa0)
|
||||
//Table 7_ Post Cursor 0_05
|
||||
#define CHX_SWING_400mV_PRE_EMP1_0dB_PRE_EMP2__0_92dB_PC005 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x4, 0x0, 0x4c)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_0dB_PRE_EMP2_0dB_PC005 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x6, 0x0, 0x72)
|
||||
#define CHX_SWING_800mV_PRE_EMP1_0dB_PRE_EMP2_0dB_PC005 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x8, 0x0, 0x98)
|
||||
#define CHX_SWING_1200mV_PRE_EMP1_0dB_PRE_EMP2_0dB_PC005 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0xc, 0x0, 0xe4)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB_PC005 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x6, 0x28, 0x5e)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB_PC005 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x9, 0x3c, 0x8d)
|
||||
#define CHX_SWING_800mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB_PC005 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0xc, 0x50, 0xbc)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_6dB_PRE_EMP2_0dB_PC005 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x8, 0x50, 0x70)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_6dB_PRE_EMP2_0dB_PC005 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0xc, 0x78, 0xa8)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_9_5dB_PRE_EMP2_0dB_PC005 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0xc, 0xa0, 0x94)
|
||||
//Table 8_ Post Cursor 0_1
|
||||
#define CHX_SWING_400mV_PRE_EMP1_0dB_PRE_EMP2__1_94dB_PC01 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x8, 0x0, 0x48)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_0dB_PRE_EMP2__1_94dB_PC01 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0xc, 0x0, 0x6c)
|
||||
#define CHX_SWING_800mV_PRE_EMP1_0dB_PRE_EMP2__1_94dB_PC01 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x10, 0x0, 0x90)
|
||||
#define CHX_SWING_1200mV_PRE_EMP1_0dB_PRE_EMP2__1_94dB_PC01 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x18, 0x0, 0xd8)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_3_5dB_PRE_EMP2__1_94dB_PC01 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0xc, 0x28, 0x58)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_3_5dB_PRE_EMP2__1_94dB_PC01 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x12, 0x3c, 0x84)
|
||||
#define CHX_SWING_800mV_PRE_EMP1_3_5dB_PRE_EMP2__1_94dB_PC01 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x18, 0x50, 0xb0)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_6dB_PRE_EMP2__1_94dB_PC01 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x10, 0x50, 0x68)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_6dB_PRE_EMP2__1_94dB_PC01 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x18, 0x78, 0x9c)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_9_5dB_PRE_EMP2__1_94dB_PC01 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x18, 0xa0, 0x88)
|
||||
//Table 9_ Post Cursor 0_15
|
||||
#define CHX_SWING_400mV_PRE_EMP1_0dB_PRE_EMP2_0dB_PC015 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0xc, 0x0, 0x44)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_0dB_PRE_EMP2_0dB_PC015 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x12, 0x0, 0x66)
|
||||
#define CHX_SWING_800mV_PRE_EMP1_0dB_PRE_EMP2_0dB_PC015 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x18, 0x0, 0x88)
|
||||
#define CHX_SWING_1200mV_PRE_EMP1_0dB_PRE_EMP2_0dB_PC015 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x24, 0x0, 0xcc)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB_PC015 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x12, 0x28, 0x52)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB_PC015 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x1b, 0x3c, 0x7b)
|
||||
#define CHX_SWING_800mV_PRE_EMP1_3_5dB_PRE_EMP2_0dB_PC015 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x24, 0x50, 0xa4)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_6dB_PRE_EMP2_0dB_PC015 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x18, 0x50, 0x60)
|
||||
#define CHX_SWING_600mV_PRE_EMP1_6dB_PRE_EMP2_0dB_PC015 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x24, 0x78, 0x90)
|
||||
#define CHX_SWING_400mV_PRE_EMP1_9_5dB_PRE_EMP2_0dB_PC015 DPTX_DP_LN_LINK_TRAINING_CTL_GEN_VALUE(0x24, 0xa0, 0x7c)
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
|
||||
#define DPTX_DP_DN_SPREAD_CTL 0x069C
|
||||
#define DPTX_DP_DN_SPREAD_ENABLE (0x1<<4)
|
||||
#define DPTX_DP_DN_SPREAD_MOD_FREQ_33Khz (0x1<<0)
|
||||
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_DP_HW_LINK_TRAINING_CTL 0x06A0
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_DP_DEBUG_CTL 0x06C0
|
||||
|
||||
#define DPTX_DP_DEBUG_CTL_PLL_LOCK (0x1<<4)
|
||||
#define DPTX_DP_DEBUG_CTL_F_PLL_LOCK (0x1<<3)
|
||||
#define DPTX_DP_DEBUG_CTL_PLL_LOCK_CTRL (0x1<<2)
|
||||
|
||||
|
||||
#define DPTX_HPD_DEGLITCH_L 0x06C4
|
||||
#define DPTX_HPD_DEGLITCH_H 0x06C8
|
||||
#define DPTX_DP_LINK_DEBUG_CTL 0x06E0
|
||||
|
||||
#define DPTX_M_VID_0 0x0700
|
||||
#define DPTX_M_VID_1 0x0704
|
||||
#define DPTX_M_VID_2 0x0708
|
||||
#define DPTX_N_VID_0 0x070C
|
||||
#define DPTX_N_VID_1 0x0710
|
||||
#define DPTX_N_VID_2 0x0714
|
||||
#define DPTX_M_VID_MON 0x0718
|
||||
#define DPTX_DP_PLL_CTL 0x071C
|
||||
#define DPTX_DP_PLL_CTL_PLL_HS2_BIT (1<<8)
|
||||
#define DPTX_DP_PLL_CTL_PWR_DN (1<<7)
|
||||
#define DPTX_DP_PLL_CTL_RESET (1<<6)
|
||||
#define DPTX_DP_PLL_CTL_LOOP_FLT_BAND_SHIFT (4)
|
||||
// For HBR 2.7Gbps
|
||||
#define DPTX_DP_PLL_CTL_LOOP_FLT_BAND_125Khz (0<<DPTX_DP_PLL_CTL_LOOP_FLT_BAND_SHIFT)
|
||||
#define DPTX_DP_PLL_CTL_LOOP_FLT_BAND_175Khz (1<<DPTX_DP_PLL_CTL_LOOP_FLT_BAND_SHIFT)
|
||||
#define DPTX_DP_PLL_CTL_LOOP_FLT_BAND_248Khz (2<<DPTX_DP_PLL_CTL_LOOP_FLT_BAND_SHIFT)
|
||||
#define DPTX_DP_PLL_CTL_LOOP_FLT_BAND_305Khz (3<<DPTX_DP_PLL_CTL_LOOP_FLT_BAND_SHIFT)
|
||||
// For HBR 1.62Gbps
|
||||
#define DPTX_DP_PLL_CTL_LOOP_FLT_BAND_166Khz (0<<DPTX_DP_PLL_CTL_LOOP_FLT_BAND_SHIFT)
|
||||
#define DPTX_DP_PLL_CTL_LOOP_FLT_BAND_234Khz (1<<DPTX_DP_PLL_CTL_LOOP_FLT_BAND_SHIFT)
|
||||
#define DPTX_DP_PLL_CTL_LOOP_FLT_BAND_333Khz (2<<DPTX_DP_PLL_CTL_LOOP_FLT_BAND_SHIFT)
|
||||
#define DPTX_DP_PLL_CTL_LOOP_FLT_BAND_406Khz (3<<DPTX_DP_PLL_CTL_LOOP_FLT_BAND_SHIFT)
|
||||
|
||||
#define DPTX_DP_PHY_PD 0x0720
|
||||
#define DPTX_DP_PHY_SEL_LOWPOWER (1<<6)
|
||||
#define DPTX_DP_PHY_PWR_DWN (1<<5)
|
||||
#define DPTX_DP_PHY_AUX_PWR_DWN (1<<4)
|
||||
#define DPTX_DP_PHY_CH1_PWR_DWN (1<<1)
|
||||
#define DPTX_DP_PHY_CH0_PWR_DWN (1<<0)
|
||||
|
||||
#define DPTX_DP_PHY_TEST 0x0724
|
||||
#define DPTX_DP_PHY_TEST_RST_MACRO (1<<5)
|
||||
#define DPTX_DP_PHY_TEST_PLL (1<<4)
|
||||
#define DPTX_DP_PHY_TEST_CH1 (1<<1)
|
||||
#define DPTX_DP_PHY_TEST_CH0 (1<<0)
|
||||
|
||||
#define DPTX_DP_VIDEO_FIFO_THRD 0x0730
|
||||
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_DP_AUDIO_MARGIN 0x073C
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_DP_DN_SPREAD_CTL_1 0x0740
|
||||
#define DPTX_DP_DN_SPREAD_CTL_2 0x0744
|
||||
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_M_AUD_0 0x0748
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_M_AUD_1 0x074C
|
||||
#define DPTX_M_AUD_2 0x0750
|
||||
#define DPTX_N_AUD_0 0x0754
|
||||
#define DPTX_N_AUD_1 0x0758
|
||||
#define DPTX_N_AUD_2 0x075C
|
||||
#define DPTX_DP_M_CAL_CTL 0x0760
|
||||
#define DPTX_DP_M_CAL_CTL_AUD_GEN_FILTER_EN (0x1<<3)
|
||||
#define DPTX_DP_M_CAL_CTL_VID_GEN_FILTER_EN (0x1<<2)
|
||||
#define DPTX_DP_M_CAL_CTL_GEN_CLK_SEL (0x1<<0)
|
||||
|
||||
#define DPTX_M_VID_GEN_FILTER_TH 0x0764
|
||||
#define DPTX_M_AUD_GEN_FILTER_TH 0x0778
|
||||
|
||||
#define DPTX_AUX_CH_STA 0x0780
|
||||
#define DPTX_AUX_CH_STA_BUSY (0x1<<4)
|
||||
#define DPTX_AUX_CH_STA_STATUS_MASK (0xf)
|
||||
#define DPTX_AUX_CH_STA_STATUS_SHIFT (0)
|
||||
#define DPTX_AUX_CH_STA_SUCCESS 0
|
||||
#define DPTX_AUX_CH_STA_NACK 1
|
||||
#define DPTX_AUX_CH_STA_TIMEOUT 2
|
||||
#define DPTX_AUX_CH_STA_UNKNOWN 3
|
||||
#define DPTX_AUX_CH_STA_DEFER 4
|
||||
#define DPTX_AUX_CH_STA_TX_SHORT 5
|
||||
#define DPTX_AUX_CH_STA_RX_SHORT 6
|
||||
#define DPTX_AUX_CH_STA_NACK_W_O_M_ERROR 7
|
||||
#define DPTX_AUX_CH_STA_I2C_NACK_ERROR 8
|
||||
|
||||
#define DPTX_AUX_ERROR_NUM 0x0784
|
||||
|
||||
#define DPTX_AUX_CH_DEFER_CTL 0x0788
|
||||
#define DPTX_AUX_CH_DEFER_CTL_EN (0x1<<7)
|
||||
#define DPTX_AUX_CH_DEFER_CTL_DEFER_COUNT_SHIFT (0)
|
||||
#define DPTX_AUX_CH_DEFER_CTL_DEFER_COUNT_MASK (0x7f)
|
||||
|
||||
#define DPTX_BUFFER_DATA_CTL 0x0790
|
||||
#define DPTX_BUFFER_DATA_CTL_CLR (1<<7)
|
||||
#define DPTX_BUFFER_DATA_CTL_COUNT_MASK (0xf)
|
||||
|
||||
|
||||
#define DPTX_AUX_CH_CTL_1 0x0794
|
||||
#define DPTX_AUX_CH_CTL_1_AUX_LENGTH_MASK (0xf)
|
||||
#define DPTX_AUX_CH_CTL_1_AUX_LENGTH_SHIFT (0x4)
|
||||
#define DPTX_AUX_CH_CTL_1_AUX_TX_COMM_NATIVE (0x1<<3)
|
||||
#define DPTX_AUX_CH_CTL_1_AUX_TX_COMM_MOT (0x1<<2)
|
||||
#define DPTX_AUX_CH_CTL_1_AUX_TX_COMM_WRITE (0x0<<0)
|
||||
#define DPTX_AUX_CH_CTL_1_AUX_TX_COMM_READ (0x1<<0)
|
||||
|
||||
#define DPTX_AUX_ADDR_7_0 0x0798
|
||||
#define DPTX_AUX_ADDR_15_8 0x079C
|
||||
#define DPTX_AUX_ADDR_19_16 0x07A0
|
||||
|
||||
#define DPTX_AUX_CH_CTL_2 0x07A4
|
||||
#define DPTX_AUX_CH_CTL_2_AUX_PN_INVERT (1<<2)
|
||||
#define DPTX_AUX_CH_CTL_2_AUX_ADDR_ONLY (1<<1)
|
||||
#define DPTX_AUX_CH_CTL_2_AUX_EN (1<<0)
|
||||
|
||||
#define DPTX_BUF_DATA_0 0x07C0
|
||||
#define DPTX_BUF_DATA_COUNT 16
|
||||
|
||||
// Registers for SOC Implementation
|
||||
#define DPTX_SOC_GENERAL_CTL 0x0800
|
||||
#define DPTX_SOC_GENERAL_CTL_AUD_M_VALUE_CMP_SPD_MASTER_SHIFT 21
|
||||
#define DPTX_SOC_GENERAL_CTL_AUD_DMA_BURST_SEL_SHIFT 19
|
||||
#define DPTX_SOC_GENERAL_CTL_AUD_BIT_MAP_TYPE_SHIFT 16
|
||||
#define DPTX_SOC_GENERAL_CTL_PCM_SIZE_SHIFT 13
|
||||
#define DPTX_SOC_GENERAL_CTL_AUDIO_MASTER_MODE_EN_SHIFT 9
|
||||
#define DPTX_SOC_GENERAL_CTL_AUDIO_MODE_SHIFT 8
|
||||
#define DPTX_SOC_GENERAL_CTL_AUDIO_CH_STATUS_SAME_SHIFT 5
|
||||
#define DPTX_SOC_GENERAL_CTL_MASTER_VIDEO_INTERLACE_EN_SHIFT 4
|
||||
#define DPTX_SOC_GENERAL_CTL_VIDEO_MASTER_MODE_EN_SHIFT 1
|
||||
#define DPTX_SOC_GENERAL_CTL_VIDEO_MODE_SHIFT 0
|
||||
|
||||
|
||||
#define DPTX_SOC_GENERAL_CTL_AUD_M_VALUE_CMP_SPD_MASTER_MASK (0x3<<DPTX_SOC_GENERAL_CTL_AUD_M_VALUE_CMP_SPD_MASTER_SHIFT)
|
||||
#define DPTX_SOC_GENERAL_CTL_AUD_DMA_BURST_SEL_MASK (0x3<<DPTX_SOC_GENERAL_CTL_AUD_DMA_BURST_SEL_SHIFT)
|
||||
#define DPTX_SOC_GENERAL_CTL_AUD_BIT_MAP_TYPE_MASK (0x3<<DPTX_SOC_GENERAL_CTL_AUD_BIT_MAP_TYPE_SHIFT)
|
||||
#define DPTX_SOC_GENERAL_CTL_PCM_SIZE_MASK (0x3<<DPTX_SOC_GENERAL_CTL_PCM_SIZE_SHIFT)
|
||||
#define DPTX_SOC_GENERAL_CTL_AUDIO_MASTER_MODE_EN_MASK (0x1<<DPTX_SOC_GENERAL_CTL_AUDIO_MASTER_MODE_EN_SHIFT)
|
||||
#define DPTX_SOC_GENERAL_CTL_AUDIO_MODE_MASK (0x1<<DPTX_SOC_GENERAL_CTL_AUDIO_MODE_SHIFT)
|
||||
|
||||
|
||||
#define DPTX_SOC_GENERAL_CTL_AUDIO_CH_STATUS_SAME (0x1<<DPTX_SOC_GENERAL_CTL_AUDIO_CH_STATUS_SAME_SHIFT)
|
||||
#define DPTX_SOC_GENERAL_CTL_MASTER_VIDEO_INTERLACE_EN (0x1<<DPTX_SOC_GENERAL_CTL_MASTER_VIDEO_INTERLACE_EN_SHIFT)
|
||||
#define DPTX_SOC_GENERAL_CTL_VIDEO_MASTER_MODE_EN (0x1<<DPTX_SOC_GENERAL_CTL_VIDEO_MASTER_MODE_EN_SHIFT)
|
||||
#define DPTX_SOC_GENERAL_CTL_VIDEO_MODE (0x1<<DPTX_SOC_GENERAL_CTL_VIDEO_MODE_SHIFT)
|
||||
|
||||
#define DPTX_H_TOTAL_MASTER 0x0804
|
||||
#define DPTX_V_TOTAL_MASTER 0x0808
|
||||
#define DPTX_H_F_PORCH_MASTER 0x080C
|
||||
#define DPTX_H_B_PORCH_MASTER 0x0810
|
||||
#define DPTX_H_ACTIVE_MASTER 0x0814
|
||||
#define DPTX_V_F_PORCH_MASTER 0x0818
|
||||
#define DPTX_V_B_PORCH_MASTER 0x081C
|
||||
#define DPTX_V_ACTIVE_MASTER 0x0820
|
||||
#define DPTX_M_VID_MASTER 0x0824
|
||||
#define DPTX_N_VID_MASTER 0x0828
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_M_AUD_MASTER 0x082C
|
||||
#define DPTX_N_AUD_MASTER 0x0830
|
||||
#define DPTX_MASTER_AUD_BUFFER_CTL 0x0834
|
||||
#define DPTX_BF_P_AUDIO_BUFFER_EMPTY_INT_MASK_SHIFT 16
|
||||
#define DPTX_BF_P_AUDIO_CHANNEL_COUNT_SHIFT 13
|
||||
#define DPTX_BF_P_AUDIO_BUFFER_LEVEL_SHIFT 7
|
||||
#define DPTX_BF_P_AUDIO_BUFFER_THRESHOLD_SHIFT 2
|
||||
#define DPTX_BF_P_AUDIO_BUFFER_EMPTY_INT_SHIFT 1
|
||||
#define DPTX_BF_P_AUDIO_BUFFER_EMPTY_INT_EN_SHIFT 0
|
||||
|
||||
#define DPTX_BF_P_AUDIO_BUFFER_EMPTY_INT_MASK (0x01<<DPTX_BF_P_AUDIO_BUFFER_EMPTY_INT_MASK_SHIFT)
|
||||
#define DPTX_BF_P_AUDIO_CHANNEL_COUNT_MASK (0x07<<DPTX_BF_P_AUDIO_CHANNEL_COUNT_SHIFT)
|
||||
#define DPTX_BF_P_AUDIO_BUFFER_LEVEL_MASK (0x3f<<DPTX_BF_P_AUDIO_BUFFER_LEVEL_SHIFT)
|
||||
#define DPTX_BF_P_AUDIO_BUFFER_THRESHOLD_MASK (0x1f<<DPTX_BF_P_AUDIO_BUFFER_THRESHOLD_SHIFT)
|
||||
#define DPTX_BF_P_AUDIO_BUFFER_EMPTY_INT (0x01<<DPTX_BF_P_AUDIO_BUFFER_EMPTY_INT_SHIFT)
|
||||
#define DPTX_BF_P_AUDIO_BUFFER_EMPTY_INT_EN (0x01<<DPTX_BF_P_AUDIO_BUFFER_EMPTY_INT_EN_SHIFT)
|
||||
|
||||
#define DPTX_MASTER_AUDIO_DATA_FROM_APB 0x0838
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA 0x083C
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH1_SHIFT 0
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH2_SHIFT 4
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH3_SHIFT 8
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH4_SHIFT 12
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH5_SHIFT 16
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH6_SHIFT 20
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH7_SHIFT 24
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH8_SHIFT 28
|
||||
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH1_MASK (0xf<<DPTX_MASTER_AUDIO_PACKET_DATA_CH1_SHIFT)
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH2_MASK (0xf<<DPTX_MASTER_AUDIO_PACKET_DATA_CH2_SHIFT)
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH3_MASK (0xf<<DPTX_MASTER_AUDIO_PACKET_DATA_CH3_SHIFT)
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH4_MASK (0xf<<DPTX_MASTER_AUDIO_PACKET_DATA_CH4_SHIFT)
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH5_MASK (0xf<<DPTX_MASTER_AUDIO_PACKET_DATA_CH5_SHIFT)
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH6_MASK (0xf<<DPTX_MASTER_AUDIO_PACKET_DATA_CH6_SHIFT)
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH7_MASK (0xf<<DPTX_MASTER_AUDIO_PACKET_DATA_CH7_SHIFT)
|
||||
#define DPTX_MASTER_AUDIO_PACKET_DATA_CH8_MASK (0xf<<DPTX_MASTER_AUDIO_PACKET_DATA_CH8_SHIFT)
|
||||
|
||||
#define DPTX_MASTER_AUDIO_GP0_STATUS_0 0x0840
|
||||
#define DPTX_MASTER_AUDIO_GP0_STATUS_1 0x0844
|
||||
#define DPTX_MASTER_AUDIO_GP0_STATUS_2 0x0848
|
||||
#define DPTX_MASTER_AUDIO_GP0_STATUS_3 0x084C
|
||||
#define DPTX_MASTER_AUDIO_GP0_STATUS_4 0x0850
|
||||
#define DPTX_MASTER_AUDIO_GP1_STATUS_0 0x0854
|
||||
#define DPTX_MASTER_AUDIO_GP1_STATUS_1 0x0858
|
||||
#define DPTX_MASTER_AUDIO_GP1_STATUS_2 0x085C
|
||||
#define DPTX_MASTER_AUDIO_GP1_STATUS_3 0x0860
|
||||
#define DPTX_MASTER_AUDIO_GP1_STATUS_4 0x0864
|
||||
|
||||
#define DPTX_MASTER_AUDIO_GP2_STATUS_0 0x0868
|
||||
#define DPTX_MASTER_AUDIO_GP2_STATUS_1 0x086C
|
||||
#define DPTX_MASTER_AUDIO_GP2_STATUS_2 0x0870
|
||||
#define DPTX_MASTER_AUDIO_GP2_STATUS_3 0x0874
|
||||
#define DPTX_MASTER_AUDIO_GP2_STATUS_4 0x0878
|
||||
|
||||
#define DPTX_MASTER_AUDIO_GP3_STATUS_0 0x087C
|
||||
#define DPTX_MASTER_AUDIO_GP3_STATUS_1 0x0880
|
||||
#define DPTX_MASTER_AUDIO_GP3_STATUS_2 0x0884
|
||||
#define DPTX_MASTER_AUDIO_GP3_STATUS_3 0x0888
|
||||
#define DPTX_MASTER_AUDIO_GP3_STATUS_4 0x088C
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_CRC_CON 0x0890
|
||||
#define DPTX_CRC_RESULT 0x0894
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_EFUSE_CON 0x0898
|
||||
#define DPTX_EFUSE_CON_EFUSE_COM (0x1<<0)
|
||||
|
||||
#define DPTX_EFUSE_STATUS 0x089c
|
||||
#define DPTX_EFUSE_STATUS_ECC_FAIL (0x1<<1)
|
||||
#define DPTX_EFUSE_STATUS_EFUSE_BUSY (0x1<<0)
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
#define DPTX_TRAINIG_DEBUG 0x0904
|
||||
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//////////////// version 1+ specific
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define DPTX_SW_RESET 0x0014
|
||||
#define DPTX_SW_RESET_OPERATION (0x1<<0)
|
||||
|
||||
// DPTX_FUNC_EN_1: 0x0018
|
||||
#define DPTX_FUNC_EN_1_MASTER (0x1<<7)
|
||||
#define DPTX_FUNC_EN_1_SLAVE (0x1<<5)
|
||||
#define DPTX_FUNC_EN_1_CRC (0x1<<1)
|
||||
|
||||
// DPTX_INT_STATE: 0x03C0
|
||||
#define DPTX_INT_STATE_1 (0x1<<1)
|
||||
|
||||
|
||||
// DPTX_INT_CTL: 0x03FC
|
||||
#define DPTX_INT_1_POLARITY_HIGH (1<<1)
|
||||
|
||||
// DPTX_DP_TRAINING_PTRN_SET: 0x0688
|
||||
#define DPTX_DP_TRAINING_PTRN_SET_SCRAMBLER_PATTERN_EMBEDDED (1<<9)
|
||||
#define DPTX_DP_TRAINING_PTRN_SET_HW_LINK_TRAINING_PATTERN_EMBEDDED (1<<8)
|
||||
|
||||
// DPTX_SOC_GENERAL_CTL: 0x0800
|
||||
#define DPTX_SOC_GENERAL_CTL_AUDIO_DMA_APB_SEL_SHIFT 3
|
||||
#define DPTX_SOC_GENERAL_CTL_VIDEO_MASTER_CLK_SEL_SHIFT 2
|
||||
|
||||
#define DPTX_SOC_GENERAL_CTL_AUDIO_DMA_APB_SEL (0x1<<DPTX_SOC_GENERAL_CTL_AUDIO_DMA_APB_SEL_SHIFT)
|
||||
#define DPTX_SOC_GENERAL_CTL_VIDEO_MASTER_CLK_SEL (0x1<<DPTX_SOC_GENERAL_CTL_VIDEO_MASTER_CLK_SEL_SHIFT)
|
||||
|
||||
#if DISPLAYPORT_VERSION < 3
|
||||
#define DPTX_COMMON_INT_1_MASK_1 0x08A0
|
||||
#define DPTX_COMMON_INT_1_MASK_2 0x08A4
|
||||
#define DPTX_COMMON_INT_1_MASK_3 0x08A8
|
||||
#define DPTX_COMMON_INT_1_MASK_4 0x08AC
|
||||
|
||||
#define DPTX_DP_INT_1_STA_MASK 0x08B0
|
||||
#endif //DISPLAYPORT_VERSION
|
||||
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//////////////// version 2+ specific
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
|
||||
// DPTX_PLL_FILTER_CTL_2
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH2_AMP_SHIFT (8)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH2_AMP_NEG_120mV (0x0<<DPTX_PLL_FILTER_CTL_2_CH2_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH2_AMP_NEG_80mV (0x1<<DPTX_PLL_FILTER_CTL_2_CH2_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH2_AMP_NEG_40mV (0x2<<DPTX_PLL_FILTER_CTL_2_CH2_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH2_AMP_0mV (0x3<<DPTX_PLL_FILTER_CTL_2_CH2_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH2_AMP_40mV (0x4<<DPTX_PLL_FILTER_CTL_2_CH2_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH2_AMP_80mV (0x5<<DPTX_PLL_FILTER_CTL_2_CH2_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH2_AMP_120mV (0x6<<DPTX_PLL_FILTER_CTL_2_CH2_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH2_AMP_160mV (0x7<<DPTX_PLL_FILTER_CTL_2_CH2_AMP_SHIFT)
|
||||
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH3_AMP_SHIFT (12)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH3_AMP_NEG_120mV (0x0<<DPTX_PLL_FILTER_CTL_2_CH3_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH3_AMP_NEG_80mV (0x1<<DPTX_PLL_FILTER_CTL_2_CH3_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH3_AMP_NEG_40mV (0x2<<DPTX_PLL_FILTER_CTL_2_CH3_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH3_AMP_0mV (0x3<<DPTX_PLL_FILTER_CTL_2_CH3_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH3_AMP_40mV (0x4<<DPTX_PLL_FILTER_CTL_2_CH3_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH3_AMP_80mV (0x5<<DPTX_PLL_FILTER_CTL_2_CH3_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH3_AMP_120mV (0x6<<DPTX_PLL_FILTER_CTL_2_CH3_AMP_SHIFT)
|
||||
#define DPTX_PLL_FILTER_CTL_2_CH3_AMP_160mV (0x7<<DPTX_PLL_FILTER_CTL_2_CH3_AMP_SHIFT)
|
||||
|
||||
#define DPTX_DP_LN2_LINK_TRAINING_CTL 0x0694
|
||||
#define DPTX_DP_LN3_LINK_TRAINING_CTL 0x0698
|
||||
|
||||
// DPTX_DP_PHY
|
||||
#define DPTX_DP_PHY_CH3_PWR_DWN (1<<3)
|
||||
#define DPTX_DP_PHY_CH2_PWR_DWN (1<<2)
|
||||
@@ -0,0 +1,17 @@
|
||||
# Copyright (C) 2009, 2015 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
GLOBAL_INCLUDES +=
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/displayport.o
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
@@ -0,0 +1,131 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/miu.h>
|
||||
#include <platform.h>
|
||||
#include <platform/chipid.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
#include "drex.h"
|
||||
|
||||
#if (TARGET_DREX_CLK_RATIO != 1) && (TARGET_DREX_CLK_RATIO != 2)
|
||||
#error "Invalid TARGET_DREX_CLK_RATIO"
|
||||
#endif
|
||||
|
||||
static u_int32_t calc_sdram_refresh(u_int32_t tREFI, int clock);
|
||||
|
||||
static uint8_t drex_mrr(uint8_t address)
|
||||
{
|
||||
uint32_t cmd_type = 9;
|
||||
uint32_t cmd_addr = ((address >> 6) & 0x3) | ((address & 0x7) << 10);
|
||||
uint32_t cmd_bank = (address >> 3) & 0x7;
|
||||
|
||||
rDIRECTCMD = (cmd_type << 24) | (cmd_bank << 16) | (cmd_addr);
|
||||
spin(2);
|
||||
|
||||
return rMRSTATUS;
|
||||
}
|
||||
|
||||
static void drex_mrw(uint8_t address, uint8_t data)
|
||||
{
|
||||
uint32_t cmd_type = 0;
|
||||
uint32_t cmd_addr = (address >> 6) | (data << 2) | ((address & 0x7) << 10);
|
||||
uint32_t cmd_bank = (address >> 3) & 0x7;
|
||||
|
||||
rDIRECTCMD = (cmd_type << 24) | (cmd_bank << 16) | (cmd_addr);
|
||||
spin(2);
|
||||
}
|
||||
|
||||
int mcu_initialize_dram(bool resume)
|
||||
{
|
||||
#if !SUPPORT_FPGA
|
||||
// Change PhyZQControl.ctrl_zq_mode_dds to 4 for DDR2 400MHz. The default value, 7, is for DDR3 667MHz
|
||||
rPHYZQCONTROL = 0xE3855431;
|
||||
// Set ctrl_start_point and ctrl_inc, enable differential DQS.
|
||||
// Set ctrl_dll_on to activate the PHY DLL
|
||||
rPHYCONTROL0 = (0x10 << 16) | (0x10 << 8) | (0x1 << 3) | (0x1 << 1);
|
||||
// Set ctrl_shiftc = 5 (90 degree shift), ctrl_ref = 8
|
||||
rPHYCONTROL1 = (0x00 << 8) | (0x8 << 4) | 0x5;
|
||||
// Set ctrl_start
|
||||
rPHYCONTROL0 = (0x10 << 16) | (0x10 << 8) | (0x1 << 3) | (0x1 << 1) | 0x1;
|
||||
#endif
|
||||
rCONCONTROL = 0x0FFF30C0 | ((TARGET_DREX_CLK_RATIO - 1) << 1);
|
||||
rMEMCONTROL = 0x00202500;
|
||||
rMEMCONFIG = 0x00F01223;
|
||||
|
||||
// Open page policy for all banks, maximum timeout before closing page
|
||||
rPRECHCONFIG = 0xFF000000;
|
||||
// Maximum timeout for going into self-refresh and dynamic power-down
|
||||
rPWRDNCONFIG = 0xFFFF00FF;
|
||||
|
||||
rTIMINGAREF = TARGET_DREX_TIMING_AREF;
|
||||
rTIMINGROW = TARGET_DREX_TIMING_ROW;
|
||||
rTIMINGDATA = TARGET_DREX_TIMING_DATA;
|
||||
rTIMINGPOWER = TARGET_DREX_TIMING_POWER;
|
||||
|
||||
#if !SUPPORT_FPGA
|
||||
// Wait for ctrl_locked to be set
|
||||
while ((rPHYSTATUS & (1 << 2)) == 0);
|
||||
// Prepare for the Force DLL resynchronization
|
||||
rPHYCONTROL1 = (0x00 << 8) | (0x8 << 4) | (0x0 << 3) | 0x5;
|
||||
// Force DLL resynchronization
|
||||
rPHYCONTROL1 = (0x00 << 8) | (0x8 << 4) | (0x1 << 3) | 0x5;
|
||||
|
||||
// ZQ calibration
|
||||
// zq_start
|
||||
rPHYZQCONTROL |= (1 << 1);
|
||||
// wait for ctrl_zq_end
|
||||
while ((rPHYSTATUS & (1 << 16)) == 0);
|
||||
// fp_resync for ZQ result update
|
||||
rPHYCONTROL1 &= ~(1 << 3);
|
||||
rPHYCONTROL1 |= 1 << 3;
|
||||
rPHYCONTROL1 &= ~(1 << 3);
|
||||
// zq_stop
|
||||
rPHYZQCONTROL &= ~(1 << 1);
|
||||
#else
|
||||
spin(100000);
|
||||
#endif
|
||||
|
||||
// NOP: exit from active/precharge power down or deep power down
|
||||
rDIRECTCMD = 0x07000000;
|
||||
spin(250);
|
||||
|
||||
// MRW63: reset memory devices and do device auto-initialization
|
||||
drex_mrw(63, 0);
|
||||
|
||||
spin(10);
|
||||
|
||||
// RL = 6, WL = 3
|
||||
drex_mrw(2, 4);
|
||||
|
||||
// Drive strength 48-ohm typical
|
||||
drex_mrw(3, 3);
|
||||
|
||||
// Turn on auto-refresh counter
|
||||
rCONCONTROL |= (1 << 5);
|
||||
|
||||
// Tunables for QoS, see radar 11065185
|
||||
rQOSTMDREX = TARGET_DREX_QOS_TIDEMARK;
|
||||
rQOSACDREX = TARGET_DREX_QOS_ACCESS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mcu_adjust_performance(void)
|
||||
{
|
||||
}
|
||||
|
||||
uint64_t mcu_get_memory_size(void)
|
||||
{
|
||||
return chipid_get_memory_density() * chipid_get_memory_ranks() * (chipid_get_memory_width() / 32);
|
||||
}
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_DREX_H
|
||||
#define __SAMSUNG_DREX_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rCONCONTROL (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x000))
|
||||
#define rMEMCONTROL (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x004))
|
||||
#define rMEMCONFIG (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x008))
|
||||
#define rDIRECTCMD (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x010))
|
||||
#define rPRECHCONFIG (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x014))
|
||||
#define rPHYCONTROL0 (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x018))
|
||||
#define rPHYCONTROL1 (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x01C))
|
||||
#define rPHYCONTROL2 (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x020))
|
||||
#define rPHYCONTROL3 (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x024))
|
||||
#define rPWRDNCONFIG (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x028))
|
||||
#define rTIMINGPZQ (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x02C))
|
||||
#define rTIMINGAREF (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x030))
|
||||
#define rTIMINGROW (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x034))
|
||||
#define rTIMINGDATA (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x038))
|
||||
#define rTIMINGPOWER (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x03C))
|
||||
#define rPHYSTATUS (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x040))
|
||||
#define rPHYZQCONTROL (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x044))
|
||||
#define rCHIP0STATUS (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x048))
|
||||
#define rCHIP1STATUS (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x04C))
|
||||
#define rAREFSTATUS (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x050))
|
||||
#define rMRSTATUS (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x054))
|
||||
|
||||
#define rQOSTMDREX (*(volatile u_int32_t *)(AXI_SPINE_BASE_ADDR + 0x400))
|
||||
#define rQOSACDREX (*(volatile u_int32_t *)(AXI_SPINE_BASE_ADDR + 0x404))
|
||||
|
||||
#endif /* ! __SAMSUNG_DREX_H */
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2011 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_DREX=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/drex.o
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <platform.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
#include "dwi.h"
|
||||
|
||||
#ifndef TARGET_DWI_FREQUENCY
|
||||
#error TARGET_DWI_FREQUENCY not defined by the target
|
||||
#endif
|
||||
|
||||
#ifndef TARGET_DWI_TRANSFER_GAP_US
|
||||
#error TARGET_DWI_TRANSFER_GAP_US not defined by the target
|
||||
#endif
|
||||
|
||||
int dwi_init(void)
|
||||
{
|
||||
u_int32_t dwi_divider, dwi_transfer_gap;
|
||||
|
||||
clock_gate(CLK_DWI, true);
|
||||
|
||||
dwi_divider = (clock_get_frequency(CLK_NCLK) + TARGET_DWI_FREQUENCY - 1) / TARGET_DWI_FREQUENCY;
|
||||
dwi_transfer_gap = (clock_get_frequency(CLK_NCLK) * TARGET_DWI_TRANSFER_GAP_US) / 1000000;
|
||||
|
||||
rDWI_CLOCK_CONFIG = DWI_CLOCK_CONFIG_CLOCK_SCALER(dwi_divider) | DWI_CLOCK_CONFIG_TX_CPHA_1;
|
||||
rDWI_TRANSFER_GAP = dwi_transfer_gap;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dwi_send_backlight_command(uint32_t backlight_command, uint32_t backlight_level)
|
||||
{
|
||||
rDWI_ITR0_TX_DATA = (backlight_command << 28) | (backlight_level & 0x7FF);
|
||||
rDWI_ITR0_CONTROL = DWI_TR_CTRL_BYTE_SWAP | DWI_TR_CTRL_BYTE_CNT(4) | DWI_TR_CTRL_TRAN_EN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_DWI_H
|
||||
#define __SAMSUNG_DWI_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rDWI_CLOCK_CONFIG (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0000))
|
||||
#define DWI_CLOCK_CONFIG_TX_CPHA_1 (1 << 0)
|
||||
#define DWI_CLOCK_CONFIG_TX_CPHA_2 (0 << 0)
|
||||
#define DWI_CLOCK_CONFIG_RX_CPHA_1 (1 << 1)
|
||||
#define DWI_CLOCK_CONFIG_RX_CPHA_2 (0 << 1)
|
||||
#define DWI_CLOCK_CONFIG_CPOL_LOW (0 << 2)
|
||||
#define DWI_CLOCK_CONFIG_CPOL_HIGH (1 << 2)
|
||||
#define DWI_CLOCK_CONFIG_CLOCK_SCALER(_x) (((_x) - 1) << 16)
|
||||
#define rDWI_TRANSFER_GAP (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0004))
|
||||
#define rDWI_ITR0_CONTROL (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0010))
|
||||
#define DWI_TR_CTRL_TRAN_EN (1 << 0)
|
||||
#define DWI_TR_CTRL_BYTE_CNT(_c) (((_c) - 1) << 4)
|
||||
#define DWI_TR_CTRL_BYTE_SWAP (1 << 6)
|
||||
#define DWI_TR_CTRL_BIT_ORDER (1 << 7)
|
||||
#define DWI_TR_CTRL_INT_EN (1 << 8)
|
||||
#define rDWI_ITR0_TX_DATA (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0014))
|
||||
#define rDWI_ITR0_RX_DATA (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0018))
|
||||
#define rDWI_ITR0_INT_STATUS (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x001C))
|
||||
#define rDWI_ITR1_CONTROL (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0020))
|
||||
#define rDWI_ITR1_TX_DATA (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0024))
|
||||
#define rDWI_ITR1_RX_DATA (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0028))
|
||||
#define rDWI_ITR1_INT_STATUS (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x002C))
|
||||
#define rDWI_ITR1_RAMP_COUNT (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0030))
|
||||
#define rDWI_ITR1_DELTAV_ACTIVE (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0034))
|
||||
#define rDWI_STR_CONTROL (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0040))
|
||||
#define rDWI_STR_TX_DATA (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0044))
|
||||
#define rDWI_STR_RX_DATA (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0048))
|
||||
#define rDWI_STR_INT_STATUS (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x004C))
|
||||
#define rDWI_STR_DELAY (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0050))
|
||||
#define rDWI_VERSION (*(volatile u_int32_t *)(DWI_BASE_ADDR + 0x0070))
|
||||
|
||||
#endif /* ! __SAMSUNG_DWI_H */
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2011 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_DWI=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/dwi.o
|
||||
@@ -0,0 +1,209 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/spi.h>
|
||||
#include <platform.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#include "gpio.h"
|
||||
|
||||
#if WITH_TARGET_CONFIG
|
||||
# include <target/pinconfig.h>
|
||||
#else
|
||||
# include <platform/pinconfig.h>
|
||||
#endif
|
||||
|
||||
u_int32_t gpio_read(gpio_t gpio)
|
||||
{
|
||||
int pad = GPIO2PAD(gpio);
|
||||
int pin = GPIO2PIN(gpio);
|
||||
|
||||
#if WITH_HW_SPI && defined(GPIO_PAD_SPI)
|
||||
if (pad == GPIO_PAD_SPI) return spi_gpio_read(pin);
|
||||
#endif
|
||||
|
||||
return (rPDATn(pad) & (1<<pin)) ? 1UL : 0UL;
|
||||
}
|
||||
|
||||
void gpio_write(gpio_t gpio, u_int32_t val)
|
||||
{
|
||||
int pad = GPIO2PAD(gpio);
|
||||
int pin = GPIO2PIN(gpio);
|
||||
|
||||
#if WITH_HW_SPI && defined(GPIO_PAD_SPI)
|
||||
if (pad == GPIO_PAD_SPI) {
|
||||
spi_gpio_write(pin, val);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
rFSEL = (pad << 16) | (pin << 8) | (val ? PCON_OUT_1 : PCON_OUT_0);
|
||||
}
|
||||
|
||||
static const int gpio_config_map[GPIO_CFG_MAX] = {
|
||||
[GPIO_CFG_IN] = PCON_IN,
|
||||
[GPIO_CFG_OUT] = PCON_OUT,
|
||||
[GPIO_CFG_OUT_0] = PCON_OUT_0,
|
||||
[GPIO_CFG_OUT_1] = PCON_OUT_1,
|
||||
[GPIO_CFG_FUNC(0)] = PCON_FUNC2,
|
||||
[GPIO_CFG_FUNC(1)] = PCON_FUNC3,
|
||||
[GPIO_CFG_FUNC(2)] = PCON_FUNC4,
|
||||
[GPIO_CFG_FUNC(3)] = PCON_FUNC5
|
||||
};
|
||||
|
||||
void gpio_configure(gpio_t gpio, u_int32_t config)
|
||||
{
|
||||
int pad = GPIO2PAD(gpio);
|
||||
int pin = GPIO2PIN(gpio);
|
||||
int func;
|
||||
|
||||
#if WITH_HW_SPI && defined(GPIO_PAD_SPI)
|
||||
if (pad == GPIO_PAD_SPI) {
|
||||
spi_gpio_configure(pin, config);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (config > GPIO_CFG_MAX) return;
|
||||
|
||||
if (config == GPIO_CFG_DFLT) {
|
||||
func = (gpio_default_config[pad].pcon >> (pin * 4)) & 0xF;
|
||||
} else {
|
||||
func = gpio_config_map[config];
|
||||
}
|
||||
|
||||
if (func == PCON_DISABLE) {
|
||||
rPPIEn(pad) &= ~(1 << pin);
|
||||
rFSEL = (pad << 16) | (pin << 8) | PCON_IN;
|
||||
} else {
|
||||
rFSEL = (pad << 16) | (pin << 8) | func;
|
||||
rPPIEn(pad) |= (1 << pin);
|
||||
}
|
||||
|
||||
/* Once we reconfigure, reset the pullup/pulldown to default. This could cause
|
||||
a glitch on outputs, but will avoid spurious transitions on inputs. We're
|
||||
between a rock and a hard place because of the GPIO block's design. */
|
||||
if (config == GPIO_CFG_DFLT) {
|
||||
uint16_t pupdn = gpio_default_config[pad].pupdn;
|
||||
uint16_t pullup = pupdn & (1 << pin);
|
||||
uint16_t pulldown = (pupdn >> 8) & (1 << pin);
|
||||
|
||||
if ((pullup != 0) && (pulldown != 0)) {
|
||||
panic("Pullup and pulldown at same time on GPIO 0x%x", gpio);
|
||||
} else if (pullup != 0) {
|
||||
rPPURn(pad) |= (1 << pin);
|
||||
rPPDRn(pad) &= ~(1 << pin);
|
||||
} else if (pulldown != 0) {
|
||||
rPPURn(pad) &= ~(1 << pin);
|
||||
rPPDRn(pad) |= (1 << pin);
|
||||
} else {
|
||||
rPPURn(pad) &= ~(1 << pin);
|
||||
rPPDRn(pad) &= ~(1 << pin);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_configure_pupdn(gpio_t gpio, int32_t pupdn)
|
||||
{
|
||||
int pad = GPIO2PAD(gpio);
|
||||
int pin = 1 << GPIO2PIN(gpio);
|
||||
|
||||
if (pupdn < GPIO_NO_PUPDN) {
|
||||
/* GPIO_PDN */
|
||||
rPPURn(pad) &= ~pin;
|
||||
rPPDRn(pad) |= pin;
|
||||
} else if (pupdn > GPIO_NO_PUPDN) {
|
||||
/* GPIO_PUP */
|
||||
rPPURn(pad) |= pin;
|
||||
rPPDRn(pad) &= ~pin;
|
||||
} else {
|
||||
/* GPIO_NO_PUPDN */
|
||||
rPPURn(pad) &= ~pin;
|
||||
rPPDRn(pad) &= ~pin;
|
||||
}
|
||||
}
|
||||
|
||||
int gpio_init_pinconfig(void)
|
||||
{
|
||||
int pad;
|
||||
int pin;
|
||||
|
||||
dprintf(DEBUG_SPEW, "gpio_init_pinconfig()\n");
|
||||
|
||||
/* XXX is there a safe way to set the pullup/pulldown config and set the pin modes? */
|
||||
|
||||
/*
|
||||
* since most of these pins are probably going to default to input coming out of the
|
||||
* boot rom, we'll set the pullup/pulldown first
|
||||
*/
|
||||
|
||||
/* load the default pullup/pulldown configuration, disallowing
|
||||
the pullup and pulldown to be set at the same time */
|
||||
for (pad = 0; pad < GPIO_GROUP_COUNT; pad++) {
|
||||
uint32_t pullup;
|
||||
uint32_t pulldown;
|
||||
uint16_t pupdn;
|
||||
|
||||
pupdn = gpio_default_config[pad].pupdn;
|
||||
pullup = pupdn & 0xFF;
|
||||
pulldown = (pupdn >> 8) & 0xFF;
|
||||
if ((pullup & pulldown) != 0)
|
||||
panic("Pullup and pulldown conflict on pins 0x%x of pad %d", pullup & pulldown, pad);
|
||||
rPPURn(pad) = pullup;
|
||||
rPPDRn(pad) = pulldown;
|
||||
}
|
||||
|
||||
/* load the default PCON values, which should also set initial PDATs for gpio out */
|
||||
for (pad = 0; pad < GPIO_GROUP_COUNT; pad++)
|
||||
{
|
||||
uint32_t pcon;
|
||||
uint32_t ppie;
|
||||
ppie = 0xFF;
|
||||
pcon = gpio_default_config[pad].pcon;
|
||||
|
||||
for (pin = 0; pin < 8; pin++) {
|
||||
if (((pcon >> (pin * 4)) & 0xF) == PCON_DISABLE) {
|
||||
pcon &= ~(0xF << (pin * 4));
|
||||
ppie &= ~(1 << pin);
|
||||
}
|
||||
}
|
||||
rPCONn(pad) = pcon;
|
||||
rPPIEn(pad) = ppie;
|
||||
}
|
||||
|
||||
#ifdef DEFAULT_ODEN
|
||||
/* set port configuration for I2Cx and TWC */
|
||||
rODEN = DEFAULT_ODEN;
|
||||
#endif
|
||||
|
||||
#if defined(DEFAULT_DSTR0)
|
||||
/* set the chip default drive strength */
|
||||
rDSTR0 = DEFAULT_DSTR0;
|
||||
#endif
|
||||
|
||||
#ifdef DEFAULT_OSC_DSTR
|
||||
/* set oscillator drive strength */
|
||||
rOSC_DSTR = DEFAULT_OSC_DSTR;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if APPLICATION_IBOOT
|
||||
|
||||
int gpio_diag_pinconfig(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* APPLICATION_IBOOT */
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __SAMSUNG_GPIO_H
|
||||
#define __SAMSUNG_GPIO_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
|
||||
/* Register Offsets for Samsung GPIOs */
|
||||
#define rPCONn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x000 + (n) * 0x20))
|
||||
#define rPDATn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x004 + (n) * 0x20))
|
||||
#define rPCTLn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x008 + (n) * 0x20))
|
||||
#define rPPURn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x00C + (n) * 0x20))
|
||||
#define rPPDRn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x010 + (n) * 0x20))
|
||||
#define rPPIEn(n) (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x014 + (n) * 0x20))
|
||||
|
||||
#define rFSEL (*(volatile u_int32_t *)(GPIO_BASE_ADDR + GPIO_FSEL_OFFSET))
|
||||
|
||||
#define rDSTR0 (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x380))
|
||||
#define rOSC_DSTR (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x388))
|
||||
|
||||
#define rODEN (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x3C0))
|
||||
#define rEMAC0 (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x3C4))
|
||||
#define rEMAC1 (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x3C8))
|
||||
#define rEMAC2 (*(volatile u_int32_t *)(GPIO_BASE_ADDR + 0x3CC))
|
||||
|
||||
|
||||
/* Base Pin Defines for Samsung GPIOs */
|
||||
#define PORT(port, pin) ((u_int32_t)((port) << 8) | pin)
|
||||
#define GPIO2PIN(gpio) ((gpio) & 0x7)
|
||||
#define GPIO2PAD(gpio) (((gpio) >> 8) & 0x1f)
|
||||
|
||||
/* Precomputes the PCON register's value */
|
||||
#define PCON(pinfunc0, pinfunc1, pinfunc2, pinfunc3, pinfunc4, pinfunc5, pinfunc6, pinfunc7) \
|
||||
((u_int32_t)(((pinfunc0) << 0) | ((pinfunc1) << 4) | ((pinfunc2) << 8) | ((pinfunc3) << 12) | \
|
||||
((pinfunc4) << 16) | ((pinfunc5) << 20) | ((pinfunc6) << 24) | ((pinfunc7) << 28)))
|
||||
|
||||
/* some PCON constants */
|
||||
enum {
|
||||
PCON_IN = 0,
|
||||
PCON_OUT = 1,
|
||||
PCON_FUNC2 = 2,
|
||||
PCON_FUNC3 = 3,
|
||||
PCON_FUNC4 = 4,
|
||||
PCON_FUNC5 = 5,
|
||||
PCON_FUNC6 = 6,
|
||||
|
||||
PCON_DISABLE = 0xd, /* not actually supported by the hardware, implies PCON_IN
|
||||
and input enable disabled */
|
||||
PCON_OUT_0 = 0xe, /* same as PCON_OUT, but also sets PDAT to zero */
|
||||
PCON_OUT_1 = 0xf /* same as PCON_OUT, but also sets PDAT to one */
|
||||
};
|
||||
|
||||
/* pull up/down configuration */
|
||||
enum {
|
||||
NO_PUPDN = 0,
|
||||
PUP = (1 << 0),
|
||||
PDN = (1 << 8)
|
||||
};
|
||||
|
||||
#define PUPDN(pinupdn0, pinupdn1, pinupdn2, pinupdn3, pinupdn4, pinupdn5, pinupdn6, pinupdn7) \
|
||||
((uint16_t)(((pinupdn0) << 0) | ((pinupdn1) << 1) | ((pinupdn2) << 2) | ((pinupdn3) << 3) | \
|
||||
((pinupdn4) << 4) | ((pinupdn5) << 5) | ((pinupdn6) << 6) | ((pinupdn7) << 7)))
|
||||
|
||||
struct gpio_default_config {
|
||||
uint32_t pcon;
|
||||
uint16_t pupdn;
|
||||
};
|
||||
|
||||
#define PINCONFIG(pcon0, pupdn0, pcon1, pupdn1, pcon2, pupdn2, pcon3, pupdn3, \
|
||||
pcon4, pupdn4, pcon5, pupdn5, pcon6, pupdn6, pcon7, pupdn7) \
|
||||
{ .pcon = PCON(pcon0, pcon1, pcon2, pcon3, pcon4, pcon5, pcon6, pcon7), \
|
||||
.pupdn = PUPDN(pupdn0, pupdn1, pupdn2, pupdn3, pupdn4, pupdn5, pupdn6, pupdn7) \
|
||||
}
|
||||
|
||||
#endif /* __SAMSUNG_GPIO_H */
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_GPIO=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/gpio.o
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef HDMI_H
|
||||
#define HDMI_H 1
|
||||
typedef enum {
|
||||
kPHYConfigReg00, //HDMIPHYCON0
|
||||
kPHYConfigReg01, //HDMIPHYCON0
|
||||
kPHYConfigReg02, //HDMIPHYCON0
|
||||
kPHYConfigReg03, //HDMIPHYCON0
|
||||
kPHYConfigReg04, //HDMIPHYCON1
|
||||
kPHYConfigReg05, //HDMIPHYCON1
|
||||
kPHYConfigReg06, //HDMIPHYCON1
|
||||
kPHYConfigReg07, //HDMIPHYCON1
|
||||
kPHYConfigReg08, //HDMIPHYCON2
|
||||
kPHYConfigReg09, //HDMIPHYCON2
|
||||
kPHYConfigReg0a, //HDMIPHYCON2
|
||||
kPHYConfigReg0b, //HDMIPHYCON2
|
||||
kPHYConfigReg0c, //HDMIPHYCON3
|
||||
kPHYConfigReg0d, //HDMIPHYCON3
|
||||
kPHYConfigReg0e, //HDMIPHYCON3
|
||||
kPHYConfigReg0f, //HDMIPHYCON3
|
||||
kPHYConfigReg10, //HDMIPHYCON4
|
||||
kPHYConfigReg11, //HDMIPHYCON4
|
||||
kPHYConfigReg12, //HDMIPHYCON4
|
||||
kPHYConfigReg13, //HDMIPHYCON4
|
||||
kPHYConfigReg14, //HDMIPHYCON5
|
||||
kPHYConfigReg15, //HDMIPHYCON5
|
||||
kPHYConfigReg16, //HDMIPHYCON5
|
||||
kPHYConfigReg17, //HDMIPHYCON5
|
||||
kPHYConfigReg18, //HDMIPHYCON6
|
||||
kPHYConfigReg19, //HDMIPHYCON6
|
||||
kPHYConfigReg1a, //HDMIPHYCON6
|
||||
kPHYConfigReg1b, //HDMIPHYCON6
|
||||
kPHYConfigReg1c, //HDMIPHYCON7
|
||||
kPHYConfigReg1d, //HDMIPHYCON7
|
||||
kPHYConfigReg1e, //HDMIPHYCON7
|
||||
kPHYConfigRegRSVD, //HDMIPHYCON7
|
||||
kPHYConfigRegCount, // count excludes the mode set control register
|
||||
kPHYConfigRegModeSet = 0x1f, //HDMIPHYCON8
|
||||
} PHYConfigReg;
|
||||
|
||||
typedef uint8_t HDMITXPHYConfig[30];
|
||||
|
||||
typedef enum HDMITXPHYConfigDepth {
|
||||
kHDMITXPHYConfigDepth8,
|
||||
kHDMITXPHYConfigDepth10,
|
||||
kHDMITXPHYConfigDepth12,
|
||||
kHDMITXPHYConfigDepthCount
|
||||
} HDMITXPHYConfigDepth;
|
||||
|
||||
typedef struct {
|
||||
HDMITXPHYConfig data;
|
||||
uint8_t pad; // Align to multiple of 4 bytes for device tree alignment
|
||||
uint8_t invalid; // If nonzero, entry is invalid
|
||||
} HDMITXPHYConfigDepthTableEntry;
|
||||
|
||||
typedef struct HDMITXPHYConfigTableEntry {
|
||||
uint32_t pixelClockHz; // target pixel clock
|
||||
HDMITXPHYConfigDepthTableEntry depth[kHDMITXPHYConfigDepthCount];
|
||||
} AppleSamsungHDMITXPHYConfigTableEntry;
|
||||
#endif
|
||||
@@ -0,0 +1,919 @@
|
||||
#include <sys.h>
|
||||
#include "hdmi.h"
|
||||
|
||||
// HDMI PHY configuration table - auto-generated by deviceTreePHYConfigGenerator - do not edit
|
||||
// deviceTreePHYConfigGenerator -i hdmi_static_config -V 1.4 --depth-limit=8 --data-amplitude=0xf --clock-amplitude=16 --slew-rate-control=0 -C --tmds-min=148.5 --data-amplitude=0x1d
|
||||
AppleSamsungHDMITXPHYConfigTableEntry hdmi_static_config[101] = {
|
||||
// 0: 23.750 MHz
|
||||
{
|
||||
0x016a6570, // 23750000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x28, 0x71, 0x40, 0x30, 0xd8, 0x00, 0x80, 0x80, 0xee, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x03, 0x25, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 1: 23.856 MHz
|
||||
{
|
||||
0x016c0380, // 23856000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x28, 0x71, 0x40, 0x4b, 0xdc, 0x00, 0x80, 0x80, 0xef, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x02, 0x25, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 2: 25.175 MHz
|
||||
{
|
||||
0x018023d8, // 25175000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2a, 0x72, 0x40, 0x30, 0xfc, 0x04, 0x83, 0xa0, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 3: 25.200 MHz
|
||||
{
|
||||
0x01808580, // 25200000 Hz
|
||||
{
|
||||
{ { 0x51, 0x2a, 0x70, 0x40, 0x00, 0x00, 0x00, 0x80, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 4: 26.976 MHz
|
||||
{
|
||||
0x019b9d20, // 26975520 Hz
|
||||
{
|
||||
{ { 0xd4, 0x87, 0x56, 0x40, 0x60, 0xd1, 0x10, 0x09, 0xa0, 0xca, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 5: 27.000 MHz
|
||||
{
|
||||
0x019bfcc0, // 27000000 Hz
|
||||
{
|
||||
{ { 0x51, 0x2d, 0x70, 0x40, 0x00, 0x00, 0x00, 0x80, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 6: 27.027 MHz
|
||||
{
|
||||
0x019c6638, // 27027000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x09, 0x08, 0x83, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 7: 29.201 MHz
|
||||
{
|
||||
0x01bd9268, // 29201000 Hz
|
||||
{
|
||||
{ { 0xd4, 0xc3, 0x74, 0x40, 0x4b, 0xcf, 0x20, 0x1d, 0xa0, 0x24, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xd2, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 8: 29.250 MHz
|
||||
{
|
||||
0x01be51d0, // 29250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x31, 0x74, 0x40, 0x20, 0xf0, 0x08, 0x87, 0xa0, 0x25, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xd2, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 9: 30.722 MHz
|
||||
{
|
||||
0x01d4c7d0, // 30722000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x33, 0x74, 0x40, 0x4b, 0x3d, 0x08, 0x45, 0xa0, 0x33, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xc8, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 10: 30.750 MHz
|
||||
{
|
||||
0x01d53530, // 30750000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x33, 0x74, 0x40, 0x20, 0x10, 0x08, 0x85, 0xa0, 0x34, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xc8, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 11: 31.500 MHz
|
||||
{
|
||||
0x01e0a6e0, // 31500000 Hz
|
||||
{
|
||||
{ { 0x52, 0x69, 0x70, 0x40, 0x00, 0x00, 0x00, 0x80, 0x80, 0x3b, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xc3, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 12: 33.750 MHz
|
||||
{
|
||||
0x0202fbf0, // 33750000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x38, 0x74, 0x40, 0x20, 0x10, 0x00, 0x80, 0x80, 0x52, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xb6, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 13: 35.000 MHz
|
||||
{
|
||||
0x02160ec0, // 35000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3a, 0x75, 0x40, 0x30, 0x20, 0x04, 0x83, 0xa0, 0x5e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xb0, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 14: 35.500 MHz
|
||||
{
|
||||
0x021dafe0, // 35500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3b, 0x75, 0x40, 0x30, 0x10, 0x08, 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xad, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 15: 35.714 MHz
|
||||
{
|
||||
0x0220f3d0, // 35714000 Hz
|
||||
{
|
||||
{ { 0xd2, 0x77, 0x75, 0x40, 0x4b, 0x07, 0x10, 0x49, 0xa0, 0x65, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xac, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 16: 36.000 MHz
|
||||
{
|
||||
0x02255100, // 36000000 Hz
|
||||
{
|
||||
{ { 0x51, 0x3c, 0x70, 0x40, 0x00, 0x00, 0x00, 0x80, 0x80, 0x68, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 17: 38.216 MHz
|
||||
{
|
||||
0x02472140, // 38216000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x30, 0x52, 0x40, 0x64, 0xd2, 0x00, 0x80, 0x80, 0x1f, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa1, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 18: 38.250 MHz
|
||||
{
|
||||
0x0247a610, // 38250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x30, 0x52, 0x40, 0x20, 0xf4, 0x00, 0x80, 0x80, 0x1f, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa1, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 19: 40.000 MHz
|
||||
{
|
||||
0x02625a00, // 40000000 Hz
|
||||
{
|
||||
{ { 0x51, 0x32, 0x50, 0x40, 0x00, 0x00, 0x00, 0x80, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 20: 48.906 MHz
|
||||
{
|
||||
0x02ea3f10, // 48906000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3d, 0x55, 0x40, 0x64, 0x35, 0x08, 0x43, 0xa0, 0x6f, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xfb, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 21: 49.000 MHz
|
||||
{
|
||||
0x02ebae40, // 49000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3d, 0x55, 0x40, 0x20, 0x10, 0x08, 0x83, 0xa0, 0x70, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xfb, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 22: 49.500 MHz
|
||||
{
|
||||
0x02f34f60, // 49500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3e, 0x55, 0x40, 0x20, 0xf8, 0x04, 0x81, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xf8, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 23: 50.000 MHz
|
||||
{
|
||||
0x02faf080, // 50000000 Hz
|
||||
{
|
||||
{ { 0x52, 0x7d, 0x50, 0x40, 0x00, 0x00, 0x00, 0x80, 0x80, 0x77, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xf6, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 24: 53.951 MHz
|
||||
{
|
||||
0x03373a40, // 53951040 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2d, 0x35, 0x40, 0x78, 0xf3, 0x02, 0x81, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe4, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 25: 54.000 MHz
|
||||
{
|
||||
0x0337f980, // 54000000 Hz
|
||||
{
|
||||
{ { 0x51, 0x2d, 0x30, 0x40, 0x00, 0x00, 0x00, 0x80, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe4, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 26: 54.054 MHz
|
||||
{
|
||||
0x0338cc70, // 54054000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2d, 0x32, 0x40, 0x64, 0x09, 0x08, 0x83, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe3, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 27: 56.250 MHz
|
||||
{
|
||||
0x035a4e90, // 56250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2f, 0x32, 0x40, 0x20, 0xf8, 0x08, 0x81, 0xa0, 0x19, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xda, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 28: 56.549 MHz
|
||||
{
|
||||
0x035ede88, // 56549000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2f, 0x32, 0x40, 0x7f, 0x3f, 0x08, 0x41, 0xa0, 0x1b, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xd9, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 29: 56.750 MHz
|
||||
{
|
||||
0x0361efb0, // 56750000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2f, 0x32, 0x40, 0x30, 0x1c, 0x08, 0x81, 0xa0, 0x1c, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xd9, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 30: 63.500 MHz
|
||||
{
|
||||
0x03c8eee0, // 63500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x35, 0x34, 0x40, 0x30, 0xf8, 0x08, 0x83, 0xa0, 0x3e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xc2, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 31: 64.109 MHz
|
||||
{
|
||||
0x03d239c7, // 64108999 Hz
|
||||
{
|
||||
{ { 0xd2, 0x6b, 0x34, 0x40, 0x7f, 0xb3, 0x10, 0x05, 0xa0, 0x41, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xc0, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 32: 65.000 MHz
|
||||
{
|
||||
0x03dfd240, // 65000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x36, 0x34, 0x40, 0x30, 0x10, 0x04, 0x81, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 33: 68.250 MHz
|
||||
{
|
||||
0x04116990, // 68250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x39, 0x35, 0x40, 0x20, 0xf8, 0x08, 0x87, 0xa0, 0x55, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xb4, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 34: 71.000 MHz
|
||||
{
|
||||
0x043b5fc0, // 71000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3b, 0x35, 0x40, 0x30, 0x10, 0x08, 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 35: 72.000 MHz
|
||||
{
|
||||
0x044aa200, // 72000000 Hz
|
||||
{
|
||||
{ { 0x51, 0x3c, 0x30, 0x40, 0x00, 0x00, 0x00, 0x80, 0x80, 0x68, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xab, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 36: 73.250 MHz
|
||||
{
|
||||
0x045db4d0, // 73250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3d, 0x35, 0x40, 0x30, 0x04, 0x08, 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 37: 74.250 MHz
|
||||
{
|
||||
0x046cf710, // 74250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3e, 0x35, 0x40, 0x20, 0xf8, 0x04, 0x81, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 38: 74.481 MHz
|
||||
{
|
||||
0x04707d68, // 74481000 Hz
|
||||
{
|
||||
{ { 0xd3, 0xba, 0x35, 0x40, 0x64, 0x1b, 0x04, 0x41, 0xa0, 0x74, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 39: 74.500 MHz
|
||||
{
|
||||
0x0470c7a0, // 74500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3e, 0x35, 0x40, 0x30, 0x08, 0x04, 0x81, 0xa0, 0x75, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 40: 75.000 MHz
|
||||
{
|
||||
0x047868c0, // 75000000 Hz
|
||||
{
|
||||
{ { 0x52, 0x7d, 0x30, 0x40, 0x00, 0x00, 0x00, 0x80, 0x80, 0x77, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa4, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 41: 78.750 MHz
|
||||
{
|
||||
0x04b1a130, // 78750000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x21, 0x11, 0x40, 0x20, 0xf4, 0x08, 0x87, 0xa0, 0xc5, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x9c, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 42: 79.500 MHz
|
||||
{
|
||||
0x04bd12e0, // 79500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x21, 0x11, 0x40, 0x20, 0x08, 0x08, 0x87, 0xa0, 0xc7, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x9b, 0x24, 0x01, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 43: 80.136 MHz
|
||||
{
|
||||
0x04c6c740, // 80136000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x21, 0x11, 0x40, 0x64, 0x4e, 0x08, 0x87, 0xa0, 0xc8, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x33, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 44: 81.804 MHz
|
||||
{
|
||||
0x04e03ae0, // 81804000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x22, 0x11, 0x40, 0x64, 0x11, 0x04, 0x83, 0xa0, 0xcd, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x2c, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 45: 82.000 MHz
|
||||
{
|
||||
0x04e33880, // 82000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x22, 0x11, 0x40, 0x30, 0x10, 0x04, 0x83, 0xa0, 0xcd, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x2c, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 46: 83.462 MHz
|
||||
{
|
||||
0x04f98770, // 83462000 Hz
|
||||
{
|
||||
{ { 0xd4, 0x8b, 0x16, 0x40, 0x4b, 0x1f, 0x10, 0x05, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x26, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 47: 83.500 MHz
|
||||
{
|
||||
0x04fa1be0, // 83500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x23, 0x11, 0x40, 0x30, 0xec, 0x08, 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x26, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 48: 84.715 MHz
|
||||
{
|
||||
0x050ca5f8, // 84715000 Hz
|
||||
{
|
||||
{ { 0xd2, 0x47, 0x16, 0x40, 0x78, 0x9f, 0x08, 0x81, 0xa0, 0xd4, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x22, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 49: 84.750 MHz
|
||||
{
|
||||
0x050d2eb0, // 84750000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x23, 0x11, 0x40, 0x20, 0x14, 0x08, 0x85, 0xa0, 0xd4, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x22, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 50: 85.500 MHz
|
||||
{
|
||||
0x0518a060, // 85500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x24, 0x11, 0x40, 0x20, 0xe8, 0x02, 0x81, 0xa0, 0xd6, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x1f, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 51: 85.860 MHz
|
||||
{
|
||||
0x051e1ea0, // 85860000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x24, 0x11, 0x40, 0x3c, 0xe5, 0x02, 0x81, 0xa0, 0xd7, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x1e, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 52: 88.750 MHz
|
||||
{
|
||||
0x054a37b0, // 88750000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x25, 0x11, 0x40, 0x30, 0xfe, 0x08, 0x83, 0xa0, 0xde, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x15, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 53: 94.387 MHz
|
||||
{
|
||||
0x05a03b38, // 94387000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x27, 0x14, 0x40, 0x7f, 0x6f, 0x02, 0x81, 0xa0, 0xec, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x04, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 54: 94.500 MHz
|
||||
{
|
||||
0x05a1f4a0, // 94500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x27, 0x11, 0x40, 0x20, 0x18, 0x08, 0x81, 0xa0, 0xec, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x04, 0x25, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 55: 101.000 MHz
|
||||
{
|
||||
0x06052340, // 101000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2a, 0x12, 0x40, 0x30, 0x08, 0x04, 0x83, 0xa0, 0xfd, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xf3, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 56: 101.250 MHz
|
||||
{
|
||||
0x0608f3d0, // 101250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2a, 0x12, 0x40, 0x20, 0x0c, 0x04, 0x83, 0xa0, 0xfd, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xf3, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 57: 102.104 MHz
|
||||
{
|
||||
0x0615fbc0, // 102104000 Hz
|
||||
{
|
||||
{ { 0xd2, 0x55, 0x12, 0x40, 0x4b, 0x0d, 0x10, 0x4b, 0xa0, 0xff, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xf1, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 58: 102.250 MHz
|
||||
{
|
||||
0x06183610, // 102250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2b, 0x12, 0x40, 0x30, 0xda, 0x08, 0x85, 0xa0, 0x00, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xf0, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 59: 102.977 MHz
|
||||
{
|
||||
0x06234de8, // 102977000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2b, 0x12, 0x40, 0x78, 0xa7, 0x08, 0x05, 0xa0, 0x01, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xef, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 60: 104.000 MHz
|
||||
{
|
||||
0x0632ea00, // 104000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2b, 0x12, 0x40, 0x30, 0x20, 0x08, 0x85, 0xa0, 0x04, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xec, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 61: 104.993 MHz
|
||||
{
|
||||
0x064210e8, // 104993000 Hz
|
||||
{
|
||||
{ { 0xd4, 0xaf, 0x12, 0x40, 0x7f, 0xfd, 0x20, 0x11, 0xa0, 0x06, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xea, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 62: 106.472 MHz
|
||||
{
|
||||
0x0658a240, // 106472000 Hz
|
||||
{
|
||||
{ { 0xd2, 0x59, 0x12, 0x40, 0x4b, 0xd7, 0x10, 0x47, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe7, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 63: 106.500 MHz
|
||||
{
|
||||
0x06590fa0, // 106500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2c, 0x12, 0x40, 0x20, 0x18, 0x02, 0x81, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe7, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 64: 107.214 MHz
|
||||
{
|
||||
0x0663f4b0, // 107214000 Hz
|
||||
{
|
||||
{ { 0xd2, 0x59, 0x12, 0x40, 0x64, 0x45, 0x10, 0x47, 0xa0, 0x0c, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe5, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 65: 108.000 MHz
|
||||
{
|
||||
0x066ff300, // 108000000 Hz
|
||||
{
|
||||
{ { 0x51, 0x2d, 0x10, 0x40, 0x00, 0x00, 0x00, 0x80, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe4, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 66: 108.108 MHz
|
||||
{
|
||||
0x067198e0, // 108108000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2d, 0x12, 0x40, 0x64, 0x09, 0x08, 0x83, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe3, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 67: 108.883 MHz
|
||||
{
|
||||
0x067d6c38, // 108883000 Hz
|
||||
{
|
||||
{ { 0xd2, 0x5b, 0x12, 0x40, 0x7f, 0xbd, 0x10, 0x45, 0xa0, 0x10, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe2, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 68: 109.000 MHz
|
||||
{
|
||||
0x067f3540, // 109000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x2d, 0x12, 0x40, 0x30, 0x28, 0x08, 0x83, 0xa0, 0x11, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xe1, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 69: 115.500 MHz
|
||||
{
|
||||
0x06e263e0, // 115500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x30, 0x12, 0x40, 0x20, 0x08, 0x00, 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xd5, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 70: 117.500 MHz
|
||||
{
|
||||
0x0700e860, // 117500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x31, 0x14, 0x40, 0x30, 0xfc, 0x08, 0x87, 0xa0, 0x26, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xd1, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 71: 118.532 MHz
|
||||
{
|
||||
0x0710a7a0, // 118532000 Hz
|
||||
{
|
||||
{ { 0xd2, 0x63, 0x14, 0x40, 0x4b, 0xbd, 0x10, 0x0d, 0xa0, 0x28, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xcf, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 72: 119.000 MHz
|
||||
{
|
||||
0x0717cbc0, // 119000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x32, 0x14, 0x40, 0x30, 0xd8, 0x04, 0x83, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xcf, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 73: 121.750 MHz
|
||||
{
|
||||
0x0741c1f0, // 121750000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x33, 0x14, 0x40, 0x30, 0xe6, 0x08, 0x85, 0xa0, 0x30, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xca, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 74: 122.500 MHz
|
||||
{
|
||||
0x074d33a0, // 122500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x33, 0x14, 0x40, 0x30, 0x04, 0x08, 0x85, 0xa0, 0x32, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xc9, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 75: 122.614 MHz
|
||||
{
|
||||
0x074ef0f0, // 122614000 Hz
|
||||
{
|
||||
{ { 0xd3, 0x99, 0x16, 0x40, 0x50, 0x13, 0x02, 0x81, 0xa0, 0x33, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xc8, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 76: 123.379 MHz
|
||||
{
|
||||
0x075a9d38, // 123379000 Hz
|
||||
{
|
||||
{ { 0xd2, 0x67, 0x14, 0x40, 0x5b, 0xbd, 0x10, 0x09, 0xa0, 0x34, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xc7, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 77: 130.250 MHz
|
||||
{
|
||||
0x07c37510, // 130250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x36, 0x14, 0x40, 0x30, 0x1a, 0x04, 0x81, 0xa0, 0x46, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xbd, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 78: 135.000 MHz
|
||||
{
|
||||
0x080befc0, // 135000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x38, 0x14, 0x40, 0x20, 0x10, 0x00, 0x80, 0x80, 0x52, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xb6, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 79: 136.488 MHz
|
||||
{
|
||||
0x0822a440, // 136488000 Hz
|
||||
{
|
||||
{ { 0xd3, 0xab, 0x15, 0x40, 0x64, 0xe6, 0x08, 0x87, 0xa0, 0x55, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xb4, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 80: 136.750 MHz
|
||||
{
|
||||
0x0826a3b0, // 136750000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x39, 0x15, 0x40, 0x30, 0xfe, 0x08, 0x87, 0xa0, 0x56, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xb4, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 81: 138.542 MHz
|
||||
{
|
||||
0x0841fbb0, // 138542000 Hz
|
||||
{
|
||||
{ { 0xd4, 0xe7, 0x15, 0x40, 0x78, 0xe9, 0x20, 0x19, 0xa0, 0x5a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xb1, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 82: 138.750 MHz
|
||||
{
|
||||
0x08452830, // 138750000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3a, 0x15, 0x40, 0x20, 0xf4, 0x04, 0x83, 0xa0, 0x5b, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xb1, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 83: 140.250 MHz
|
||||
{
|
||||
0x085c0b90, // 140250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3a, 0x15, 0x40, 0x20, 0x1c, 0x04, 0x83, 0xa0, 0x5f, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xaf, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 84: 146.250 MHz
|
||||
{
|
||||
0x08b79910, // 146250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3d, 0x15, 0x40, 0x20, 0xfc, 0x08, 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa8, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 85: 147.136 MHz
|
||||
{
|
||||
0x08c51e00, // 147136000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3d, 0x15, 0x40, 0x4b, 0x2e, 0x08, 0x83, 0xa0, 0x70, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa7, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 86: 148.250 MHz
|
||||
{
|
||||
0x08d61d90, // 148250000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3e, 0x15, 0x40, 0x30, 0xea, 0x04, 0x81, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x07, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa6, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 87: 148.500 MHz
|
||||
{
|
||||
0x08d9ee20, // 148500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x3e, 0x15, 0x40, 0x20, 0xf8, 0x04, 0x81, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa5, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 88: 149.426 MHz
|
||||
{
|
||||
0x08e80f50, // 149426000 Hz
|
||||
{
|
||||
{ { 0xd4, 0xf9, 0x15, 0x40, 0x7f, 0x0b, 0x20, 0x07, 0xa0, 0x76, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa4, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 89: 154.000 MHz
|
||||
{
|
||||
0x092dda80, // 154000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x20, 0x00, 0x40, 0x30, 0x08, 0x00, 0x80, 0x80, 0xc1, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0xa0, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 90: 155.851 MHz
|
||||
{
|
||||
0x094a18f8, // 155851000 Hz
|
||||
{
|
||||
{ { 0xd2, 0x41, 0x06, 0x40, 0x7f, 0xc1, 0x08, 0x07, 0xa0, 0xc3, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x9e, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 91: 156.000 MHz
|
||||
{
|
||||
0x094c5f00, // 156000000 Hz
|
||||
{
|
||||
{ { 0x52, 0x41, 0x00, 0x40, 0x00, 0x00, 0x00, 0x80, 0x80, 0xc3, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x9e, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 92: 156.794 MHz
|
||||
{
|
||||
0x09587c90, // 156794000 Hz
|
||||
{
|
||||
{ { 0xd4, 0x83, 0x06, 0x40, 0x60, 0xbf, 0x10, 0x4d, 0xa0, 0xc4, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x9d, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 93: 157.000 MHz
|
||||
{
|
||||
0x095ba140, // 157000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x21, 0x01, 0x40, 0x30, 0xe4, 0x08, 0x87, 0xa0, 0xc4, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x9d, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 94: 157.500 MHz
|
||||
{
|
||||
0x09634260, // 157500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x21, 0x01, 0x40, 0x20, 0xf4, 0x08, 0x87, 0xa0, 0xc5, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x9c, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 95: 159.358 MHz
|
||||
{
|
||||
0x097f9c30, // 159358000 Hz
|
||||
{
|
||||
{ { 0xd4, 0x85, 0x06, 0x40, 0x78, 0x9f, 0x10, 0x0b, 0xa0, 0xc7, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x9a, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 96: 159.500 MHz
|
||||
{
|
||||
0x0981c6e0, // 159500000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x21, 0x01, 0x40, 0x30, 0x16, 0x08, 0x87, 0xa0, 0xc7, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x9a, 0x24, 0x02, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 97: 160.963 MHz
|
||||
{
|
||||
0x099819b8, // 160963000 Hz
|
||||
{
|
||||
{ { 0xd2, 0x43, 0x06, 0x40, 0x7f, 0x45, 0x08, 0x05, 0xa0, 0xc9, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x31, 0x25, 0x03, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 98: 161.000 MHz
|
||||
{
|
||||
0x0998aa40, // 161000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x22, 0x01, 0x40, 0x30, 0xd4, 0x04, 0x83, 0xa0, 0xc9, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x31, 0x25, 0x03, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 99: 161.750 MHz
|
||||
{
|
||||
0x09a41bf0, // 161750000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x22, 0x01, 0x40, 0x30, 0xe3, 0x04, 0x83, 0xa0, 0xca, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x30, 0x25, 0x03, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
// 100: 162.000 MHz
|
||||
{
|
||||
0x09a7ec80, // 162000000 Hz
|
||||
{
|
||||
{ { 0xd1, 0x22, 0x01, 0x40, 0x20, 0xf0, 0x04, 0x83, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x0e, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x82, 0x54, 0x2f, 0x25, 0x03, 0x00, 0x00, 0x01 }, 0, 0 }, // 24 bpp
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 30 bpp (invalid)
|
||||
{ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 0, 1 }, // 36 bpp (invalid)
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
size_t hdmi_static_config_size = sizeof( hdmi_static_config );
|
||||
@@ -0,0 +1,998 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef _REGS_H
|
||||
#define _REGS_H
|
||||
|
||||
#define CTRL_BASE_ADDR (HDMI_BASE_ADDR + 0x00000) //controller
|
||||
#define HDMI_CORE_BASE_ADDR (HDMI_BASE_ADDR + 0x10000) //HDMI
|
||||
#define SPDIF_BASE_ADDR (HDMI_BASE_ADDR + 0x30000) //SPDIF receiver
|
||||
#define I2S_BASE_ADDR (HDMI_BASE_ADDR + 0x40000) //I2S receiver
|
||||
#define TG_BASE_ADDR (HDMI_BASE_ADDR + 0x50000) //HDMI timing generator
|
||||
#define E_FUSE_BASE_ADDR (HDMI_BASE_ADDR + 0x60000) //E-FUSE controller
|
||||
#define CEC_BASE_ADDR (HDMI_BASE_ADDR + 0x70000) //CEC
|
||||
#define I2C_BASE_ADDR (HDMI_BASE_ADDR + 0x80000) //I2C
|
||||
|
||||
#define PHY_I2C_ADDRESS 0x70
|
||||
#define IICCONFIG_IICCON 0x00000201
|
||||
#define IICCONFIG_FIFOCON 0x00000000
|
||||
#define IICCONFIG_IICBUSCON 0x00000000
|
||||
#define IICCONFIG_TIMEOUTCON 0xffffffff
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - Generic HDMI -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// General Control Packet Subpacket Byte 0
|
||||
#define GCP_SB0_CLR_AVMUTE 0x10
|
||||
#define GCP_SB0_SET_AVMUTE 0x01
|
||||
|
||||
// General Control Packet Subpacket Byte 1
|
||||
#define GCP_SB1_CD_SHIFT 0
|
||||
#define GCP_SB1_CD_MASK 0x07
|
||||
#define GCP_SB1_CD_NONE 0
|
||||
#define GCP_SB1_CD_24_BPP 4
|
||||
#define GCP_SB1_CD_30_BPP 5
|
||||
#define GCP_SB1_CD_36_BPP 6
|
||||
#define GCP_SB1_CD_48_BPP 7
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - PHY registers -
|
||||
//
|
||||
// Note:
|
||||
// Register names are in hexadecimal.
|
||||
// Definitions of registers 01~1E are PHY version dependent.
|
||||
// The HDMI V1.3 TX may be used with either PHY version (V1.3 or V1.4).
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define PHY_CONFIG_REG00 0x00u // (R/W) Unused Reserved register
|
||||
#define PHY_CONFIG_REG01 0x01u // (R/W) First byte of PHY configuration
|
||||
#define PHY_CONFIG_REG02 0x02u // (R/W)
|
||||
#define PHY_CONFIG_REG03 0x03u // (R/W)
|
||||
#define PHY_CONFIG_REG04 0x04u // (R/W)
|
||||
#define PHY_CONFIG_REG05 0x05u // (R/W)
|
||||
#define PHY_CONFIG_REG06 0x06u // (R/W)
|
||||
#define PHY_CONFIG_REG07 0x07u // (R/W)
|
||||
#define PHY_CONFIG_REG08 0x08u // (R/W)
|
||||
#define PHY_CONFIG_REG09 0x09u // (R/W)
|
||||
#define PHY_CONFIG_REG0A 0x0Au // (R/W)
|
||||
#define PHY_CONFIG_REG0B 0x0Bu // (R/W)
|
||||
#define PHY_CONFIG_REG0C 0x0Cu // (R/W)
|
||||
#define PHY_CONFIG_REG0D 0x0Du // (R/W)
|
||||
#define PHY_CONFIG_REG0E 0x0Eu // (R/W)
|
||||
#define PHY_CONFIG_REG0F 0x0Fu // (R/W)
|
||||
#define PHY_CONFIG_REG10 0x10u // (R/W)
|
||||
#define PHY_CONFIG_REG11 0x11u // (R/W)
|
||||
#define PHY_CONFIG_REG12 0x12u // (R/W)
|
||||
#define PHY_CONFIG_REG13 0x13u // (R/W)
|
||||
#define PHY_CONFIG_REG14 0x14u // (R/W)
|
||||
#define PHY_CONFIG_REG15 0x15u // (R/W)
|
||||
#define PHY_CONFIG_REG16 0x16u // (R/W)
|
||||
#define PHY_CONFIG_REG17 0x17u // (R/W)
|
||||
#define PHY_CONFIG_REG18 0x18u // (R/W)
|
||||
#define PHY_CONFIG_REG19 0x19u // (R/W)
|
||||
#define PHY_CONFIG_REG1A 0x1Au // (R/W)
|
||||
#define PHY_CONFIG_REG1B 0x1Bu // (R/W)
|
||||
#define PHY_CONFIG_REG1C 0x1Cu // (R/W)
|
||||
#define PHY_CONFIG_REG1D 0x1Du // (R/W)
|
||||
#define PHY_CONFIG_REG1E 0x1Eu // (R/W) Last byte of PHY configuration
|
||||
|
||||
#define PHY_CONFIG_MODE_SET 0x1Fu // (R/W) Control register for PHY config
|
||||
#define PHY_CONFIG_MODE_SET_IN_PROGRESS 0x00 // Set this value before loading REG01-REG1E
|
||||
#define PHY_CONFIG_MODE_SET_DONE 0x80 // Set this value after loading REG01-REG1E
|
||||
|
||||
#define PHY_CONFIG_REG_COUNT 0x20u
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDMI v1.3 PHY registers -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// REG01
|
||||
#define PHY_V1P3_CONFIG_REG01_GEN_PD 0x80 // Sigma delta modulator clock generator Power Down
|
||||
#define PHY_V1P3_CONFIG_REG01_BIAS_PD 0x20 // Bias Power Down - PLL & Bias required for HPD
|
||||
|
||||
// REG05
|
||||
#define PHY_V1P3_CONFIG_REG05_PLL_PD 0x20 // PLL Power Down - PLL & Bias required for HPD
|
||||
|
||||
// REG17
|
||||
#define PHY_V1P3_CONFIG_REG17_TX_PD 0x02 // TMDS TX power down
|
||||
#define PHY_V1P3_CONFIG_REG17_PCG_PD 0x01 // Pixel clock generator Power Down
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDMI v1.4 PHY registers -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// REG1D
|
||||
#define PHY_V1P4_CONFIG_REG1D_I2C_PDEN 0x80 // Enable the power down controls below
|
||||
#define PHY_V1P4_CONFIG_REG1D_PLL_PD 0x40 // PLL & Bias Power Down - PLL & Bias required for HPD
|
||||
#define PHY_V1P4_CONFIG_REG1D_TX_CLKSER_PD 0x20 // Clock Serializer Power Down
|
||||
#define PHY_V1P4_CONFIG_REG1D_TX_CLKDRV_PD 0x10 // TMDS Clock Driver Power Down
|
||||
#define PHY_V1P4_CONFIG_REG1D_TX_DATDRV_PD 0x04 // TMDS Data Driver Power Down
|
||||
#define PHY_V1P4_CONFIG_REG1D_TX_DATSER_PD 0x02 // TMDS Data Serializer Power Down
|
||||
#define PHY_V1P4_CONFIG_REG1D_TX_CLK_PD 0x01 // TX Internal Clock Buffer/Divider Power Down
|
||||
|
||||
// TX Power Down bits
|
||||
#define PHY_V1P4_CONFIG_REG1D_TX_DRV_PD (PHY_V1P4_CONFIG_REG1D_TX_DATDRV_PD |\
|
||||
PHY_V1P4_CONFIG_REG1D_TX_CLKDRV_PD)
|
||||
|
||||
// Power Down bits (excluding I2C_PDEN and PLL_PD)
|
||||
#define PHY_V1P4_CONFIG_REG1D_PD_WITH_HPD (PHY_V1P4_CONFIG_REG1D_TX_CLKSER_PD | \
|
||||
PHY_V1P4_CONFIG_REG1D_TX_CLKDRV_PD | \
|
||||
PHY_V1P4_CONFIG_REG1D_TX_DATDRV_PD | \
|
||||
PHY_V1P4_CONFIG_REG1D_TX_DATSER_PD | \
|
||||
PHY_V1P4_CONFIG_REG1D_TX_CLK_PD)
|
||||
|
||||
// All Power Down bits (excluding I2C_PDEN)
|
||||
#define PHY_V1P4_CONFIG_REG1D_FULL_PD (PHY_V1P4_CONFIG_REG1D_PLL_PD | PHY_V1P4_CONFIG_REG1D_PD_WITH_HPD)
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - Control Registers (CTRL_BASE) -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#define CTRL_INTC_CON 0x0000u // (R/W) Specifies the interrupt control register. [0x00]
|
||||
#define CTRL_INTC_CON_POL_SHIFT 7
|
||||
#define CTRL_INTC_CON_POL_MASK 0x80
|
||||
#define CTRL_INTC_CON_POL_HIGH 0 // Active high
|
||||
#define CTRL_INTC_CON_POL_LOW 1 // Active low
|
||||
#define CTRL_INTC_CON_EN_GLOBAL 0x40
|
||||
#define CTRL_INTC_CON_EN_I2S 0x20
|
||||
#define CTRL_INTC_CON_EN_CEC 0x10
|
||||
#define CTRL_INTC_CON_EN_HPD_PLUG 0x08
|
||||
#define CTRL_INTC_CON_EN_HPD_UNPLUG 0x04
|
||||
#define CTRL_INTC_CON_EN_SPDIF 0x02
|
||||
#define CTRL_INTC_CON_EN_HDCP 0x01
|
||||
|
||||
#define CTRL_INTC_CON_EN_HPD_CHG (CTRL_INTC_CON_EN_HPD_PLUG|CTRL_INTC_CON_EN_HPD_UNPLUG)
|
||||
|
||||
#define CTRL_INTC_FLAG 0x0004u // (R/W) Specifies the interrupt flag register. [0x00]
|
||||
#define CTRL_INTC_FLAG_I2S 0x20
|
||||
#define CTRL_INTC_FLAG_CEC 0x10
|
||||
#define CTRL_INTC_FLAG_HPD_PLUG 0x08
|
||||
#define CTRL_INTC_FLAG_HPD_UNPLUG 0x04
|
||||
#define CTRL_INTC_FLAG_SPDIF 0x02
|
||||
#define CTRL_INTC_FLAG_HDCP 0x01
|
||||
|
||||
#define CTRL_INTC_FLAG_HPD_CHG (CTRL_INTC_FLAG_HPD_PLUG|CTRL_INTC_FLAG_HPD_UNPLUG)
|
||||
|
||||
#define CTRL_HDCP_KEY_STATUS 0x0008u // (R/O) Specifies the HDCP key status. [0x00]
|
||||
#define CTRL_HDCP_KEY_STATUS_LOAD_DONE 0x01
|
||||
|
||||
#define CTRL_HPD_STATUS 0x000Cu // (R/O) Specifies the value of HPD signal. [0x00]
|
||||
#define CTRL_HPD_STATUS_PLUGGED 0x01
|
||||
|
||||
// Common definitions for AUDIO_CLKSEL
|
||||
#define CTRL_AUDIO_CLK_MASK 0x01
|
||||
#define CTRL_AUDIO_CLK_PCLK 0
|
||||
#define CTRL_AUDIO_CLK_SPDIF 1
|
||||
|
||||
// Common definitions for PHY_RSTOUT
|
||||
#define CTRL_HDMI_PHY_RSTOUT_RESET 0x01 // Reset HDMI PHY (active high)
|
||||
|
||||
// Common definitions for CORE_RSTOUT
|
||||
#define CTRL_HDMI_CORE_RSTOUT_RESET_F 0x01 // Reset HDMI core (active low)
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDMI Core Registers (HDMI_CORE_BASE) -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define HDMI_CON_0 0x0000u // (R/W) Specifies the HDMI system control register 0. [0x00]
|
||||
#define HDMI_CON_0_BLUE_SCR_EN 0x20 // Enable "blue screen" mode (TX video mute)
|
||||
#define HDMI_CON_0_ENCODING_RETAIN_BIT_ORDER 0x10 // Reverse (0) or retain (1)
|
||||
#define HDMI_CON_0_ASP_EN 0x04
|
||||
#define HDMI_CON_0_SYSTEM_EN 0x01
|
||||
|
||||
#define HDMI_CON_1 0x0004u // (R/W) Specifies the HDMI system control register 1. [0x00]
|
||||
#define HDMI_CON_1_PXL_LMT_CTRL_SHIFT 5
|
||||
#define HDMI_CON_1_PXL_LMT_CTRL_MASK 0x60
|
||||
#define HDMI_CON_1_PXL_LMT_CTRL_BYPASS_MODE 0
|
||||
#define HDMI_CON_1_PXL_LMT_CTRL_RGB_MODE 1
|
||||
#define HDMI_CON_1_PXL_LMT_CTRL_YCBCR_MODE 2
|
||||
|
||||
#define HDMI_CON_2 0x0008u // (R/W) Specifies the HDMI system control register 2. [0x00]
|
||||
#define HDMI_CON_2_VID_PERIOD_EN 0x20
|
||||
#define HDMI_CON_2_DVI_BAND_EN 0x02
|
||||
|
||||
#define HDMI_STATUS 0x0010u // (R/W) Specifies the HDMI system status register. [0x00]
|
||||
#define HDMI_STATUS_AUTHEN_ACK 0x80
|
||||
#define HDMI_STATUS_AUD_FIFO_OVF_INT 0x40
|
||||
#define HDMI_STATUS_UPDATE_Ri_INT 0x10 // Indicates that the {Ri} value should be read (HDCP)
|
||||
#define HDMI_STATUS_An_WRITE_INT 0x04 // Indicates that the {An} random value is ready (HDCP)
|
||||
#define HDMI_STATUS_WATCHDOG_INT 0x02
|
||||
#define HDMI_STATUS_I2C_INIT_INT 0x01
|
||||
|
||||
#define HDMI_STATUS_EN 0x0020u // (R/W) Specifies the HDMI system status enable register. [0x00]
|
||||
#define HDMI_STATUS_EN_AUD_FIFO_OVF_EN 0x40
|
||||
#define HDMI_STATUS_EN_UPDATE_Ri_EN 0x10
|
||||
#define HDMI_STATUS_EN_An_WRITE_EN 0x04
|
||||
#define HDMI_STATUS_EN_WATCHDOG_EN 0x02
|
||||
#define HDMI_STATUS_EN_I2C_INIT_EN 0x01
|
||||
|
||||
// Enable mask including all HDCP interrupts except WATCHDOG_INT, which is not used.
|
||||
#define HDMI_STATUS_EN_HDCP_EN (HDMI_STATUS_EN_UPDATE_Ri_EN|HDMI_STATUS_EN_An_WRITE_EN|HDMI_STATUS_EN_I2C_INIT_EN)
|
||||
|
||||
#define HDMI_HPD 0x0030u // (R/W) Specifies the HPD control register. [0x00]
|
||||
#define HDMI_HPD_SW_HPD 0x02
|
||||
#define HDMI_HPD_HPD_SEL_SW_HPD 0x01
|
||||
|
||||
#define HDMI_MODE_SEL 0x0040u // (R/W) Selects the HDMI/DVI mode. [0x00]
|
||||
#define HDMI_MODE_SEL_MODE_SHIFT 0
|
||||
#define HDMI_MODE_SEL_MODE_MASK 0x03
|
||||
#define HDMI_MODE_SEL_MODE_DISABLED 0
|
||||
#define HDMI_MODE_SEL_MODE_DVI 1
|
||||
#define HDMI_MODE_SEL_MODE_HDMI 2
|
||||
|
||||
#define HDMI_ENC_EN 0x0044u // (R/W) Specifies the HDCP encryption enable register [0x00]
|
||||
#define HDMI_ENC_EN_HDCP_ENC_EN 0x01
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDMI Video Related Registers -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define HDMI_YMAX 0x0060u // (R/W) Specifies the maximum Y (or R, G, B) pixel value [0xeb]
|
||||
#define HDMI_YMIN 0x0064u // (R/W) Specifies the minimum Y (or R, G, B) pixel value [0x10]
|
||||
|
||||
#define HDMI_CMAX 0x0068u // (R/W) Specifies the maximum Cb/Cr pixel value [0xf0]
|
||||
#define HDMI_CMIN 0x006Cu // (R/W) Specifies the minimum Cb/Cr pixel value [0x10]
|
||||
|
||||
#define HDMI_H_BLANK_0 0x00A0u // (R/W) Specifies the horizontal blanking setting [0x00]
|
||||
#define HDMI_H_BLANK_1 0x00A4u // (R/W) Specifies the horizontal blanking setting [0x00]
|
||||
|
||||
#define HDMI_VSYNC_POL 0x00E4u // (R/W) Specifies the vertical sync polarity control register [0x00]
|
||||
|
||||
#define HDMI_INT_PRO_MODE 0x00E8u // (R/W) Specifies the interlace/progressive control register [0x00]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDMI Audio Related Registers -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// Common definitions for HDMI_ASP_CON
|
||||
#define HDMI_ASP_CON_AUD_TYPE_SHIFT 5 // Audio packet type field position
|
||||
#define HDMI_ASP_CON_AUD_TYPE_MASK 0x60
|
||||
#define HDMI_ASP_CON_AUD_TYPE_ASP 0u // Audio Sample Packet
|
||||
#define HDMI_ASP_CON_AUD_TYPE_1BIT 1u // One-bit audio packet
|
||||
#define HDMI_ASP_CON_AUD_TYPE_HBR 2u // High Bit Rate packet
|
||||
#define HDMI_ASP_CON_AUD_TYPE_DST 3u // Direct Stream Transport packet
|
||||
|
||||
#define HDMI_ASP_CON_AUD_MODE_SHIFT 4 // Audio packet layout field position
|
||||
#define HDMI_ASP_CON_AUD_MODE_MASK 0x10
|
||||
#define HDMI_ASP_CON_AUD_MODE_TWO_CHANNEL 0u // Layout 0 (two-channel mode)
|
||||
#define HDMI_ASP_CON_AUD_MODE_MULTI_CHANNEL 1u // Layout 1 (multi-channel mode)
|
||||
|
||||
#define HDMI_ASP_CON_SP_PRE_SHIFT 0 // Sample Present field position (not used in two-channel mode)
|
||||
#define HDMI_ASP_CON_SP_PRE_MASK 0x0F
|
||||
|
||||
// Common definitions for HDMI_ACR_CON:
|
||||
#define HDMI_ACR_CON_ALT_CTS_RATE_SHIFT 3 // Alternate CTS rate field position
|
||||
#define HDMI_ACR_CON_ALT_CTS_RATE_MASK 0x18
|
||||
#define HDMI_ACR_CON_ALT_CTS_RATE_CONSTANT_CTS 0 // Always use CTS value 1
|
||||
#define HDMI_ACR_CON_ALT_CTS_RATE_1_TO_1 1 // 1:1 (CTS value 1 : CTS value 2)
|
||||
#define HDMI_ACR_CON_ALT_CTS_RATE_2_TO_1 2 // 2:1 (CTS value 1 : CTS value 2)
|
||||
#define HDMI_ACR_CON_ALT_CTS_RATE_3_TO_1 3 // 3:1 (CTS value 1 : CTS value 2)
|
||||
|
||||
#define HDMI_ACR_CON_ACR_TX_MODE_SHIFT 0 // ACR transmit mode field position
|
||||
#define HDMI_ACR_CON_ACR_TX_MODE_MASK 0x07
|
||||
#define HDMI_ACR_CON_ACR_TX_MODE_DISABLED 0 // Do not transmit the ACR packet
|
||||
#define HDMI_ACR_CON_ACR_TX_MODE_ONCE 1 // Transmit one packet, when it becomes available
|
||||
#define HDMI_ACR_CON_ACR_TX_MODE_INTERVAL 2 // Transmit ACR_TXCNT times during every VBI period
|
||||
#define HDMI_ACR_CON_ACR_TX_MODE_COUNTING 3 // Transfers by counting i_clk_vid for a given CTS value in ACR_CTS0:2
|
||||
#define HDMI_ACR_CON_ACR_TX_MODE_MEASURED_CTS 4 // Mesured CTS mode. Note: The 7 LSBs of ACR_N should be zero.
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDMI Packet Related Registers -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// Common definitions for:
|
||||
// GCP_CON[GCP_CON]
|
||||
// ACP_CON[ACP_TX_CON]
|
||||
// ISRC_CON[ISRC_TX_CON]
|
||||
// AVI_CON[AVI_TX_CON]
|
||||
// AUI_CON[AUI_TX_CON]
|
||||
// MPG_CON[MPG_TX_CON]
|
||||
// SPD_CON[SPD_TX_CON
|
||||
// GAMUT_CON[GAMUT_CON]
|
||||
#define HDMI_PKT_CON_PKT_TX_CON_SHIFT 0
|
||||
#define HDMI_PKT_CON_PKT_TX_CON_MASK 0x03
|
||||
#define HDMI_PKT_CON_PKT_TX_CON_DISABLED 0
|
||||
#define HDMI_PKT_CON_PKT_TX_CON_SEND_ONCE 1
|
||||
#define HDMI_PKT_CON_PKT_TX_CON_SEND_ALWAYS 2
|
||||
|
||||
// Common definitions for GCP_CON
|
||||
#define HDMI_GCP_CON_VSYNC_SHIFT 2
|
||||
#define HDMI_GCP_CON_VSYNC_MASK 0x0C
|
||||
#define HDMI_GCP_CON_VSYNC_NEITHER_FIELD 0
|
||||
#define HDMI_GCP_CON_VSYNC_FIELD2 1
|
||||
#define HDMI_GCP_CON_VSYNC_FIELD1 2
|
||||
#define HDMI_GCP_CON_VSYNC_BOTH_FIELDS 3
|
||||
|
||||
// Common definitions for DC_CONTROL
|
||||
#define HDMI_DC_CONTROL_DEEP_COLOR_MODE_SHIFT 0
|
||||
#define HDMI_DC_CONTROL_DEEP_COLOR_MODE_MASK 0x03
|
||||
#define HDMI_DC_CONTROL_DEEP_COLOR_MODE_8_BPC (0 << HDMI_DC_CONTROL_DEEP_COLOR_MODE_SHIFT)
|
||||
#define HDMI_DC_CONTROL_DEEP_COLOR_MODE_10_BPC (1 << HDMI_DC_CONTROL_DEEP_COLOR_MODE_SHIFT)
|
||||
#define HDMI_DC_CONTROL_DEEP_COLOR_MODE_12_BPC (2 << HDMI_DC_CONTROL_DEEP_COLOR_MODE_SHIFT)
|
||||
|
||||
// Common definitions for VIDEO_PATTERN_GEN
|
||||
#define HDMI_VIDEO_PATTERN_GEN_PATTERN_ENABLE 1 // Uses internally generated video pattern
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDCP Related Registers -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define HDMI_HDCP_SHA1_00 0x0000u // (R/W) Specifies the SHA-1 value from repeater. [0x00]
|
||||
#define HDMI_HDCP_KSV_LIST_0 0x0050u // (R/W) Specifies the KSV list from repeater. [0x00]
|
||||
|
||||
#define HDMI_HDCP_KSV_LIST_CON 0x0064u // (R/W) Controls the KSV list. [0x01]
|
||||
#define HDMI_HDCP_KSV_LIST_CON_WRITE 0x08
|
||||
#define HDMI_HDCP_KSV_LIST_CON_EMPTY 0x04
|
||||
#define HDMI_HDCP_KSV_LIST_CON_END 0x02
|
||||
#define HDMI_HDCP_KSV_LIST_CON_READ_DONE 0x01
|
||||
|
||||
#define HDMI_HDCP_SHA_RESULT 0x0070u // (R/W) Specifies the SHA-1 checking result register. [0x00]
|
||||
#define HDMI_HDCP_SHA_RESULT_VALID_READY 0x02
|
||||
#define HDMI_HDCP_SHA_RESULT_VALID 0x01
|
||||
|
||||
#define HDMI_HDCP_SHA_RESULT_OK (HDMI_HDCP_SHA_RESULT_VALID_READY|HDMI_HDCP_SHA_RESULT_VALID)
|
||||
|
||||
#define HDMI_HDCP_CTRL1 0x0080u // (R/W) Specifies the HDCP control register1. [0x00]
|
||||
#define HDMI_HDCP_CTRL1_TIMEOUT 0x04
|
||||
#define HDMI_HDCP_CTRL1_CP_DESIRED 0x02
|
||||
|
||||
#define HDMI_HDCP_CTRL2 0x0084u // (R/W) Specifies the HDCP control register2. [0x00]
|
||||
#define HDMI_HDCP_CTRL2_REVOCATION_SET 0x01
|
||||
|
||||
#define HDMI_HDCP_CHECK_RESULT 0x0090u // (R/W) Checks the result of Ri and Pj values. [0x00]
|
||||
#define HDMI_HDCP_CHECK_RESULT_Ri_SHIFT 0
|
||||
#define HDMI_HDCP_CHECK_RESULT_Ri_MASK 0x03
|
||||
#define HDMI_HDCP_CHECK_RESULT_Ri_RESET 0
|
||||
#define HDMI_HDCP_CHECK_RESULT_Ri_MISMATCH 2
|
||||
#define HDMI_HDCP_CHECK_RESULT_Ri_MATCH 3
|
||||
|
||||
#define HDMI_HDCP_BKSV_0 0x00A0u // (R/W) Specifies the KSV of Rx. [0x00]
|
||||
#define HDMI_HDCP_AKSV_0 0x00C0u // (R/W) Specifies the KSV of Tx. [0x00]
|
||||
#define HDMI_HDCP_An_0 0x00E0u // (R/W) Specifies the an value. [0x00]
|
||||
#define HDMI_HDCP_BCAPS 0x0100u // (R/W) Specifies the BCAPS from Rx. [0x00]
|
||||
#define HDMI_HDCP_BSTATUS_0 0x0110u // (R/W) Specifies the BSTATUS from Rx. [0x00]
|
||||
#define HDMI_HDCP_BSTATUS_1 0x0114u // (R/W) Specifies the BSTATUS from Rx. [0x00]
|
||||
#define HDMI_HDCP_Ri_0 0x0140u // (R/W) Specifies the Ri value of Tx. [0x00]
|
||||
#define HDMI_HDCP_Ri_1 0x0144u // (R/W) Specifies the Ri value of Tx. [0x00]
|
||||
#define HDMI_HDCP_I2C_INT 0x0180u // (R/W) Specifies the I2C interrupt flag. [0x00]
|
||||
#define HDMI_HDCP_AN_INT 0x0190u // (R/W) Specifies the An value ready interrupt flag. [0x00]
|
||||
#define HDMI_HDCP_WATCHDOG_INT 0x01A0u // (R/W) Specifies the Watchdog interrupt flag. [0x00]
|
||||
#define HDMI_HDCP_Ri_INT 0x01B0u // (R/W) Specifies the Ri value update interrupt flag. [0x00]
|
||||
|
||||
#define HDMI_HDCP_Ri_COMPARE_0 0x01D0u // (R/W) Specifies the HDCP Ri interrupt frame number index register 0. [0x80]
|
||||
#define HDMI_HDCP_Ri_COMPARE_1 0x01D4u // (R/W) Specifies the HDCP Ri interrupt frame number index register 1. [0x7f]
|
||||
#define HDMI_HDCP_Ri_COMPARE_ENABLE 0x80
|
||||
#define HDMI_HDCP_FRAME_INDEX_MASK 0x7F
|
||||
|
||||
#define HDMI_HDCP_FRAME_COUNT 0x01E0u // (R/W) Specifies the current value of frame count index in the hardware. [0x00]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - SPDIF Receiver Registers (SPDIF_BASE) -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define SPDIFIN_CLK_CTRL 0x0000u // (R/W) Specifies the SPDIFIN clock control register. [0x02]
|
||||
#define SPDIFIN_OP_CTRL 0x0004u // (R/W) Specifies the SPDIFIN operation control register 1. [0x00]
|
||||
#define SPDIFIN_IRQ_MASK 0x0008u // (R/W) Specifies the SPDIFIN interrupt request mask register. [0x00]
|
||||
#define SPDIFIN_IRQ_STATUS 0x000Cu // (R/W) Specifies the SPDIFIN interrupt request status register. [0x00]
|
||||
#define SPDIFIN_CONFIG_1 0x0010u // (R/W) Specifies the SPDIFIN configuration register 1. [0x02]
|
||||
#define SPDIFIN_CONFIG_2 0x0014u // (R/W) Specifies the SPDIFIN configuration register 2. [0x00]
|
||||
#define SPDIFIN_USER_VALUE_1 0x0020u // (R/W) Specifies the SPDIFIN user value register 1. [0x00]
|
||||
#define SPDIFIN_USER_VALUE_2 0x0024u // (R/W) Specifies the SPDIFIN user value register 2. [0x00]
|
||||
#define SPDIFIN_USER_VALUE_3 0x0028u // (R/W) Specifies the SPDIFIN user value register 3. [0x00]
|
||||
#define SPDIFIN_USER_VALUE_4 0x002Cu // (R/W) Specifies the SPDIFIN user value register 4. [0x00]
|
||||
#define SPDIFIN_CH_STATUS_0_1 0x0030u // (R/O) Specifies the SPDIFIN channel status register 0-1. [0x00]
|
||||
#define SPDIFIN_CH_STATUS_0_2 0x0034u // (R/O) Specifies the SPDIFIN channel status register 0-2. [0x00]
|
||||
#define SPDIFIN_CH_STATUS_0_3 0x0038u // (R/O) Specifies the SPDIFIN channel status register 0-3. [0x00]
|
||||
#define SPDIFIN_CH_STATUS_0_4 0x003Cu // (R/O) Specifies the SPDIFIN channel status register 0-4. [0x00]
|
||||
#define SPDIFIN_CH_STATUS_1 0x0040u // (R/O) Specifies the SPDIFIN channel status register 1. [0x00]
|
||||
#define SPDIFIN_FRAME_PERIOD_1 0x0048u // (R/O) Specifies the SPDIFIN frame period register 1. [0x00]
|
||||
#define SPDIFIN_FRAME_PERIOD_2 0x004Cu // (R/O) Specifies the SPDIFIN frame period register 2. [0x00]
|
||||
#define SPDIFIN_Pc_INFO_1 0x0050u // (R/O) Specifies the SPDIFIN PC info register 1. [0x00]
|
||||
#define SPDIFIN_Pc_INFO_2 0x0054u // (R/O) Specifies the SPDIFIN PC info register 2. [0x00]
|
||||
#define SPDIFIN_Pd_INFO_1 0x0058u // (R/O) Specifies the SPDIFIN PD info register 1. [0x00]
|
||||
#define SPDIFIN_Pd_INFO_2 0x005Cu // (R/O) Specifies the SPDIFIN PD Info register 2. [0x00]
|
||||
#define SPDIFIN_DATA_BUF_0_1 0x0060u // (R/O) Specifies the SPDIFIN data buffer register 0_1. [0x00]
|
||||
#define SPDIFIN_DATA_BUF_0_2 0x0064u // (R/O) Specifies the SPDIFIN data buffer register 0_2. [0x00]
|
||||
#define SPDIFIN_DATA_BUF_0_3 0x0068u // (R/O) Specifies the SPDIFIN data buffer register 0_3. [0x00]
|
||||
#define SPDIFIN_USER_BUF_0 0x006Cu // (R/O) Specifies the SPDIFIN user buffer register 0. [0x00]
|
||||
#define SPDIFIN_DATA_BUF_1_1 0x0070u // (R/O) Specifies the SPDIFIN data buffer register 1_1. [0x00]
|
||||
#define SPDIFIN_DATA_BUF_1_2 0x0074u // (R/O) Specifies the SPDIFIN data buffer register 1_2. [0x00]
|
||||
#define SPDIFIN_DATA_BUF_1_3 0x0078u // (R/O) Specifies the SPDIFIN data buffer register 1_3. [0x00]
|
||||
#define SPDIFIN_USER_BUF_1 0x007Cu // (R/O) Specifies the SPDIFIN user buffer register 1. [0x00]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - I2S Receiver Registers (I2S_BASE) -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define I2S_CLK_CON 0x0000u // (R/W) Specifies the I2S clock enable register. [0x00]
|
||||
#define I2S_CLK_CON_I2S_EN 0x01
|
||||
|
||||
#define I2S_CON_1 0x0004u // (R/W) Specifies the I2S control register 1. [0x00]
|
||||
#define I2S_CON_1_SCLK_POL_SHIFT 1 // SCLK polarity field (r_sc_pol) position
|
||||
#define I2S_CON_1_SCLK_POL_MASK 0x02 // SCLK polarity field (r_sc_pol)
|
||||
#define I2S_CON_1_SCLK_POL_FALLING_EDGE 0 // SDATA is syncrhonous to SCLK falling edge
|
||||
#define I2S_CON_1_SCLK_POL_RISING_EDGE 1 // SDATA is synchronous to SCLK rising edge
|
||||
|
||||
#define I2S_CON_1_LRCLK_POL_SHIFT 0 // LRCLK polarity field (r_ch_pol) position
|
||||
#define I2S_CON_1_LRCLK_POL_MASK 0x01 // LRCLK polarity field (r_ch_pol)
|
||||
#define I2S_CON_1_LRCLK_POL_LOW 0 // Left channel for low polarity
|
||||
#define I2S_CON_1_LRCLK_POL_HIGH 1 // Left channel for high polarity
|
||||
|
||||
#define I2S_CON_2 0x0008u // (R/W) Specifies the I2S control register 2. [0x16]
|
||||
#define I2S_CON_2_MLSB_SHIFT 6 // I2S bit order field position
|
||||
#define I2S_CON_2_MLSB_MASK 0x40
|
||||
#define I2S_CON_2_MLSB_MSB_FIRST 0 // MSB first mode
|
||||
#define I2S_CON_2_MLSB_LSB_FIRST 1 // LSB first mode
|
||||
|
||||
#define I2S_CON_2_BIT_CH_SHIFT 4 // Bit clock per frame field position
|
||||
#define I2S_CON_2_BIT_CH_MASK 0x30
|
||||
#define I2S_CON_2_BIT_CH_32FS 0 // Bit clock = 32*Fs
|
||||
#define I2S_CON_2_BIT_CH_48FS 1 // Bit clock = 48*Fs
|
||||
|
||||
#define I2S_CON_2_DATA_NUM_SHIFT 2 // Serial data bits per channel field position
|
||||
#define I2S_CON_2_DATA_NUM_MASK 0x0c
|
||||
#define I2S_CON_2_DATA_NUM_16_BITS 1 // 16 bits per channel
|
||||
#define I2S_CON_2_DATA_NUM_20_BITS 2 // 20 bits per channel
|
||||
#define I2S_CON_2_DATA_NUM_24_BITS 3 // 24 bits per channel
|
||||
|
||||
#define I2S_CON_2_I2S_MODE_SHIFT 0 // I2S mode field position
|
||||
#define I2S_CON_2_I2S_MODE_MASK 0x03
|
||||
#define I2S_CON_2_I2S_MODE_BASIC_FORMAT 0 // I2S basic format
|
||||
#define I2S_CON_2_I2S_MODE_LEFT_JUSTIFIED 2 // Left-justified format
|
||||
#define I2S_CON_2_I2S_MODE_RIGHT_JUSTIFIED 3 // Right-justified format
|
||||
|
||||
#define I2S_PIN_SEL_0 0x000Cu // (R/W) Specifies the I2S input pin selection register 0. [0x77]
|
||||
#define I2S_PIN_SEL_0_LRCLK_SHIFT 0
|
||||
#define I2S_PIN_SEL_0_LRCLK_MASK 0x07
|
||||
|
||||
#define I2S_PIN_SEL_0_SCLK_SHIFT 4
|
||||
#define I2S_PIN_SEL_0_SCLK_MASK 0x70
|
||||
|
||||
#define I2S_PIN_SEL_1 0x0010u // (R/W) Specifies the I2S input pin selection register 1. [0x77]
|
||||
#define I2S_PIN_SEL_1_SDATA0_SHIFT 0
|
||||
#define I2S_PIN_SEL_1_SDATA0_MASK 0x07
|
||||
|
||||
#define I2S_PIN_SEL_1_SDATA1_SHIFT 4
|
||||
#define I2S_PIN_SEL_1_SDATA1_MASK 0x70
|
||||
|
||||
#define I2S_PIN_SEL_2 0x0014u // (R/W) Specifies the I2S input pin selection register 2. [0x77]
|
||||
#define I2S_PIN_SEL_2_SDATA2_SHIFT 0
|
||||
#define I2S_PIN_SEL_2_SDATA2_MASK 0x07
|
||||
|
||||
#define I2S_PIN_SEL_2_SDATA3_SHIFT 4
|
||||
#define I2S_PIN_SEL_2_SDATA3_MASK 0x70
|
||||
|
||||
#define I2S_PIN_SEL_3 0x0018u // (R/W) Specifies the I2S input pin selection register 3. [0x07]
|
||||
#define I2S_PIN_SEL_3_DSD_D5_SHIFT 0
|
||||
#define I2S_PIN_SEL_3_DSD_D5_MASK 0x07
|
||||
|
||||
#define I2S_DSD_CON 0x001Cu // (R/W) Specifies the I2S DSD control register. [0x02]
|
||||
|
||||
#define I2S_IN_MUX_CON 0x0020u // (R/W) Specifies the I2S In/Mux control register. [0x60]
|
||||
#define I2S_IN_MUX_CON_F_NUM_SHIFT 5
|
||||
#define I2S_IN_MUX_CON_F_NUM_MASK 0xe0
|
||||
#define I2S_IN_MUX_CON_F_NUM_NONE 0 // Does not filter
|
||||
#define I2S_IN_MUX_CON_F_NUM_2 1 // 2-stage filter
|
||||
#define I2S_IN_MUX_CON_F_NUM_3 2 // 3-stage filter
|
||||
#define I2S_IN_MUX_CON_F_NUM_4 3 // 4-stage filter
|
||||
#define I2S_IN_MUX_CON_F_NUM_5 4 // 5-stage filter
|
||||
|
||||
#define I2S_IN_MUX_CON_IN_EN 0x10
|
||||
|
||||
#define I2S_IN_MUX_CON_AUDIO_SEL_SHIFT 2 // AUDIO_SEL field position
|
||||
#define I2S_IN_MUX_CON_AUDIO_SEL_MASK 0x0c
|
||||
#define I2S_IN_MUX_CON_AUDIO_SEL_SPDIF 0 // Selects SPDIF audio data
|
||||
#define I2S_IN_MUX_CON_AUDIO_SEL_I2S 1 // Selects I2S audio data
|
||||
#define I2S_IN_MUX_CON_AUDIO_SEL_DSD 2 // Selects DSD audio data
|
||||
|
||||
#define I2S_IN_MUX_CON_CUV_SEL_SHIFT 1 // CUV_SEL field position
|
||||
#define I2S_IN_MUX_CON_CUV_SEL_MASK 0x02
|
||||
#define I2S_IN_MUX_CON_CUV_SEL_SPDIF 0 // Selects SPDIF CUV data
|
||||
#define I2S_IN_MUX_CON_CUV_SEL_I2S 1 // Selects I2S CUV data
|
||||
|
||||
#define I2S_IN_MUX_CON_MUX_EN 0x01
|
||||
|
||||
#define I2S_CH_ST_CON 0x0024u // (R/W) Specifies the I2S channel status control register. [0x00]
|
||||
#define I2S_CH_ST_CON_RELOAD 0x01
|
||||
|
||||
#define I2S_CH_ST_REG_COUNT 5 // Number of channel status registers
|
||||
|
||||
#define I2S_CH_ST_0 0x0028u // (R/W) Specifies the I2S channel status block 0. [0x00]
|
||||
#define I2S_CH_ST_1 0x002Cu // (R/W) Specifies the I2S channel status block 1. [0x00]
|
||||
#define I2S_CH_ST_2 0x0030u // (R/W) Specifies the I2S channel status block 2. [0x00]
|
||||
#define I2S_CH_ST_3 0x0034u // (R/W) Specifies the I2S channel status block 3. [0x00]
|
||||
#define I2S_CH_ST_4 0x0038u // (R/W) Specifies the I2S channel status block 4. [0x00]
|
||||
|
||||
#define I2S_CH_ST_SH_0 0x003Cu // (R/O) Specifies the I2S channel status block shadow register 0. [0x00]
|
||||
#define I2S_CH_ST_SH_1 0x0040u // (R/O) Specifies the I2S channel status block shadow register 1. [0x00]
|
||||
#define I2S_CH_ST_SH_2 0x0044u // (R/O) Specifies the I2S channel status block shadow register 2. [0x00]
|
||||
#define I2S_CH_ST_SH_3 0x0048u // (R/O) Specifies the I2S channel status block shadow register 3. [0x00]
|
||||
#define I2S_CH_ST_SH_4 0x004Cu // (R/O) Specifies the I2S channel status block shadow register 4. [0x00]
|
||||
|
||||
#define I2S_VD_DATA 0x0050u // (R/W) Specifies the I2S audio sample validity register. [0x00]
|
||||
#define I2S_MUX_CH 0x0054u // (R/W) Specifies the I2S channel enable register. [0x03]
|
||||
|
||||
#define I2S_MUX_CUV 0x0058u // (R/W) Specifies the I2S CUV enable register. [0x03]
|
||||
#define I2S_MUX_CUV_R_EN 0x02
|
||||
#define I2S_MUX_CUV_L_EN 0x01
|
||||
|
||||
#define I2S_CH0_L_0 0x0064u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH0_L_1 0x0068u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH0_L_2 0x006Cu // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH0_L_3 0x0070u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH0_R_0 0x0074u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH0_R_1 0x0078u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH0_R_2 0x007Cu // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH0_R_3 0x0080u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH1_L_0 0x0084u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH1_L_1 0x0088u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH1_L_2 0x008Cu // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH1_L_3 0x0090u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH1_R_0 0x0094u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH1_R_1 0x0098u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH1_R_2 0x009Cu // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH1_R_3 0x00A0u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH2_L_0 0x00A4u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH2_L_1 0x00A8u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH2_L_2 0x00ACu // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH2_L_3 0x00B0u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH2_R_0 0x00B4u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH2_R_1 0x00B8u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH2_R_2 0x00BCu // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_Ch2_R_3 0x00C0u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH3_L_0 0x00C4u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH3_L_1 0x00C8u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH3_L_2 0x00CCu // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH3_R_0 0x00D0u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH3_R_1 0x00D4u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CH3_R_2 0x00D8u // (R/O) Specifies the I2S PCM output data register. [0x00]
|
||||
#define I2S_CUV_L_R 0x00DCu // (R/O) Specifies the I2S CUV output data register. [0x00]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - Timing Generator Registers (TG_BASE) -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define TG_CMD 0x0000u // (R/W) Specifies the command register. [0x00]
|
||||
#define TG_CMD_FIELD_EN 0x02 // Enables field mode (for interlaced formats)
|
||||
#define TG_CMD_TG_EN 0x01
|
||||
|
||||
#define TG_CFG 0x0004u // (R/W) Specifies the pixel repetition ratio. [0x00]
|
||||
|
||||
#define TG_H_FSZ_L 0x0018u // (R/W) Specifies the horizontal full size. [0x72]
|
||||
#define TG_H_FSZ_H 0x001Cu // (R/W) Specifies the horizontal full size. [0x06]
|
||||
|
||||
#define TG_HACT_ST_L 0x0020u // (R/W) Specifies the horizontal active start. [0x05]
|
||||
#define TG_HACT_ST_H 0x0024u // (R/W) Specifies the horizontal active start. [0x01]
|
||||
|
||||
#define TG_HACT_SZ_L 0x0028u // (R/W) Specifies the horizontal active size. [0x00]
|
||||
#define TG_HACT_SZ_H 0x002Cu // (R/W) Specifies the horizontal active size. [0x05]
|
||||
|
||||
#define TG_V_FSZ_L 0x0030u // (R/W) Specifies the vertical full line size. [0xEE]
|
||||
#define TG_V_FSZ_H 0x0034u // (R/W) Specifies the vertical full line size. [0x02]
|
||||
|
||||
#define TG_VSYNC_L 0x0038u // (R/W) Specifies the vertical sync position. [0x01]
|
||||
#define TG_VSYNC_H 0x003Cu // (R/W) Specifies the vertical sync position. [0x00]
|
||||
|
||||
#define TG_VSYNC2_L 0x0040u // (R/W) Specifies the vertical sync position for bottom field. [0x33]
|
||||
#define TG_VSYNC2_H 0x0044u // (R/W) Specifies the vertical sync position for bottom field. [0x02]
|
||||
|
||||
#define TG_VACT_ST_L 0x0048u // (R/W) Specifies the vertical sync active start position. [0x1a]
|
||||
#define TG_VACT_ST_H 0x004Cu // (R/W) Specifies the vertical sync active start position. [0x00]
|
||||
|
||||
#define TG_VACT_SZ_L 0x0050u // (R/W) Specifies the vertical active size. [0xd0]
|
||||
#define TG_VACT_SZ_H 0x0054u // (R/W) Specifies the vertical active size. [0x02]
|
||||
|
||||
#define TG_FIELD_CHG_L 0x0058u // (R/W) Specifies the HDMI field change position. [0x33]
|
||||
#define TG_FIELD_CHG_H 0x005Cu // (R/W) Specifies the HDMI field change position. [0x02]
|
||||
|
||||
#define TG_VACT_ST2_L 0x0060u // (R/W) Specifies the HDMI vertical active start position for bottom field. [0x48]
|
||||
#define TG_VACT_ST2_H 0x0064u // (R/W) Specifies the HDMI vertical active start position for bottom field. [0x02]
|
||||
|
||||
#define TG_VSYNC_TOP_HDMI_L 0x0078u // (R/W) Specifies the HDMI VSYNC position for top field. [0x01]
|
||||
#define TG_VSYNC_TOP_HDMI_H 0x007Cu // (R/W) Specifies the HDMI VSYNC position for top field. [0x00]
|
||||
|
||||
#define TG_VSYNC_BOT_HDMI_L 0x0080u // (R/W) Specifies the HDMI VSYNC position for bottom field. [0x33]
|
||||
#define TG_VSYNC_BOT_HDMI_H 0x0084u // (R/W) Specifies the HDMI VSYNC position for bottom field. [0x02]
|
||||
|
||||
#define TG_FIELD_TOP_HDMI_L 0x0088u // (R/W) Specifies the HDMI top field start position. [0x01]
|
||||
#define TG_FIELD_TOP_HDMI_H 0x008Cu // (R/W) Specifies the HDMI top field start position. [0x00]
|
||||
|
||||
#define TG_FIELD_BOT_HDMI_L 0x0090u // (R/W) Specifies the HDMI bottom field start position. [0X33]
|
||||
#define TG_FIELD_BOT_HDMI_H 0x0094u // (R/W) Specifies the HDMI bottom field start position. [0x02]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDCP E-Fuse Control Registers (eFUSE_BASE) -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define EFUSE_HDCP_CTRL 0x0000u // ( W) Specifies the HDCP e-fuse reading control. [0x00]
|
||||
#define EFUSE_HDCP_CTRL_HDCP_KEY_READ 0x01
|
||||
|
||||
#define EFUSE_HDCP_STATUS 0x0004u // (R/O) Specifies the HDCP e-fuse reading status. [0x00]
|
||||
#define EFUSE_HDCP_STATUS_ECC_FAIL 0x04
|
||||
#define EFUSE_HDCP_STATUS_ECC_BUSY 0x02
|
||||
#define EFUSE_HDCP_STATUS_ECC_DONE 0x01
|
||||
|
||||
#define EFUSE_ADDR_WIDTH 0x0008u // (R/W) Specifies the address width. [0x14]
|
||||
#define EFUSE_SIGDEV_ASSERT 0x000Cu // (R/W) Specifies the SIGDEV asserting position. [0x00]
|
||||
#define EFUSE_SIGDEV_DEASSERT 0x0010u // (R/W) Specifies the SIGDEV de-asserting position. [0x08]
|
||||
#define EFUSE_PRCHG_ASSERT 0x0014u // (R/W) Specifies the PRCHG asserting position. [0x00]
|
||||
#define EFUSE_PRCHG_DEASSERT 0x0018u // (R/W) Specifies the PRCHG de-asserting position. [0x0C]
|
||||
#define EFUSE_FSET_ASSERT 0x001Cu // (R/W) Specifies the FSET asserting position. [0x04]
|
||||
#define EFUSE_FSET_DEASSERT 0x0020u // (R/W) Specifies the FSET de-asserting position. [0x10]
|
||||
#define EFUSE_SENSING 0x0024u // (R/W) Specifies the sensing width. [0x14]
|
||||
#define EFUSE_SCK_ASSERT 0x0028u // (R/W) Specifies the SCK asserting position. [0x04]
|
||||
#define EFUSE_SCK_DEASSERT 0x002Cu // (R/W) Specifies the SCK de-asserting position. [0x0C]
|
||||
#define EFUSE_SDOUT_OFFSET 0x0030u // (R/W) Specifies the SDOUT offset. [0x10]
|
||||
#define EFUSE_READ_OFFSET 0x0034u // (R/W) Specifies the READ offset. [0x14]
|
||||
|
||||
#define EFUSE_HDCP_SW_KEY 0x0040u // (R/W) Specifies the software-provided HDCP test key.
|
||||
#define EFUSE_HDCP_KEY_CTRL 0x0580u // (R/W) Specifies the HDCP key control register.
|
||||
#define EFUSE_HDCP_KEY_CTRL_WRITE_KEY 0x01
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDMI CEC Registers (CEC_BASE) -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define CEC_TX_STATUS_0 0x0000u // (R/O) Specifies the CEC TX status #0. [0x00]
|
||||
#define CEC_TX_STATUS_1 0x0004u // (R/O) Specifies the CEC TX status #1. [0x00]
|
||||
#define CEC_RX_STATUS_0 0x0008u // (R/O) Specifies the CEC RX status #0. [0x00]
|
||||
#define CEC_RX_STATUS_1 0x000Cu // (R/O) Specifies the CEC Rx status #1. [0x00]
|
||||
#define CEC_INTR_MASK 0x0010u // (R/W) Specifies the CEC interrupt masking control. [0x00]
|
||||
#define CEC_INTR_CLEAR 0x0014u // (R/W) Specifies the CEC interrupt clearing control. [0x00]
|
||||
#define CEC_LOGIC_ADDR 0x0020u // (R/W) Specifies the HDMI Tx logical address. [0x0F]
|
||||
#define CEC_DIVISOR_0 0x0030u // (R/W) Specifies the divisor used in counting 0.05ms. [0x00]
|
||||
#define CEC_DIVISOR_1 0x0034u // (R/W) Specifies the divisor used in counting 0.05ms. [0x00]
|
||||
#define CEC_DIVISOR_2 0x0038u // (R/W) Specifies the divisor used in counting 0.05ms. [0x00]
|
||||
#define CEC_DIVISOR_3 0x003Cu // (R/W) Specifies the divisor used in counting 0.05ms. [0x00]
|
||||
#define CEC_TX_CTRL 0x0040u // (R/W) Specifies the CEC Tx control. [0x50]
|
||||
#define CEC_TX_BYTE_NUM 0x0044u // (R/W) Specifies the number of blocks in a message that has to be sent. [0x00]
|
||||
#define CEC_TX_STATUS_2 0x0060u // (R/O) Specifies the CEC Tx status #2. [0x00]
|
||||
#define CEC_TX_STATUS_3 0x0064u // (R/O) Specifies the CEC Tx status #3. [0x00]
|
||||
#define CEC_TX_BUFFER_0 0x0080u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_1 0x0084u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_2 0x0088u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_3 0x008Cu // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_4 0x0090u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_5 0x0094u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_6 0x0098u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_7 0x009Cu // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_8 0x00A0u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_9 0x00A4u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_10 0x00A8u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_11 0x00ACu // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_12 0x00B0u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_13 0x00B4u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_14 0x00B8u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_TX_BUFFER_15 0x00BCu // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_CTRL 0x00C0u // (R/W) Specifies the CEC RX control. [0x00]
|
||||
#define CEC_RX_STATUS_2 0x00E0u // (R/O) Specifies the CEC RX status #2. [0x00]
|
||||
#define CEC_RX_STATUS_3 0x00E4u // (R/O) Specifies the CEC RX status #3. [0x00]
|
||||
#define CEC_RX_BUFFER_0 0x0100u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_1 0x0104u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_2 0x0108u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_3 0x010Cu // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_4 0x0110u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_5 0x0114u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_6 0x0118u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_7 0x011Cu // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_8 0x0120u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_9 0x0124u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_10 0x0128u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_11 0x012Cu // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_12 0x0130u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_13 0x0134u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_14 0x0138u // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_RX_BUFFER_15 0x013Cu // (R/W) Specifies the byte #0 to #15 of CEC message. [0x00]
|
||||
#define CEC_FILTER_CTRL 0x0180u // (R/W) Specifies the CEC filter control. [0x81]
|
||||
#define CEC_FILTER_TH 0x0184u // (R/W) Specifies the filter threshold value. [0x03]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - Control Registers (CTRL_BASE) -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define CTRL_INTC_CON_1 0x0010u // (R/W) Interrupt Control Register 1 [0x00]
|
||||
|
||||
#define CTRL_INTC_FLAG_1 0x0014u // (R/W) Interrupt Flag Register 1 [0x00]
|
||||
|
||||
#define CTRL_PHY_STATUS_0 0x0020u // (R/O) PHY status Register 0 [0x00]
|
||||
#define CTRL_PHY_STATUS_0_PHY_READY 0x1
|
||||
|
||||
#define CTRL_PHY_STATUS_CMU 0x0024u // (R/O) PHY CMU status Register [0x00]
|
||||
|
||||
#define CTRL_PHY_STATUS_PLL 0x0028u // (R/O) PHY PLL status Register [0x00]
|
||||
|
||||
#define CTRL_PHY_CON_0 0x0030u // (R/W) PHY Control Register [0x01]
|
||||
#define CTRL_PHY_CON_0_PHY_PWR_OFF 0x01
|
||||
|
||||
#define CTRL_HPD_CTRL 0x0040u // (R/W) HPD Signal Control Register [0x02]
|
||||
|
||||
#define CTRL_HPD_ST 0x0044u // (R/W) HPD Status Register [0x00]
|
||||
|
||||
#define CTRL_HPD_TH_x 0x0050u // (R/W) HPD filter threshold value Register [0x00]
|
||||
|
||||
#define CTRL_AUDIO_CLKSEL 0x0070u // (R/W) Selects the audio system clock. [0x01]
|
||||
|
||||
#define CTRL_PHY_RSTOUT 0x0074u // (R/W) Specifies the HDMI PHY reset out. [0x01]
|
||||
|
||||
#define CTRL_PHY_VPLL 0x0078u // (R/O) Specifies the HDMI PHY VPLL monitor. [0x00]
|
||||
|
||||
#define CTRL_PHY_CMU 0x007Cu // (R/O) Specifies the HDMI PHY CMU monitor. [0x00]
|
||||
|
||||
#define CTRL_CORE_RSTOUT 0x0080u // (R/W) Specifies the HDMI TX core software reset. [0x01]
|
||||
|
||||
#define CTRL_HDMI_VERSION_0 0x0100u // (R/O) Specifies the HDMI_LINK Version information. HDMI_VERSION[7:0] [0x08]
|
||||
#define CTRL_HDMI_VERSION_1 0x0104u // (R/O) Specifies the HDMI_LINK Version information. HDMI_VERSION[15:8] [0x00]
|
||||
#define CTRL_HDMI_VERSION_2 0x0108u // (R/O) Specifies the HDMI_LINK Version information. HDMI_VERSION[23:16] [0x00]
|
||||
#define CTRL_HDMI_VERSION_3 0x010Cu // (R/O) Specifies the HDMI_LINK Version information. HDMI_VERSION[31:24] [0x00]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDMI Video Related Registers -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// HDMI_CON_0 definitions
|
||||
#define HDMI_CON_0_YCBCR422_SEL 0x08 // YCbCr Video Input Mode (0=4:4:4, 1=4:2:2)
|
||||
|
||||
#define HDMI_V2_BLANK_0 0x00B0u // (R/W) Specifies the vertical blanking setting. [0x00]
|
||||
#define HDMI_V2_BLANK_1 0x00B4u // (R/W) Specifies the vertical blanking setting. [0x00]
|
||||
#define HDMI_V1_BLANK_0 0x00B8u // (R/W) Specifies the vertical blanking setting. [0x00]
|
||||
#define HDMI_V1_BLANK_1 0x00BCu // (R/W) Specifies the vertical blanking setting. [0x00]
|
||||
|
||||
#define HDMI_V_LINE_0 0x00C0u // (R/W) Specifies the horizontal line setting. [0x00]
|
||||
#define HDMI_V_LINE_1 0x00C4u // (R/W) Specifies the horizontal line setting. [0x00]
|
||||
#define HDMI_H_LINE_0 0x00C8u // (R/W) Specifies the vertical line setting. [0x00]
|
||||
#define HDMI_H_LINE_1 0x00CCu // (R/W) Specifies the vertical line setting. [0x00]
|
||||
|
||||
#define HDMI_HSYNC_POL 0x00E0u // (R/W) Specifies the Horizontal sync polarity control register [0x00]
|
||||
|
||||
#define HDMI_V_BLANK_F0_0 0x0110u // (R/W) Specifies the vertical blanking setting for bottom field. [0xff]
|
||||
#define HDMI_V_BLANK_F0_1 0x0114u // (R/W) Specifies the vertical blanking setting for bottom field. [0x1f]
|
||||
#define HDMI_V_BLANK_F1_0 0x0118u // (R/W) Specifies the vertical blanking setting for bottom field. [0xff]
|
||||
#define HDMI_V_BLANK_F1_1 0x011Cu // (R/W) Specifies the vertical blanking setting for bottom field. [0x1f]
|
||||
|
||||
#define HDMI_H_SYNC_START_0 0x0120u // (R/W) Specifies Horizontal sync generation setting [0x00]
|
||||
#define HDMI_H_SYNC_START_1 0x0124u // (R/W) Specifies Horizontal sync generation setting [0x00]
|
||||
|
||||
#define HDMI_H_SYNC_END_0 0x0128u // (R/W) Specifies Horizontal sync generation setting [0x00]
|
||||
#define HDMI_H_SYNC_END_1 0x012Cu // (R/W) Specifies Horizontal sync generation setting [0x00]
|
||||
|
||||
#define HDMI_V_SYNC_LINE_BEF_2_0 0x0130u // (R/W) Specifies Vertical sync generation for top field or frame [0xff]
|
||||
#define HDMI_V_SYNC_LINE_BEF_2_1 0x0134u // (R/W) Specifies Vertical sync generation for top field or frame [0x1f]
|
||||
#define HDMI_V_SYNC_LINE_BEF_1_0 0x0138u // (R/W) Specifies Vertical sync generation for top field or frame [0xff]
|
||||
#define HDMI_V_SYNC_LINE_BEF_1_1 0x013Cu // (R/W) Specifies Vertical sync generation for top field or frame [0x1f]
|
||||
|
||||
#define HDMI_V_SYNC_LINE_AFT_2_0 0x0140u // (R/W) Specifies Vertical sync generation for bottom field - vertical position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_2_1 0x0144u // (R/W) Specifies Vertical sync generation for bottom field - vertical position [0x1f]
|
||||
#define HDMI_V_SYNC_LINE_AFT_1_0 0x0148u // (R/W) Specifies Vertical sync generation for bottom field - vertical position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_1_1 0x014Cu // (R/W) Specifies Vertical sync generation for bottom field - vertical position [0x1f]
|
||||
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_2_0 0x0150u // (R/W) Specifies Vertical sync generation for bottom field - horizontal position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_2_1 0x0154u // (R/W) Specifies Vertical sync generation for bottom field - horizontal position [0x1f]
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_1_0 0x0158u // (R/W) Specifies Vertical sync generation for bottom field - horizontal position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_1_1 0x015Cu // (R/W) Specifies Vertical sync generation for bottom field - horizontal position [0x1f]
|
||||
|
||||
#define HDMI_V_BLANK_F2_0 0x0160u // (R/W) Specifies Vertical blanking setting for third field [0xff]
|
||||
#define HDMI_V_BLANK_F2_1 0x0164u // (R/W) Specifies Vertical blanking setting for third field [0x1f]
|
||||
#define HDMI_V_BLANK_F3_0 0x0168u // (R/W) Specifies Vertical blanking setting for thrid field [0xff]
|
||||
#define HDMI_V_BLANK_F3_1 0x016Cu // (R/W) Specifies Vertical blanking setting for thrid field [0x1f]
|
||||
|
||||
#define HDMI_V_BLANK_F4_0 0x0170u // (R/W) Specifies Vertical blanking setting for fourth field [0xff]
|
||||
#define HDMI_V_BLANK_F4_1 0x0174u // (R/W) Specifies Vertical blanking setting for fourth field [0x1f]
|
||||
#define HDMI_V_BLANK_F5_0 0x0178u // (R/W) Specifies Vertical blanking setting for fourth field [0xff]
|
||||
#define HDMI_V_BLANK_F5_1 0x017Cu // (R/W) Specifies Vertical blanking setting for fourth field [0x1f]
|
||||
|
||||
#define HDMI_V_SYNC_LINE_AFT_3_0 0x0180u // (R/W) Specifies Vertical sync generation for third field - vertical position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_3_1 0x0184u // (R/W) Specifies Vertical sync generation for third field - vertical position [0x1f]
|
||||
#define HDMI_V_SYNC_LINE_AFT_4_0 0x0188u // (R/W) Specifies Vertical sync generation for third field - vertical position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_4_1 0x018Cu // (R/W) Specifies Vertical sync generation for third field - vertical position [0x1f]
|
||||
|
||||
#define HDMI_V_SYNC_LINE_AFT_5_0 0x0190u // (R/W) Specifies Vertical sync generation for fourth field - vertical position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_5_1 0x0194u // (R/W) Specifies Vertical sync generation for fourth field - vertical position [0x1f]
|
||||
#define HDMI_V_SYNC_LINE_AFT_6_0 0x0198u // (R/W) Specifies Vertical sync generation for fourth field - vertical position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_6_1 0x019Cu // (R/W) Specifies Vertical sync generation for fourth field - vertical position [0x1f]
|
||||
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_3_0 0x01A0u // (R/W) Specifies Vertical sync generation for third field - horizontal position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_3_1 0x01A4u // (R/W) Specifies Vertical sync generation for third field - horizontal position [0x1f]
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_4_0 0x01A8u // (R/W) Specifies Vertical sync generation for third field - horizontal position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_4_1 0x01ACu // (R/W) Specifies Vertical sync generation for third field - horizontal position [0x1f]
|
||||
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_5_0 0x01B0u // (R/W) Specifies Vertical sync generation for fourth field - horizontal position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_5_1 0x01B4u // (R/W) Specifies Vertical sync generation for fourth field - horizontal position [0x1f]
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_6_0 0x01B8u // (R/W) Specifies Vertical sync generation for fourth field - horizontal position [0xff]
|
||||
#define HDMI_V_SYNC_LINE_AFT_PXL_6_1 0x01BCu // (R/W) Specifies Vertical sync generation for fourth field - horizontal position [0x1f]
|
||||
|
||||
#define HDMI_VACT_SPACE1_0 0x01C0u // (R/W) Specifies 1st Vertical Active Space start line [0xff]
|
||||
#define HDMI_VACT_SPACE1_1 0x01C4u // (R/W) Specifies 1st Vertical Active Space end line [0x1f]
|
||||
#define HDMI_VACT_SPACE2_0 0x01C8u // (R/W) Specifies 1st Vertical Active Space start line [0xff]
|
||||
#define HDMI_VACT_SPACE2_1 0x01CCu // (R/W) Specifies 1st Vertical Active Space end line [0x1f]
|
||||
|
||||
#define HDMI_VACT_SPACE3_0 0x01D0u // (R/W) Specifies 2nd Vertical Active Space start line [0xff]
|
||||
#define HDMI_VACT_SPACE3_1 0x01D4u // (R/W) Specifies 2nd Vertical Active Space end line [0x1f]
|
||||
#define HDMI_VACT_SPACE4_0 0x01D8u // (R/W) Specifies 2nd Vertical Active Space start line [0xff]
|
||||
#define HDMI_VACT_SPACE4_1 0x01DCu // (R/W) Specifies 2nd Vertical Active Space end line [0x1f]
|
||||
|
||||
#define HDMI_VACT_SPACE5_0 0x01E0u // (R/W) Specifies 3rd Vertical Active Space start line [0xff]
|
||||
#define HDMI_VACT_SPACE5_1 0x01E4u // (R/W) Specifies 3rd Vertical Active Space end line [0x1f]
|
||||
#define HDMI_VACT_SPACE6_0 0x01E8u // (R/W) Specifies 3rd Vertical Active Space start line [0xff]
|
||||
#define HDMI_VACT_SPACE6_1 0x01ECu // (R/W) Specifies 3rd Vertical Active Space end line [0x1f]
|
||||
|
||||
#define HDMI_GCP_CON 0x0200u // (R/W) Specifies GCP packet control register [0x04]
|
||||
#define HDMI_GCP_BYTE1 0x0210u // (R/W) Specifies GCP packet body [0x00]
|
||||
#define HDMI_GCP_BYTE2 0x0214u // (R/W) Specifies GCP packet body [0x00]
|
||||
#define HDMI_GCP_BYTE3 0x0218u // (R/W) Specifies GCP packet body [0x00]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDMI Audio Related Registers -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define HDMI_ASP_CON 0x0300u // (R/W) Specifies the ASP packet control register. [0x00]
|
||||
#define HDMI_ASP_SP_FLAT 0x0304u // (R/W) Specifies the ASP packet sp_flat bit control. [0x00]
|
||||
#define HDMI_ASP_CHCFG0 0x0310u // (R/W) Specifies the ASP audio channel configuration. [0x08]
|
||||
#define HDMI_ASP_CHCFG1 0x0314u // (R/W) Specifies the ASP audio channel configuration. [0x1a]
|
||||
#define HDMI_ASP_CHCFG2 0x0318u // (R/W) Specifies the ASP audio channel configuration. [0x2c]
|
||||
#define HDMI_ASP_CHCFG3 0x031Cu // (R/W) Specifies the ASP audio channel configuration. [0x3e]
|
||||
|
||||
#define HDMI_ACR_CON 0x0400u // (R/W) Specifies the ACR packet control register. [0x00]
|
||||
|
||||
#define HDMI_ACR_MCTS0 0x0410u // (R/W) Specifies the measured CTS value. [0x01]
|
||||
#define HDMI_ACR_MCTS1 0x0414u // (R/W) Specifies the measured CTS value. [0x00]
|
||||
#define HDMI_ACR_MCTS2 0x0418u // (R/W) Specifies the measured CTS value. [0x00]
|
||||
|
||||
#define HDMI_ACR_N0 0x0430u // (R/W) Specifies the N value for ACR packet. [0xe8]
|
||||
#define HDMI_ACR_N1 0x0434u // (R/W) Specifies the N value for ACR packet. [0x03]
|
||||
#define HDMI_ACR_N2 0x0438u // (R/W) Specifies the N value for ACR packet. [0x00]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDMI Packet Related Registers -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define HDMI_ACP_CON 0x0500u // (R/W) Specifies the ACP packet control register. [0x00]
|
||||
#define HDMI_ACP_TYPE 0x0514u // (R/W) Specifies the ACP packet header. [0x00]
|
||||
#define HDMI_ACP_DATA00 0x0520u // (R/W) Specifies the ACP packet body. [0x00]
|
||||
|
||||
#define HDMI_ISRC_CON 0x0600u // (R/W) Specifies the ACR packet control register. [0x00]
|
||||
#define HDMI_ISRC1_HEADER1 0x0614u // (R/W) Specifies the ISCR1 packet header. [0x00]
|
||||
#define HDMI_ISRC1_DATA00 0x0620u // (R/W) Specifies the ISRC1 packet body. [0x00]
|
||||
#define HDMI_ISRC2_DATA00 0x06A0u // (R/W) Specifies the ISRC2 packet body. [0x00]
|
||||
|
||||
#define HDMI_AVI_CON 0x0700u // (R/W) Specifies the AVI packet control register. [0x00]
|
||||
#define HDMI_AVI_HEADER0 0x0710u // (R/W) Specifies the AVI packet header. [0x00]
|
||||
#define HDMI_AVI_HEADER1 0x0714u // (R/W) Specifies the AVI packet header. [0x00]
|
||||
#define HDMI_AVI_HEADER2 0x0718u // (R/W) Specifies the AVI packet header. [0x00]
|
||||
#define HDMI_AVI_CHECK_SUM 0x071Cu // (R/W) Specifies the AVI packet checksum. [0x00]
|
||||
#define HDMI_AVI_BYTE01 0x0720u // (R/W) Specifies the AVI packet body. [0x00]
|
||||
|
||||
#define HDMI_AUI_CON 0x0800u // (R/W) Specifies the AUI packet control register. [0x00]
|
||||
#define HDMI_AUI_HEADER0 0x0810u // (R/W) Specifies AUI packet header. [0x00]
|
||||
#define HDMI_AUI_HEADER1 0x0814u // (R/W) Specifies AUI packet header. [0x00]
|
||||
#define HDMI_AUI_HEADER2 0x0818u // (R/W) Specifies AUI packet header. [0x00]
|
||||
#define HDMI_AUI_CHECK_SUM 0x081Cu // (R/W) Specifies the AUI packet checksum. [0x00]
|
||||
#define HDMI_AUI_BYTE1 0x0820u // (R/W) Specifies the AUI packet body. [0x00]
|
||||
|
||||
#define HDMI_MPG_CON 0x0900u // (R/W) Specifies the ACR packet control register. [0x00]
|
||||
#define HDMI_MPG_CHECK_SUM 0x091Cu // (R/W) Specifies the MPG packet checksum. [0x00]
|
||||
#define HDMI_MPG_BYTE1 0x0920u // (R/W) Specifies the MPG packet body. [0x00]
|
||||
|
||||
#define HDMI_SPD_CON 0x0A00u // (R/W) Specifies the SPD packet control register. [0x00]
|
||||
#define HDMI_SPD_HEADER0 0x0A10u // (R/W) Specifies the SPD packet header. [0x00]
|
||||
#define HDMI_SPD_HEADER1 0x0A14u // (R/W) Specifies the SPD packet header. [0x00]
|
||||
#define HDMI_SPD_HEADER2 0x0A18u // (R/W) Specifies the SPD packet header. [0x00]
|
||||
#define HDMI_SPD_DATA00 0x0A20u // (R/W) Specifies the SPD packet checksum. [0x00]
|
||||
#define HDMI_SPD_DATA01 0x0A24u // (R/W) Specifies the SPD packet body. [0x00]
|
||||
|
||||
#define HDMI_GAMUT_CON 0x0B00u // (R/W) Specifies GAMUT packet control register. [0x00]
|
||||
#define HDMI_GAMUT_HEADER0 0x0B10u // (R/W) Specifies GAMUT packet header. [0x00]
|
||||
#define HDMI_GAMUT_HEADER1 0x0B14u // (R/W) Specifies GAMUT packet header. [0x00]
|
||||
#define HDMI_GAMUT_HEADER2 0x0B18u // (R/W) Specifies GAMUT packet header. [0x00]
|
||||
#define HDMI_GAMUT_METADATA00 0x0B20u // (R/W) Specifies GAMUT packet body. [0x00]
|
||||
|
||||
#define HDMI_VSI_CON 0x0C00u // (R/W) Specifies VSI packet control register. [0x00]
|
||||
#define HDMI_VSI_HEADER0 0x0C10u // (R/W) Specifies VSI packet header. [0x00]
|
||||
#define HDMI_VSI_HEADER1 0x0C14u // (R/W) Specifies VSI packet header. [0x00]
|
||||
#define HDMI_VSI_HEADER2 0x0C18u // (R/W) Specifies VSI packet header. [0x00]
|
||||
#define HDMI_VSI_DATA00 0x0C20u // (R/W) Specifies VSI packet checksum. [0x00]
|
||||
#define HDMI_VSI_DATA01 0x0C24u // (R/W) Specifies VSI packet body. [0x00]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - HDMI Miscellaneous Registers -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define HDMI_DC_CONTROL 0x0D00u // (R/W) Specifies Deep Color Control Register [0x00]
|
||||
|
||||
#define HDMI_VIDEO_PATTERN_GEN 0x0D04u // (R/W) Specifies Video Pattern Generation Register [0x00]
|
||||
|
||||
#define HDMI_An_Seed_Sel 0x0E48u // (R/W) An seed selection register [0xFF]
|
||||
#define HDMI_An_Seed_0 0x0E58u // (R/W) An seed value register [0x00]
|
||||
#define HDMI_An_Seed_1 0x0E5Cu // (R/W) An seed value register [0x00]
|
||||
#define HDMI_An_Seed_2 0x0E60u // (R/W) An seed value register [0x00]
|
||||
#define HDMI_An_Seed_3 0x0E64u // (R/W) An seed value register [0x00]
|
||||
|
||||
#define HDMI_RGB_ROUND_EN 0xD500u // (R/W) Specifies round enable for 8/10 bit R/G/B in video_receiver [0x00]
|
||||
|
||||
#define HDMI_VACT_SPACE_R_0 0xD504u // (R/W) Specifies vertical active space R [0x00]
|
||||
#define HDMI_VACT_SPACE_R_1 0xD508u // (R/W) Specifies vertical active space R [0x00]
|
||||
#define HDMI_VACT_SPACE_G_0 0xD50Cu // (R/W) Specifies vertical active space G [0x00]
|
||||
#define HDMI_VACT_SPACE_G_1 0xD510u // (R/W) Specifies vertical active space G [0x00]
|
||||
#define HDMI_VACT_SPACE_B_0 0xD514u // (R/W) Specifies vertical active space B [0x00]
|
||||
#define HDMI_VACT_SPACE_B_1 0xD518u // (R/W) Specifies vertical active space B [0x00]
|
||||
|
||||
#define HDMI_BLUE_SCREEN_R_0 0xD520u // (R/W) Specifies R Pixel values for blue screen [3:0] [0x00]
|
||||
#define HDMI_BLUE_SCREEN_R_1 0xD524u // (R/W) Specifies R Pixel values for blue screen [11:4] [0x00]
|
||||
#define HDMI_BLUE_SCREEN_G_0 0xD528u // (R/W) Specifies G Pixel values for blue screen [3:0] [0x00]
|
||||
#define HDMI_BLUE_SCREEN_G_1 0xD52Cu // (R/W) Specifies G Pixel values for blue screen [11:4] [0x00]
|
||||
#define HDMI_BLUE_SCREEN_B_0 0xD530u // (R/W) Specifies B Pixel values for blue screen [3:0] [0x00]
|
||||
#define HDMI_BLUE_SCREEN_B_1 0xD534u // (R/W) Specifies B Pixel values for blue screen [11:4] [0x00]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - Timing Generator Registers (TG_BASE) -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#define TG_VACT_ST3_L 0x0068u // (R/W) Specifies the HDMI vertical active start position for 3rd bottom field. [0x7B]
|
||||
#define TG_VACT_ST3_H 0x006Cu // (R/W) Specifies the HDMI vertical active start position for 3rd bottom field. [0x04]
|
||||
|
||||
#define TG_VACT_ST4_L 0x0070u // (R/W) Specifies the HDMI vertical active start position for 4th bottom field. [0xAE]
|
||||
#define TG_VACT_ST4_H 0x0074u // (R/W) Specifies the HDMI vertical active start position for 4th bottom field. [0x06]
|
||||
|
||||
#define TG_3D_FP 0x00F0u // (R/W) Specifies the Stereoscopy timing enable [0x00]
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// MARK: - I2C Bridge / HDMI PHY Registers (I2C_BASE) -
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// Note: Most IIC definitions based on AppleS5L8900XI2C/AppleS5L8747XI2C, which is the same controller
|
||||
|
||||
#define IICCON 0x0000u // (R/W) Control register [0x0000_0000]
|
||||
#define kIICConAckGen (0x00000080)
|
||||
#define kIICConBusHold (0x00000010)
|
||||
|
||||
#define IICSTAT 0x0004u // (R/W) Control/status register [0x0000_0000]
|
||||
#define kIICStatMaster (0x00000080)
|
||||
#define kIICStatTx (0x00000040)
|
||||
#define kIICStatBB (0x00000020)
|
||||
#define kIICStatSOE (0x00000010)
|
||||
#define kIICStatLRB (0x00000001)
|
||||
|
||||
#define IICADD 0x0008u // (R/W) Bus address register [0x0000_0000]
|
||||
#define IICDS 0x000Cu // (R/W) Transmit/receive data shift register [0x0000_0000]
|
||||
#define FIFOCON 0x0018u // (R/W) Tx/Rx FIFO control register [0x0000_0000]
|
||||
#define FIFOSTAT 0x001Cu // (R/W) Tx/Rx FIFO status register [0x0000_0000]
|
||||
|
||||
#define IICINT 0x0020u // (R/W) Interrupt status register [0x0000_X000]
|
||||
#define kIICIntAll (0x00003F00u)
|
||||
#define kIICIntStop (0x00002000u)
|
||||
#define kIICIntStart (0x00001000u)
|
||||
#define kIICIntTx (0x00000800u)
|
||||
#define kIICIntRx (0x00000400u)
|
||||
#define kIICIntTimeOut (0x00000200u)
|
||||
#define kIICIntBusHold (0x00000100u)
|
||||
|
||||
#define IICVER 0x0024u // (R/O) Version register [0x0000_0007]
|
||||
#define SW_RESET 0x002Cu // (R/W) Software reset register [0x0000_0000]
|
||||
#define kIICSwReset (0x00000001)
|
||||
|
||||
#define IICBUSCON 0x0030u // (R/W) Bus control register [0x0000_0000]
|
||||
#define TIMEOUT_CON 0x0034u // (R/W) Internal timer setting register [0xFFFF_FFFF]
|
||||
|
||||
#define HDMIPHY_ID 0x0080u // (R/W) I2C device ID of HDMI PHY [0x0000_0000]
|
||||
|
||||
#define HDMIPHYCON_STAT 0x0084u // (R/O) Status of write operation to HDMIPHYCON0~8 [0x0000_0000]
|
||||
#define HDMIPHYCON_STAT_IN_PROGRESS 0x1
|
||||
|
||||
#define HDMIPHYCON0 0x80088 // (R/W) Reg00~Reg03 of HDMI PHY [0x101F_9101]
|
||||
#define HDMIPHYCON1 0x8008C // (R/W) Reg04~Reg07 of HDMI PHY [0x08EF_5B40]
|
||||
#define HDMIPHYCON2 0x80090 // (R/W) Reg08~Reg0B of HDMI PHY [0xD8B9_2081]
|
||||
#define HDMIPHYCON3 0x80094 // (R/W) Reg0C~Reg0F of HDMI PHY [0x80AC_A045]
|
||||
#define HDMIPHYCON4 0x80098 // (R/W) Reg10~Reg13 of HDMI PHY [0x8412_8008]
|
||||
#define HDMIPHYCON5 0x8009C // (R/W) Reg14~Reg17 of HDMI PHY [0x8624_2408]
|
||||
#define HDMIPHYCON6 0x800A0 // (R/W) Reg18~Reg1B of HDMI PHY [0x0124_A654]
|
||||
#define HDMIPHYCON7 0x800A4 // (R/W) Reg1C~Reg1E of HDMI PHY [0x0001_0000]
|
||||
#define HDMIPHYCON8 0x800A8 // (R/W) Reg1F of HDMI PHY [0x0000_0080]
|
||||
|
||||
#endif /* !_REGS_H */
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (C) 2012 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
GLOBAL_INCLUDES +=
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/hdmi.o \
|
||||
$(LOCAL_DIR)/hdmi_static_config.o
|
||||
@@ -0,0 +1,507 @@
|
||||
/*
|
||||
* Copyright (C) 2008-2015 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/mipi.h>
|
||||
#include <platform.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <target/gpiodef.h>
|
||||
|
||||
#include "dsim.h"
|
||||
|
||||
#define DISPLAY_CONFIG_PLL_P(x) (((x) >> 26) & 0x03F)
|
||||
#define DISPLAY_CONFIG_PLL_M(x) (((x) >> 16) & 0x3FF)
|
||||
#define DISPLAY_CONFIG_PLL_S(x) (((x) >> 12) & 0x007)
|
||||
#define DISPLAY_CONFIG_PLL_B(x) (((x) >> 8) & 0x00F)
|
||||
#define DISPLAY_CONFIG_ESC_DIV(x) (((x) >> 4) & 0x00F)
|
||||
#define DISPLAY_CONFIG_LANES(x) (((x) >> 0) & 0x00F)
|
||||
|
||||
#define DSIM_LANE_MASK ((1 << DSIM_LANE_COUNT) - 1)
|
||||
|
||||
static u_int32_t lane_count;
|
||||
static u_int32_t lane_mask;
|
||||
static uint32_t esc_clock_div;
|
||||
|
||||
static bool dsim_enabled;
|
||||
|
||||
int mipi_dsim_init(struct display_timing *timing, enum colorspace color)
|
||||
{
|
||||
bool video_mode = true;
|
||||
u_int32_t tmp, pll_config, pix_format, afc_code = 0;
|
||||
u_int32_t config = rDSIM_CONFIG_HfpMode;
|
||||
bool afc_enable = false;
|
||||
uint32_t display_config;
|
||||
|
||||
dprintf(DEBUG_CRITICAL, "mipi_dsim_init()\n");
|
||||
|
||||
memcpy(&display_config, timing->display_config, sizeof(display_config));
|
||||
// Extract Lane configuration
|
||||
lane_count = DISPLAY_CONFIG_LANES(display_config);
|
||||
lane_mask = (1 << lane_count) - 1;
|
||||
|
||||
// Extract PLL configuration
|
||||
pll_config = (rDSIM_PLLCTRL_P(DISPLAY_CONFIG_PLL_P(display_config)) |
|
||||
rDSIM_PLLCTRL_M(DISPLAY_CONFIG_PLL_M(display_config)) |
|
||||
rDSIM_PLLCTRL_S(DISPLAY_CONFIG_PLL_S(display_config)));
|
||||
|
||||
// Extract Pixel Format
|
||||
if (timing->display_depth <= 18) pix_format = 5;
|
||||
else pix_format = 7;
|
||||
|
||||
//Extract escape clock divisor
|
||||
esc_clock_div = DISPLAY_CONFIG_ESC_DIV(display_config);
|
||||
|
||||
clock_gate(CLK_MIPI, true);
|
||||
|
||||
// Configure clock selections
|
||||
rDSIM_CLKCTRL = (rDSIM_CLKCTRL_EscClkEn |
|
||||
((pll_config == 0) ? rDSIM_CLKCTRL_PllBypass : 0) |
|
||||
rDSIM_CLKCTRL_ByteClkSrc((pll_config == 0) ? 1 : 0) | // SOC or DSIM PLL
|
||||
rDSIM_CLKCTRL_EscPrescalar(DISPLAY_CONFIG_ESC_DIV(display_config)));
|
||||
|
||||
// Select frequency band
|
||||
rDSIM_PLLCTRL = rDSIM_PLLCTRL_FreqBand(DISPLAY_CONFIG_PLL_B(display_config));
|
||||
|
||||
#ifdef TARGET_DSIM_THS_PREPARE
|
||||
//Adjust tHS-PREPARE on the phy
|
||||
rDSIM_PLLCTRL |= rDSIM_PLLCTRL_PreprCtl(TARGET_DSIM_THS_PREPARE);
|
||||
#endif //TARGET_DSIM_THS_PREPARE
|
||||
|
||||
// Configure PLL if needed
|
||||
if (pll_config != 0) {
|
||||
#if DSIM_VERSION == 1
|
||||
u_int32_t fin_pll;
|
||||
|
||||
// Assume that AFC will be used
|
||||
afc_enable = true;
|
||||
|
||||
// Set the AFC code in PHYACCHR
|
||||
fin_pll = clock_get_frequency(CLK_NCLK) / (1000000 * DISPLAY_CONFIG_PLL_P(display_config));
|
||||
|
||||
// These code values are only for the 45nm PHY (i.e. DSIM_VERSION == 1)
|
||||
switch (fin_pll) {
|
||||
case 6: afc_code = 1; break;
|
||||
case 7: afc_code = 0; break;
|
||||
case 8: afc_code = 3; break;
|
||||
case 9: afc_code = 2; break;
|
||||
case 10: afc_code = 5; break;
|
||||
case 11: afc_code = 4; break;
|
||||
case 12: afc_code = 4; break;
|
||||
default : afc_enable = false; break;
|
||||
}
|
||||
#endif
|
||||
|
||||
// If needed, enable AFC
|
||||
if (afc_enable) {
|
||||
rDSIM_PHYACCHR = rDSIM_PHYACCHR_AFC(afc_code) | rDSIM_PHYACCHR_AFC_ENABLE;
|
||||
}
|
||||
|
||||
rDSIM_PLLTMR = 300000; // 1ms - HACK: assuming 300MHz hperf2
|
||||
|
||||
rDSIM_PLLCTRL |= pll_config;
|
||||
rDSIM_PLLCTRL |= rDSIM_PLLCTRL_PllEn;
|
||||
|
||||
while ((rDSIM_STATUS & rDSIM_STATUS_PllStable) == 0);
|
||||
}
|
||||
|
||||
// Issue software reset
|
||||
rDSIM_SWRST = rDSIM_SWRST_SwRst;
|
||||
|
||||
// If needed, enable AFC again
|
||||
if (afc_enable) {
|
||||
// PLL must be off to change AFC setting
|
||||
rDSIM_PLLCTRL &= ~rDSIM_PLLCTRL_PllEn;
|
||||
|
||||
rDSIM_PHYACCHR = rDSIM_PHYACCHR_AFC(afc_code) | rDSIM_PHYACCHR_AFC_ENABLE;
|
||||
|
||||
// Turn PLL back on
|
||||
rDSIM_PLLCTRL |= rDSIM_PLLCTRL_PllEn;
|
||||
}
|
||||
|
||||
// Wait for software reset to complete
|
||||
while ((rDSIM_STATUS & rDSIM_STATUS_SwRstRls) == 0);
|
||||
|
||||
#ifdef TARGET_DSIM_DPHYCTL
|
||||
rDSIM_PHYACCHR |= rDSIM_PHYACCHR_DPHYCTL(TARGET_DSIM_DPHYCTL);
|
||||
#endif // TARGET_DSIM_DPHYCTL
|
||||
|
||||
#if TARGET_DSIM_DOWN_CODE
|
||||
rDSIM_PHYACCHR |= rDSIM_PHYACCHR_DOWN_CODE(TARGET_DSIM_DOWN_CODE);
|
||||
rDSIM_PHYACCHR2 |= rDSIM_PHYACCHR2_DOWN_CODE(TARGET_DSIM_DOWN_CODE);
|
||||
#endif // TARGET_DSIM_DOWN_CODE
|
||||
|
||||
#ifdef TARGET_DSIM_UP_CODE
|
||||
rDSIM_PHYACCHR |= rDSIM_PHYACCHR_UP_CODE(TARGET_DSIM_UP_CODE);
|
||||
rDSIM_PHYACCHR2 |= rDSIM_PHYACCHR2_UP_CODE(TARGET_DSIM_UP_CODE);
|
||||
#endif // TARGET_DSIM_UP_CODE
|
||||
|
||||
#ifdef TARGET_DSIM_SUPPRESS
|
||||
rDSIM_SUPPRESS |= TARGET_DSIM_SUPPRESS;
|
||||
#endif // TARGET_DSIM_SUPPRESS
|
||||
|
||||
// Use the same resolution as CLCD
|
||||
rDSIM_MDRESOL = (rDSIM_MDRESOL_MainVResol(timing->v_active) |
|
||||
rDSIM_MDRESOL_MainHResol(timing->h_active));
|
||||
|
||||
#ifdef TARGET_DISP_VIDEO_MODE
|
||||
video_mode = TARGET_DISP_VIDEO_MODE;
|
||||
#endif //TARGET_DISP_VIDEO_MODE
|
||||
|
||||
if (video_mode) {
|
||||
// The vertical blanking settings are the same as the CLCD settings
|
||||
rDSIM_MVPORCH = (rDSIM_MVPORCH_CmdAllow(13) |
|
||||
rDSIM_MVPORCH_StableVfp(timing->v_front_porch) |
|
||||
rDSIM_MVPORCH_MainVbp(timing->v_back_porch));
|
||||
rDSIM_MSYNC = (timing->v_pulse_width << 22);
|
||||
|
||||
// The horizontal blanking settings are constants which are
|
||||
// sufficent for all lane counts, frequencies and CLCD settings
|
||||
// Hfp = 15
|
||||
// Hbp = 14
|
||||
// Hsa = 1
|
||||
rDSIM_MHPORCH = (15 << 16) | (14 << 0);
|
||||
rDSIM_MSYNC |= (1 << 0);
|
||||
}
|
||||
#if DSIM_VERSION == 3
|
||||
else {
|
||||
rDSIM_I80_LPVALID_ST = (timing->h_active * 3) + 100;
|
||||
}
|
||||
#endif // DSIM_VERSION == 3
|
||||
|
||||
rDSIM_SSCNT = 0xa;
|
||||
|
||||
#ifdef TARGET_DSIM_CONFIG
|
||||
config = TARGET_DSIM_CONFIG;
|
||||
#endif
|
||||
|
||||
rDSIM_CONFIG = (rDSIM_CONFIG_BurstMode |
|
||||
rDSIM_CONFIG_AutoMode |
|
||||
config |
|
||||
rDSIM_CONFIG_MainPixFormat(pix_format) |
|
||||
rDSIM_CONFIG_NumOfDatLane(DSIM_LANE_COUNT - 1) |
|
||||
rDSIM_CONFIG_LaneEn(DSIM_LANE_MASK) |
|
||||
rDSIM_CONFIG_LaneClkEn);
|
||||
if (video_mode) {
|
||||
rDSIM_CONFIG |= rDSIM_CONFIG_VideoMode;
|
||||
}
|
||||
|
||||
#ifdef TARGET_NO_BURST_MODE
|
||||
if (TARGET_NO_BURST_MODE) {
|
||||
rDSIM_CONFIG &= ~rDSIM_CONFIG_BurstMode;
|
||||
}
|
||||
#endif
|
||||
rDSIM_CLKCTRL |= (rDSIM_CLKCTRL_ByteClkEn |
|
||||
rDSIM_CLKCTRL_LaneEscClkEn(DSIM_LANE_MASK) |
|
||||
rDSIM_CLKCTRL_LaneEscClkEnClk);
|
||||
|
||||
rDSIM_FIFOCTRL = 0x1F;
|
||||
rDSIM_FIFOTHLD = 0x1FF;
|
||||
|
||||
// Force Stop state on all lanes
|
||||
rDSIM_ESCMODE = (rDSIM_ESCMODE_CmdLpdt | rDSIM_ESCMODE_ForceStopstate);
|
||||
spin(1 * 1000);
|
||||
rDSIM_ESCMODE &= ~rDSIM_ESCMODE_ForceStopstate;
|
||||
|
||||
// Wait for Stop state on all lanes
|
||||
tmp = rDSIM_STATUS_StopstateClk | rDSIM_STATUS_StopstateDat(DSIM_LANE_MASK);
|
||||
while ((rDSIM_STATUS & tmp) != tmp);
|
||||
|
||||
// Request ULPS mode on all lanes
|
||||
rDSIM_ESCMODE = (rDSIM_ESCMODE_CmdLpdt | rDSIM_ESCMODE_TxUlpsClk | rDSIM_ESCMODE_TxUlpsDat);
|
||||
|
||||
// Wait for ULPS mode on all lanes
|
||||
tmp = rDSIM_STATUS_UlpsClk | rDSIM_STATUS_UlpsDat(DSIM_LANE_MASK);
|
||||
while ((rDSIM_STATUS & tmp) != tmp);
|
||||
|
||||
// Set the lane configuration
|
||||
rDSIM_CONFIG &= ~(rDSIM_CONFIG_NumOfDatLaneMsk | rDSIM_CONFIG_LaneEnMsk);
|
||||
rDSIM_CONFIG |= rDSIM_CONFIG_NumOfDatLane(lane_count - 1) | rDSIM_CONFIG_LaneEn(lane_mask);
|
||||
|
||||
// Enable the configured lanes
|
||||
rDSIM_CLKCTRL &= ~rDSIM_CLKCTRL_LaneEscClkEnMsk;
|
||||
rDSIM_CLKCTRL |= rDSIM_CLKCTRL_LaneEscClkEn(lane_mask);
|
||||
|
||||
// Request exit ULPS mode on configured lanes
|
||||
rDSIM_ESCMODE |= (rDSIM_ESCMODE_TxUlpsClkExit | rDSIM_ESCMODE_TxUlpsExit);
|
||||
|
||||
// Wait for exit ULPS mode on configured lanes
|
||||
tmp = rDSIM_STATUS_UlpsClk | rDSIM_STATUS_UlpsDat(lane_mask);
|
||||
while ((rDSIM_STATUS & tmp) != 0);
|
||||
|
||||
// Clear exit ULPS mode request and ULPS mode request
|
||||
rDSIM_ESCMODE &= ~(rDSIM_ESCMODE_TxUlpsClkExit | rDSIM_ESCMODE_TxUlpsExit);
|
||||
spin(1 * 1000);
|
||||
rDSIM_ESCMODE &= ~(rDSIM_ESCMODE_TxUlpsClk | rDSIM_ESCMODE_TxUlpsDat);
|
||||
|
||||
// Wait for Stop state on configured lanes
|
||||
tmp = rDSIM_STATUS_StopstateClk | rDSIM_STATUS_StopstateDat(lane_mask);
|
||||
while ((rDSIM_STATUS & tmp) != tmp);
|
||||
|
||||
#if DSIM_VERSION == 3
|
||||
if (!video_mode) {
|
||||
rDSIM_ULPSIN = TARGET_DSI_ULPS_IN_DELAY;
|
||||
rDSIM_ULPSEND = TARGET_DSI_ULPS_END_DELAY;
|
||||
rDSIM_ULPSOUT = TARGET_DSI_ULPS_OUT_DELAY;
|
||||
|
||||
//<rdar://problem/18037708> SkiHillVail12S5356c: panic(cpu 0 caller 0x855223df): "_waitUntilPayloadFifoIsEmpty: Timeout Waiting for payload fifo to empty"
|
||||
rDSIM_ESCMODE |= rDSIM_ESCMODE_Auto_Ulps_Clk;
|
||||
}
|
||||
|
||||
#endif //DSIM_VERSION == 3
|
||||
|
||||
dsim_enabled = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mipi_dsim_quiesce(void)
|
||||
{
|
||||
u_int32_t tmp, pllctrl, phyacchr;
|
||||
|
||||
dprintf(DEBUG_CRITICAL, "mipi_dsim_quiesce()\n");
|
||||
|
||||
if (!dsim_enabled) return 0;
|
||||
|
||||
// Save the PLLCTRL and PHYACCHR settings before software reset
|
||||
pllctrl = rDSIM_PLLCTRL;
|
||||
phyacchr = rDSIM_PHYACCHR;
|
||||
|
||||
// Issue software reset
|
||||
rDSIM_SWRST = rDSIM_SWRST_SwRst;
|
||||
|
||||
// Turn off the PLL if it was on
|
||||
rDSIM_PLLCTRL = pllctrl & ~rDSIM_PLLCTRL_PllEn;
|
||||
|
||||
// Restore PHYACCHR setting
|
||||
rDSIM_PHYACCHR = phyacchr;
|
||||
|
||||
// If the PLL was on, turn it back on
|
||||
rDSIM_PLLCTRL = pllctrl;
|
||||
|
||||
// Wait for reset to complete
|
||||
while ((rDSIM_STATUS & rDSIM_STATUS_SwRstRls) == 0);
|
||||
|
||||
// Set the lane configuration
|
||||
rDSIM_CONFIG &= ~(rDSIM_CONFIG_NumOfDatLaneMsk | rDSIM_CONFIG_LaneEnMsk);
|
||||
rDSIM_CONFIG |= (rDSIM_CONFIG_NumOfDatLane(DSIM_LANE_COUNT - 1) |
|
||||
rDSIM_CONFIG_LaneEn(DSIM_LANE_MASK) |
|
||||
rDSIM_CONFIG_LaneClkEn);
|
||||
|
||||
// Enable the configured lanes
|
||||
rDSIM_CLKCTRL &= ~(rDSIM_CLKCTRL_TxRequestHsClk | rDSIM_CLKCTRL_LaneEscClkEnMsk);
|
||||
rDSIM_CLKCTRL |= rDSIM_CLKCTRL_LaneEscClkEn(DSIM_LANE_MASK);
|
||||
|
||||
// Force Stop state on all lanes
|
||||
rDSIM_ESCMODE = (rDSIM_ESCMODE_CmdLpdt | rDSIM_ESCMODE_ForceStopstate);
|
||||
spin(1 * 1000);
|
||||
rDSIM_ESCMODE &= ~rDSIM_ESCMODE_ForceStopstate;
|
||||
|
||||
// Wait for Stop state on all lanes
|
||||
tmp = rDSIM_STATUS_StopstateClk | rDSIM_STATUS_StopstateDat(DSIM_LANE_MASK);
|
||||
while ((rDSIM_STATUS & tmp) != tmp);
|
||||
|
||||
// Request ULPS mode on all lanes
|
||||
rDSIM_ESCMODE = (rDSIM_ESCMODE_CmdLpdt | rDSIM_ESCMODE_TxUlpsClk | rDSIM_ESCMODE_TxUlpsDat);
|
||||
|
||||
// Wait for ULPS mode on all lanes
|
||||
tmp = rDSIM_STATUS_UlpsClk | rDSIM_STATUS_UlpsDat(DSIM_LANE_MASK);
|
||||
while ((rDSIM_STATUS & tmp) != tmp);
|
||||
|
||||
// Turn off internal clocks
|
||||
rDSIM_CLKCTRL = 0x00000000;
|
||||
rDSIM_CONFIG = rDSIM_CONFIG_VideoMode;
|
||||
rDSIM_ESCMODE = 0x00000000;
|
||||
rDSIM_PLLCTRL = 0x00000000;
|
||||
|
||||
clock_gate(CLK_MIPI, false);
|
||||
|
||||
dsim_enabled = false;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mipi_dsim_enable_high_speed(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
rDSIM_CLKCTRL |= rDSIM_CLKCTRL_TxRequestHsClk;
|
||||
while ((rDSIM_STATUS & rDSIM_STATUS_TxReadyHsClk) == 0);
|
||||
} else {
|
||||
rDSIM_CLKCTRL &= ~rDSIM_CLKCTRL_TxRequestHsClk;
|
||||
while ((rDSIM_STATUS & rDSIM_STATUS_TxReadyHsClk) != 0);
|
||||
}
|
||||
}
|
||||
|
||||
void mipi_dsim_enable_video(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
rDSIM_MDRESOL |= rDSIM_MDRESOL_MainStandby;
|
||||
} else {
|
||||
rDSIM_MDRESOL &= ~rDSIM_MDRESOL_MainStandby;
|
||||
}
|
||||
}
|
||||
|
||||
int mipi_dsim_send_short_command(u_int8_t cmd, u_int8_t data0, u_int8_t data1)
|
||||
{
|
||||
uint32_t escape_clock_period_us;
|
||||
uint32_t mipi_byte_clock_frequency;
|
||||
|
||||
mipi_byte_clock_frequency = clock_get_frequency(CLK_MIPI)/ 8;
|
||||
escape_clock_period_us = (100000000 * esc_clock_div) /mipi_byte_clock_frequency;
|
||||
escape_clock_period_us = (escape_clock_period_us/100) < 1 ? 1 : (escape_clock_period_us/100);
|
||||
|
||||
rDSIM_PKTHDR = (cmd & 0x3f) | (((u_int32_t)data0) << 8) | (((u_int32_t)data1) << 16);
|
||||
|
||||
//10 ESC clocks before checking the status bit.
|
||||
spin (10 * escape_clock_period_us);
|
||||
|
||||
//check for command header to have been sent
|
||||
while ((rDSIM_FIFOCTRL & rDSIM_FIFOCTRL_EmptyHSfr) == 0);
|
||||
//check for command payload to have been sent
|
||||
while ((rDSIM_FIFOCTRL & rDSIM_FIFOCTRL_EmptyLSfr) == 0);
|
||||
|
||||
spin(22 + ((343 * 1000000 * esc_clock_div)/mipi_byte_clock_frequency));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mipi_dsim_send_long_command(u_int8_t cmd, const u_int8_t *data, u_int32_t length)
|
||||
{
|
||||
u_int32_t cnt, payload = 0;
|
||||
|
||||
for (cnt = 0; cnt < length; cnt++) {
|
||||
payload = (payload >> 8) | ((u_int32_t)data[cnt] << 24);
|
||||
if ((cnt & 3) == 3) {
|
||||
rDSIM_PAYLOAD = payload;
|
||||
payload = 0;
|
||||
}
|
||||
}
|
||||
if (payload) {
|
||||
payload >>= 32 - ((length & 3) * 8);
|
||||
rDSIM_PAYLOAD = payload;
|
||||
}
|
||||
|
||||
for (cnt = 0; cnt < 5; cnt++) {
|
||||
rDSIM_PAYLOAD = 0;
|
||||
}
|
||||
|
||||
length += 20;
|
||||
return mipi_dsim_send_short_command(cmd, length & 0xff, (length >> 8) & 0xff);
|
||||
}
|
||||
|
||||
int mipi_dsim_read_short_command(u_int8_t cmd, u_int8_t *data)
|
||||
{
|
||||
u_int32_t tmp, i = 0;
|
||||
|
||||
// Clear pending interrupts
|
||||
rDSIM_INTSRC = 0xffffffff;
|
||||
|
||||
mipi_dsim_send_short_command(cmd, data[0], data[1]);
|
||||
|
||||
while (1) {
|
||||
tmp = rDSIM_INTSRC;
|
||||
|
||||
if (tmp & rDSIM_INTSRC_RxAck) return -1;
|
||||
if (tmp & rDSIM_INTSRC_LpdrTout) return -1;
|
||||
// Ignore errors for now (not all drivers do ECC)
|
||||
// if (tmp & rDSIM_INTSRC_AnyError) return -1;
|
||||
|
||||
if (tmp & rDSIM_INTSRC_RxDatDone) break;
|
||||
|
||||
// Hardware timeout depends on having a receiver, and
|
||||
// completing BTA. This isn't guaranteed for dev boards.
|
||||
if (++i == 5) {
|
||||
dprintf(DEBUG_CRITICAL, "mipi: timing out\n");
|
||||
return -1;
|
||||
}
|
||||
spin(50 * 1000);
|
||||
}
|
||||
|
||||
while (rDSIM_FIFOCTRL & rDSIM_FIFOCTRL_EmptyRx);
|
||||
|
||||
tmp = rDSIM_RXFIFO;
|
||||
|
||||
switch (tmp & 0x3f) {
|
||||
case DSIM_RSP_READ_1B:
|
||||
case DSIM_RSP_DSC_READ_1B:
|
||||
data[0] = (tmp >> 8) & 0xff;
|
||||
data[1] = 0;
|
||||
break;
|
||||
case DSIM_RSP_READ_2B:
|
||||
case DSIM_RSP_DSC_READ_2B:
|
||||
data[0] = (tmp >> 8) & 0xff;
|
||||
data[1] = (tmp >> 16) & 0xff;
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mipi_dsim_read_long_command(u_int8_t cmd, u_int8_t *data, u_int32_t *length)
|
||||
{
|
||||
u_int32_t tmp, len, maxlen, i = 0;
|
||||
|
||||
maxlen = *length;
|
||||
|
||||
// Clear pending interrupts
|
||||
rDSIM_INTSRC = 0xffffffff;
|
||||
|
||||
mipi_dsim_send_short_command(cmd, data[0], data[1]);
|
||||
|
||||
while (1) {
|
||||
tmp = rDSIM_INTSRC;
|
||||
|
||||
if (tmp & rDSIM_INTSRC_RxAck) return -1;
|
||||
if (tmp & rDSIM_INTSRC_LpdrTout) return -1;
|
||||
// Ignore errors for now (not all drivers do ECC)
|
||||
// if (tmp & rDSIM_INTSRC_AnyError) return -1;
|
||||
|
||||
if (tmp & rDSIM_INTSRC_RxDatDone) break;
|
||||
|
||||
// Hardware timeout depends on having a receiver, and
|
||||
// completing BTA. This isn't guaranteed for dev boards.
|
||||
if (++i == 5) {
|
||||
dprintf(DEBUG_CRITICAL, "mipi: timing out\n");
|
||||
return -1;
|
||||
}
|
||||
spin(50 * 1000);
|
||||
}
|
||||
|
||||
while (rDSIM_FIFOCTRL & rDSIM_FIFOCTRL_EmptyRx);
|
||||
|
||||
tmp = rDSIM_RXFIFO;
|
||||
|
||||
switch (tmp & 0x3f) {
|
||||
case DSIM_RSP_LONG_READ:
|
||||
case DSIM_RSP_DSC_LONG_READ:
|
||||
break;
|
||||
default:
|
||||
dprintf(DEBUG_CRITICAL, "mipi: weird response %08x\n", tmp);
|
||||
return -1;
|
||||
}
|
||||
|
||||
len = (tmp >> 8) & 0xffff;
|
||||
if (len < maxlen)
|
||||
*length = len;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if ((i % 4) == 0) {
|
||||
while (rDSIM_FIFOCTRL & rDSIM_FIFOCTRL_EmptyRx);
|
||||
tmp = rDSIM_RXFIFO;
|
||||
}
|
||||
if (i < maxlen)
|
||||
data[i] = tmp & 0xff;
|
||||
tmp >>= 8;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,171 @@
|
||||
/*
|
||||
* Copyright (C) 2008-2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __SAMSUNG_DSIM_H
|
||||
#define __SAMSUNG_DSIM_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rDSIM_STATUS (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00))
|
||||
#define rDSIM_STATUS_PllStable (0x80000000)
|
||||
#define rDSIM_STATUS_SwRstRls (0x00100000)
|
||||
#define rDSIM_STATUS_Direction (0x00010000)
|
||||
#define rDSIM_STATUS_TxReadyHsClk (0x00000400)
|
||||
#define rDSIM_STATUS_UlpsClk (0x00000200)
|
||||
#define rDSIM_STATUS_StopstateClk (0x00000100)
|
||||
#define rDSIM_STATUS_UlpsDatMsk (0xf << 4)
|
||||
#define rDSIM_STATUS_UlpsDat(d) (((d) & 0xf) << 4)
|
||||
#define rDSIM_STATUS_StopstateDatMsk (0xf << 0)
|
||||
#define rDSIM_STATUS_StopstateDat(d) (((d) & 0xf) << 0)
|
||||
#define rDSIM_SWRST (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x04))
|
||||
#define rDSIM_SWRST_FuncRst (0x00010000)
|
||||
#define rDSIM_SWRST_SwRst (0x00000001)
|
||||
#define rDSIM_CLKCTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x08))
|
||||
#define rDSIM_CLKCTRL_TxRequestHsClk (0x80000000)
|
||||
#define rDSIM_CLKCTRL_EscClkEn (0x10000000)
|
||||
#define rDSIM_CLKCTRL_PllBypass (0x08000000)
|
||||
#define rDSIM_CLKCTRL_ByteClkSrcMsk (0x3 << 25)
|
||||
#define rDSIM_CLKCTRL_ByteClkSrc(d) (((d) & 0x3) << 25)
|
||||
#define rDSIM_CLKCTRL_ByteClkEn (0x01000000)
|
||||
#define rDSIM_CLKCTRL_LaneEscClkEnMsk (0xf << 20)
|
||||
#define rDSIM_CLKCTRL_LaneEscClkEn(d) (((d) & 0xf) << 20)
|
||||
#define rDSIM_CLKCTRL_LaneEscClkEnClk (0x00080000)
|
||||
#define rDSIM_CLKCTRL_EscPrescalar(d) ((d) & 0xffff)
|
||||
#define rDSIM_TIMEOUT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0C))
|
||||
#define rDSIM_CONFIG (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x10))
|
||||
#define rDSIM_CONFIG_DPDN_Test_En (0x80000000)
|
||||
#define rDSIM_CONFIG_TxTypeSfr (0x10000000)
|
||||
#define rDSIM_CONFIG_SyncInform (0x08000000)
|
||||
#define rDSIM_CONFIG_BurstMode (0x04000000)
|
||||
#define rDSIM_CONFIG_VideoMode (0x02000000)
|
||||
#define rDSIM_CONFIG_AutoMode (0x01000000)
|
||||
#define rDSIM_CONFIG_HseMode (0x00800000)
|
||||
#define rDSIM_CONFIG_HfpMode (0x00400000)
|
||||
#define rDSIM_CONFIG_HbpMode (0x00200000)
|
||||
#define rDSIM_CONFIG_HsaMode (0x00100000)
|
||||
#define rDSIM_CONFIG_MainVc(d) (((d) & 0x3) << 18)
|
||||
#define rDSIM_CONFIG_MainPixFormat(d) (((d) & 0x7) << 12)
|
||||
#define rDSIM_CONFIG_NumOfDatLaneMsk (0x3 << 5)
|
||||
#define rDSIM_CONFIG_NumOfDatLane(d) (((d) & 0x3) << 5)
|
||||
#define rDSIM_CONFIG_LaneEnMsk (0xf << 1)
|
||||
#define rDSIM_CONFIG_LaneEn(d) (((d) & 0xf) << 1)
|
||||
#define rDSIM_CONFIG_LaneClkEn (0x00000001)
|
||||
#define rDSIM_ESCMODE (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x14))
|
||||
#define rDSIM_ESCMODE_ForceStopstate (0x00100000)
|
||||
#define rDSIM_ESCMODE_ForceBTA (0x00010000)
|
||||
#if DSIM_VERSION == 3
|
||||
#define rDSIM_ESCMODE_Auto_Ulps_Data (1 << 9)
|
||||
#define rDSIM_ESCMODE_Auto_Ulps_Clk (1 << 8)
|
||||
#endif // DSIM_VERSION == 3
|
||||
#define rDSIM_ESCMODE_CmdLpdt (0x00000080)
|
||||
#define rDSIM_ESCMODE_TxLpdt (0x00000040)
|
||||
#define rDSIM_ESCMODE_TxTriggerRst (0x00000010)
|
||||
#define rDSIM_ESCMODE_TxUlpsDat (0x00000008)
|
||||
#define rDSIM_ESCMODE_TxUlpsExit (0x00000004)
|
||||
#define rDSIM_ESCMODE_TxUlpsClk (0x00000002)
|
||||
#define rDSIM_ESCMODE_TxUlpsClkExit (0x00000001)
|
||||
#define rDSIM_MDRESOL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x18))
|
||||
#define rDSIM_MDRESOL_MainStandby (0x80000000)
|
||||
#define rDSIM_MDRESOL_MainVResol(d) (((d) & 0x7ff) << 16)
|
||||
#define rDSIM_MDRESOL_MainHResol(d) ((d) & 0x7ff)
|
||||
#define rDSIM_MVPORCH (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x1C))
|
||||
#define rDSIM_MVPORCH_CmdAllow(d) (((d) & 0xf) << 28)
|
||||
#define rDSIM_MVPORCH_StableVfp(d) (((d) & 0x7ff) << 16)
|
||||
#define rDSIM_MVPORCH_MainVbp(d) ((d) & 0x7ff)
|
||||
#define rDSIM_MHPORCH (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x20))
|
||||
#define rDSIM_MSYNC (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x24))
|
||||
#define rDSIM_SSCNT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x28))
|
||||
#define rDSIM_INTSRC (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x2C))
|
||||
#define rDSIM_INTSRC_SwRstRelease (0x40000000)
|
||||
#define rDSIM_INTSRC_PllStable (0x80000000)
|
||||
#define rDSIM_INTSRC_LpdrTout (0x00200000)
|
||||
#define rDSIM_INTSRC_RxDatDone (0x00040000)
|
||||
#define rDSIM_INTSRC_RxAck (0x00010000)
|
||||
#define rDSIM_INTSRC_AnyError (0x0000ffff)
|
||||
#define rDSIM_INTMSK (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x30))
|
||||
#define rDSIM_PKTHDR (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x34))
|
||||
#define rDSIM_PAYLOAD (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x38))
|
||||
#define rDSIM_RXFIFO (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x3C))
|
||||
#define rDSIM_FIFOTHLD (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x40))
|
||||
#define rDSIM_FIFOCTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x44))
|
||||
#define rDSIM_FIFOCTRL_FullRx (0x02000000)
|
||||
#define rDSIM_FIFOCTRL_EmptyRx (0x01000000)
|
||||
#define rDSIM_FIFOCTRL_FullHSfr (0x00800000)
|
||||
#define rDSIM_FIFOCTRL_EmptyHSfr (0x00400000)
|
||||
#define rDSIM_FIFOCTRL_FullLSfr (0x00200000)
|
||||
#define rDSIM_FIFOCTRL_EmptyLSfr (0x00100000)
|
||||
#define rDSIM_FIFOCTRL_FullHI80 (0x00080000)
|
||||
#define rDSIM_FIFOCTRL_EmptyHI80 (0x00040000)
|
||||
#define rDSIM_FIFOCTRL_FullLI870 (0x00020000)
|
||||
#define rDSIM_FIFOCTRL_EmptyLI80 (0x00010000)
|
||||
#define rDSIM_FIFOCTRL_FullHMain (0x00000800)
|
||||
#define rDSIM_FIFOCTRL_EmptyHMain (0x00000400)
|
||||
#define rDSIM_FIFOCTRL_FullLMain (0x00000200)
|
||||
#define rDSIM_FIFOCTRL_EmptyLMain (0x00000100)
|
||||
#define rDSIM_FIFOCTRL_nInitRx (0x00000010)
|
||||
#define rDSIM_FIFOCTRL_nInitSfr (0x00000008)
|
||||
#define rDSIM_FIFOCTRL_nInitI80 (0x00000004)
|
||||
#define rDSIM_FIFOCTRL_nInitMain (0x00000001)
|
||||
#define rDSIM_MEMACCHR (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x48))
|
||||
#define rDSIM_PLLCTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x4C))
|
||||
#define rDSIM_PLLCTRL_HSzeroCtl(d) (((d) & 0xf) << 28)
|
||||
#define rDSIM_PLLCTRL_FreqBand(d) (((d) & 0xf) << 24)
|
||||
#define rDSIM_PLLCTRL_PllEn (0x00800000)
|
||||
#define rDSIM_PLLCTRL_PreprCtl(d) (((d) & 0x7) << 20)
|
||||
#if DSIM_VERSION == 0
|
||||
#define rDSIM_PLLCTRL_P(d) (((d) & 0x3f) << 14)
|
||||
#define rDSIM_PLLCTRL_M(d) (((d) & 0x3ff) << 4)
|
||||
#else
|
||||
#define rDSIM_PLLCTRL_P(d) (((d) & 0x3f) << 13)
|
||||
#define rDSIM_PLLCTRL_M(d) (((d) & 0x1ff) << 4)
|
||||
#endif
|
||||
#define rDSIM_PLLCTRL_S(d) (((d) & 0x7) << 1)
|
||||
#define rDSIM_PLLCTRL_DpDnSwap (0x00000001)
|
||||
#define rDSIM_PLLTMR (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x50))
|
||||
#define rDSIM_PHYACCHR (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x54))
|
||||
#if DSIM_VERSION < 2
|
||||
#define rDSIM_PHYACCHR_UP_CODE(d) (((d) & 0xc) << (26 - 2))
|
||||
#else
|
||||
#define rDSIM_PHYACCHR_UP_CODE(d) (0 << 0)
|
||||
#endif
|
||||
#define rDSIM_PHYACCHR_AFC_ENABLE (0x00004000)
|
||||
#define rDSIM_PHYACCHR_DPHYCTL(d) (((d) & 0x3f) << 8)
|
||||
#define rDSIM_PHYACCHR_AFC(d) (((d) & 0x7) << 5)
|
||||
#if DSIM_VERSION < 2
|
||||
#define rDSIM_PHYACCHR_DOWN_CODE(d) (((d) & 0x1) << (3 - 0))
|
||||
#else
|
||||
#define rDSIM_PHYACCHR_DOWN_CODE(d) (0 << 0) //NOOP
|
||||
#endif
|
||||
#define rDSIM_PHYACCHR2 (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x58))
|
||||
#if DSIM_VERSION < 2
|
||||
#define rDSIM_PHYACCHR2_UP_CODE(d) ((((d) & 0x2) << (17 - 1)) | (((d) & 0x1) << (8 - 0)))
|
||||
#define rDSIM_PHYACCHR2_DOWN_CODE(d) (0 << 0) //NOOP
|
||||
#else
|
||||
#define rDSIM_PHYACCHR2_UP_CODE(d) (((d) & 0x7) << 19)
|
||||
#define rDSIM_PHYACCHR2_DOWN_CODE(d) (((d) & 0x7) << 4)
|
||||
#endif
|
||||
#define rDSIM_PHYACCHR2_PrprCtlClk(d) (((d) & 0x7) << 16)
|
||||
|
||||
#if DSIM_VERSION == 3
|
||||
#define rDSIM_ULPSIN (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x60))
|
||||
#define rDSIM_ULPSOUT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x64))
|
||||
#define rDSIM_ULPSEND (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x68))
|
||||
#endif //DSIM_VERSION == 3
|
||||
|
||||
#define rDSIM_SUPPRESS (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x6C))
|
||||
#define rDSIM_SUPPRESS_Line_Timeout_Disable (0x00000001)
|
||||
|
||||
#if DSIM_VERSION == 3
|
||||
#define rDSIM_I80_LPVALID_ST (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x70))
|
||||
#endif //DSIM_VERSION == 3
|
||||
|
||||
#define rDSIM_VERINFO (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0C))
|
||||
|
||||
#endif /* __SAMSUNG_DSIM_H */
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (C) 2008 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_MIPI_DSIM=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/dsim.o
|
||||
@@ -0,0 +1,717 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <string.h>
|
||||
#include "AppleS5L8900XPKE-hardware.h"
|
||||
|
||||
|
||||
#define AppleS5L8900XPKE_hardware_DEBUG 0
|
||||
#undef absolutetime_to_nanoseconds
|
||||
|
||||
#if AppleS5L8900XPKE_hardware_DEBUG
|
||||
static void debug_data(uint8_t *data, size_t length)
|
||||
{
|
||||
uint32_t i=0;
|
||||
printf("data %p,%d\n" , data, length);
|
||||
for (i = 0; i < length; i++) {
|
||||
if( !(i%256) )
|
||||
printf("Seg : %p \n", data);
|
||||
printf("%02X, ", *(data + i));
|
||||
if ((i % 16) == 15)
|
||||
printf("\n");
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
#define debug(fmt, args...) printf("AppleS5L8900XPKE-hardware::%s: " fmt "\n", __FUNCTION__ , ##args)
|
||||
#else
|
||||
#define debug(fmt, args...)
|
||||
#define debug_data(data, length)
|
||||
#endif
|
||||
|
||||
|
||||
#if IN_KERNEL
|
||||
extern uint64_t iodelay_time[3];
|
||||
static uint64_t delay_time;
|
||||
#endif
|
||||
|
||||
|
||||
uint32_t
|
||||
PkeSetMode(uint32_t uSegSize)
|
||||
{
|
||||
uint32_t uWriteVal;
|
||||
|
||||
switch (uSegSize) {
|
||||
case PKE_SEG_SIZE_256:
|
||||
uWriteVal = PKE_REGVAL_SEG_SIZE_SEGSIZE_256;
|
||||
break;
|
||||
|
||||
case PKE_SEG_SIZE_128:
|
||||
uWriteVal = PKE_REGVAL_SEG_SIZE_SEGSIZE_128;
|
||||
break;
|
||||
|
||||
case PKE_SEG_SIZE_64:
|
||||
uWriteVal = PKE_REGVAL_SEG_SIZE_SEGSIZE_64;
|
||||
break;
|
||||
|
||||
default:
|
||||
uWriteVal = 0;
|
||||
debug("error setting segment size/mode\n");
|
||||
}
|
||||
|
||||
/* ! write SEG_SIZE and MODE_ID */
|
||||
return (uWriteVal | PKE_REGMASK_SEG_SIZE_MUSTBEONE);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
PkeGetSegmentCount(uint32_t uSegSize)
|
||||
{
|
||||
/* return segment total number */
|
||||
switch (uSegSize) {
|
||||
case PKE_SEG_SIZE_256:
|
||||
return PKE_SEG_NUM_CASE256;
|
||||
case PKE_SEG_SIZE_128:
|
||||
return PKE_SEG_NUM_CASE128;
|
||||
case PKE_SEG_SIZE_64:
|
||||
return PKE_SEG_NUM_CASE64;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t get_precision(uint32_t uBitLen)
|
||||
{
|
||||
uint32_t uPrecision;
|
||||
|
||||
if (uBitLen <= PKE_LEN_BIT_512) {
|
||||
uPrecision = PKE_SIZE_PREC_0;
|
||||
} else if ((uBitLen <= PKE_LEN_BIT_1024) && (uBitLen != PKE_LEN_BIT_672) && (uBitLen != PKE_LEN_BIT_864)) {
|
||||
uPrecision = PKE_SIZE_PREC_1;
|
||||
} else if ((uBitLen <= PKE_LEN_BIT_1536) && (uBitLen != PKE_LEN_BIT_1280) && (uBitLen != PKE_LEN_BIT_1408)) {
|
||||
uPrecision = PKE_SIZE_PREC_2;
|
||||
} else {
|
||||
uPrecision = PKE_SIZE_PREC_3;
|
||||
}
|
||||
return uPrecision;
|
||||
}
|
||||
|
||||
static uint32_t get_chunkSize(uint32_t uBitLen, uint32_t uPrecision)
|
||||
{
|
||||
uint32_t uDiv, uChunk;
|
||||
|
||||
switch (uPrecision) {
|
||||
case PKE_SIZE_PREC_0:
|
||||
if (uBitLen < PKE_LEN_BIT_128) {
|
||||
uBitLen = PKE_LEN_BIT_128;
|
||||
}
|
||||
uDiv = uBitLen >> 5;
|
||||
uChunk = uDiv;
|
||||
if (uBitLen - (uChunk << 5)) {
|
||||
uDiv++;
|
||||
}
|
||||
uChunk = --uDiv;
|
||||
break;
|
||||
|
||||
case PKE_SIZE_PREC_1:
|
||||
uDiv = uBitLen >> 6;
|
||||
uChunk = uDiv;
|
||||
if (uBitLen - (uChunk << 6)) {
|
||||
uDiv++;
|
||||
}
|
||||
uChunk = --uDiv;
|
||||
break;
|
||||
|
||||
case PKE_SIZE_PREC_2:
|
||||
uDiv = (uBitLen / 3) >> 5;
|
||||
uChunk = uDiv;
|
||||
if (uBitLen - ((uChunk * 3) << 5)) {
|
||||
uDiv++;
|
||||
}
|
||||
uChunk = --uDiv;
|
||||
break;
|
||||
|
||||
case PKE_SIZE_PREC_3:
|
||||
uDiv = uBitLen >> 7;
|
||||
uChunk = uDiv;
|
||||
if (uBitLen - (uChunk << 7)) {
|
||||
uDiv++;
|
||||
}
|
||||
uChunk = --uDiv;
|
||||
break;
|
||||
default:
|
||||
debug("Unsupported precision value: %u", uPrecision);
|
||||
uChunk = 0;
|
||||
}
|
||||
return (((uChunk << 3) + 8) << 2);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
config_pke_key_len(uint32_t uBitLen)
|
||||
{
|
||||
uint32_t uDiv, uChunk, uPrecision;
|
||||
|
||||
/* 1. Get Precision */
|
||||
uPrecision = get_precision(uBitLen);
|
||||
|
||||
/* 2. Get chunck size */
|
||||
uChunk = get_chunkSize(uBitLen, uPrecision);
|
||||
|
||||
/* 3. Set precision and chunksize */
|
||||
uDiv = ((uChunk >> 2) - 8) | uPrecision;
|
||||
|
||||
#if IN_KERNEL
|
||||
//Set the IODelay time based on uBitLen.
|
||||
if (uBitLen <= PKE_LEN_BIT_512) {
|
||||
delay_time = iodelay_time[0];
|
||||
}
|
||||
else if (uBitLen <= PKE_LEN_BIT_1024) {
|
||||
delay_time = iodelay_time[1];
|
||||
}
|
||||
else {
|
||||
delay_time = iodelay_time[2];
|
||||
}
|
||||
#endif
|
||||
|
||||
return uDiv;
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
RSAPkeSetInOut(uint32_t uDest, uint32_t uSrc1, uint32_t uSrc2)
|
||||
{
|
||||
uint32_t uPosition = 0;
|
||||
|
||||
/*! Set segment ID of src and dest */
|
||||
uPosition = ((uSrc1 << PKE_REGSHIFT_SEG_ID_A_SEG_ID)
|
||||
| (uSrc2 << PKE_REGSHIFT_SEG_ID_B_SEG_ID)
|
||||
| (uDest << PKE_REGSHIFT_SEG_ID_S_SEG_ID));
|
||||
|
||||
return uPosition;
|
||||
}
|
||||
|
||||
static inline bool
|
||||
RSAPkeRun(volatile struct pke_regs *registers, uint32_t uCmdVal)
|
||||
{
|
||||
/*! Run PKE */
|
||||
registers->pke_start = uCmdVal;
|
||||
|
||||
#if IN_KERNEL
|
||||
IODelay(delay_time);
|
||||
#endif
|
||||
|
||||
do {
|
||||
if (!(registers->pke_start & PKE_REGMASK_START_EXEC_ON))
|
||||
return true;
|
||||
} while (1);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
static bool shift_left(uint32_t *data, uint32_t data_size)
|
||||
{
|
||||
int prev_carry = 0, cur_carry = 0;
|
||||
uint32_t itr = 0;
|
||||
|
||||
for (itr=0; itr < (data_size/sizeof(uint32_t)); itr++) {
|
||||
cur_carry = data[itr] >> 31;
|
||||
data[itr] = (data[itr] << 1) + prev_carry;
|
||||
prev_carry = cur_carry;
|
||||
}
|
||||
return prev_carry;
|
||||
}
|
||||
|
||||
|
||||
static int32_t highestSetBit(uint32_t *data1, uint32_t data_size)
|
||||
{
|
||||
int32_t ix = data_size/sizeof(uint32_t) - 1; // Most significant word.
|
||||
|
||||
while( ix>=0 && data1[ix]==0) {
|
||||
ix--;
|
||||
}
|
||||
|
||||
if(ix < 0)
|
||||
return -1; //mods is zero.
|
||||
|
||||
uint32_t msNZword = data1[ix];
|
||||
uint32_t b = ((ix+1) * sizeof(uint32_t) * DATA_BYTE_TO_BIT) - 1 ;
|
||||
// Now find the highest set bit.
|
||||
uint32_t mask = 0x80000000;
|
||||
while ((msNZword & mask) == 0) {
|
||||
mask >>= 1;
|
||||
b--;
|
||||
}
|
||||
return b;
|
||||
}
|
||||
|
||||
|
||||
static bool is_greater(uint32_t *data1, uint32_t *data2, uint32_t data_size)
|
||||
{
|
||||
uint32_t itr = data_size/sizeof(uint32_t) - 1; //start at the last word.
|
||||
|
||||
do {
|
||||
if(data1[itr] > data2[itr])
|
||||
return true;
|
||||
else if(data1[itr] < data2[itr])
|
||||
return false;
|
||||
//check next word;
|
||||
}while(itr--);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Do data1 = data1 - data2 */
|
||||
static uint32_t sub(uint32_t *data1, uint32_t *data2, uint32_t data_size)
|
||||
{
|
||||
uint32_t borrow = 0;
|
||||
uint32_t itr = 0;
|
||||
|
||||
for(itr=0; itr < (data_size/sizeof(uint32_t)); itr++) {
|
||||
if(borrow) {
|
||||
if(data1[itr] != 0)
|
||||
borrow = 0; //No need to borrow again.
|
||||
data1[itr] -= 1;
|
||||
}
|
||||
|
||||
if( data1[itr] < data2[itr] )
|
||||
borrow = 1;
|
||||
|
||||
data1[itr] -= data2[itr];
|
||||
}
|
||||
if(borrow)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*Do data1 = data1 + data2 */
|
||||
static uint32_t add(uint32_t *data1, uint32_t *data2, uint32_t data_size)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
int carry = 0;
|
||||
uint32_t itr = 0;
|
||||
|
||||
for(itr=0; itr < (data_size/sizeof(uint32_t)); itr++) {
|
||||
temp = data1[itr] + data2[itr] + carry;
|
||||
if(temp < data1[itr] || (temp == data1[itr] && carry))
|
||||
carry = 1;
|
||||
else
|
||||
carry = 0;
|
||||
data1[itr] = temp;
|
||||
}
|
||||
return carry;
|
||||
}
|
||||
|
||||
// The src buffer is assumed to be word aligned at this point.
|
||||
// The hardware register is 4 byte aligned.
|
||||
// The data is in little Endian.
|
||||
static inline void copy_into_segment(volatile uint8_t *memory, uint32_t segment_id, uint32_t segment_size, uint8_t *data, uint32_t length)
|
||||
{
|
||||
volatile uint8_t *dst = memory + segment_id * segment_size;
|
||||
uint32_t ii=0;
|
||||
|
||||
//Make sure the buffer is word aligned.
|
||||
//assert((data & 3) == 0); //We don't assert in iBoot. The only interface makes sure we have aligned buffer.
|
||||
|
||||
uint32_t newLength = length & ~3 ;
|
||||
//Copy words.
|
||||
for(ii=0; ii<(newLength/4); ii++)
|
||||
*((uint32_t*)dst + ii) = *((uint32_t*)data + ii);
|
||||
|
||||
//See if you have less than a word left to copy.
|
||||
if(length & 3) { //have less than 4 bytes left to copy.
|
||||
uint8_t wordData[4] = {0,0,0,0};
|
||||
uint8_t *bytesLeft = data + newLength;
|
||||
for(ii=0; ii<(length & 3); ii++) {
|
||||
wordData[ii] = *(bytesLeft + ii);
|
||||
}
|
||||
*((uint32_t*)(dst+newLength)) = *((uint32_t*)wordData);
|
||||
}
|
||||
|
||||
//zero fill the rest of the segment.
|
||||
uint32_t bytesCopied = ((length+3) & ~3);
|
||||
uint32_t left = segment_size - bytesCopied;
|
||||
if(left) {
|
||||
uint32_t *dest = (uint32_t *)(dst + bytesCopied);
|
||||
for(ii=0; ii<(left/4); ii++)
|
||||
*(dest+ii) = 0x00000000;
|
||||
}
|
||||
}
|
||||
|
||||
/* Calculate R0 in software.
|
||||
rzero has memory allocated of size modulus_length and is zero filled.
|
||||
*/
|
||||
bool rsa_cal_R0(uint32_t * const mods, uint32_t modulus_length, uint32_t *rzero)
|
||||
{
|
||||
debug("called");
|
||||
|
||||
uint32_t precision = get_precision(modulus_length*DATA_BYTE_TO_BIT);
|
||||
uint32_t chunk_size = get_chunkSize(modulus_length*DATA_BYTE_TO_BIT, precision);
|
||||
|
||||
//precision is 1,2,3,4 instead of 0,1,2,3
|
||||
precision += 1;
|
||||
|
||||
/* Compute 2^b */
|
||||
uint32_t power = (chunk_size / 16) + 1;
|
||||
if (precision == 3)
|
||||
power = power * 3;
|
||||
power = power + (precision * (chunk_size + 16));
|
||||
|
||||
//compute the most significant bit set in the modulus.
|
||||
int32_t b = highestSetBit((uint32_t*)mods, modulus_length);
|
||||
if(b == -1)
|
||||
return false;
|
||||
|
||||
//store 2^b in rzero.
|
||||
bzero(rzero, modulus_length);
|
||||
rzero[(b/32)] = 1 << (b % 32);
|
||||
|
||||
/* Calculate (2^(power-b) * 2^b) mod M */
|
||||
uint32_t itr;
|
||||
for(itr=0; itr<(power-b); itr++) {
|
||||
bool carry = shift_left(rzero, modulus_length); //Shift left.
|
||||
if (carry || is_greater(rzero, mods, modulus_length))
|
||||
sub(rzero, (uint32_t*)mods, modulus_length);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Compute the value of R^2 using the hardware.
|
||||
The value of rzero (R0) is calculated in softare and passed into the function
|
||||
The hardware should be reset before calling this function.
|
||||
The value of R^2 is returned thru' rsquare (memory for this is allocated before calling this function and of modulus_length size)
|
||||
*/
|
||||
static bool rsa_cal_R2modM(volatile struct pke_regs *registers, volatile uint8_t *memory, uint32_t seg_size, uint32_t * const mods, uint32_t mods_length, uint32_t *rsquare, uint32_t *r2_segid)
|
||||
{
|
||||
debug("called");
|
||||
|
||||
if(!rsquare) //Need rzero (which should be in rsquare) to proceed
|
||||
return false;
|
||||
|
||||
//Set the key length;
|
||||
registers->pke_key_len = config_pke_key_len(mods_length*DATA_BYTE_TO_BIT);
|
||||
//Set segment size;
|
||||
registers->pke_seg_size = PkeSetMode(seg_size);
|
||||
registers->pke_seg_sign = 0;
|
||||
registers->pke_seg_id = 0;
|
||||
|
||||
/* Use hardware to calculate R1 thru' Rn and finally R^2 */
|
||||
//Load modulus always into seg0.
|
||||
copy_into_segment(memory, mod_segid, seg_size, (uint8_t*)mods, mods_length);
|
||||
|
||||
//based on seg_size compute the seg_ids to store the (2^(power-b) * 2^b) mod M
|
||||
// and the final value of R^2
|
||||
uint32_t rzero_segid, rsq_segid;
|
||||
switch (seg_size) {
|
||||
case PKE_SEG_SIZE_256:
|
||||
rzero_segid = PKE_SEG_ID_05;
|
||||
rsq_segid = PKE_SEG_ID_06;
|
||||
break;
|
||||
case PKE_SEG_SIZE_128:
|
||||
rzero_segid = PKE_SEG_ID_12;
|
||||
rsq_segid = PKE_SEG_ID_14;
|
||||
break;
|
||||
case PKE_SEG_SIZE_64:
|
||||
rzero_segid = PKE_SEG_ID_28;
|
||||
rsq_segid = PKE_SEG_ID_29;
|
||||
break;
|
||||
default:
|
||||
//Should not happen.
|
||||
return false;
|
||||
}
|
||||
//Load the rzero into the hardware.
|
||||
copy_into_segment(memory, rzero_segid, seg_size, (uint8_t*)rsquare, mods_length);
|
||||
|
||||
uint32_t precision = (registers->pke_key_len&PKE_REGMASK_KEY_LEN_PREC_ID) + 1;
|
||||
//Compute the number of hardware iterations based on precision.
|
||||
uint32_t square_count;
|
||||
if (precision == 1 || precision == 3)
|
||||
square_count = 4;
|
||||
else if (precision == 2)
|
||||
square_count = 5;
|
||||
else /* precision == 4 */
|
||||
square_count = 6;
|
||||
|
||||
//Set pre load modulus on when using the hardware for the first time.
|
||||
uint32_t start_mask = PKE_REGMASK_START_PLDM_ON | PKE_REGMASK_START_EXEC_ON;
|
||||
uint32_t itr = 1;
|
||||
uint32_t temp_segid = rsq_segid;
|
||||
while (itr <= square_count) {
|
||||
//setup seg_id pointers on the hardware
|
||||
registers->pke_seg_id = RSAPkeSetInOut(temp_segid, rzero_segid, rzero_segid);
|
||||
//kick the hardware.
|
||||
if(!RSAPkeRun(registers, start_mask))
|
||||
return false;
|
||||
itr++;
|
||||
if(itr > square_count)
|
||||
break;
|
||||
//swap the segids and do the square again.
|
||||
temp_segid += rzero_segid;
|
||||
rzero_segid = temp_segid - rzero_segid;
|
||||
temp_segid -= rzero_segid;
|
||||
start_mask = PKE_REGMASK_START_EXEC_ON; //dont have to laod M again.
|
||||
}
|
||||
|
||||
// Check the sign value of temp_segid and add modulus if negative.
|
||||
uint32_t uRead, uMask;
|
||||
uMask = (1 << temp_segid);
|
||||
uRead = registers->pke_seg_sign & uMask;
|
||||
//If negative then add modulus.
|
||||
if(uRead) {
|
||||
add( (uint32_t*)(memory+(temp_segid*seg_size)), (uint32_t*)mods, mods_length);
|
||||
}
|
||||
|
||||
*r2_segid = temp_segid;
|
||||
|
||||
//Clean up the temp space used.
|
||||
bzero((uint8_t*) memory+rzero_segid*seg_size, mods_length);
|
||||
|
||||
/* Reset the signbits */
|
||||
registers->pke_seg_sign = 0;
|
||||
memcpy(rsquare, (uint8_t *) memory+rsq_segid*seg_size, mods_length);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/* Calculate exponential.
|
||||
The options parameter passed in indicates if R^2 is passed in or needs to be computed.
|
||||
Options = 00 => Compute R^2 and don't care about caching. *rsquare is ignored.
|
||||
Options = 01 => Compute R^2 and return it for caching. *rsquare has mem allocated and is of size modulus_length
|
||||
Options = 10 => Use passed in R^2 value.
|
||||
|
||||
Reset the hardware before calling this function.
|
||||
*/
|
||||
bool rsa_cal_exp(void *dst, uint32_t *len, uint32_t options,
|
||||
uint8_t *rsquare, uint32_t *rsquare_length,
|
||||
uint8_t * const base, uint32_t base_length,
|
||||
uint8_t * const expn, uint32_t expn_length,
|
||||
uint8_t * const modulus, uint32_t modulus_length,
|
||||
volatile struct pke_regs *registers, volatile uint8_t *memory)
|
||||
{
|
||||
debug("called");
|
||||
|
||||
/* Perform validation checks */
|
||||
if(modulus_length % 4)
|
||||
return false;
|
||||
|
||||
uint32_t segment_size, num_segments;
|
||||
|
||||
if (modulus_length <= (PKE_SEG_SIZE_64)) {
|
||||
segment_size = PKE_SEG_SIZE_64;
|
||||
} else if (modulus_length <= (PKE_SEG_SIZE_128)) {
|
||||
segment_size = PKE_SEG_SIZE_128;
|
||||
} else if (modulus_length <= (PKE_SEG_SIZE_256)) {
|
||||
segment_size = PKE_SEG_SIZE_256;
|
||||
} else
|
||||
return false; /* key too long */
|
||||
|
||||
num_segments = PkeGetSegmentCount(segment_size);
|
||||
|
||||
if ( !num_segments ||
|
||||
base_length > segment_size ||
|
||||
expn_length > segment_size ||
|
||||
modulus_length > segment_size)
|
||||
return false;
|
||||
|
||||
/* Sane input, so proceed */
|
||||
|
||||
//rsquare segid must always be the last seg ID.
|
||||
uint32_t rsq_segid = num_segments - 1;
|
||||
|
||||
if( (options&kIOPKEAcceleratorComputeRsquareMask) == 0 ) { //Compute rsquare.
|
||||
if(!(options&kIOPKEAcceleratorPreProcessingDone)) { //R0 was not cacluated. should only happen in iBoot.
|
||||
if(!rsquare){
|
||||
//should not happen. The expectation is that memory for rsquare should be allocated.
|
||||
return false;
|
||||
}
|
||||
rsa_cal_R0((uint32_t*)modulus, modulus_length, (uint32_t*)rsquare);
|
||||
}
|
||||
//Compute R^2
|
||||
if(!rsa_cal_R2modM(registers, memory, segment_size, (uint32_t*)modulus, modulus_length, (uint32_t*)rsquare, &rsq_segid))
|
||||
return false;
|
||||
*rsquare_length = modulus_length;
|
||||
}
|
||||
else { //This would have been done while calculating R^2.
|
||||
//Set the key length;
|
||||
registers->pke_key_len = config_pke_key_len(modulus_length*DATA_BYTE_TO_BIT);
|
||||
//Set segment size;
|
||||
registers->pke_seg_size = PkeSetMode(segment_size);
|
||||
/* Reset the signbits */
|
||||
registers->pke_seg_sign = 0;
|
||||
registers->pke_seg_id = 0;
|
||||
|
||||
//Load modulus into seg0;
|
||||
copy_into_segment(memory, mod_segid, segment_size, modulus, modulus_length);
|
||||
//copy the rsquare into the hardware segment.
|
||||
memcpy((uint8_t*)memory+(rsq_segid*segment_size), rsquare, modulus_length);
|
||||
}
|
||||
|
||||
/* Compute (base * r^2 mod M) using hardware */
|
||||
//Copy base into tmp_segid.
|
||||
copy_into_segment(memory, tmp_segid, segment_size, base, base_length);
|
||||
//Setup the segid pointers.
|
||||
registers->pke_seg_id = RSAPkeSetInOut(iter_segid, tmp_segid, rsq_segid);
|
||||
|
||||
//Kick the hardware with pre load modulus bit set.
|
||||
if(!RSAPkeRun(registers, (PKE_REGMASK_START_PLDM_ON | PKE_REGMASK_START_EXEC_ON)))
|
||||
return false;
|
||||
|
||||
/* compute (1*R^2modM) using hardware. */
|
||||
registers->pke_seg_size |= PKE_REGVAL_SEG_SIZE_FUNC_ID_A1; // A*1
|
||||
//When PKE_REGVAL_SEG_SIZE_FUNC_ID_A1 is set, the hardware ignores the segid_B pointer
|
||||
registers->pke_seg_id = RSAPkeSetInOut(acum_segid, rsq_segid, rsq_segid);
|
||||
if(!RSAPkeRun(registers, PKE_REGMASK_START_EXEC_ON))
|
||||
return false;
|
||||
|
||||
// Clear the PKE_REGVAL_SEG_SIZE_FUNC_ID_A1 bit.
|
||||
registers->pke_seg_size &= ~PKE_REGVAL_SEG_SIZE_FUNC_ID_A1;
|
||||
|
||||
/* Run the PKE */
|
||||
uint32_t *exp_word = (uint32_t*)expn;
|
||||
/* word aligned byte length */
|
||||
uint32_t uExpLen = ((expn_length + (DATA_WORD_TO_BYTE - 1)) & (~0x3));
|
||||
|
||||
uint32_t last_word = exp_word[(uExpLen/DATA_WORD_TO_BYTE) - 1];
|
||||
uint32_t uIndex = (DATA_WORD_TO_BYTE*DATA_BYTE_TO_BIT) - (highestSetBit(&last_word, DATA_WORD_TO_BYTE) + 1);
|
||||
for (; uIndex < (uExpLen * DATA_BYTE_TO_BIT); uIndex++) {
|
||||
unsigned int word;
|
||||
unsigned int bit;
|
||||
|
||||
uint32_t offset = (uExpLen / DATA_WORD_TO_BYTE) - (uIndex / (DATA_WORD_TO_BYTE * DATA_BYTE_TO_BIT)) - 1;
|
||||
word = exp_word[offset];
|
||||
|
||||
registers->pke_seg_id = RSAPkeSetInOut(tmp_segid, acum_segid, acum_segid);
|
||||
if(!RSAPkeRun(registers, PKE_REGMASK_START_EXEC_ON))
|
||||
return false;
|
||||
|
||||
bit = word & (0x80000000 >> (uIndex % (DATA_WORD_TO_BYTE * DATA_BYTE_TO_BIT)));
|
||||
|
||||
if (bit) {
|
||||
//debug("bit %d set", uIndex);
|
||||
registers->pke_seg_id = RSAPkeSetInOut(acum_segid, tmp_segid, iter_segid);
|
||||
if(!RSAPkeRun(registers, PKE_REGMASK_START_EXEC_ON))
|
||||
return false;
|
||||
} else {
|
||||
memcpy( (uint8_t *) memory + acum_segid * segment_size,
|
||||
(uint8_t *) memory + tmp_segid * segment_size,
|
||||
segment_size);
|
||||
|
||||
if (registers->pke_seg_sign & (0x01 << tmp_segid))
|
||||
registers->pke_seg_sign |= (0x01 << acum_segid);
|
||||
else
|
||||
registers->pke_seg_sign &= ~(0x01 << acum_segid);
|
||||
}
|
||||
}
|
||||
|
||||
/* Factor out R^-1 from the result */
|
||||
registers->pke_seg_size |= PKE_REGVAL_SEG_SIZE_FUNC_ID_A1; // A*1
|
||||
registers->pke_seg_id = RSAPkeSetInOut(tmp_segid, acum_segid, acum_segid);
|
||||
if (!RSAPkeRun(registers, PKE_REGMASK_START_EXEC_ON))
|
||||
return false;
|
||||
registers->pke_seg_size &= ~PKE_REGVAL_SEG_SIZE_FUNC_ID_A1; // A*B
|
||||
|
||||
// Check the sign value of tmp_segid and add modulus if negative.
|
||||
uint32_t uRead, uMask;
|
||||
uMask = (1 << tmp_segid);
|
||||
uRead = registers->pke_seg_sign & uMask;
|
||||
//If negative then add modulus.
|
||||
if(uRead) {
|
||||
registers->pke_seg_sign &= ~uMask; //clear the sign.
|
||||
add( (uint32_t*)(memory+(tmp_segid*segment_size)), (uint32_t*)modulus, modulus_length);
|
||||
}
|
||||
|
||||
/* Copy data out */
|
||||
memcpy(dst, (uint8_t*)memory+(tmp_segid*segment_size), modulus_length);
|
||||
*len = modulus_length;
|
||||
return true;
|
||||
}
|
||||
|
||||
#if IN_KERNEL
|
||||
|
||||
bool internalTest(volatile struct pke_regs *registers, volatile uint8_t *memory, uint32_t mod_size, uint64_t *time_micro)
|
||||
{
|
||||
uint8_t buff[mod_size];
|
||||
uint32_t segment_size;
|
||||
|
||||
if (mod_size <= (PKE_SEG_SIZE_64)) {
|
||||
segment_size = PKE_SEG_SIZE_64;
|
||||
} else if (mod_size <= (PKE_SEG_SIZE_128)) {
|
||||
segment_size = PKE_SEG_SIZE_128;
|
||||
} else if (mod_size <= (PKE_SEG_SIZE_256)) {
|
||||
segment_size = PKE_SEG_SIZE_256;
|
||||
} else
|
||||
return false; /* key too long */
|
||||
|
||||
uint32_t rsq_segid;
|
||||
switch (segment_size) {
|
||||
case PKE_SEG_SIZE_256:
|
||||
rsq_segid = PKE_SEG_ID_06;
|
||||
break;
|
||||
case PKE_SEG_SIZE_128:
|
||||
rsq_segid = PKE_SEG_ID_14;
|
||||
break;
|
||||
case PKE_SEG_SIZE_64:
|
||||
rsq_segid = PKE_SEG_ID_29;
|
||||
break;
|
||||
default:
|
||||
//Should not happen.
|
||||
return false;
|
||||
}
|
||||
|
||||
registers->pke_key_len = config_pke_key_len(mod_size*DATA_BYTE_TO_BIT);
|
||||
//Set segment size;
|
||||
registers->pke_seg_size = PkeSetMode(segment_size);
|
||||
/* Reset the signbits */
|
||||
registers->pke_seg_sign = 0;
|
||||
registers->pke_seg_id = 0;
|
||||
|
||||
debug("key: %x, reg_key: %x, modsize:%u, reg_segsize: %u", config_pke_key_len(mod_size*DATA_BYTE_TO_BIT), registers->pke_key_len, mod_size, registers->pke_seg_size);
|
||||
|
||||
//Load modulus into seg0;
|
||||
memset(buff, 0xF0, mod_size);
|
||||
copy_into_segment(memory, mod_segid, segment_size, buff, mod_size);
|
||||
//Set R^2
|
||||
memset(buff, 0xE5, mod_size);
|
||||
copy_into_segment(memory, rsq_segid, segment_size, buff, mod_size);
|
||||
//Set A
|
||||
memset(buff, 0xD2, mod_size);
|
||||
copy_into_segment(memory, iter_segid, segment_size, buff, mod_size);
|
||||
|
||||
|
||||
//Setup the segid pointers.
|
||||
registers->pke_seg_id = RSAPkeSetInOut(iter_segid, tmp_segid, tmp_segid);
|
||||
|
||||
uint64_t tasm0, tasm1, tasm2, asm_ns;
|
||||
tasm0 = mach_absolute_time();
|
||||
tasm1 = mach_absolute_time();
|
||||
|
||||
//Kick the hardware with pre load modulus bit set.
|
||||
if(!RSAPkeRun(registers, (PKE_REGMASK_START_PLDM_ON | PKE_REGMASK_START_EXEC_ON)))
|
||||
return false;
|
||||
|
||||
tasm2 = mach_absolute_time();
|
||||
absolutetime_to_nanoseconds( (tasm2 + tasm0 - tasm1 - tasm1), &asm_ns);
|
||||
//debug("Single multiply time: %lluns\n", asm_ns);
|
||||
|
||||
*time_micro = (asm_ns/1000) - 5;
|
||||
|
||||
//clear the hardware.
|
||||
registers->pke_key_len = 0;
|
||||
registers->pke_seg_size = 0;
|
||||
registers->pke_seg_sign = 0;
|
||||
registers->pke_seg_id = 0;
|
||||
|
||||
bzero((uint8_t*)memory+(tmp_segid*segment_size), mod_size);
|
||||
bzero((uint8_t*)memory+(mod_segid*segment_size), mod_size);
|
||||
bzero((uint8_t*)memory+(iter_segid*segment_size), mod_size);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,194 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef _IOKIT_APPLES5L8900XPKE_HARDWARE_H
|
||||
#define _IOKIT_APPLES5L8900XPKE_HARDWARE_H
|
||||
|
||||
#define IN_KERNEL 0
|
||||
|
||||
#if IN_KERNEL
|
||||
#include <IOKit/IOLib.h>
|
||||
#endif
|
||||
|
||||
struct pke_regs {
|
||||
uint32_t pke_key_len; // 0x000
|
||||
#define S5L8900XPKE_key_len(_precision, _chunk_size) (((_precision) & 0x03) | ((((_chunk_size) / 32) & 0x0f) << 3))
|
||||
uint32_t pad004; // 0x004
|
||||
uint32_t pke_start; // 0x008
|
||||
#define S5L8900XPKE_exec_on (1<<0)
|
||||
#define S5L8900XPKE_pldm_on (1<<3)
|
||||
uint32_t pke_seg_id; // 0x00c
|
||||
#define S5L8900XPKE_seg_ids(_a, _b, _m, _s) (((_a) << 24 ) | ((_b) << 16) | ((_m) << 8) | (_s))
|
||||
uint32_t pke_seg_sign; // 0x010
|
||||
uint32_t pke_seg_size; // 0x014
|
||||
#define S5L8900XPKE_func_id (1<<0)
|
||||
#define S5L8900XPKE_seg_256 (0x00 << 6)
|
||||
#define S5L8900XPKE_seg_128 (0x01 << 6)
|
||||
#define S5L8900XPKE_seg_64 (0x02 << 6)
|
||||
uint32_t pke_intmode; // 0x018
|
||||
#define S5L8900XPKE_interrupt (1<<0)
|
||||
uint32_t pke_int; // 0x01c
|
||||
#define S5L8900XPKE_end_int (1<<0)
|
||||
uint32_t pke_int_mask; // 0x020
|
||||
#define S5L8900XPKE_end_mask (1<<0)
|
||||
uint32_t pke_sw_reset;
|
||||
#define S5L8900XPKE_reset (1<<0)
|
||||
};
|
||||
|
||||
|
||||
/* ========================================================================= */
|
||||
/* D E F I N E S */
|
||||
/* ========================================================================= */
|
||||
|
||||
#define kIOPKEAcceleratorComputeRsquareMask 0x10
|
||||
#define kIOPKEAcceleratorCacheRsquare 0x01
|
||||
#define kIOPKEAcceleratorPreProcessingDone 0x100
|
||||
#define kIOPKEMaxBits 2048
|
||||
#define kIOPKEUserDataEndianessMask (1<<7)
|
||||
|
||||
/** \define
|
||||
* definition of data format size
|
||||
*/
|
||||
#define DATA_WORD_TO_BYTE 4 /*4BYTE=1WORD*/
|
||||
#define DATA_BYTE_TO_BIT 8 /*1BYTE=8BIT*/
|
||||
|
||||
#define DATA_SHIFT_FOR_256 8 /*2^8=256*/
|
||||
#define DATA_SHIFT_FOR_128 7 /*2^7=128*/
|
||||
#define DATA_SHIFT_FOR_64 6 /*2^6=64*/
|
||||
|
||||
#define PKE_REGSHIFT_KEY_LEN_CHNK_SZ 3
|
||||
|
||||
/** \define
|
||||
* definition of PKE precision size
|
||||
*/
|
||||
#define PKE_SIZE_PREC_0 0 /*single*/
|
||||
#define PKE_SIZE_PREC_1 1
|
||||
#define PKE_SIZE_PREC_2 2
|
||||
#define PKE_SIZE_PREC_3 3
|
||||
|
||||
|
||||
/** \define
|
||||
* definition of PKE key bit length
|
||||
*/
|
||||
#define PKE_LEN_BIT_128 128 /* min size of bit length*/
|
||||
#define PKE_LEN_BIT_512 512
|
||||
#define PKE_LEN_BIT_672 672
|
||||
#define PKE_LEN_BIT_864 864
|
||||
#define PKE_LEN_BIT_1024 1024
|
||||
#define PKE_LEN_BIT_1280 1280
|
||||
#define PKE_LEN_BIT_1408 1408
|
||||
#define PKE_LEN_BIT_1536 1536
|
||||
#define PKE_LEN_BIT_2048 2048 /*max size of bit length*/
|
||||
|
||||
/** \define
|
||||
* definition of PKE Segment Size
|
||||
*/
|
||||
#define PKE_SEG_SIZE_256 (1<<DATA_SHIFT_FOR_256) /*256 byte*/
|
||||
#define PKE_SEG_SIZE_128 (1<<DATA_SHIFT_FOR_128) /*128 byte*/
|
||||
#define PKE_SEG_SIZE_64 (1<<DATA_SHIFT_FOR_64) /*64 byte*/
|
||||
|
||||
/** \define
|
||||
* definition of PKE Segment Max Number (depend on segment size)
|
||||
*/
|
||||
#define PKE_SEG_NUM_CASE256 7
|
||||
#define PKE_SEG_NUM_CASE128 15
|
||||
#define PKE_SEG_NUM_CASE64 30
|
||||
|
||||
/** \define
|
||||
* definition of PKE Function mode
|
||||
*/
|
||||
#define PKE_FUNC_MODE_AB 0
|
||||
#define PKE_FUNC_MODE_A1 1
|
||||
|
||||
|
||||
/** \define
|
||||
* definition of PKE Register field data
|
||||
*/
|
||||
/* key len bits */
|
||||
#define PKE_REGSHIFT_KEY_LEN_CHNK_SZ 3
|
||||
#define PKE_REGSHIFT_KEY_LEN_PREC_ID 0
|
||||
|
||||
#define PKE_REGMASK_KEY_LEN_CHNK_SZ (15 << PKE_REGSHIFT_KEY_LEN_CHNK_SZ )
|
||||
#define PKE_REGMASK_KEY_LEN_PREC_ID (3 << PKE_REGSHIFT_KEY_LEN_PREC_ID )
|
||||
|
||||
/* start bits */
|
||||
#define PKE_REGSHIFT_START_PLDM_ON 3
|
||||
#define PKE_REGSHIFT_START_EXEC_ON 0
|
||||
|
||||
#define PKE_REGMASK_START_PLDM_ON (1 << PKE_REGSHIFT_START_PLDM_ON )
|
||||
#define PKE_REGMASK_START_EXEC_ON (1 << PKE_REGSHIFT_START_EXEC_ON )
|
||||
|
||||
/* seg id bits */
|
||||
#define PKE_REGSHIFT_SEG_ID_A_SEG_ID 24
|
||||
#define PKE_REGSHIFT_SEG_ID_B_SEG_ID 16
|
||||
#define PKE_REGSHIFT_SEG_ID_M_SEG_ID 8
|
||||
#define PKE_REGSHIFT_SEG_ID_S_SEG_ID 0
|
||||
|
||||
/* seg size bits */
|
||||
#define PKE_REGSHIFT_SEG_SIZE_SEGSIZE 6
|
||||
#define PKE_REGSHIFT_SEG_SIZE_FUNC_ID 1
|
||||
#define PKE_REGSHIFT_SEG_SIZE_MUSTBEONE 0
|
||||
|
||||
#define PKE_REGMASK_SEG_SIZE_SEGSIZE (3 << PKE_REGSHIFT_SEG_SIZE_SEGSIZE)
|
||||
#define PKE_REGMASK_SEG_SIZE_FUNC_ID (1 << PKE_REGSHIFT_SEG_SIZE_FUNC_ID)
|
||||
#define PKE_REGMASK_SEG_SIZE_MUSTBEONE (1 << PKE_REGSHIFT_SEG_SIZE_MUSTBEONE )
|
||||
|
||||
#define PKE_REGVAL_SEG_SIZE_SEGSIZE_256 (0 << PKE_REGSHIFT_SEG_SIZE_SEGSIZE)
|
||||
#define PKE_REGVAL_SEG_SIZE_SEGSIZE_128 (1 << PKE_REGSHIFT_SEG_SIZE_SEGSIZE)
|
||||
#define PKE_REGVAL_SEG_SIZE_SEGSIZE_64 (2 << PKE_REGSHIFT_SEG_SIZE_SEGSIZE)
|
||||
#define PKE_REGVAL_SEG_SIZE_FUNC_ID_AB (0 << PKE_REGSHIFT_SEG_SIZE_FUNC_ID)
|
||||
#define PKE_REGVAL_SEG_SIZE_FUNC_ID_A1 (1 << PKE_REGSHIFT_SEG_SIZE_FUNC_ID)
|
||||
|
||||
/** \enum PKE_SegID_et
|
||||
* enumeation of segment ID
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PKE_SEG_ID_00 = 0,
|
||||
PKE_SEG_ID_01,
|
||||
PKE_SEG_ID_02,
|
||||
PKE_SEG_ID_03,
|
||||
PKE_SEG_ID_04,
|
||||
PKE_SEG_ID_05,
|
||||
PKE_SEG_ID_06, /*last segment ID in the 256byte segment block*/
|
||||
PKE_SEG_ID_07,
|
||||
PKE_SEG_ID_08,
|
||||
PKE_SEG_ID_09,
|
||||
PKE_SEG_ID_10,
|
||||
PKE_SEG_ID_11,
|
||||
PKE_SEG_ID_12,
|
||||
PKE_SEG_ID_13,
|
||||
PKE_SEG_ID_14, /*last segment ID in the 128byte segment block*/
|
||||
PKE_SEG_ID_15,
|
||||
PKE_SEG_ID_16,
|
||||
PKE_SEG_ID_17,
|
||||
PKE_SEG_ID_18,
|
||||
PKE_SEG_ID_19,
|
||||
PKE_SEG_ID_20,
|
||||
PKE_SEG_ID_21,
|
||||
PKE_SEG_ID_22,
|
||||
PKE_SEG_ID_23,
|
||||
PKE_SEG_ID_24,
|
||||
PKE_SEG_ID_25,
|
||||
PKE_SEG_ID_26,
|
||||
PKE_SEG_ID_27,
|
||||
PKE_SEG_ID_28,
|
||||
PKE_SEG_ID_29 /*last segment ID in the 64byte segment block*/
|
||||
}PKE_SegID_et;
|
||||
|
||||
enum {
|
||||
mod_segid = PKE_SEG_ID_00, /* ! moduler seg id MUST be '0' */
|
||||
tmp_segid = PKE_SEG_ID_01,
|
||||
acum_segid = PKE_SEG_ID_02,
|
||||
iter_segid = PKE_SEG_ID_03
|
||||
};
|
||||
|
||||
|
||||
#endif /* _IOKIT_APPLES5L8900XPKE_HARDWARE_H */
|
||||
@@ -0,0 +1,930 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
# $Copyright:
|
||||
# ----------------------------------------------------------------
|
||||
# This confidential and proprietary software may be used only as
|
||||
# authorized by a licensing agreement from Samsung Limited
|
||||
# (C) COPYRIGHT 1999,2001,2002 Samsung Limited
|
||||
# ALL RIGHTS RESERVED
|
||||
# The entire notice above must be reproduced on all authorized
|
||||
# copies and copies may only be made to the extent permitted
|
||||
# by a licensing agreement from Samsung Limited.
|
||||
# ----------------------------------------------------------------
|
||||
# File: DevPke_R2modM.s
|
||||
# Tornado2 File: tor_cal_R2modM.s
|
||||
# Revision: 1.0
|
||||
# 2004.05.18. V1.0
|
||||
# - Calculate R^2 modM value
|
||||
# 2005.01.12 V1.1
|
||||
# - ARM/Thumb interworking enabled in ARMv4(SC100)
|
||||
#
|
||||
# ----------------------------------------------------------------
|
||||
# Assembler Tornado device driver
|
||||
#
|
||||
# adapted for as(1); comments are bumped to the next line.
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
.text
|
||||
|
||||
.globl _L_TCR_BASE
|
||||
.globl _L_SEG_BASE
|
||||
|
||||
# TORNADO2 control area 0x3D000000
|
||||
# Segment base address 0x3D000800
|
||||
_L_TCR_BASE: .long PKE_BASE_ADDR
|
||||
_L_SEG_BASE: .long PKE_BASE_ADDR+0x0800
|
||||
|
||||
# segment ids used for calculation depending on segment size
|
||||
.set SEG_4, 04
|
||||
.set SEG_5, 05
|
||||
.set SEG_6, 06
|
||||
.set SEG_12, 12
|
||||
.set SEG_13, 13
|
||||
.set SEG_14, 14
|
||||
.set SEG_27, 27
|
||||
.set SEG_28, 28
|
||||
.set SEG_29, 29
|
||||
|
||||
L_00000040: .long 0x00000040
|
||||
L_00004000: .long 0x00004000
|
||||
L_20000000: .long 0x20000000
|
||||
|
||||
# segment operand operation config
|
||||
L_04040006: .long 0x04040006
|
||||
L_05050004: .long 0x05050004
|
||||
L_05050006: .long 0x05050006
|
||||
L_06060005: .long 0x06060005
|
||||
L_0C0C000E: .long 0x0C0C000E
|
||||
L_0D0D000C: .long 0x0D0D000C
|
||||
L_0D0D000E: .long 0x0D0D000E
|
||||
L_0E0E000D: .long 0x0E0E000D
|
||||
L_1B1B001D: .long 0x1B1B001D
|
||||
L_1C1C001D: .long 0x1C1C001D
|
||||
L_1C1C001b: .long 0x1C1C001b
|
||||
L_1D1D001C: .long 0x1D1D001C
|
||||
|
||||
# bit test mask
|
||||
L_80000000: .long 0x80000000
|
||||
|
||||
|
||||
# BIT_LEN is programmer defined real key size.
|
||||
|
||||
###############################################
|
||||
#### NAME : PkeCalR2modM ####
|
||||
#### Tornado NAME : tor_cal_R2modM ####
|
||||
###############################################
|
||||
.globl _PkeCalR2modM
|
||||
#================================================
|
||||
# Name : PkeCalR2modM(int BIT_LEN)
|
||||
# Tornado Name : tor_cal_R2modM(int BIT_LEN)
|
||||
# Function : 1. Clear the last 3 segment area
|
||||
# 2. Calculate R*2^((C/16)+1) modM value
|
||||
# 3. Calculate R*RmodM by using TORNADO
|
||||
# and save this value in Seg6 or Seg14 or Seg29.
|
||||
# 4. Clear temp segment area.
|
||||
# Requisite : Modulus value must be copied from memory to Seg0
|
||||
# before using this function.
|
||||
# Argument
|
||||
# int BIT_LEN : real Key size
|
||||
#================================================
|
||||
_PkeCalR2modM:
|
||||
stmfd sp!, {r1-r12,lr}
|
||||
# reserved register values
|
||||
# r0 = BIT_LEN
|
||||
# r12= Loop_count(hw_size/32)
|
||||
#====================
|
||||
# Clear CryptoRAM area (Seg4 ~ Seg6) when SEG_SIZE=0
|
||||
#====================
|
||||
# read SEG_SIZE
|
||||
ldr r1, _L_TCR_BASE
|
||||
ldr r2, [r1,$0x14]
|
||||
and r2, r2, $0xC0
|
||||
mov r2, r2, LSR #6
|
||||
cmp r2, #1
|
||||
bhi clr_64
|
||||
# 1 segment = 64byte
|
||||
blt clr_256
|
||||
# 1 segment = 256byte
|
||||
|
||||
## else 1 segment =128byte
|
||||
ldr r1, =SEG_12
|
||||
# Start position
|
||||
ldr r2,_L_SEG_BASE
|
||||
orr r1,r2,r1, lsl #7
|
||||
ldr r2, =96
|
||||
b start_clr
|
||||
clr_64:
|
||||
ldr r1, =SEG_27
|
||||
# Start position
|
||||
ldr r2,_L_SEG_BASE
|
||||
orr r1,r2,r1, lsl #6
|
||||
ldr r2, =48
|
||||
b start_clr
|
||||
clr_256:
|
||||
ldr r1, =SEG_4
|
||||
# Start position
|
||||
ldr r2,_L_SEG_BASE
|
||||
orr r1,r2,r1, lsl #8
|
||||
ldr r2, =192
|
||||
start_clr:
|
||||
mov r3,#0
|
||||
mov r4,r3
|
||||
mov r5,r3
|
||||
mov r6,r3
|
||||
mov r7,r3
|
||||
mov r8,r3
|
||||
mov r9,r3
|
||||
mov r10,r3
|
||||
clear_loop_cal:
|
||||
stmia r1!, {r3-r10}
|
||||
subs r2,r2,#8
|
||||
bne clear_loop_cal
|
||||
#====================================================
|
||||
# Calculate Montgomery constant
|
||||
#====================================================
|
||||
# 1. Calculate R0=R*2^((c/16)+1)modM
|
||||
# 2. Calculate R1,R2, .. Rn
|
||||
# R[i]=(R[i-1]^2)*R^(-1)modM
|
||||
# n such that 2^n=p*16 (p=1 ==> n=4 # ... P=4 ==> n=6)
|
||||
# 3. If final output is neg, change it to pos one
|
||||
#=====================================================
|
||||
mov r1,r0
|
||||
# save BIT_LEN in r1
|
||||
#====================
|
||||
# Calculate R0=R*2^((c/16)+1)modM
|
||||
#====================
|
||||
|
||||
# cal power=(p*(c+16)+(c/16)+1)
|
||||
ldr r0, _L_TCR_BASE
|
||||
ldr r0,[r0]
|
||||
and r2,r0,#0x03
|
||||
add r2,r2,#1
|
||||
# p value
|
||||
and r3,r0,#0x78
|
||||
add r3,r3,#0x08
|
||||
mov r3,r3, lsl #2
|
||||
# c value
|
||||
mul r12,r2,r3
|
||||
mov r12,r12,LSR #5
|
||||
# r12= Loop_count(hw_size/32)
|
||||
add r4,r3,#16
|
||||
mul r6,r4,r2
|
||||
# r6=p*(c+16)
|
||||
mov r5,r3, LSR #4
|
||||
add r5,r5,#1
|
||||
# r5=(c/16)+1
|
||||
mov r0, #3
|
||||
mov r3,r5
|
||||
cmp r2, #3
|
||||
muleq r5,r3,r0
|
||||
# precision = 0x10 case
|
||||
add r2,r6,r5
|
||||
# store power in r2
|
||||
|
||||
# calculate b value
|
||||
ldr r0, _L_SEG_BASE
|
||||
add r3,r1,#31
|
||||
mov r3,r3,LSR #5
|
||||
# r3= (BIT_LEN+31)/32
|
||||
mov r3,r3,lsl #2
|
||||
sub r3,r3,#4
|
||||
add r0,r0,r3
|
||||
# r0 = MSW address of Modulus
|
||||
mov r7,r1
|
||||
# r7= BIT_LEN
|
||||
add r7,r7,#0x1F
|
||||
mov r7,r7,LSR #5
|
||||
mov r7,r7,lsl #5
|
||||
# r7=(r7+31)/32*32
|
||||
next_MSW:
|
||||
# Searching MSW
|
||||
cmp r7,#0
|
||||
beq end_tor_calR2
|
||||
## if r2=0 then goto end_...
|
||||
ldr r4,[r0],#-4
|
||||
cmp r4,#0
|
||||
subeq r7,r7,#32
|
||||
beq next_MSW
|
||||
ldr r5,L_80000000
|
||||
next_MSB:
|
||||
ands r6,r4,r5
|
||||
subeq r7,r7,#1
|
||||
mov r5,r5,LSR #1
|
||||
beq next_MSB
|
||||
|
||||
# b = r7
|
||||
sub r3,r2,r7
|
||||
# r3=power - b
|
||||
|
||||
# b is real bit size of Modulus
|
||||
|
||||
# cal a=8-(power-b)%8 (1<= a <=8)
|
||||
mod8_loop:
|
||||
cmp r3,#8
|
||||
blt cal_a
|
||||
sub r3,r3,#8
|
||||
b mod8_loop
|
||||
cal_a:
|
||||
rsb r3,r3,#8
|
||||
# r3=a
|
||||
|
||||
# read SEG_SIZE
|
||||
ldr r4, _L_TCR_BASE
|
||||
ldr r8, [r4,#0x14]
|
||||
and r8, r8, #0xC0
|
||||
mov r8, r8, LSR #6
|
||||
cmp r8, #1
|
||||
bhi cal_64
|
||||
# 1 segment = 64byte
|
||||
blt cal_256
|
||||
# 1 segment = 256byte
|
||||
|
||||
## else 1 segment =128byte
|
||||
ldr r4, =SEG_12
|
||||
# Start position
|
||||
ldr r8,_L_SEG_BASE
|
||||
orr r4,r8,r4, lsl #7
|
||||
b cal_segset_endup
|
||||
cal_64:
|
||||
ldr r4, =SEG_28
|
||||
# Start position
|
||||
ldr r8,_L_SEG_BASE
|
||||
orr r4,r8,r4, lsl #6
|
||||
b cal_segset_endup
|
||||
cal_256:
|
||||
ldr r4, =SEG_5
|
||||
# Start position
|
||||
ldr r8,_L_SEG_BASE
|
||||
orr r4,r8,r4, lsl #8
|
||||
cal_segset_endup:
|
||||
sub r5,r7,r3
|
||||
mov r6,r5, LSR #5
|
||||
add r4,r4,r6, lsl #2
|
||||
# r4=SEG_4+((b-a)/32)*4
|
||||
mod32_loop:
|
||||
cmp r5,#32
|
||||
blt load_power
|
||||
sub r5,r5,#32
|
||||
# r5=(b-a)%32
|
||||
b mod32_loop
|
||||
load_power:
|
||||
mov r6,#0x01
|
||||
mov r6,r6, lsl r5
|
||||
str r6,[r4]
|
||||
# (0x01<<(BIT_LEN-a)%32)
|
||||
div_modM:
|
||||
#loop round value < ((power-b+a)/8)
|
||||
sub r2,r2,r7
|
||||
add r2,r2,r3
|
||||
mov r0,r2,LSR #3
|
||||
# r0=(power-b+a)/8
|
||||
|
||||
# reserved reg : r0, r1=BIT_LEN, r12=hw_size/32
|
||||
|
||||
# available reg :r2-11
|
||||
stmfd sp!, {r0}
|
||||
# available reg :r0,r2-r12 r1=store r12 value while shift_block
|
||||
#====================
|
||||
# Start div_byte
|
||||
#====================
|
||||
start_div_byte:
|
||||
mov r3,#9
|
||||
# 9=8 count value +1
|
||||
stmfd sp!,{r3}
|
||||
# !!tor_dev_byte 8 count value is saved in stack!!
|
||||
mov r1,r12
|
||||
reload_shift:
|
||||
# read SEG_SIZE
|
||||
ldr r0, _L_TCR_BASE
|
||||
ldr r2, [r0,#0x14]
|
||||
and r2, r2, #0xC0
|
||||
mov r2, r2, LSR #6
|
||||
cmp r2, #1
|
||||
bhi reload_64
|
||||
# 1 segment = 64byte
|
||||
blt reload_256
|
||||
# 1 segment = 256byte
|
||||
|
||||
## else 1 segment =128byte
|
||||
ldr r0, =SEG_12
|
||||
# Start position
|
||||
ldr r2,_L_SEG_BASE
|
||||
orr r0,r2,r0, lsl #7
|
||||
b reload_segset_endup
|
||||
reload_64:
|
||||
ldr r0, =SEG_28
|
||||
# Start position
|
||||
ldr r2,_L_SEG_BASE
|
||||
orr r0,r2,r0, lsl #6
|
||||
b reload_segset_endup
|
||||
reload_256:
|
||||
ldr r0, =SEG_5
|
||||
# Start position
|
||||
ldr r2,_L_SEG_BASE
|
||||
orr r0,r2,r0, lsl #8
|
||||
reload_segset_endup:
|
||||
mov r3,#0
|
||||
# clr r3
|
||||
mov r12,r1
|
||||
ldmfd sp!,{r5}
|
||||
subs r5,r5,#1
|
||||
stmfd sp!,{r5}
|
||||
beq end_div_byte
|
||||
cmp r12,#8
|
||||
blt shift_one
|
||||
#====================
|
||||
# Start shift left operation
|
||||
#====================
|
||||
shift_block:
|
||||
|
||||
# r0=address,r3=carry1,r2=carry2
|
||||
|
||||
# r4-r11=working reg,r12=shift loop counter
|
||||
#ldm r0, {r4-r11}
|
||||
ldmia r0, {r4,r5,r6,r7,r8,r9,r10,r11}
|
||||
mov r2,r4, LSR #31
|
||||
# save carry
|
||||
add r4,r3,r4, lsl #1
|
||||
# shift
|
||||
mov r3,r5, LSR #31
|
||||
# save carry
|
||||
add r5,r2,r5, lsl #1
|
||||
# shift
|
||||
mov r2,r6, LSR #31
|
||||
# save carry
|
||||
add r6,r3,r6, lsl #1
|
||||
# shift
|
||||
mov r3,r7, LSR #31
|
||||
# save carry
|
||||
add r7,r2,r7, lsl #1
|
||||
# shift
|
||||
mov r2,r8, LSR #31
|
||||
# save carry
|
||||
add r8,r3,r8, lsl #1
|
||||
# shift
|
||||
mov r3,r9, LSR #31
|
||||
# save carry
|
||||
add r9,r2,r9, lsl #1
|
||||
# shift
|
||||
mov r2,r10, LSR #31
|
||||
# save carry
|
||||
add r10,r3,r10, lsl #1
|
||||
# shift
|
||||
mov r3,r11, LSR #31
|
||||
# save carry
|
||||
add r11,r2,r11, lsl #1
|
||||
# shift
|
||||
stmia r0!,{r4-r11}
|
||||
sub r12,r12,#8
|
||||
cmp r12,#8
|
||||
bge shift_block
|
||||
shift_one:
|
||||
cmp r12,#0
|
||||
beq cmp_carry1
|
||||
ldr r4,[r0]
|
||||
mov r2,r4, LSR #31
|
||||
add r4,r3,r4, lsl #1
|
||||
mov r3,r2
|
||||
str r4,[r0],#4
|
||||
sub r12,r12,#1
|
||||
b shift_one
|
||||
#====================
|
||||
# Start compare operation
|
||||
#====================
|
||||
cmp_carry1:
|
||||
cmp r3,#0
|
||||
bne tor_sub
|
||||
greater_equal:
|
||||
|
||||
# available reg:r2-r12
|
||||
sub r0,r0 ,#4
|
||||
# MSW address of power(0xE04XX)
|
||||
ldr r2, _L_SEG_BASE
|
||||
# Modulus pointer value
|
||||
and r3,r0,#0xFF
|
||||
add r2,r2,r3
|
||||
# MSW address of Modulus(0xE00XX)
|
||||
test_loop:
|
||||
ldr r3,[r0],#-4
|
||||
# r3=power value
|
||||
ldr r4,[r2],#-4
|
||||
# r2=Modulus value
|
||||
cmp r3,r4
|
||||
beq test_loop
|
||||
bhi tor_sub
|
||||
# pow>Mod
|
||||
|
||||
# pow <Mod
|
||||
mov r3,#0
|
||||
# clr carry1 for shift_block
|
||||
mov r12,r1
|
||||
# reload hw_size/32 (word count value)
|
||||
b reload_shift
|
||||
#====================
|
||||
# Do Power - Modulus
|
||||
#====================
|
||||
tor_sub:
|
||||
|
||||
# read SEG_SIZE
|
||||
ldr r0, _L_TCR_BASE
|
||||
ldr r3, [r0,#0x14]
|
||||
and r3, r3, #0xC0
|
||||
mov r3, r3, LSR #6
|
||||
cmp r3, #1
|
||||
bhi sub_64
|
||||
# 1 segment = 64byte
|
||||
blt sub_256
|
||||
# 1 segment = 256byte
|
||||
|
||||
## else 1 segment =128byte
|
||||
ldr r0, =SEG_12
|
||||
# Start position
|
||||
cmp r0, #0
|
||||
# !! Set carry for sub !!
|
||||
ldr r3,_L_SEG_BASE
|
||||
orr r0,r3,r0, lsl #7
|
||||
b sub_segset_endup
|
||||
sub_64:
|
||||
ldr r0, =SEG_28
|
||||
# Start position
|
||||
cmp r0, #0
|
||||
# !! Set carry for sub !!
|
||||
ldr r3,_L_SEG_BASE
|
||||
orr r0,r3,r0, lsl #6
|
||||
b sub_segset_endup
|
||||
sub_256:
|
||||
ldr r0, =SEG_5
|
||||
# Start position
|
||||
cmp r0, #0
|
||||
# !! Set carry for sub !!
|
||||
ldr r3,_L_SEG_BASE
|
||||
orr r0,r3,r0, lsl #8
|
||||
sub_segset_endup:
|
||||
mov r12,r1
|
||||
# reload hw_size/32 (word count value)
|
||||
mov r2,#0
|
||||
# clear r2
|
||||
and r4,r12,#0x07
|
||||
# check multiple of 8
|
||||
teq r4,#0
|
||||
beq multy_sub
|
||||
single_sub:
|
||||
ldr r5,[r0]
|
||||
# load power
|
||||
ldr r6,[r3],#4
|
||||
# load M
|
||||
sbcs r5,r5,r6
|
||||
str r5,[r0],#4
|
||||
sub r12,r12,#1
|
||||
sub r4,r4,#1
|
||||
teq r4,#0
|
||||
bne single_sub
|
||||
teq r12,#0
|
||||
beq sub_end
|
||||
#r4,r5,r6,....r11 available
|
||||
multy_sub:
|
||||
ldmia r0, {r4-r7}
|
||||
# load power
|
||||
ldmia r3!, {r8-r11}
|
||||
# load M
|
||||
sbcs r4, r4, r8
|
||||
sbcs r5, r5, r9
|
||||
sbcs r6, r6, r10
|
||||
sbcs r7, r7, r11
|
||||
stmia r0!, {r4-r7}
|
||||
|
||||
ldmia r0, {r4-r7}
|
||||
# load power
|
||||
ldmia r3!, {r8-r11}
|
||||
# load M
|
||||
sbcs r4, r4, r8
|
||||
sbcs r5, r5, r9
|
||||
sbcs r6, r6, r10
|
||||
sbcs r7, r7, r11
|
||||
stmia r0!, {r4-r7}
|
||||
sub r12, r12, #8
|
||||
# don't change carry
|
||||
teq r12, #0
|
||||
# don't change carry
|
||||
bne multy_sub
|
||||
sub_end:
|
||||
b reload_shift
|
||||
#====================
|
||||
# End div_byte
|
||||
#====================
|
||||
end_div_byte:
|
||||
mov r12,r1
|
||||
ldmfd sp!,{r4,r5}
|
||||
# r4 = 8 counter, r5=(pwr-b+a)/8
|
||||
subs r5,r5,#1
|
||||
stmfd sp!,{r5}
|
||||
bne start_div_byte
|
||||
# restart tor_div_byte
|
||||
ldmfd sp!,{r5}
|
||||
# release SP (stack pointer)
|
||||
#====================
|
||||
# Calculate R1 to Rn
|
||||
#====================
|
||||
ldr r0, _L_TCR_BASE
|
||||
mov r2,#0x01
|
||||
ldr r3,[r0]
|
||||
ldr r5,[r0,#0x14]
|
||||
and r5, r5, #0xC0
|
||||
mov r5, r5, LSR #6
|
||||
# SEG_SIZE value
|
||||
and r4,r3,#0x03
|
||||
# r4=precision
|
||||
cmp r4,#1
|
||||
bhi mon_mul_6
|
||||
beq mon_mul_5
|
||||
mon_mul_4:
|
||||
|
||||
# run 1
|
||||
ldr r3, L_1C1C001D
|
||||
# Seg29=Seg28*Seg28
|
||||
cmp r5,#0
|
||||
ldreq r3, L_05050006
|
||||
# Seg6=Seg5 * Seg5
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0C0C000E
|
||||
# Seg14=Seg12*Seg12
|
||||
mov r4,#0x09
|
||||
# run TORNADO with preload
|
||||
str r3,[r0,#0xC]
|
||||
# write TCR_1
|
||||
str r4,[r0,#8]
|
||||
# write CTR2
|
||||
## !!! S/W Pooling !!!
|
||||
bl sw_polling_loop
|
||||
|
||||
|
||||
# run 2
|
||||
ldr r3, L_1D1D001C
|
||||
# Seg28=Seg29*Seg29
|
||||
cmp r5,#0
|
||||
ldreq r3, L_06060005
|
||||
# Seg5=Seg6 * Seg6
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0E0E000D
|
||||
# Seg13=Seg14*Seg14
|
||||
bl start_tor_cal
|
||||
|
||||
# run 3
|
||||
ldr r3, L_1C1C001b
|
||||
# Seg27=Seg28*Seg28
|
||||
cmp r5,#0
|
||||
ldreq r3, L_05050004
|
||||
# Seg4=Seg5 * Seg5
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0D0D000C
|
||||
# Seg12=Seg13*Seg13
|
||||
bl start_tor_cal
|
||||
|
||||
# run 4
|
||||
ldr r3, L_1B1B001D
|
||||
# Seg29=Seg27*Seg27
|
||||
ldr r6, L_20000000
|
||||
# check SEG_SIGN of Seg29
|
||||
cmp r5,#0
|
||||
ldreq r3, L_04040006
|
||||
# Seg6=Seg4 * Seg4
|
||||
ldreq r6, L_00000040
|
||||
# check SEG_SIGN of Seg6
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0C0C000E
|
||||
# Seg14=Seg12*Seg12
|
||||
ldreq r6, L_00004000
|
||||
# check SEG_SIGN of Seg14
|
||||
bl start_tor_cal
|
||||
|
||||
ldr r5,[r0,#0x10]
|
||||
ands r5,r5,r6
|
||||
# read SOS bit
|
||||
bne add_modulus
|
||||
b clear_end
|
||||
mon_mul_5:
|
||||
|
||||
# run 1
|
||||
ldr r3, L_1C1C001D
|
||||
# Seg29=Seg28*Seg28
|
||||
cmp r5,#0
|
||||
ldreq r3, L_05050006
|
||||
# Seg6=Seg5 * Seg5
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0C0C000E
|
||||
# Seg14=Seg12*Seg12
|
||||
mov r4,#0x09
|
||||
# run TORNADO with preload
|
||||
str r3,[r0,#0xC]
|
||||
# write CTR1
|
||||
str r4,[r0,#8]
|
||||
# write CTR2
|
||||
## !!! S/W Pooling !!!
|
||||
bl sw_polling_loop
|
||||
|
||||
|
||||
# run 2
|
||||
ldr r3, L_1D1D001C
|
||||
# Seg28=Seg29*Seg29
|
||||
cmp r5,#0
|
||||
ldreq r3, L_06060005
|
||||
# Seg5=Seg6 * Seg6
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0E0E000D
|
||||
# Seg13=Seg14*Seg14
|
||||
bl start_tor_cal
|
||||
|
||||
# run 3
|
||||
ldr r3, L_1C1C001D
|
||||
# Seg29=Seg28*Seg28
|
||||
cmp r5,#0
|
||||
ldreq r3, L_05050006
|
||||
# Seg6=Seg5 * Seg5
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0D0D000E
|
||||
# Seg14=Seg13*Seg13
|
||||
bl start_tor_cal
|
||||
|
||||
# run 4
|
||||
ldr r3, L_1D1D001C
|
||||
# Seg28=Seg29*Seg29
|
||||
cmp r5,#0
|
||||
ldreq r3, L_06060005
|
||||
# Seg5=Seg6 * Seg6
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0E0E000D
|
||||
# Seg13=Seg14*Seg14
|
||||
bl start_tor_cal
|
||||
|
||||
# run 5
|
||||
ldr r3, L_1C1C001D
|
||||
# Seg29=Seg28*Seg28
|
||||
ldr r6, L_20000000
|
||||
# check SEG_SIGN of Seg29
|
||||
cmp r5,#0
|
||||
ldreq r3, L_05050006
|
||||
# Seg6=Seg5 * Seg5
|
||||
ldreq r6, L_00000040
|
||||
# check SEG_SIGN of Seg6
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0D0D000E
|
||||
# Seg14=Seg13*Seg13
|
||||
ldreq r6, L_00004000
|
||||
# check SEG_SIGN of Seg14
|
||||
bl start_tor_cal
|
||||
|
||||
ldr r5,[r0,#0x10]
|
||||
ands r5,r5,r6
|
||||
# read SOS bit
|
||||
bne add_modulus
|
||||
b clear_end
|
||||
mon_mul_6:
|
||||
cmp r4,#0x02
|
||||
# In case of precision=3
|
||||
beq mon_mul_4
|
||||
|
||||
# run 1
|
||||
ldr r3, L_1C1C001D
|
||||
# Seg29=Seg28*Seg28
|
||||
cmp r5,#0
|
||||
ldreq r3, L_05050006
|
||||
# Seg6=Seg5 * Seg5
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0C0C000E
|
||||
# Seg14=Seg12*Seg12
|
||||
mov r4,#0x09
|
||||
# run TORNADO with preload
|
||||
str r3,[r0,#0xC]
|
||||
# write CTR1
|
||||
str r4,[r0,#8]
|
||||
# write CTR2
|
||||
## !!! S/W Pooling !!!
|
||||
bl sw_polling_loop
|
||||
|
||||
|
||||
# run 2
|
||||
ldr r3, L_1D1D001C
|
||||
# Seg28=Seg29*Seg29
|
||||
cmp r5,#0
|
||||
ldreq r3, L_06060005
|
||||
# Seg5=Seg6 * Seg6
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0E0E000D
|
||||
# Seg13=Seg14*Seg14
|
||||
bl start_tor_cal
|
||||
|
||||
# run 3
|
||||
ldr r3, L_1C1C001D
|
||||
# Seg29=Seg28*Seg28
|
||||
cmp r5,#0
|
||||
ldreq r3, L_05050006
|
||||
# Seg6=Seg5 * Seg5
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0D0D000E
|
||||
# Seg14=Seg13*Seg13
|
||||
bl start_tor_cal
|
||||
|
||||
# run 4
|
||||
ldr r3, L_1D1D001C
|
||||
# Seg28=Seg29*Seg29
|
||||
cmp r5,#0
|
||||
ldreq r3, L_06060005
|
||||
# Seg5=Seg6 * Seg6
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0E0E000D
|
||||
# Seg13=Seg14*Seg14
|
||||
bl start_tor_cal
|
||||
|
||||
# run 5
|
||||
ldr r3, L_1C1C001b
|
||||
# Seg27=Seg28*Seg28
|
||||
cmp r5,#0
|
||||
ldreq r3, L_05050004
|
||||
# Seg4=Seg5 * Seg5
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0D0D000C
|
||||
# Seg12=Seg13*Seg13
|
||||
bl start_tor_cal
|
||||
|
||||
# run 6
|
||||
ldr r3, L_1B1B001D
|
||||
# Seg29=Seg27*Seg27
|
||||
ldr r6, L_20000000
|
||||
# check SEG_SIGN of Seg29
|
||||
cmp r5,#0
|
||||
ldreq r3, L_04040006
|
||||
# Seg6=Seg4 * Seg4
|
||||
ldreq r6, L_00000040
|
||||
# check SEG_SIGN of Seg6
|
||||
cmp r5,#1
|
||||
ldreq r3, L_0C0C000E
|
||||
# Seg14=Seg12*Seg12
|
||||
ldreq r6, L_00004000
|
||||
# check SEG_SIGN of Seg14
|
||||
bl start_tor_cal
|
||||
|
||||
ldr r5,[r0,#0x10]
|
||||
ands r5,r5,r6
|
||||
# read SOS bit
|
||||
bne add_modulus
|
||||
b clear_end
|
||||
|
||||
start_tor_cal:
|
||||
str r3,[r0,#0xC]
|
||||
# write TCR_3
|
||||
str r2,[r0,#8]
|
||||
# write TCR_2
|
||||
## sw polling for FPGA and CO-Working processor setting
|
||||
sw_polling_loop:
|
||||
ldr r4,[r0,#0x08]
|
||||
ands r4,r4,#0x01
|
||||
bne sw_polling_loop
|
||||
mov pc,lr
|
||||
|
||||
add_modulus:
|
||||
|
||||
# read SEG_SIZE
|
||||
ldr r0, _L_TCR_BASE
|
||||
ldr r1, [r0,#0x14]
|
||||
and r1, r1, #0xC0
|
||||
mov r1, r1, LSR #6
|
||||
cmp r1, #1
|
||||
bhi add_64
|
||||
# 1 segment = 64byte
|
||||
blt add_256
|
||||
# 1 segment = 256byte
|
||||
|
||||
## else 1 segment =128byte
|
||||
ldr r0, =SEG_14
|
||||
# Start position
|
||||
ldr r1,_L_SEG_BASE
|
||||
orr r0,r1,r0, lsl #7
|
||||
b add_segset_endup
|
||||
add_64:
|
||||
ldr r0, =SEG_29
|
||||
# Start position
|
||||
ldr r1,_L_SEG_BASE
|
||||
orr r0,r1,r0, lsl #6
|
||||
b add_segset_endup
|
||||
add_256:
|
||||
ldr r0, =SEG_6
|
||||
# Start position
|
||||
ldr r1,_L_SEG_BASE
|
||||
orr r0,r1,r0, lsl #8
|
||||
add_segset_endup:
|
||||
movs r2,r2, LSR #2
|
||||
# clear Carry
|
||||
and r4,r12,#0x03
|
||||
# check multiple of 4
|
||||
teq r4,#0
|
||||
beq multy_add
|
||||
single_add:
|
||||
ldr r5,[r0]
|
||||
ldr r6,[r1],#4
|
||||
adcs r5,r5,r6
|
||||
str r5,[r0],#4
|
||||
sub r12,r12,#1
|
||||
sub r4,r4,#1
|
||||
teq r4,#0
|
||||
bne single_add
|
||||
teq r12,#0
|
||||
beq clear_end
|
||||
multy_add:
|
||||
ldmia r0, {r3-r6}
|
||||
# load Source data
|
||||
ldmia r1!, {r7-r10}
|
||||
# load M
|
||||
adcs r3, r3, r7
|
||||
adcs r4, r4, r8
|
||||
adcs r5, r5, r9
|
||||
adcs r6, r6, r10
|
||||
stmia r0!, {r3-r6}
|
||||
sub r12,r12, #4
|
||||
teq r12,#0
|
||||
bne multy_add
|
||||
|
||||
#====================
|
||||
# clear used temp area
|
||||
#====================
|
||||
clear_end:
|
||||
|
||||
# read SEG_SIZE
|
||||
ldr r0, _L_TCR_BASE
|
||||
ldr r0,[r0,#0x14]
|
||||
and r1,r0,#0xC0
|
||||
mov r1, r1, LSR #6
|
||||
cmp r1, #1
|
||||
bhi clear_64
|
||||
# 1 segment = 64byte
|
||||
blt clear_256
|
||||
# 1 segment = 256byte
|
||||
|
||||
## else 1 segment =128byte
|
||||
ldr r0, =SEG_12
|
||||
# Start position
|
||||
ldr r1,_L_SEG_BASE
|
||||
orr r0,r1,r0, lsl #7
|
||||
ldr r1, =64
|
||||
b start_clear
|
||||
clear_64:
|
||||
ldr r0, =SEG_27
|
||||
# Start position
|
||||
ldr r1,_L_SEG_BASE
|
||||
orr r0,r1,r0, lsl #6
|
||||
ldr r1, =32
|
||||
b start_clear
|
||||
clear_256:
|
||||
ldr r0, =SEG_4
|
||||
# Start position
|
||||
ldr r1,_L_SEG_BASE
|
||||
orr r0,r1,r0, lsl #8
|
||||
ldr r1, =128
|
||||
# clear 2 segment
|
||||
start_clear:
|
||||
mov r2,#0
|
||||
mov r3,r2
|
||||
mov r4,r2
|
||||
mov r5,r2
|
||||
mov r6,r2
|
||||
mov r7,r2
|
||||
mov r8,r2
|
||||
mov r9,r2
|
||||
mov r10,r2
|
||||
clear_temp:
|
||||
stmia r0!, {r3-r10}
|
||||
subs r1,r1,#8
|
||||
bne clear_temp
|
||||
# clear the last segment sign value
|
||||
# read SEG_SIZE
|
||||
ldr r0, _L_TCR_BASE
|
||||
ldr r1, [r0,#0x14]
|
||||
and r1, r1, #0xC0
|
||||
mov r1, r1, LSR #6
|
||||
mov r0, #6
|
||||
cmp r1, #1
|
||||
moveq r0, #14
|
||||
# r0 = the last segment Num
|
||||
movhi r0, #29
|
||||
mov r1, #0x01
|
||||
mov r2,r1, lsl r0
|
||||
ldr r3, _L_TCR_BASE
|
||||
add r3,r3,#0x10
|
||||
ldr r4,[r3]
|
||||
bic r4,r4,r2
|
||||
str r4,[r3]
|
||||
end_tor_calR2:
|
||||
ldmfd sp!, {r1-r12,r14}
|
||||
# END PkeCalR2modM
|
||||
bx r14
|
||||
|
||||
# END
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <drivers/pke.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/power.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <string.h>
|
||||
#include <sys.h>
|
||||
|
||||
#include "AppleS5L8900XPKE-hardware.h"
|
||||
|
||||
|
||||
#define Pke_Shim_DEBUG 0
|
||||
|
||||
#if Pke_Shim_DEBUG
|
||||
static void debug_data(uint8_t *data, size_t length)
|
||||
{
|
||||
uint32_t i=0;
|
||||
printf("data %p,%d\n" , data, length);
|
||||
for (i = 0; i < length; i++) {
|
||||
if( !(i%256) )
|
||||
printf("Seg : %p \n", data);
|
||||
printf("%02X, ", *(data + i));
|
||||
if ((i % 16) == 15)
|
||||
printf("\n");
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
#define debug(fmt, args...) printf("pke_new::%s: " fmt "\n", __FUNCTION__ , ##args)
|
||||
#else
|
||||
#define debug(fmt, args...)
|
||||
#define debug_data(data, length)
|
||||
#endif
|
||||
|
||||
|
||||
//PKE hardware memory map.
|
||||
static volatile struct pke_regs *registers = (struct pke_regs *)PKE_BASE_ADDR;
|
||||
static volatile uint8_t *memory = (uint8_t*)(PKE_BASE_ADDR + 0x800);
|
||||
|
||||
extern bool rsa_cal_exp(void *dst, uint32_t *len, uint32_t options,
|
||||
uint8_t *rsquare, uint32_t *rsquare_length,
|
||||
uint8_t * const base, uint32_t base_length,
|
||||
uint8_t * const expn, uint32_t expn_length,
|
||||
uint8_t * const modulus, uint32_t modulus_length,
|
||||
volatile struct pke_regs *registers, volatile uint8_t *memory);
|
||||
|
||||
bool pke_do_exp(uint8_t *dst, size_t *len, size_t key_length,
|
||||
uint8_t * const base, size_t base_length,
|
||||
uint8_t * const expn, size_t expn_length,
|
||||
uint8_t * const mods, size_t mods_length)
|
||||
{
|
||||
bool ret = false;
|
||||
uint32_t rsquare[64]; //word aligned 256byte buffer.
|
||||
uint32_t rlen = sizeof(rsquare);
|
||||
|
||||
clock_gate(CLK_PKE, true);
|
||||
platform_power_set_gate(PWRBIT_USB, true);
|
||||
|
||||
#if Pke_Shim_DEBUG
|
||||
utime_t st, et;
|
||||
st = system_time();
|
||||
#endif
|
||||
ret = rsa_cal_exp(dst, (uint32_t*)len, 0,
|
||||
(uint8_t*)rsquare, &rlen,
|
||||
base, (uint32_t)base_length,
|
||||
expn, (uint32_t)expn_length,
|
||||
mods, (uint32_t)mods_length,
|
||||
registers, memory);
|
||||
#if Pke_Shim_DEBUG
|
||||
et = system_time();
|
||||
debug("rsa_cal_exp took %llu micros for keylen: %lu", (et-st), key_length);
|
||||
//debug("The result:");
|
||||
//debug_data(dst, *len);
|
||||
#endif
|
||||
|
||||
clock_gate(CLK_PKE, false);
|
||||
return ret;
|
||||
}
|
||||
@@ -0,0 +1,21 @@
|
||||
# Copyright (C) 2007-2008 Apple Inc. All rights reserved.
|
||||
# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_PKE=1
|
||||
|
||||
MODULES += \
|
||||
lib/pki
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/pke.o \
|
||||
$(LOCAL_DIR)/AppleS5L8900XPKE-hardware.o
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __SAMSUNG_RGBOUT_H
|
||||
#define __SAMSUNG_RGBOUT_H
|
||||
|
||||
void rgbout_enable_clocks(bool enable);
|
||||
void rgbout_init(struct display_timing *timing);
|
||||
void rgbout_enable_timing_generator(bool enable);
|
||||
bool rgbout_get_enable_timing_generator(void);
|
||||
void rgbout_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl);
|
||||
|
||||
#endif /* __SAMSUNG_RGBOUT_H */
|
||||
@@ -0,0 +1,107 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <drivers/display.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
#include "rgbout_regs.h"
|
||||
|
||||
static void rgbout_load_gamma_table();
|
||||
|
||||
void rgbout_enable_clocks(bool enable)
|
||||
{
|
||||
int device;
|
||||
|
||||
#ifdef DISP0_BASE_ADDR
|
||||
if (RGBOUT_DISPLAYPIPE_BASE_ADDR == DISP0_BASE_ADDR) {
|
||||
device = CLK_DISP0;
|
||||
} else
|
||||
#endif
|
||||
#ifdef DISP1_BASE_ADDR
|
||||
if (RGBOUT_DISPLAYPIPE_BASE_ADDR == DISP1_BASE_ADDR) {
|
||||
device = CLK_DISP1;
|
||||
} else
|
||||
#endif
|
||||
panic("rgb_enable_clocks: unsupported rgbout_displaypipe_base_addr: %p", (void *)RGBOUT_DISPLAYPIPE_BASE_ADDR);
|
||||
|
||||
// Enable/disable displaypipe and clcd clocks
|
||||
if (enable) {
|
||||
clock_gate(device, true);
|
||||
clock_gate(CLK_RGBOUT, true);
|
||||
}
|
||||
else {
|
||||
clock_gate(CLK_RGBOUT, false);
|
||||
clock_gate(device, false);
|
||||
}
|
||||
}
|
||||
|
||||
void rgbout_init(struct display_timing *timing)
|
||||
{
|
||||
// reset RBOUT
|
||||
rRGBOUTSRESET = 1;
|
||||
while((rRGBOUTSRESET & 1) != 0);
|
||||
|
||||
//configure RGBOUT
|
||||
rRGBOUTDITHCFG = 0; // disable dithering
|
||||
rRGBOUTOTFCON = 0; // no interlace, frame
|
||||
rRGBOUTOTFTCON6 = (timing->h_active - 1); // display width
|
||||
rRGBOUTOTFTCON3 = (timing->v_active - 1); // display height
|
||||
rRGBOUTCFG = (1 << 5) | (0 << 3) | (3); // color mode - RGB,
|
||||
// color space conversion - off
|
||||
// display-module - DP
|
||||
rRGBOUTPOPLATENCY = (timing->v_pulse_width + timing->v_back_porch - 2); // <rdar://problem/10134376>
|
||||
}
|
||||
|
||||
bool rgbout_get_enable_timing_generator(void)
|
||||
{
|
||||
return ((rRGBOUTCTL & ((1 << 3) | (1 << 0))) == ((1 << 3) | (1 << 0)));
|
||||
}
|
||||
|
||||
void rgbout_enable_timing_generator(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
rRGBOUTCTL = (1 << 3) | (1 << 0); // set rgbout-on, frontend-ready
|
||||
}
|
||||
else {
|
||||
rRGBOUTSRESET = 1; // reset
|
||||
while((rRGBOUTSRESET & 1) != 0);
|
||||
}
|
||||
}
|
||||
|
||||
void rgbout_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut)
|
||||
{
|
||||
const u_int32_t gamma_data[256] = {
|
||||
0x10044,0x11048,0x1204c,0x13050,0x14050,0x14054,0x15058,0x1605c,0x17060,0x18064,0x19068,0x1a06c,0x1b06c,0x1b070,0x1c074,0x1d078,0x1e07c,0x1f080,0x20084,0x21088,0x22088,0x2208c,0x23090,0x24094,0x25098,0x2609c,0x270a0,0x280a4,0x290a4,0x290a8,0x2a0ac,0x2b0b0,0x2c0b4,0x2d0b8,0x2e0bc,0x2f0c0,0x300c4,0x310c4,0x310c8,0x320cc,0x330d0,0x340d4,0x350d8,0x360dc,0x370e0,0x380e0,0x380e4,0x390e8,0x3a0ec,0x3b0f0,0x3c0f4,0x3d0f8,0x3e0fc,0x3f0fc,0x3f100,0x40104,0x41108,0x4210c,0x43110,0x44114,0x45118,0x46118,0x4611c,0x47120,0x48124,0x49128,0x4a12c,0x4b130,0x4c134,0x4d134,0x4d138,0x4e13c,0x4f140,0x50144,0x51148,0x5214c,0x53150,0x54154,0x55154,0x55158,0x5615c,0x57160,0x58164,0x59168,0x5a16c,0x5b170,0x5c170,0x5c174,0x5d178,0x5e17c,0x5f180,0x60184,0x61188,0x6218c,0x6318c,0x63190,0x64194,0x65198,0x6619c,0x671a0,0x681a4,0x691a8,0x6a1a8,0x6a1ac,0x6b1b0,0x6c1b4,0x6d1b8,0x6e1bc,0x6f1c0,0x701c4,0x711c8,0x721c8,0x721cc,0x731d0,0x741d4,0x751d8,0x761dc,0x771e0,0x781e4,0x791e4,0x791e8,0x7a1ec,0x7b1f0,0x7c1f4,0x7d1f8,0x7e1fc,0x7f200,0x80200,0x80204,0x81208,0x8220c,0x83210,0x84214,0x85218,0x8621c,0x8721c,0x87220,0x88224,0x89228,0x8a22c,0x8b230,0x8c234,0x8d238,0x8e238,0x8e23c,0x8f240,0x90244,0x91248,0x9224c,0x93250,0x94254,0x95258,0x96258,0x9625c,0x97260,0x98264,0x99268,0x9a26c,0x9b270,0x9c274,0x9d274,0x9d278,0x9e27c,0x9f280,0xa0284,0xa1288,0xa228c,0xa3290,0xa4290,0xa4294,0xa5298,0xa629c,0xa72a0,0xa82a4,0xa92a8,0xaa2ac,0xab2ac,0xab2b0,0xac2b4,0xad2b8,0xae2bc,0xaf2c0,0xb02c4,0xb12c8,0xb22cc,0xb32cc,0xb32d0,0xb42d4,0xb52d8,0xb62dc,0xb72e0,0xb82e4,0xb92e8,0xba2e8,0xba2ec,0xbb2f0,0xbc2f4,0xbd2f8,0xbe2fc,0xbf300,0xc0304,0xc1304,0xc1308,0xc230c,0xc3310,0xc4314,0xc5318,0xc631c,0xc7320,0xc8320,0xc8324,0xc9328,0xca32c,0xcb330,0xcc334,0xcd338,0xce33c,0xcf33c,0xcf340,0xd0344,0xd1348,0xd234c,0xd3350,0xd4354,0xd5358,0xd635c,0xd735c,0xd7360,0xd8364,0xd9368,0xda36c,0xdb370,0xdc374,0xdd378,0xde378,0xde37c,0xdf380,0xe0384,0xe1388,0xe238c,0xe3390,0xe4394,0xe5394,0xe5398,0xe639c,0xe73a0,0xe83a4,0xe93a8,0xea3ac,0xeb3b0,0xec3b0,0xec3b4,0xed3b8,0xee3bc,0xef3c0,0xef3c0
|
||||
};
|
||||
int i;
|
||||
u_int32_t reg_val;
|
||||
|
||||
// set write access for gamma table
|
||||
reg_val = rRGBOUTGMTBLACCCON;
|
||||
rRGBOUTGMTBLACCCON = reg_val & ~((1<<16) | (0xf<<12) | (0xff));
|
||||
|
||||
for (i = 0; i < 256; i++) {
|
||||
rRGBOUTGMTBLACCCON = reg_val | ((1 << 16) | (0x4 << 12) | (i)); // 0100 gamma for R
|
||||
rRGBOUTGMTBLWDATA = (0 << 31) | (gamma_data[i] & 0x000FFFFF);
|
||||
}
|
||||
|
||||
for (i = 0; i < 256; i++) {
|
||||
rRGBOUTGMTBLACCCON = reg_val | ((1 << 16) | (0x5 << 12) | (i)); // 0101 gamma for G
|
||||
rRGBOUTGMTBLWDATA = (0 << 31) | (gamma_data[i] & 0x000FFFFF);
|
||||
}
|
||||
|
||||
for (i = 0; i < 256; i++) {
|
||||
rRGBOUTGMTBLACCCON = reg_val | ((1 << 16) | (0x6 << 12) | (i)); // 0110 gamma for B
|
||||
rRGBOUTGMTBLWDATA = (0 << 31) | (gamma_data[i] & 0x000FFFFF);
|
||||
}
|
||||
|
||||
rRGBOUTGMCON = 0x9; // enable gamma correction
|
||||
}
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __SAMSUNG_RGBOUT_REGS_H
|
||||
#define __SAMSUNG_RGBOUT_REGS_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rRGBOUTCTL (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x00))
|
||||
#define rRGBOUTCFG (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x04))
|
||||
#define rRGBOUTSRESET (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x08))
|
||||
#define rRGBOUTDITHCFG (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x1C))
|
||||
#define rRGBOUTOTFCON (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x24))
|
||||
#define rRGBOUTOTFTCON3 (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x34))
|
||||
#define rRGBOUTOTFTCON6 (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x40))
|
||||
#define rRGBOUTGMCON (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x4C))
|
||||
#define rRGBOUTGMTBLACCCON (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x54))
|
||||
#define rRGBOUTGMTBLWDATA (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x58))
|
||||
#define rRGBOUTPOPLATENCY (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x6C))
|
||||
#define rRGBOUTDPCONSTCOLOR (*(volatile u_int32_t *)(RGBOUT_BASE_ADDR + 0x7C))
|
||||
|
||||
#endif /* __SAMSUNG_RGBOUT_REGS_H */
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (C) 2012 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
DISPLAYPIPE_BASE_ADDR=RGBOUT_DISPLAYPIPE_BASE_ADDR \
|
||||
WITH_DBE_RGBOUT=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/rgbout.o
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <sys/menu.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
|
||||
#include "rosc.h"
|
||||
|
||||
static void rosc_ops(int location, int type, int period);
|
||||
|
||||
static void rosc_ops(int location, int type, int period)
|
||||
{
|
||||
u_int32_t coe = 0;
|
||||
|
||||
#if ROSC_WITH_CLOCK
|
||||
clock_gate(CLK_ROSC, true);
|
||||
#endif
|
||||
coe = ROSC_PRESCALE * (clock_get_frequency(CLK_PCLK)/ROSC_INTERVAL);
|
||||
/* NOP */
|
||||
rROSC_CMD = ROSC_CMD_NOP;
|
||||
while ((rROSC_CMD & ROSC_CMD_STOP) != 0);
|
||||
/* Configure the ring osc */
|
||||
rROSC_CFG = ROSC_CFG_INT_DURATION | (1<<(ROSC_VTH - type + 3)) | (location<<0);
|
||||
if (!period) {
|
||||
u_int32_t res = 0;
|
||||
/* one shot */
|
||||
rROSC_CUR_STAT = 0;
|
||||
rROSC_CMD = ROSC_CMD_RUN_ONCE;
|
||||
spin(1 * 1000);
|
||||
while ((rROSC_CMD & ROSC_CMD_STOP) != 0) {
|
||||
}
|
||||
res = rROSC_CUR_STAT;
|
||||
printf(" current: %dMHz\n", ((res + 2) * coe)/ROSC_1MHZ);
|
||||
} else {
|
||||
u_int32_t res1 = 0;
|
||||
u_int32_t res2 = 0;
|
||||
|
||||
/* Free run */
|
||||
rROSC_MAX_STAT = 0;
|
||||
rROSC_MIN_STAT = 0xFFF;
|
||||
rROSC_CMD = ROSC_CMD_START;
|
||||
spin(period * 1000);
|
||||
rROSC_CMD = ROSC_CMD_STOP;
|
||||
|
||||
while ((rROSC_CMD & ROSC_CMD_STOP) != 0) {
|
||||
}
|
||||
res1 = rROSC_MAX_STAT;
|
||||
res2 = rROSC_MIN_STAT;
|
||||
printf(" maximum: %dMHz, minimum %dMHz\n", ((res1 + 2) * coe)/ROSC_1MHZ, ((res2 + 2) * coe)/ROSC_1MHZ);
|
||||
|
||||
}
|
||||
#if ROSC_WITH_CLOCK
|
||||
clock_gate(CLK_ROSC, false);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
#if defined(WITH_MENU) && WITH_MENU
|
||||
|
||||
static int do_rosc(int argc, struct cmd_arg *args)
|
||||
{
|
||||
int period;
|
||||
|
||||
if (!security_allow_modes(kSecurityModeHWAccess)) {
|
||||
printf("Permission Denied\n");
|
||||
return -1;
|
||||
}
|
||||
if (argc < 2)
|
||||
period = 0;
|
||||
else
|
||||
period = args[1].u;
|
||||
|
||||
if (period) {
|
||||
printf("Ring OSC clock test in free run mode for %d mili seconds\n", period);
|
||||
} else {
|
||||
printf("Ring OSC clock test in one shot mode\n");
|
||||
}
|
||||
|
||||
for (int i = 0; i < ROSC_NUM; i++) {
|
||||
for (int j = 0; j < ROSC_VTH; j++) {
|
||||
if ((1<<(i + j * 5)) & ROSC_MASK) {
|
||||
switch (j) {
|
||||
case 0:
|
||||
printf(" HVT%d", i);
|
||||
break;
|
||||
case 1:
|
||||
printf(" RVT%d", i);
|
||||
break;
|
||||
case 2:
|
||||
printf(" LVT%d", i);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
rosc_ops(i, j, period);
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
MENU_COMMAND_DEBUG(rosc, do_rosc, "Ring OSC reading", NULL);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __APPLE_ROSC_H
|
||||
#define __APPLE_ROSC_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define ROSC_INTERVAL 0x40000
|
||||
#define ROSC_PRESCALE 0x100
|
||||
#define ROSC_VTH (3)
|
||||
#define ROSC_NUM (5)
|
||||
|
||||
#define rROSC_CMD (*(volatile u_int32_t *)(ROSC_BASE_ADDR + 0x000000))
|
||||
#define rROSC_CFG (*(volatile u_int32_t *)(ROSC_BASE_ADDR + 0x000004))
|
||||
#define rROSC_CUR_STAT (*(volatile u_int32_t *)(ROSC_BASE_ADDR + 0x000008))
|
||||
#define rROSC_MAX_STAT (*(volatile u_int32_t *)(ROSC_BASE_ADDR + 0x00000c))
|
||||
#define rROSC_MIN_STAT (*(volatile u_int32_t *)(ROSC_BASE_ADDR + 0x000010))
|
||||
#define rROSC_VER (*(volatile u_int32_t *)(ROSC_BASE_ADDR + 0x0000A0))
|
||||
|
||||
#define ROSC_CMD_NOP (0<<0)
|
||||
#define ROSC_CMD_RUN_ONCE (1<<0)
|
||||
#define ROSC_CMD_START (2<<0)
|
||||
#define ROSC_CMD_STOP (3<<0)
|
||||
|
||||
#define ROSC_CFG_INT_DURATION ((ROSC_INTERVAL-1)<<8)
|
||||
#define ROSC_1MHZ 1000000
|
||||
#endif /* ! __APPLE_ROSC_H */
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_ROSC=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/rosc.o
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_SHA1=1
|
||||
|
||||
MODULES += \
|
||||
drivers/sha1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/sha1.o
|
||||
@@ -0,0 +1,212 @@
|
||||
/*
|
||||
* Copyright (C) 2007-2008 Apple Inc. All rights reserved.
|
||||
* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <debug.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/int.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <sys.h>
|
||||
#include <sys/task.h>
|
||||
|
||||
#include "sha1.h"
|
||||
|
||||
|
||||
static const sha1_regs sha1_reg = {
|
||||
&rSHA1_ADDR_CONF, &rSHA1_ADDR_SWRESET, &rSHA1_ADDR_INT_SRC, &rSHA1_ADDR_INT_MASK,
|
||||
&rSHA1_ADDR_ENDIAN, &rSHA1_ADDR_CODE0, &rSHA1_ADDR_CODE1, &rSHA1_ADDR_CODE2,
|
||||
&rSHA1_ADDR_CODE3, &rSHA1_ADDR_CODE4, &rSHA1_ADDR_DATA0, &rSHA1_ADDR_DATA1,
|
||||
&rSHA1_ADDR_DATA2, &rSHA1_ADDR_DATA3, &rSHA1_ADDR_DATA4, &rSHA1_ADDR_DATA5,
|
||||
&rSHA1_ADDR_DATA6, &rSHA1_ADDR_DATA7, &rSHA1_ADDR_DATA8, &rSHA1_ADDR_DATA9,
|
||||
&rSHA1_ADDR_DATA10, &rSHA1_ADDR_DATA11, &rSHA1_ADDR_DATA12, &rSHA1_ADDR_DATA13,
|
||||
&rSHA1_ADDR_DATA14, &rSHA1_ADDR_DATA15, &rSHA1_MASTER_MODE, &rSHA1_MS_START_ADDR,
|
||||
&rSHA1_MS_SIZE };
|
||||
static sha1_status sha1Status = { 0, 0, 0 };
|
||||
|
||||
static void sha1Run(u_int8_t *buf);
|
||||
static void Sha1NewInit(void);
|
||||
|
||||
void Sha1NewAddEnd(u_int32_t dataLen, u_int32_t offset, u_int32_t startCmd);
|
||||
|
||||
|
||||
static void Sha1NewInit(void)
|
||||
{
|
||||
const sha1_regs *reg;
|
||||
|
||||
reg = &sha1_reg;
|
||||
clock_gate(CLK_SHA1, true);
|
||||
|
||||
/* wait for SHA-1 engine idle */
|
||||
while(*reg->con & (0x1<<0))
|
||||
;
|
||||
/* Software reset */
|
||||
*reg->swreset = 0x1;
|
||||
*reg->swreset = 0x0;
|
||||
|
||||
/* Reset Configuration Register */
|
||||
*reg->con = 0x0;
|
||||
|
||||
/* Always use slave mode */
|
||||
*reg->mode = 0x0;
|
||||
|
||||
/* Always use twist / little endian */
|
||||
*reg->twist = 0x0;
|
||||
|
||||
sha1Status.cmd = 1;
|
||||
sha1Status.offset = 0;
|
||||
sha1Status.length = 0;
|
||||
}
|
||||
|
||||
/* Fill the frame buffer and send it out
|
||||
* the buffer size is always 64 bytes
|
||||
* Caller is responsible to set the End bit and 0 padding
|
||||
*/
|
||||
static void sha1Run(u_int8_t *buf)
|
||||
{
|
||||
const sha1_regs *reg;
|
||||
|
||||
reg = &sha1_reg;
|
||||
|
||||
/* Fill the buffer */
|
||||
for (int i = 0; i < 16; i++) {
|
||||
volatile u_int32_t *data;
|
||||
data = reg->data0;
|
||||
#if WITH_UNALIGNED_MEM
|
||||
*(data + i) = ((u_int32_t *)buf)[i];
|
||||
#else
|
||||
*(data + i) = (buf[i*4] << 0)|(buf[i*4+1] << 8)|(buf[i*4+2] << 16)|(buf[i*4+3] << 24);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Run the SHA1 engine */
|
||||
if (sha1Status.cmd) {
|
||||
/* Start new hash code */
|
||||
*reg->con &= ~(1<<3);
|
||||
sha1Status.cmd = 0;
|
||||
} else {
|
||||
/* Continue hash code */
|
||||
*reg->con |= (1<<3);
|
||||
}
|
||||
|
||||
*reg->con |= 1<<1;
|
||||
while(*reg->con & (1<<0))
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
/************************************************************************
|
||||
* void sha1_hw_calculate(const void *buf, size_t len, u_int32_t *result)
|
||||
* -- We are using slave mode only so the code would be portable
|
||||
* between H1, H2, M1, M2.
|
||||
* -- Caller's responsibility to make sure buffer can hold 20 bytes
|
||||
* SHA1 code.
|
||||
************************************************************************/
|
||||
void sha1_hw_calculate(const void *buf, size_t len, u_int32_t *result)
|
||||
{
|
||||
u_int32_t length, counter;
|
||||
u_int8_t *frame;
|
||||
u_int64_t sha1TotalBits;
|
||||
u_int8_t sha1TotalLenAdd[8];
|
||||
const sha1_regs *reg;
|
||||
|
||||
Sha1NewInit();
|
||||
|
||||
reg = &sha1_reg;
|
||||
frame = (u_int8_t *)buf;
|
||||
length = len;
|
||||
counter =0;
|
||||
|
||||
/* Prepare the 64 bits length */
|
||||
sha1TotalBits = len * 8;
|
||||
sha1TotalLenAdd[0] = ((sha1TotalBits >> 32) & (0xff << 24)) >> 24;
|
||||
sha1TotalLenAdd[1] = ((sha1TotalBits >> 32) & (0xff << 16)) >> 16;
|
||||
sha1TotalLenAdd[2] = ((sha1TotalBits >> 32) & (0xff << 8)) >> 8;
|
||||
sha1TotalLenAdd[3] = ((sha1TotalBits >> 32) & (0xff << 0)) >> 0;
|
||||
sha1TotalLenAdd[4] = (sha1TotalBits & (0xff << 24)) >> 24;
|
||||
sha1TotalLenAdd[5] = (sha1TotalBits & (0xff << 16)) >> 16;
|
||||
sha1TotalLenAdd[6] = (sha1TotalBits & (0xff << 8)) >> 8;
|
||||
sha1TotalLenAdd[7] = (sha1TotalBits & (0xff << 0)) >> 0;
|
||||
|
||||
while (length > 64) {
|
||||
sha1Run(&frame[sha1Status.length]);
|
||||
sha1Status.length += 64;
|
||||
length -= 64;
|
||||
counter += 64;
|
||||
if (0x7FFFF < counter) {
|
||||
task_yield();
|
||||
counter = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (length > 55) {
|
||||
/* Not enough space for the length bytes */
|
||||
u_int8_t frameBuf[64];
|
||||
|
||||
for (u_int32_t i = 0; i < 64; i++) {
|
||||
if (length > i) {
|
||||
frameBuf[i] = frame[sha1Status.length++];
|
||||
} else if (length == i) {
|
||||
frameBuf[i] = 0x80;
|
||||
} else {
|
||||
frameBuf[i] = 0x0;
|
||||
}
|
||||
}
|
||||
sha1Run(frameBuf);
|
||||
|
||||
/* Add End bit 0x80 if not added above */
|
||||
if (length == 64) {
|
||||
frameBuf[0] = 0x80;
|
||||
} else {
|
||||
frameBuf[0] = 0x0;
|
||||
}
|
||||
|
||||
/* Start a new frame to hold the length */
|
||||
for (int j = 1; j < 56; j++) {
|
||||
frameBuf[j] = 0x0;
|
||||
}
|
||||
|
||||
/* Now store the length */
|
||||
for (int k = 0; k < 8; k++) {
|
||||
frameBuf[56 + k] = sha1TotalLenAdd[k];
|
||||
}
|
||||
sha1Run(frameBuf);
|
||||
} else {
|
||||
/* Add End bit 0x80 and 0 padding */
|
||||
u_int8_t frameBuf[64];
|
||||
|
||||
for (u_int32_t i = 0; i < 56; i++) {
|
||||
if (length > i) {
|
||||
frameBuf[i] = frame[sha1Status.length++];
|
||||
} else if (length == i) {
|
||||
frameBuf[i] = 0x80;
|
||||
} else {
|
||||
frameBuf[i] = 0x0;
|
||||
}
|
||||
}
|
||||
|
||||
/* Now store the length */
|
||||
for (int j = 0; j < 8; j++) {
|
||||
frameBuf[56 + j] = sha1TotalLenAdd[j];
|
||||
}
|
||||
sha1Run(frameBuf);
|
||||
|
||||
}
|
||||
|
||||
/* Get the result */
|
||||
result[0] = *reg->code0;
|
||||
result[1] = *reg->code1;
|
||||
result[2] = *reg->code2;
|
||||
result[3] = *reg->code3;
|
||||
result[4] = *reg->code4;
|
||||
|
||||
clock_gate(CLK_SHA1, false);
|
||||
}
|
||||
@@ -0,0 +1,98 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Computer, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_SHA1_H
|
||||
#define __SAMSUNG_SHA1_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rSHA1_ADDR_CONF (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x00))
|
||||
#define rSHA1_ADDR_SWRESET (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x04))
|
||||
#define rSHA1_ADDR_INT_SRC (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x08))
|
||||
#define rSHA1_ADDR_INT_MASK (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x0C))
|
||||
#define rSHA1_ADDR_ENDIAN (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x10))
|
||||
|
||||
#define rSHA1_ADDR_CODE0 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x20))
|
||||
#define rSHA1_ADDR_CODE1 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x24))
|
||||
#define rSHA1_ADDR_CODE2 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x28))
|
||||
#define rSHA1_ADDR_CODE3 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x2C))
|
||||
#define rSHA1_ADDR_CODE4 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x30))
|
||||
|
||||
#define rSHA1_ADDR_DATA0 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x40))
|
||||
#define rSHA1_ADDR_DATA1 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x44))
|
||||
#define rSHA1_ADDR_DATA2 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x48))
|
||||
#define rSHA1_ADDR_DATA3 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x4C))
|
||||
#define rSHA1_ADDR_DATA4 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x50))
|
||||
#define rSHA1_ADDR_DATA5 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x54))
|
||||
#define rSHA1_ADDR_DATA6 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x58))
|
||||
#define rSHA1_ADDR_DATA7 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x5C))
|
||||
#define rSHA1_ADDR_DATA8 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x60))
|
||||
#define rSHA1_ADDR_DATA9 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x64))
|
||||
#define rSHA1_ADDR_DATA10 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x68))
|
||||
#define rSHA1_ADDR_DATA11 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x6C))
|
||||
#define rSHA1_ADDR_DATA12 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x70))
|
||||
#define rSHA1_ADDR_DATA13 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x74))
|
||||
#define rSHA1_ADDR_DATA14 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x78))
|
||||
#define rSHA1_ADDR_DATA15 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x7C))
|
||||
|
||||
#define rSHA1_MASTER_MODE (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x80))
|
||||
#define rSHA1_MS_START_ADDR (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x84))
|
||||
#define rSHA1_VERISON (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x88))
|
||||
#define rSHA1_MS_SIZE (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x8C))
|
||||
#define rSHA1_FIFO_PARAM (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x90))
|
||||
#define rSHA1_FIFO_CMD (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x94))
|
||||
#define rSHA1_TX_FIFO_STAT (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x98))
|
||||
#define rSHA1_TX_FIFO (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0xA0))
|
||||
|
||||
struct sha1_regs {
|
||||
volatile u_int32_t *con;
|
||||
volatile u_int32_t *swreset;
|
||||
volatile u_int32_t *int_src;
|
||||
volatile u_int32_t *int_mask;
|
||||
volatile u_int32_t *twist;
|
||||
|
||||
volatile u_int32_t *code0;
|
||||
volatile u_int32_t *code1;
|
||||
volatile u_int32_t *code2;
|
||||
volatile u_int32_t *code3;
|
||||
volatile u_int32_t *code4;
|
||||
|
||||
volatile u_int32_t *data0;
|
||||
volatile u_int32_t *data1;
|
||||
volatile u_int32_t *data2;
|
||||
volatile u_int32_t *data3;
|
||||
volatile u_int32_t *data4;
|
||||
volatile u_int32_t *data5;
|
||||
volatile u_int32_t *data6;
|
||||
volatile u_int32_t *data7;
|
||||
volatile u_int32_t *data8;
|
||||
volatile u_int32_t *data9;
|
||||
volatile u_int32_t *data10;
|
||||
volatile u_int32_t *data11;
|
||||
volatile u_int32_t *data12;
|
||||
volatile u_int32_t *data13;
|
||||
volatile u_int32_t *data14;
|
||||
volatile u_int32_t *data15;
|
||||
|
||||
volatile u_int32_t *mode;
|
||||
volatile u_int32_t *start_addr;
|
||||
volatile u_int32_t *ms_size;
|
||||
};
|
||||
typedef struct sha1_regs sha1_regs;
|
||||
|
||||
struct sha1_status {
|
||||
u_int32_t offset;
|
||||
u_int32_t cmd;
|
||||
u_int32_t length;
|
||||
};
|
||||
typedef struct sha1_status sha1_status;
|
||||
|
||||
#endif /* __SAMSUNG_SHA1_H */
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_SPI=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/spi.o
|
||||
@@ -0,0 +1,721 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <debug.h>
|
||||
#include <lib/libc.h>
|
||||
#include <platform.h>
|
||||
#include <platform/int.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/soc/hwisr.h>
|
||||
#include <sys.h>
|
||||
#include <sys/task.h>
|
||||
|
||||
#include "spi.h"
|
||||
|
||||
#ifndef SPIS_MASK
|
||||
#define SPIS_MASK ((1 << SPIS_COUNT) - 1)
|
||||
#endif
|
||||
|
||||
#define SPI_DMA 0
|
||||
|
||||
#define SPI_AGD_MODE 1
|
||||
|
||||
//#define DEBUG_SPI_SPEW DEBUG_SPEW
|
||||
#ifndef DEBUG_SPI_SPEW
|
||||
#define DEBUG_SPI_SPEW (0x7FFFFFFF)
|
||||
#endif
|
||||
|
||||
/* previously from libc.h, but it pollutes the namespace there */
|
||||
#define BITS_SHIFT(x, high, low) (((x) >> (low)) & ((1<<((high)-(low)+1))-1))
|
||||
|
||||
/* spi driver, copy and customize */
|
||||
|
||||
enum spi_clk {
|
||||
PCLK,
|
||||
NCLK
|
||||
};
|
||||
|
||||
static struct spi_status_t {
|
||||
int bits; // 8, 16, 32
|
||||
int clkpol; // clock polarity
|
||||
int clkpha; // clock phase
|
||||
enum spi_clk clk; // PCLK or NCLK
|
||||
int baud;
|
||||
bool master;
|
||||
bool dma;
|
||||
|
||||
/* interrupt driven stuff */
|
||||
const void *tx_buf;
|
||||
size_t tx_pos;
|
||||
size_t tx_len;
|
||||
void *rx_buf;
|
||||
size_t rx_pos;
|
||||
size_t rx_len;
|
||||
int overrun_errors;
|
||||
|
||||
struct task_event event;
|
||||
|
||||
uint32_t shadow_spcon;
|
||||
|
||||
#if SPI_DMA
|
||||
/* dma stuff */
|
||||
dma_t tx_dma;
|
||||
struct iovec tx_iov;
|
||||
struct dma_xfer_t tx_xfer;
|
||||
|
||||
dma_t rx_dma;
|
||||
struct iovec rx_iov;
|
||||
struct dma_xfer_t rx_xfer;
|
||||
#endif
|
||||
|
||||
/* completion flags */
|
||||
volatile int tx_complete;
|
||||
volatile int rx_complete;
|
||||
} spi_status[SPIS_COUNT];
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t *spclkcon;
|
||||
volatile uint32_t *spcon;
|
||||
volatile uint32_t *spsta;
|
||||
volatile uint32_t *sppin;
|
||||
volatile uint32_t *sptdat;
|
||||
volatile uint32_t *sprdat;
|
||||
volatile uint32_t *sppre;
|
||||
volatile uint32_t *spcnt;
|
||||
volatile uint32_t *spidd;
|
||||
volatile uint32_t *spirto;
|
||||
volatile uint32_t *spihangd;
|
||||
volatile uint32_t *spiswrst;
|
||||
volatile uint32_t *spiver;
|
||||
volatile uint32_t *sptdcnt;
|
||||
uint32_t clock;
|
||||
uint32_t irq;
|
||||
} spi_regs_t;
|
||||
|
||||
static const spi_regs_t spi_regs[] = {
|
||||
#if SPIS_COUNT > 0
|
||||
{ &rSPCLKCON0, &rSPCON0, &rSPSTA0, &rSPPIN0, &rSPTDAT0, &rSPRDAT0, &rSPPRE0, &rSPCNT0,
|
||||
&rSPIDD0, &rSPIRTO0, &rSPIHANGD0, &rSPISWRST0, &rSPIVER0, &rSPTDCNT0, CLK_SPI0, INT_SPI0 },
|
||||
#endif
|
||||
#if SPIS_COUNT > 1
|
||||
{ &rSPCLKCON1, &rSPCON1, &rSPSTA1, &rSPPIN1, &rSPTDAT1, &rSPRDAT1, &rSPPRE1, &rSPCNT1,
|
||||
&rSPIDD1, &rSPIRTO1, &rSPIHANGD1, &rSPISWRST1, &rSPIVER1, &rSPTDCNT1, CLK_SPI1, INT_SPI1 },
|
||||
#endif
|
||||
#if SPIS_COUNT > 2
|
||||
{ &rSPCLKCON2, &rSPCON2, &rSPSTA2, &rSPPIN2, &rSPTDAT2, &rSPRDAT2, &rSPPRE2, &rSPCNT2,
|
||||
&rSPIDD2, &rSPIRTO2, &rSPIHANGD2, &rSPISWRST2, &rSPIVER2, &rSPTDCNT2, CLK_SPI2, INT_SPI2 },
|
||||
#endif
|
||||
#if SPIS_COUNT > 3
|
||||
{ &rSPCLKCON3, &rSPCON3, &rSPSTA3, &rSPPIN3, &rSPTDAT3, &rSPRDAT3, &rSPPRE3, &rSPCNT3,
|
||||
&rSPIDD3, &rSPIRTO3, &rSPIHANGD3, &rSPISWRST3, &rSPIVER3, &rSPTDCNT3, CLK_SPI3, INT_SPI3 },
|
||||
#endif
|
||||
#if SPIS_COUNT > 4
|
||||
{ &rSPCLKCON4, &rSPCON4, &rSPSTA4, &rSPPIN4, &rSPTDAT4, &rSPRDAT4, &rSPPRE4, &rSPCNT4,
|
||||
&rSPIDD4, &rSPIRTO4, &rSPIHANGD4, &rSPISWRST4, &rSPIVER4, &rSPTDCNT4, CLK_SPI4, INT_SPI4 },
|
||||
#endif
|
||||
};
|
||||
|
||||
static const spi_regs_t *spiregs(int port)
|
||||
{
|
||||
if (port < 0 || port >= SPIS_COUNT || !(SPIS_MASK & (1 << port)))
|
||||
panic("Trying to access a nonexisted spi port\n");
|
||||
|
||||
return &spi_regs[port];
|
||||
}
|
||||
|
||||
static void spi_set_port_enable(int port, bool enable)
|
||||
{
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
|
||||
if (enable)
|
||||
*regs->spclkcon = 1;
|
||||
else
|
||||
*regs->spclkcon = 0;
|
||||
}
|
||||
|
||||
#if SPI_DMA
|
||||
static void spi_set_port_dma(int port, bool dma)
|
||||
{
|
||||
if (dma == spi_status[port].dma)
|
||||
return;
|
||||
|
||||
if (spi_status[port].dma) {
|
||||
release_dma_channel(spi_status[port].tx_dma);
|
||||
release_dma_channel(spi_status[port].rx_dma);
|
||||
spi_status[port].tx_dma = spi_status[port].rx_dma = -1;
|
||||
}
|
||||
|
||||
if (dma) {
|
||||
spi_status[port].tx_dma = acquire_dma_channel(DMA_DEVICE_MEMORY, DMA_DEVICE_SPI_0 + port, 1, 1);
|
||||
spi_status[port].rx_dma = acquire_dma_channel(DMA_DEVICE_SPI_0 + port, DMA_DEVICE_MEMORY, 1, 1);
|
||||
dprintf(DEBUG_INFO, "spi_set_port_dma: allocated channels, tx %d rx %d\n", spi_status[port].tx_dma, spi_status[port].rx_dma);
|
||||
}
|
||||
|
||||
spi_status[port].dma = dma;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void spi_set_baud(int port, int baud)
|
||||
{
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
uint32_t clkrate;
|
||||
int div;
|
||||
int actual_baud;
|
||||
|
||||
if (spi_status[port].clk == PCLK)
|
||||
clkrate = clock_get_frequency(CLK_PCLK);
|
||||
else
|
||||
clkrate = clock_get_frequency(CLK_NCLK);
|
||||
|
||||
div = clkrate / baud;
|
||||
#if SPI_VERSION > 0
|
||||
if (div < 1) div = 1;
|
||||
#else
|
||||
if (div < 2) div = 2;
|
||||
#endif
|
||||
actual_baud = clkrate / div;
|
||||
|
||||
dprintf(DEBUG_SPI_SPEW, "spi_set_baud: port %d clk %s (%d Hz) baud %d, divider %d, actual baud %d\n",
|
||||
port, (spi_status[port].clk == PCLK) ? "PCLK" : "NCLK", clkrate, baud, div, actual_baud);
|
||||
|
||||
if (div >= (1<<10))
|
||||
dprintf(DEBUG_CRITICAL, "spi_set_baud: warning, div 0x%x is too big to fit in register\n", div);
|
||||
|
||||
*regs->sppre = div;
|
||||
spi_status[port].baud = baud;
|
||||
}
|
||||
|
||||
//small routine to get the baudrate for a divider
|
||||
//helper function to be able todo automated testing
|
||||
static int spi_baud_from_div(int port, int div)
|
||||
{
|
||||
int clkrate;
|
||||
|
||||
if (spi_status[port].clk == PCLK)
|
||||
clkrate = clock_get_frequency(CLK_PCLK);
|
||||
else
|
||||
clkrate = clock_get_frequency(CLK_NCLK);
|
||||
|
||||
if (div < 2) div = 2;
|
||||
return (clkrate / div);
|
||||
}
|
||||
|
||||
void spi_set_interdatadelay(int port,int usecs)
|
||||
{
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
uint32_t clocks;
|
||||
|
||||
clocks = ((1ULL * clock_get_frequency(CLK_PCLK) * usecs) + 1000000 - 1) / 1000000;
|
||||
|
||||
*regs->spidd = clocks;
|
||||
dprintf(DEBUG_SPI_SPEW, "spidd: %d\n",*regs->spidd);
|
||||
}
|
||||
|
||||
void spi_set_clk(int port, enum spi_clk clk)
|
||||
{
|
||||
spi_status[port].clk = clk;
|
||||
}
|
||||
|
||||
void spi_setup(int port, int baud, int width, bool master, int clkpol, int clkpha)
|
||||
{
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
|
||||
if (regs == 0)
|
||||
return;
|
||||
|
||||
spi_set_port_enable(port, false);
|
||||
|
||||
switch (width) {
|
||||
default:
|
||||
case 8:
|
||||
spi_status[port].bits = 0;
|
||||
break;
|
||||
case 16:
|
||||
spi_status[port].bits = 1;
|
||||
break;
|
||||
case 32:
|
||||
spi_status[port].bits = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
spi_status[port].clkpol = clkpol ? 1 : 0;
|
||||
spi_status[port].clkpha = clkpha ? 1 : 0;
|
||||
spi_set_baud(port, baud);
|
||||
spi_status[port].master = master;
|
||||
|
||||
/* set up the control register */
|
||||
spi_status[port].shadow_spcon =
|
||||
(spi_status[port].clkpha << SPICON_CPHA_SHIFT) |
|
||||
(spi_status[port].clkpol << SPICON_CPOL_SHIFT) |
|
||||
((spi_status[port].master ? 3 : 0) << SPICON_MASTER_SHIFT) | // if in master mode, enable clock
|
||||
((spi_status[port].dma ? 2 : 1) << SPICON_MODE_SHIFT) |
|
||||
(0 << SPICON_MSBFT_SHIFT) | // MSB first
|
||||
(((spi_status[port].clk == PCLK) ? 0 : 1) << SPICON_CLK_SEL_SHIFT) |
|
||||
(spi_status[port].bits << SPICON_BIT_LEN_SHIFT) | // 8/16/32 bit width
|
||||
(0 << SPICON_DMA_SIZE_SHIFT); // 4 byte IRQ/DMA
|
||||
*regs->spcon = spi_status[port].shadow_spcon;
|
||||
|
||||
*regs->sppin = (1 << 1);
|
||||
|
||||
spi_set_port_enable(port, true); // the port has to be enabled before you write to the FIFO.
|
||||
|
||||
dprintf(DEBUG_SPI_SPEW, "spcon 0x%x\n", *regs->spcon);
|
||||
}
|
||||
|
||||
static void spi_flush_tx_fifo(int port)
|
||||
{
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
|
||||
*regs->spclkcon |= (1<<2);
|
||||
}
|
||||
|
||||
static void spi_flush_rx_fifo(int port)
|
||||
{
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
|
||||
*regs->spclkcon |= (1<<3);
|
||||
}
|
||||
|
||||
static void spi_interrupt(void *arg)
|
||||
{
|
||||
int port = (int)arg;
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
uint32_t status;
|
||||
uint32_t i;
|
||||
|
||||
status = *regs->spsta;
|
||||
*regs->spsta = status;
|
||||
|
||||
dprintf(DEBUG_SPI_SPEW, "spi_interrupt(): %d, status 0x%08x / 0x%08x\n", port, status, *regs->spcon);
|
||||
|
||||
if (status & (1 << 3)) { // data collision error
|
||||
dprintf(DEBUG_SPI_SPEW, "spi_int, port %d: data collision (lost rx bytes)\n", port);
|
||||
spi_status[port].overrun_errors++;
|
||||
}
|
||||
if (status & (1 << 0)) { // rx done
|
||||
dprintf(DEBUG_SPI_SPEW, "spi_int, port %d: rx done, status 0x%x, tx pos %zu, rx pos %zu\n",
|
||||
port, status, spi_status[port].tx_pos, spi_status[port].rx_pos);
|
||||
dprintf(DEBUG_SPI_SPEW, "\ttx fifo %d rx fifo %d\n",
|
||||
BITS_SHIFT(status, SPSTA_TX_FIFO_BIT_HI, SPSTA_TX_FIFO_BIT_LO),
|
||||
BITS_SHIFT(status, SPSTA_RX_FIFO_BIT_HI, SPSTA_RX_FIFO_BIT_LO));
|
||||
if (!(status & ((1 << 22) | (1 << 1))))
|
||||
goto handle_rx;
|
||||
}
|
||||
if (status & ((1 << 22) | (1 << 1))) { // transfer done or ready
|
||||
/* deal with tx */
|
||||
handle_tx:
|
||||
if (spi_status[port].tx_buf) {
|
||||
if (spi_status[port].tx_pos >= spi_status[port].tx_len) {
|
||||
/* we're done */
|
||||
spi_status[port].tx_complete = 1;
|
||||
spi_status[port].tx_buf = 0;
|
||||
#if SPI_VERSION > 0
|
||||
spi_status[port].shadow_spcon &= ~(1 << SPICON_IE_TX_SHIFT);
|
||||
*regs->spcon = spi_status[port].shadow_spcon;
|
||||
#endif
|
||||
dprintf(DEBUG_SPI_SPEW, "spi_tx %d: tx done, pos %zu len %zu\n", port, spi_status[port].tx_pos, spi_status[port].tx_len);
|
||||
} else {
|
||||
uint32_t txfifo_left = SPI_FIFO_SIZE - BITS_SHIFT(status, SPSTA_TX_FIFO_BIT_HI, SPSTA_TX_FIFO_BIT_LO);
|
||||
uint32_t to_transfer = spi_status[port].tx_len - spi_status[port].tx_pos;
|
||||
|
||||
to_transfer = __min(txfifo_left, to_transfer);
|
||||
|
||||
dprintf(DEBUG_SPI_SPEW, "spi_tx %d: txfifo_left %d, to_transfer %d, pos %zu, len %zu\n",
|
||||
port, txfifo_left, to_transfer, spi_status[port].tx_pos, spi_status[port].tx_len);
|
||||
|
||||
for (i=0; i < to_transfer; i++)
|
||||
*regs->sptdat = ((uint8_t *)spi_status[port].tx_buf)[spi_status[port].tx_pos + i];
|
||||
|
||||
spi_status[port].tx_pos += to_transfer;
|
||||
}
|
||||
}
|
||||
|
||||
/* look for rx */
|
||||
handle_rx:
|
||||
if (spi_status[port].rx_buf) {
|
||||
uint32_t tmp;
|
||||
uint32_t rxfifo = BITS_SHIFT(status, SPSTA_RX_FIFO_BIT_HI, SPSTA_RX_FIFO_BIT_LO);
|
||||
uint32_t to_transfer = spi_status[port].rx_len - spi_status[port].rx_pos;
|
||||
|
||||
to_transfer = __min(rxfifo, to_transfer);
|
||||
|
||||
dprintf(DEBUG_SPI_SPEW, "spi_rx %d: fifo %d, to_transfer %d, pos %zu, len %zu\n",
|
||||
port, rxfifo, to_transfer, spi_status[port].rx_pos, spi_status[port].rx_len);
|
||||
|
||||
for (i=0; i < to_transfer; i++) {
|
||||
tmp = *regs->sprdat;
|
||||
// dprintf(DEBUG_SPI_SPEW, "sprdat: 0x%x\n",tmp);
|
||||
((uint8_t *)spi_status[port].rx_buf)[spi_status[port].rx_pos + i] = tmp; //*regs->sprdat;
|
||||
}
|
||||
|
||||
spi_status[port].rx_pos += to_transfer;
|
||||
|
||||
if (spi_status[port].rx_pos >= spi_status[port].rx_len) {
|
||||
spi_status[port].rx_complete = 1;
|
||||
spi_status[port].rx_buf = 0;
|
||||
spi_status[port].shadow_spcon &= ~(1 << SPICON_IE_RX_SHIFT);
|
||||
*regs->spcon = spi_status[port].shadow_spcon;
|
||||
//Hm, so RX finished, is it possible that TX is finished aswell?
|
||||
goto handle_tx;
|
||||
}
|
||||
|
||||
#if !SPI_AGD_MODE
|
||||
if (spi_status[port].tx_buf == 0) {
|
||||
uint32_t txfifo_left = SPI_FIFO_SIZE - BITS_SHIFT(status, SPSTA_TX_FIFO_BIT_HI, SPSTA_TX_FIFO_BIT_LO);
|
||||
uint32_t cnt = spi_status[port].rx_len - spi_status[port].rx_pos;
|
||||
if (cnt > txfifo_left) cnt = txfifo_left;
|
||||
while (cnt--) *regs->sptdat = 0xff;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
if ((spi_status[port].tx_buf == 0) && (spi_status[port].rx_buf == 0)) {
|
||||
spi_status[port].shadow_spcon &= ~(1 << SPICON_IE_TR_SHIFT);
|
||||
*regs->spcon = spi_status[port].shadow_spcon;
|
||||
event_signal(&spi_status[port].event);
|
||||
}
|
||||
}
|
||||
|
||||
#if SPI_DMA
|
||||
static void spi_dma_tx_handler(struct dma_xfer_t *xfer, int error)
|
||||
{
|
||||
struct spi_status_t *spi = xfer->user;
|
||||
|
||||
dprintf(DEBUG_SPI_SPEW, "spi_dma_tx_handler(): %d\n", error);
|
||||
|
||||
spi->tx_complete = 1;
|
||||
}
|
||||
|
||||
static void spi_dma_rx_handler(struct dma_xfer_t *xfer, int error)
|
||||
{
|
||||
struct spi_status_t *spi = xfer->user;
|
||||
|
||||
dprintf(DEBUG_SPI_SPEW, "spi_dma_rx_handler(): %d\n", error);
|
||||
|
||||
spi->rx_complete = 1;
|
||||
}
|
||||
|
||||
static void spi_cancel_dma(int port)
|
||||
{
|
||||
if(spi_status[port].dma) {
|
||||
cancel_dma_transfers(spi_status[port].rx_dma);
|
||||
cancel_dma_transfers(spi_status[port].tx_dma);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bool spi_tx_complete(int port)
|
||||
{
|
||||
return spi_status[port].tx_complete;
|
||||
}
|
||||
|
||||
bool spi_rx_complete(int port)
|
||||
{
|
||||
return spi_status[port].rx_complete;
|
||||
}
|
||||
|
||||
int spi_write_etc(int port, const void *buf, size_t len, bool wait, bool with_rx)
|
||||
{
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
uint32_t i;
|
||||
int err = 0;
|
||||
|
||||
dprintf(DEBUG_SPI_SPEW, "spi_write(): port %d (%p) buf %p len %zu\n", port, &spi_status[port], buf, len);
|
||||
|
||||
if (regs == 0)
|
||||
return -1;
|
||||
|
||||
/* clear the tx & rx fifos */
|
||||
spi_flush_tx_fifo(port);
|
||||
spi_flush_rx_fifo(port);
|
||||
|
||||
#if SPI_DMA
|
||||
if (spi_status[port].dma) {
|
||||
spi_status[port].tx_iov.iov_base = (void *)buf;
|
||||
spi_status[port].tx_iov.iov_len = len;
|
||||
spi_status[port].tx_xfer.dev_addr = (void *)regs->sptdat;
|
||||
spi_status[port].tx_xfer.handler = spi_dma_tx_handler;
|
||||
spi_status[port].tx_xfer.iov = &spi_status[port].tx_iov;
|
||||
spi_status[port].tx_xfer.niov = 1;
|
||||
spi_status[port].tx_xfer.user = &spi_status[port];
|
||||
spi_status[port].tx_xfer.platform_flags = H1_DMA_FLAG__8BIT_TRANSFER | H1_DMA_FLAG__4_BURST_PERIPHERAL;
|
||||
spi_status[port].tx_complete = 0;
|
||||
|
||||
if (!with_rx)
|
||||
*regs->spcnt = 0;
|
||||
|
||||
spi_set_port_enable(port, true);
|
||||
|
||||
platform_cache_operation(CACHE_CLEAN | CACHE_INVALIDATE, 0, 0);
|
||||
err = queue_dma_transfer(spi_status[port].tx_dma, &spi_status[port].tx_xfer);
|
||||
if (err < 0) {
|
||||
dprintf(DEBUG_CRITICAL, "error 0x%x queuing tx dma\n", err);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (wait) {
|
||||
while (!spi_status[port].tx_complete || BITS_SHIFT(regs->spsta, SPSTA_TX_FIFO_BIT_HI, SPSTA_TX_FIFO_BIT_LO)) {
|
||||
task_yield();
|
||||
// dprintf(DEBUG_SPI_SPEW, "spsta 0x%x\n", *regs->spsta);
|
||||
}
|
||||
err = len;
|
||||
}
|
||||
} else {
|
||||
#endif
|
||||
spi_status[port].tx_buf = buf;
|
||||
spi_status[port].tx_pos = __min(len, 8u);
|
||||
spi_status[port].tx_len = len;
|
||||
spi_status[port].tx_complete = 0;
|
||||
spi_status[port].rx_buf = 0;
|
||||
spi_status[port].rx_pos = 0;
|
||||
spi_status[port].rx_len = 0;
|
||||
|
||||
event_unsignal(&spi_status[port].event);
|
||||
|
||||
if (with_rx) {
|
||||
spi_status[port].shadow_spcon |= (1 << SPICON_IE_RX_SHIFT);
|
||||
} else {
|
||||
*regs->spcnt = 0;
|
||||
}
|
||||
|
||||
for (i=0; i < spi_status[port].tx_pos; i++)
|
||||
*regs->sptdat = ((uint8_t *)buf)[i];
|
||||
|
||||
#if SPI_VERSION > 0
|
||||
*regs->sptdcnt = len;
|
||||
spi_status[port].shadow_spcon |= (1 << SPICON_IE_TX_SHIFT);
|
||||
#endif
|
||||
|
||||
spi_status[port].shadow_spcon |= (1 << SPICON_IE_TR_SHIFT);
|
||||
*regs->spcon = spi_status[port].shadow_spcon;
|
||||
|
||||
spi_set_port_enable(port, true);
|
||||
|
||||
if (wait) {
|
||||
while (!spi_status[port].tx_complete) {
|
||||
event_wait(&spi_status[port].event);
|
||||
}
|
||||
|
||||
while (BITS_SHIFT(*regs->spsta, SPSTA_TX_FIFO_BIT_HI, SPSTA_TX_FIFO_BIT_LO));
|
||||
|
||||
err = len;
|
||||
}
|
||||
#if SPI_DMA
|
||||
}
|
||||
#endif
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
int spi_write(int port, const void *buf, size_t len)
|
||||
{
|
||||
return spi_write_etc(port, buf, len, true, false);
|
||||
}
|
||||
|
||||
int spi_read_etc(int port, void *buf, size_t len, bool wait, bool with_tx)
|
||||
{
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
bool enable_tx_int = false;
|
||||
int err = 0;
|
||||
|
||||
dprintf(DEBUG_SPI_SPEW, "spi_read(): port %d (%p) buf %p len %zu\n", port, &spi_status[port], buf, len);
|
||||
|
||||
if (regs == 0)
|
||||
return -1;
|
||||
|
||||
/* clear the tx & rx fifos */
|
||||
spi_flush_tx_fifo(port);
|
||||
spi_flush_rx_fifo(port);
|
||||
|
||||
#if SPI_DMA
|
||||
if (spi_status[port].dma) {
|
||||
spi_status[port].rx_iov.iov_base = (void *)buf;
|
||||
spi_status[port].rx_iov.iov_len = len;
|
||||
spi_status[port].rx_xfer.dev_addr = (void *)regs->sprdat;
|
||||
spi_status[port].rx_xfer.handler = spi_dma_rx_handler;
|
||||
spi_status[port].rx_xfer.iov = &spi_status[port].rx_iov;
|
||||
spi_status[port].rx_xfer.niov = 1;
|
||||
spi_status[port].rx_xfer.user = &spi_status[port];
|
||||
spi_status[port].rx_xfer.platform_flags = H1_DMA_FLAG__8BIT_TRANSFER | H1_DMA_FLAG__4_BURST_PERIPHERAL;
|
||||
spi_status[port].rx_complete = 0;
|
||||
|
||||
*regs->spcnt = len;
|
||||
|
||||
spi_set_port_enable(port, true);
|
||||
|
||||
if (!with_tx) {
|
||||
spi_set_port_enable(port, true);
|
||||
/* start the transmitter, which should start the receive */
|
||||
spi_status[port].shadow_spcon |= (1 << SPICON_AGD_SHIFT); // set auto garbage bit
|
||||
}
|
||||
|
||||
platform_cache_operation(CACHE_CLEAN | CACHE_INVALIDATE, 0, 0);
|
||||
err = queue_dma_transfer(spi_status[port].rx_dma, &spi_status[port].rx_xfer);
|
||||
if (err < 0) {
|
||||
dprintf(DEBUG_CRITICAL, "error 0x%x queuing rx dma\n", err);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (wait) {
|
||||
while (!spi_status[port].rx_complete) {
|
||||
task_yield();
|
||||
// dprintf(DEBUG_SPI_SPEW, "spsta 0x%x\n", *regs->spsta);
|
||||
}
|
||||
if (!with_tx) {
|
||||
spi_status[port].shadow_spcon &= ~(1 << SPICON_AGD_SHIFT); // clear auto garbage bit
|
||||
*regs->spcon = spi_status[port].shadow_spcon;
|
||||
}
|
||||
err = len;
|
||||
}
|
||||
} else {
|
||||
#endif
|
||||
spi_status[port].rx_buf = buf;
|
||||
spi_status[port].rx_pos = 0;
|
||||
spi_status[port].rx_len = len;
|
||||
spi_status[port].rx_complete = 0;
|
||||
spi_status[port].overrun_errors = 0;
|
||||
spi_status[port].tx_buf = 0;
|
||||
spi_status[port].tx_pos = 0;
|
||||
spi_status[port].tx_len = 0;
|
||||
|
||||
event_unsignal(&spi_status[port].event);
|
||||
|
||||
*regs->spcnt = len;
|
||||
|
||||
spi_set_port_enable(port, true);
|
||||
|
||||
if (with_tx) {
|
||||
enable_tx_int = true;
|
||||
} else {
|
||||
/* start the transmitter, which should start the receive */
|
||||
#if SPI_AGD_MODE
|
||||
spi_status[port].shadow_spcon |= (1 << SPICON_AGD_SHIFT); // set auto garbage bit
|
||||
#else
|
||||
int cnt = spi_status[port].rx_len - spi_status[port].rx_pos;
|
||||
if (cnt > SPI_FIFO_SIZE) cnt = SPI_FIFO_SIZE;
|
||||
while (cnt--) *regs->sptdat = 0xff;
|
||||
enable_tx_int = true;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if SPI_VERSION > 0
|
||||
if (enable_tx_int) {
|
||||
*regs->sptdcnt = len;
|
||||
spi_status[port].shadow_spcon |= (1 << SPICON_IE_TX_SHIFT);
|
||||
}
|
||||
#endif
|
||||
|
||||
spi_status[port].shadow_spcon |= (1 << SPICON_IE_RX_SHIFT) | (1 << SPICON_IE_TR_SHIFT);
|
||||
*regs->spcon = spi_status[port].shadow_spcon;
|
||||
|
||||
if (wait) {
|
||||
while (!spi_status[port].rx_complete) {
|
||||
event_wait(&spi_status[port].event);
|
||||
}
|
||||
if (!with_tx) {
|
||||
spi_status[port].shadow_spcon &= ~(1 << SPICON_AGD_SHIFT); // clear auto garbage bit
|
||||
*regs->spcon = spi_status[port].shadow_spcon;
|
||||
}
|
||||
|
||||
err = len;
|
||||
}
|
||||
#if SPI_DMA
|
||||
}
|
||||
#endif
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
int spi_read(int port, void *buf, size_t len)
|
||||
{
|
||||
return spi_read_etc(port, buf, len, true, false);
|
||||
}
|
||||
|
||||
void spi_init(void)
|
||||
{
|
||||
uint32_t port;
|
||||
const spi_regs_t *regs;
|
||||
|
||||
dprintf(DEBUG_CRITICAL, "spi_init()\n");
|
||||
|
||||
/* clear out the spi structure */
|
||||
bzero(spi_status, sizeof(spi_status));
|
||||
|
||||
for (port = 0; port < SPIS_COUNT; port++) {
|
||||
regs = spiregs(port);
|
||||
if (!regs)
|
||||
continue;
|
||||
|
||||
event_init(&spi_status[port].event, EVENT_FLAG_AUTO_UNSIGNAL, false);
|
||||
|
||||
/* make sure the clock is on for this device */
|
||||
clock_gate(regs->clock, true);
|
||||
|
||||
/* default clock source to NCLK */
|
||||
spi_status[port].clk = NCLK;
|
||||
|
||||
/* turn off all the spi ports */
|
||||
spi_set_port_enable(port, false);
|
||||
|
||||
#if SPI_DMA
|
||||
/* start off in interrupt driven mode */
|
||||
spi_status[port].tx_dma = spi_status[port].rx_dma = -1;
|
||||
spi_set_port_dma(port, false);
|
||||
#endif
|
||||
|
||||
/* register interrupt handlers */
|
||||
install_int_handler(regs->irq, &spi_interrupt, (void *)port);
|
||||
unmask_int(regs->irq);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t spi_gpio_read(int port)
|
||||
{
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
|
||||
if (regs == 0)
|
||||
return 0;
|
||||
|
||||
return (*regs->sppin >> 1) & 1;
|
||||
}
|
||||
|
||||
void spi_gpio_write(int port, uint32_t val)
|
||||
{
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
|
||||
if (regs == 0)
|
||||
return;
|
||||
|
||||
if (val) *regs->sppin |= (1 << 1);
|
||||
else *regs->sppin &= ~(1 << 1);
|
||||
}
|
||||
|
||||
void spi_gpio_configure(int port, uint32_t config)
|
||||
{
|
||||
const spi_regs_t *regs = spiregs(port);
|
||||
|
||||
if (regs == 0)
|
||||
return;
|
||||
|
||||
switch (config) {
|
||||
case GPIO_CFG_OUT_0 :
|
||||
*regs->sppin &= ~(1 << 1);
|
||||
break;
|
||||
|
||||
case GPIO_CFG_OUT_1 :
|
||||
*regs->sppin |= (1 << 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,136 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Computer, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_SPI_H
|
||||
#define __SAMSUNG_SPI_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rSPCLKCON0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x00))
|
||||
#define rSPCON0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x04))
|
||||
#define rSPSTA0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x08))
|
||||
#define rSPPIN0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x0C))
|
||||
#define rSPTDAT0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x10))
|
||||
#define rSPRDAT0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x20))
|
||||
#define rSPPRE0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x30))
|
||||
#define rSPCNT0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x34))
|
||||
#define rSPIDD0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x38))
|
||||
#define rSPIRTO0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x3C))
|
||||
#define rSPIHANGD0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x40))
|
||||
#define rSPISWRST0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x44))
|
||||
#define rSPIVER0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x48))
|
||||
#define rSPTDCNT0 (*(volatile u_int32_t *)(SPI0_BASE_ADDR + 0x4C))
|
||||
|
||||
#define rSPCLKCON1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x00))
|
||||
#define rSPCON1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x04))
|
||||
#define rSPSTA1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x08))
|
||||
#define rSPPIN1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x0C))
|
||||
#define rSPTDAT1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x10))
|
||||
#define rSPRDAT1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x20))
|
||||
#define rSPPRE1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x30))
|
||||
#define rSPCNT1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x34))
|
||||
#define rSPIDD1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x38))
|
||||
#define rSPIRTO1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x3C))
|
||||
#define rSPIHANGD1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x40))
|
||||
#define rSPISWRST1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x44))
|
||||
#define rSPIVER1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x48))
|
||||
#define rSPTDCNT1 (*(volatile u_int32_t *)(SPI1_BASE_ADDR + 0x4C))
|
||||
|
||||
#define rSPCLKCON2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x00))
|
||||
#define rSPCON2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x04))
|
||||
#define rSPSTA2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x08))
|
||||
#define rSPPIN2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x0C))
|
||||
#define rSPTDAT2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x10))
|
||||
#define rSPRDAT2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x20))
|
||||
#define rSPPRE2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x30))
|
||||
#define rSPCNT2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x34))
|
||||
#define rSPIDD2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x38))
|
||||
#define rSPIRTO2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x3C))
|
||||
#define rSPIHANGD2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x40))
|
||||
#define rSPISWRST2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x44))
|
||||
#define rSPIVER2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x48))
|
||||
#define rSPTDCNT2 (*(volatile u_int32_t *)(SPI2_BASE_ADDR + 0x4C))
|
||||
|
||||
#define rSPCLKCON3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x00))
|
||||
#define rSPCON3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x04))
|
||||
#define rSPSTA3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x08))
|
||||
#define rSPPIN3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x0C))
|
||||
#define rSPTDAT3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x10))
|
||||
#define rSPRDAT3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x20))
|
||||
#define rSPPRE3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x30))
|
||||
#define rSPCNT3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x34))
|
||||
#define rSPIDD3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x38))
|
||||
#define rSPIRTO3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x3C))
|
||||
#define rSPIHANGD3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x40))
|
||||
#define rSPISWRST3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x44))
|
||||
#define rSPIVER3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x48))
|
||||
#define rSPTDCNT3 (*(volatile u_int32_t *)(SPI3_BASE_ADDR + 0x4C))
|
||||
|
||||
#define rSPCLKCON4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x00))
|
||||
#define rSPCON4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x04))
|
||||
#define rSPSTA4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x08))
|
||||
#define rSPPIN4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x0C))
|
||||
#define rSPTDAT4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x10))
|
||||
#define rSPRDAT4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x20))
|
||||
#define rSPPRE4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x30))
|
||||
#define rSPCNT4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x34))
|
||||
#define rSPIDD4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x38))
|
||||
#define rSPIRTO4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x3C))
|
||||
#define rSPIHANGD4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x40))
|
||||
#define rSPISWRST4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x44))
|
||||
#define rSPIVER4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x48))
|
||||
#define rSPTDCNT4 (*(volatile u_int32_t *)(SPI4_BASE_ADDR + 0x4C))
|
||||
|
||||
#if SPI_VERSION == 0
|
||||
#define SPICON_SHIFT_OFFSET0 (0)
|
||||
#define SPICON_SHIFT_OFFSET1 (0)
|
||||
#define SPICON_SHIFT_OFFSET2 (0)
|
||||
#else
|
||||
#define SPICON_SHIFT_OFFSET0 (2)
|
||||
#define SPICON_SHIFT_OFFSET1 (3)
|
||||
#define SPICON_SHIFT_OFFSET2 (-1)
|
||||
#endif
|
||||
|
||||
#define SPICON_AGD_SHIFT (0)
|
||||
#define SPICON_CPHA_SHIFT (1)
|
||||
#define SPICON_CPOL_SHIFT (2)
|
||||
#define SPICON_MASTER_SHIFT (3)
|
||||
#define SPICON_CLK_EN_SHIFT (4)
|
||||
#define SPICON_MODE_SHIFT (5)
|
||||
#define SPICON_IE_RX_SHIFT (7)
|
||||
#define SPICON_IE_TR_SHIFT (8)
|
||||
#define SPICON_IE_MME_SHIFT (9)
|
||||
#define SPICON_IE_DCE_SHIFT (10)
|
||||
#define SPICON_MSBFT_SHIFT (11 + SPICON_SHIFT_OFFSET0)
|
||||
#define SPICON_CLK_SEL_SHIFT (12 + SPICON_SHIFT_OFFSET0)
|
||||
#define SPICON_BIT_LEN_SHIFT (13 + SPICON_SHIFT_OFFSET0)
|
||||
#define SPICON_DMA_SIZE_SHIFT (15 + SPICON_SHIFT_OFFSET0)
|
||||
#define SPICON_DATA_SWAP_SHIFT (16 + SPICON_SHIFT_OFFSET1)
|
||||
#define SPICON_RX_DELAY_SHIFT (17 + SPICON_SHIFT_OFFSET1)
|
||||
#define SPICON_IE_TX_SHIFT (21)
|
||||
#define SPICON_DELAY_SEL_SHIFT (27 + SPICON_SHIFT_OFFSET2)
|
||||
|
||||
|
||||
#if SPI_VERSION == 0
|
||||
#define SPI_FIFO_BITS (4)
|
||||
#define SPSTA_TX_FIFO_BIT_LO (4)
|
||||
#define SPSTA_RX_FIFO_BIT_LO (8)
|
||||
#else
|
||||
#define SPI_FIFO_BITS (5)
|
||||
#define SPSTA_TX_FIFO_BIT_LO (6)
|
||||
#define SPSTA_RX_FIFO_BIT_LO (11)
|
||||
#endif
|
||||
|
||||
#define SPSTA_TX_FIFO_BIT_HI (SPSTA_TX_FIFO_BIT_LO + SPI_FIFO_BITS - 1)
|
||||
#define SPSTA_RX_FIFO_BIT_HI (SPSTA_RX_FIFO_BIT_LO + SPI_FIFO_BITS - 1)
|
||||
#define SPI_FIFO_SIZE (1 << (SPI_FIFO_BITS - 1))
|
||||
|
||||
#endif /* __SAMSUNG_SPI_H */
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_SWI=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/swi.o
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <platform.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/gpio.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <target/gpiodef.h>
|
||||
|
||||
#include "swi.h"
|
||||
|
||||
#define SWI_FREQUENCY (2000000)
|
||||
|
||||
int swi_backlight_enable(u_int32_t iset_code, u_int32_t backlight_level)
|
||||
{
|
||||
u_int32_t swi_div;
|
||||
|
||||
clock_gate(CLK_SWI, true);
|
||||
|
||||
swi_div = (clock_get_frequency(CLK_NCLK) + SWI_FREQUENCY - 1) / SWI_FREQUENCY;
|
||||
|
||||
rSWI_CON = SWI_CON_SWI_CLK_DIV(swi_div - 1) | SWI_CON_SWI_OFF_STATE_HIGH | SWI_CON_SWI_EN;
|
||||
|
||||
/* Some targets support 8 bits, others support 11. Assume that the input value is in range. */
|
||||
rSWI_ITR_DATA = 0x0080 | iset_code | ((backlight_level & 0x780) << 1) | (backlight_level & 0x7F);
|
||||
|
||||
rSWI_ITR_COM = SWI_ITR_COM_SWI_ITR_MODE_16BIT | SWI_ITR_COM_SWI_ITR_SET;
|
||||
while ((rSWI_ITR_COM & SWI_ITR_COM_SWI_ITR_SET) != 0);
|
||||
|
||||
#ifdef GPIO_BACKLIGHT_EN
|
||||
gpio_write(GPIO_BACKLIGHT_EN, (backlight_level != 0) ? GPIO_BACKLIGHT_POLARITY : !GPIO_BACKLIGHT_POLARITY);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_SWI_H
|
||||
#define __SAMSUNG_SWI_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rSWI_CON (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x00))
|
||||
#define SWI_CON_SWI_CLK_DIV(n) (((n) & 0xFF) << 8)
|
||||
#define SWI_CON_SWI_CLK_SEL_NCLK (0 << 2)
|
||||
#define SWI_CON_SWI_CLK_SEL_PCLK (1 << 2)
|
||||
#define SWI_CON_SWI_OFF_STATE_LOW (0 << 1)
|
||||
#define SWI_CON_SWI_OFF_STATE_HIGH (1 << 1)
|
||||
#define SWI_CON_SWI_EN (1 << 0)
|
||||
#define rSWI_SWRESET (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x04))
|
||||
#define rSWI_TIMING (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x08))
|
||||
#define rSWI_INT_FLAG (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x0C))
|
||||
#define rSWI_INT_MASK (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x10))
|
||||
#define rSWI_ITR_COM (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x14))
|
||||
#define SWI_ITR_COM_SWI_ITR_MODE_8BIT (0 << 1)
|
||||
#define SWI_ITR_COM_SWI_ITR_MODE_16BIT (1 << 1)
|
||||
#define SWI_ITR_COM_SWI_ITR_SET (1 << 0)
|
||||
#define rSWI_ITR_DATA (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x18))
|
||||
#define rSWI_STR_COM (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x1C))
|
||||
#define rSWI_STR_DATA (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x20))
|
||||
#define rSWI_STR_DLY (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x24))
|
||||
#define rSWI_HTR_COM (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x28))
|
||||
#define rSWI_HTR_DATA (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x2C))
|
||||
#define rSWI_VERISON (*(volatile u_int32_t *)(SWI_BASE_ADDR + 0x30))
|
||||
|
||||
#endif /* ! __SAMSUNG_SWI_H */
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_TIMER=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/timer.o
|
||||
@@ -0,0 +1,484 @@
|
||||
/*
|
||||
* Copyright (C) 2007-2009 Apple Inc. All rights reserved.
|
||||
* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <debug.h>
|
||||
#include <platform.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/int.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/soc/hwisr.h>
|
||||
#include <sys.h>
|
||||
#include <sys/callout.h>
|
||||
|
||||
#include "timer.h"
|
||||
|
||||
/* 16-bit timers */
|
||||
#define TIMER_A 0
|
||||
#define TIMER_B 1
|
||||
#define TIMER_C 2
|
||||
#define TIMER_D 3
|
||||
|
||||
/* 32-bit timers */
|
||||
#define TIMER_E 4
|
||||
#define TIMER_F 5
|
||||
#define TIMER_G 6
|
||||
#define TIMER_H 7
|
||||
|
||||
/* 64-bit timer */
|
||||
#define TIMER_64 8
|
||||
|
||||
#define INVALID_TIMER -1
|
||||
|
||||
#ifndef TIMER_DEADLINE_TIMER
|
||||
# if TIMER_DEADLINE_USE16
|
||||
# define TIMER_DEADLINE_TIMER TIMER_D
|
||||
# else
|
||||
# define TIMER_DEADLINE_TIMER TIMER_E
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* timer16/32 stuff */
|
||||
typedef struct {
|
||||
volatile u_int32_t *tcon;
|
||||
volatile u_int32_t *tcmd;
|
||||
volatile u_int32_t *tdata0;
|
||||
volatile u_int32_t *tdata1;
|
||||
volatile u_int32_t *tpre;
|
||||
volatile u_int32_t *tcnt;
|
||||
} timer_regs_t;
|
||||
|
||||
static const timer_regs_t timer_regs_list[] = {
|
||||
{ &rTACON, &rTACMD, &rTADATA0, &rTADATA1, &rTAPRE, &rTACNT },
|
||||
{ &rTBCON, &rTBCMD, &rTBDATA0, &rTBDATA1, &rTBPRE, &rTBCNT },
|
||||
{ &rTCCON, &rTCCMD, &rTCDATA0, &rTCDATA1, &rTCPRE, &rTCCNT },
|
||||
{ &rTDCON, &rTDCMD, &rTDDATA0, &rTDDATA1, &rTDPRE, &rTDCNT },
|
||||
{ &rTECON, &rTECMD, &rTEDATA0, &rTEDATA1, &rTEPRE, &rTECNT },
|
||||
{ &rTFCON, &rTFCMD, &rTFDATA0, &rTFDATA1, &rTFPRE, &rTFCNT },
|
||||
{ &rTGCON, &rTGCMD, &rTGDATA0, &rTGDATA1, &rTGPRE, &rTGCNT },
|
||||
{ &rTHCON, &rTHCMD, &rTHDATA0, &rTHDATA1, &rTHPRE, &rTHCNT }
|
||||
};
|
||||
static const timer_regs_t *timer_regs(int timer);
|
||||
|
||||
enum timer_clk {
|
||||
PCLK,
|
||||
NCLK,
|
||||
SLOWCLK,
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
/* configuration */
|
||||
enum timer_clk source_clk;
|
||||
uint32_t divider_bits;
|
||||
int prescalar;
|
||||
|
||||
/* callout routine */
|
||||
void (*ovf_tick)(void);
|
||||
void (*mat0_tick)(void);
|
||||
void (*mat1_tick)(void);
|
||||
} timer_status_t;
|
||||
|
||||
static timer_status_t timer_status[TIMER_H+1];
|
||||
|
||||
enum timer_mode {
|
||||
MODE_INTERVAL = 0,
|
||||
MODE_PWM = 0x2,
|
||||
MODE_PDM = 0x3,
|
||||
MODE_ONESHOT_PWM = 0x4,
|
||||
MODE_ONESHOT_PDM = 0x5,
|
||||
MODE_CAPTURE = 0x6,
|
||||
};
|
||||
|
||||
static void setup_timer(int timer, uint32_t data0, uint32_t data1, enum timer_mode mode, bool countdown, bool countdown_start, bool start_polarity);
|
||||
static void setup_timer_clk(int timer, enum timer_clk clk, int divider, int prescalar);
|
||||
static void start_stop_timer(int timer, bool start);
|
||||
|
||||
static void timer_deadline(void);
|
||||
static void (* timer_deadline_func)(void);
|
||||
|
||||
/* timer 64 stuff */
|
||||
static u_int64_t read_timer64(void);
|
||||
|
||||
static int timer64_ticks_per_sec; // for system time
|
||||
static uint64_t timer64_scale;
|
||||
|
||||
static void timer32_int(void *);
|
||||
static void timer16_int(void *);
|
||||
|
||||
static u_int64_t read_timer64(void)
|
||||
{
|
||||
u_int32_t low, high;
|
||||
|
||||
retry:
|
||||
high = rTM64_CNTH;
|
||||
low = rTM64_CNTL;
|
||||
if (high != rTM64_CNTH)
|
||||
goto retry;
|
||||
|
||||
return (u_int64_t)high << 32 | low;
|
||||
}
|
||||
|
||||
static u_int32_t read_timer(int timer)
|
||||
{
|
||||
const timer_regs_t *regs = timer_regs(timer);
|
||||
|
||||
return *regs->tcnt;
|
||||
}
|
||||
|
||||
static const timer_regs_t *timer_regs(int timer)
|
||||
{
|
||||
if (timer == TIMER_64)
|
||||
panic("timer_regs: asked for invalid timer registers\n");
|
||||
|
||||
return &timer_regs_list[timer];
|
||||
}
|
||||
|
||||
static void setup_timer_clk(int timer, enum timer_clk clk, int divider, int prescalar)
|
||||
{
|
||||
if (clk == SLOWCLK) {
|
||||
timer_status[timer].source_clk = PCLK;
|
||||
timer_status[timer].divider_bits = 6;
|
||||
} else {
|
||||
timer_status[timer].source_clk = clk;
|
||||
switch (divider) {
|
||||
case 2:
|
||||
timer_status[timer].divider_bits = 0;
|
||||
break;
|
||||
case 4:
|
||||
timer_status[timer].divider_bits = 1;
|
||||
break;
|
||||
case 16:
|
||||
timer_status[timer].divider_bits = 2;
|
||||
break;
|
||||
case 64:
|
||||
timer_status[timer].divider_bits = 3;
|
||||
break;
|
||||
case 1:
|
||||
timer_status[timer].divider_bits = 4;
|
||||
break;
|
||||
default:
|
||||
dprintf(DEBUG_CRITICAL, "setup_timer_clk: invalid divider %d\n", divider);
|
||||
}
|
||||
}
|
||||
timer_status[timer].prescalar = prescalar;
|
||||
}
|
||||
|
||||
static void setup_timer(int timer, uint32_t data0, uint32_t data1, enum timer_mode mode, bool countdown, bool countdown_start, bool start_polarity)
|
||||
{
|
||||
start_stop_timer(timer, false);
|
||||
|
||||
switch (timer) {
|
||||
case TIMER_A: case TIMER_B: case TIMER_C: case TIMER_D: {
|
||||
const timer_regs_t *regs = timer_regs(timer);
|
||||
|
||||
/* setup timer (16 bit) */
|
||||
*regs->tcon = (start_polarity ? (1<<11) : 0) |
|
||||
(mode << 3) |
|
||||
(timer_status[timer].divider_bits<<8) | ((timer_status[timer].source_clk == NCLK) ? (1<<6) : 0) |
|
||||
(7<<12); // mode, upcount (no downcount feature), divider, clock source, enable all ints
|
||||
*regs->tpre = timer_status[timer].prescalar;
|
||||
*regs->tdata0 = data0;
|
||||
*regs->tdata1 = data1;
|
||||
*regs->tcmd = 2; // initialize the timer
|
||||
break;
|
||||
}
|
||||
case TIMER_E: case TIMER_F: case TIMER_G: case TIMER_H: {
|
||||
const timer_regs_t *regs = timer_regs(timer);
|
||||
|
||||
/* setup timer (32 bit) */
|
||||
*regs->tcon = (countdown_start ? (1<<28) : 0) |
|
||||
(countdown ? (1<<24) : 0) |
|
||||
(start_polarity ? (1<<11) : 0) |
|
||||
(mode << 3) |
|
||||
(timer_status[timer].divider_bits<<8) | ((timer_status[timer].source_clk == NCLK) ? (1<<6) : 0) |
|
||||
(7<<12); // mode, downcount, pwm/pdm start bit, divider, clock source, enable all ints
|
||||
*regs->tpre = timer_status[timer].prescalar;
|
||||
*regs->tdata0 = data0;
|
||||
*regs->tdata1 = data1;
|
||||
*regs->tcmd = 2; // initialize the timer
|
||||
break;
|
||||
}
|
||||
default:
|
||||
panic("setup_timer: timer %d not supported\n", timer);
|
||||
}
|
||||
}
|
||||
|
||||
static void start_stop_timer(int timer, bool start)
|
||||
{
|
||||
switch (timer) {
|
||||
case TIMER_A: case TIMER_B: case TIMER_C: case TIMER_D:
|
||||
case TIMER_E: case TIMER_F: case TIMER_G: case TIMER_H: {
|
||||
const timer_regs_t *regs = timer_regs(timer);
|
||||
if (start)
|
||||
*regs->tcmd = 1; // start it
|
||||
else
|
||||
*regs->tcmd = 0; // stop it
|
||||
break;
|
||||
}
|
||||
case TIMER_64:
|
||||
if (start)
|
||||
rTM64_CON &= ~0xf;
|
||||
else
|
||||
rTM64_CON |= 0xa;
|
||||
break;
|
||||
default:
|
||||
panic("start_stop_timer: timer %d not supported\n", timer);
|
||||
}
|
||||
}
|
||||
|
||||
int timer_init(u_int32_t timer)
|
||||
{
|
||||
dprintf(DEBUG_SPEW, "timers_init()\n");
|
||||
|
||||
#ifndef TIMER_NO_INIT
|
||||
clock_gate(CLK_TIMER, true);
|
||||
|
||||
/* stop all timers */
|
||||
start_stop_timer(TIMER_A, false);
|
||||
start_stop_timer(TIMER_B, false);
|
||||
start_stop_timer(TIMER_C, false);
|
||||
start_stop_timer(TIMER_D, false);
|
||||
start_stop_timer(TIMER_E, false);
|
||||
start_stop_timer(TIMER_F, false);
|
||||
start_stop_timer(TIMER_G, false);
|
||||
start_stop_timer(TIMER_H, false);
|
||||
start_stop_timer(TIMER_64, false);
|
||||
|
||||
setup_timer_clk(TIMER_A, NCLK, 2, 0);
|
||||
setup_timer_clk(TIMER_B, NCLK, 2, 0);
|
||||
setup_timer_clk(TIMER_C, NCLK, 2, 0);
|
||||
setup_timer_clk(TIMER_D, NCLK, 2, 0);
|
||||
setup_timer_clk(TIMER_E, NCLK, 2, 0);
|
||||
setup_timer_clk(TIMER_F, NCLK, 2, 0);
|
||||
setup_timer_clk(TIMER_G, NCLK, 2, 0);
|
||||
setup_timer_clk(TIMER_H, NCLK, 2, 0);
|
||||
|
||||
/* set up the 64-bit timer */
|
||||
rTM64_CON = 0xa; // disable it
|
||||
rTM64_DATA0L = 0xffffffff;
|
||||
rTM64_DATA0H = 0xffffffff;
|
||||
rTM64_DATA1L = 0xffffffff;
|
||||
rTM64_DATA1H = 0xffffffff;
|
||||
rTM64_CON = (3<<15) | (1 << 4); // set nclk source, prescalar at /2, enable
|
||||
|
||||
/* calculate how fast timer64 is running */
|
||||
timer64_ticks_per_sec = clock_get_frequency(CLK_NCLK) / 2;
|
||||
#else
|
||||
# ifndef TIMER_TICK_RATE
|
||||
# error TIMER_TICK_RATE not defined but we did not init the timebase
|
||||
# endif
|
||||
timer64_ticks_per_sec = TIMER_TICK_RATE;
|
||||
#endif
|
||||
|
||||
// Precompute a 44.20 fixed-point representation of the microsecond to ticks conversion rate.
|
||||
// This limits the maximum number of microseconds that can be represented to 44 bits worth of ticks.
|
||||
timer64_scale = ((uint64_t)timer64_ticks_per_sec << 20) / (1000 * 1000);
|
||||
|
||||
dprintf(DEBUG_SPEW, "timer64 running at %u Hz, will wrap around in %llu secs\n",
|
||||
timer64_ticks_per_sec, 0xffffffffffffffffULL / timer64_ticks_per_sec);
|
||||
|
||||
dprintf(DEBUG_SPEW, "using 64-bit timer for system time\n");
|
||||
|
||||
/* install interrupt handler */
|
||||
#if TIMER_DEADLINE_USE16
|
||||
install_int_handler(INT_TIMERIRQ, &timer16_int, (void *)1);
|
||||
unmask_int(INT_TIMERIRQ);
|
||||
#else
|
||||
install_int_handler(INT_TIMERFIQ, &timer32_int, (void *)1);
|
||||
unmask_int(INT_TIMERFIQ);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void timer_gpio(int timer, int level)
|
||||
{
|
||||
setup_timer(timer, 0, 0, MODE_PWM, false, false, level);
|
||||
}
|
||||
|
||||
static void timer_handle_int(int timer, u_int32_t status)
|
||||
{
|
||||
if (status & (1<<2)) {
|
||||
// overflow
|
||||
if (timer_status[timer].ovf_tick)
|
||||
timer_status[timer].ovf_tick();
|
||||
}
|
||||
if (status & (1<<1)) {
|
||||
// int1
|
||||
if (timer_status[timer].mat1_tick)
|
||||
timer_status[timer].mat1_tick();
|
||||
}
|
||||
if (status & (1<<0)) {
|
||||
// int0
|
||||
if (timer_status[timer].mat0_tick)
|
||||
timer_status[timer].mat0_tick();
|
||||
}
|
||||
}
|
||||
|
||||
static void timer16_int(void *arg)
|
||||
{
|
||||
u_int32_t tcon;
|
||||
|
||||
tcon = rTACON;
|
||||
if (tcon & (7<<16)) {
|
||||
timer_handle_int(TIMER_A, tcon >> 16);
|
||||
rTACON |= tcon & (7<<16);
|
||||
}
|
||||
tcon = rTBCON;
|
||||
if (tcon & (7<<16)) {
|
||||
timer_handle_int(TIMER_B, tcon >> 16);
|
||||
rTBCON |= tcon & (7<<16);
|
||||
}
|
||||
tcon = rTCCON;
|
||||
if (tcon & (7<<16)) {
|
||||
timer_handle_int(TIMER_C, tcon >> 16);
|
||||
rTCCON |= tcon & (7<<16);
|
||||
}
|
||||
tcon = rTDCON;
|
||||
if (tcon & (7<<16)) {
|
||||
timer_handle_int(TIMER_D, tcon >> 16);
|
||||
rTDCON |= tcon & (7<<16);
|
||||
}
|
||||
}
|
||||
|
||||
static void timer32_int(void *arg)
|
||||
{
|
||||
u_int32_t tm32_status, tm32_ack, status, cnt;
|
||||
|
||||
tm32_status = rTM32_INT;
|
||||
tm32_ack = 0;
|
||||
cnt = 0;
|
||||
|
||||
#if TIMER_VERSION != 0
|
||||
status = (tm32_status >> (cnt * 8)) & 0x7;
|
||||
timer_handle_int(TIMER_H, status);
|
||||
tm32_ack |= (status << (cnt * 8));
|
||||
cnt++;
|
||||
#endif
|
||||
status = (tm32_status >> (cnt * 8)) & 0x7;
|
||||
timer_handle_int(TIMER_G, status);
|
||||
tm32_ack |= (status << (cnt * 8));
|
||||
cnt++;
|
||||
|
||||
status = (tm32_status >> (cnt * 8)) & 0x7;
|
||||
timer_handle_int(TIMER_F, status);
|
||||
tm32_ack |= (status << (cnt * 8));
|
||||
cnt++;
|
||||
|
||||
status = (tm32_status >> (cnt * 8)) & 0x7;
|
||||
timer_handle_int(TIMER_E, status);
|
||||
tm32_ack |= (status << (cnt * 8));
|
||||
cnt++;
|
||||
|
||||
rTM32_INT = tm32_ack;
|
||||
}
|
||||
|
||||
static void timer_deadline(void)
|
||||
{
|
||||
|
||||
// printf("deadline interrupt at %llu\n", read_timer64());
|
||||
/* stop the timer */
|
||||
start_stop_timer(TIMER_DEADLINE_TIMER, false);
|
||||
|
||||
/* call the handler */
|
||||
if (timer_deadline_func)
|
||||
timer_deadline_func();
|
||||
}
|
||||
|
||||
u_int64_t timer_get_ticks()
|
||||
{
|
||||
return read_timer64();
|
||||
}
|
||||
|
||||
u_int32_t timer_get_tick_rate(void)
|
||||
{
|
||||
return timer64_ticks_per_sec;
|
||||
}
|
||||
|
||||
utime_t timer_ticks_to_usecs(uint64_t ticks)
|
||||
{
|
||||
return (ticks * 1000 * 1000) / timer64_ticks_per_sec;
|
||||
}
|
||||
|
||||
uint64_t timer_usecs_to_ticks(utime_t usecs)
|
||||
{
|
||||
return (usecs * timer64_scale) >> 20;
|
||||
}
|
||||
|
||||
void timer_stop_all(void)
|
||||
{
|
||||
#ifndef TIMER_NO_INIT
|
||||
/* stop all timers */
|
||||
start_stop_timer(TIMER_A, false);
|
||||
start_stop_timer(TIMER_B, false);
|
||||
start_stop_timer(TIMER_C, false);
|
||||
start_stop_timer(TIMER_D, false);
|
||||
start_stop_timer(TIMER_E, false);
|
||||
start_stop_timer(TIMER_F, false);
|
||||
start_stop_timer(TIMER_G, false);
|
||||
start_stop_timer(TIMER_H, false);
|
||||
start_stop_timer(TIMER_64, false);
|
||||
#endif
|
||||
}
|
||||
|
||||
void timer_deadline_enter(uint64_t deadline, void (* callback)(void))
|
||||
{
|
||||
uint64_t ticks;
|
||||
uint32_t decr;
|
||||
|
||||
timer_deadline_func = callback;
|
||||
if (callback != NULL) {
|
||||
/* convert absolute deadline to relative time */
|
||||
ticks = read_timer64();
|
||||
if (deadline <= ticks) {
|
||||
// printf("setting deadline %llu before current time %llu\n", deadline, ticks);
|
||||
deadline = 1;
|
||||
} else {
|
||||
// printf("setting deadline %llu (0x%llx away)\n", deadline, deadline - ticks);
|
||||
deadline -= ticks;
|
||||
}
|
||||
|
||||
/* clamp the deadline to our maximum */
|
||||
#if TIMER_DEADLINE_USE16
|
||||
decr = (deadline > 0xffff) ? 0xffff : deadline;
|
||||
#else
|
||||
decr = (deadline > 0xffffffff) ? 0xffffffff : deadline;
|
||||
#endif
|
||||
// printf(" decr 0x%x\n", decr);
|
||||
|
||||
/*
|
||||
* Start the timer in interval mode. We will stop it when we handle the
|
||||
* interrupt, so it doesn't really matter as long as we get an interrupt after
|
||||
* (decr) ticks or so.
|
||||
*/
|
||||
timer_status[TIMER_DEADLINE_TIMER].mat0_tick = timer_deadline;
|
||||
setup_timer(TIMER_DEADLINE_TIMER, decr, 0, MODE_INTERVAL, false, false, 0);
|
||||
start_stop_timer(TIMER_DEADLINE_TIMER, true);
|
||||
} else {
|
||||
/* stop the timer */
|
||||
start_stop_timer(TIMER_DEADLINE_TIMER, false);
|
||||
}
|
||||
}
|
||||
|
||||
u_int32_t timer_get_entropy(void)
|
||||
{
|
||||
return arch_get_entropy(&rTM64_CNTL);
|
||||
}
|
||||
|
||||
void wdt_enable(void)
|
||||
{
|
||||
rWDTCON = (1 << 20) | (15 << 16) | (4 << 12) | (0xA << 8);
|
||||
}
|
||||
|
||||
void wdt_chip_reset(void)
|
||||
{
|
||||
rWDTCON = (1 << 20) | (0 << 16) | (0 << 15) | (0 << 12) | (0 << 8) | (0 << 0);
|
||||
}
|
||||
@@ -0,0 +1,121 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Computer, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_TIMER_H
|
||||
#define __SAMSUNG_TIMER_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
/**
|
||||
* Timer A
|
||||
*/
|
||||
#define rTACON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x0))
|
||||
#define rTACMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x4))
|
||||
#define rTADATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x8))
|
||||
#define rTADATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xC))
|
||||
#define rTAPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10))
|
||||
#define rTACNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x14))
|
||||
/**
|
||||
* Timer B
|
||||
*/
|
||||
#define rTBCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x20))
|
||||
#define rTBCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x24))
|
||||
#define rTBDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x28))
|
||||
#define rTBDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x2C))
|
||||
#define rTBPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x30))
|
||||
#define rTBCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x34))
|
||||
/**
|
||||
* Timer C
|
||||
*/
|
||||
#define rTCCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x40))
|
||||
#define rTCCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x44))
|
||||
#define rTCDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x48))
|
||||
#define rTCDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x4C))
|
||||
#define rTCPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x50))
|
||||
#define rTCCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x54))
|
||||
/**
|
||||
* Timer D
|
||||
*/
|
||||
#define rTDCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x60))
|
||||
#define rTDCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x64))
|
||||
#define rTDDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x68))
|
||||
#define rTDDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x6C))
|
||||
#define rTDPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x70))
|
||||
#define rTDCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x74))
|
||||
|
||||
//64-Bit Timer Register
|
||||
#define rTM64_CNTH (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x80))
|
||||
#define rTM64_CNTL (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x84))
|
||||
#define rTM64_CON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x88))
|
||||
|
||||
#define rTM64_DATA0H (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x8C))
|
||||
#define rTM64_DATA0L (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x90))
|
||||
#define rTM64_DATA1H (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x94))
|
||||
#define rTM64_DATA1L (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x98))
|
||||
/**
|
||||
* Timer E
|
||||
*/
|
||||
#define rTECON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xA0))
|
||||
#define rTECMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xA4))
|
||||
#define rTEDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xA8))
|
||||
#define rTEDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xAC))
|
||||
#define rTEPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xB0))
|
||||
#define rTECNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xB4))
|
||||
/**
|
||||
* Timer F
|
||||
*/
|
||||
#define rTFCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xC0))
|
||||
#define rTFCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xC4))
|
||||
#define rTFDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xC8))
|
||||
#define rTFDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xCC))
|
||||
#define rTFPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xD0))
|
||||
#define rTFCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xD4))
|
||||
/**
|
||||
* Timer G
|
||||
*/
|
||||
#define rTGCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xE0))
|
||||
#define rTGCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xE4))
|
||||
#define rTGDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xE8))
|
||||
#define rTGDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xEC))
|
||||
#define rTGPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xF0))
|
||||
#define rTGCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xF4))
|
||||
/**
|
||||
* Timer H
|
||||
*/
|
||||
#define rTHCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x100))
|
||||
#define rTHCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x104))
|
||||
#define rTHDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x108))
|
||||
#define rTHDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10C))
|
||||
#define rTHPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x100))
|
||||
#define rTHCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x104))
|
||||
|
||||
#if TIMER_VERSION == 0
|
||||
#define rTM32_INT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xF8))
|
||||
#else
|
||||
#define rTM32_INT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x118))
|
||||
#endif
|
||||
|
||||
#define rTM_INT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10000))
|
||||
/**
|
||||
* Timer counter register (RO)
|
||||
*/
|
||||
#define rTM32_CNT_E (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10004))
|
||||
#define rTM32_CNT_F (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10008))
|
||||
#define rTM32_CNT_G (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x1000C))
|
||||
|
||||
#define rTM64_CNTH2 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10010))
|
||||
#define rTM64_CNTL2 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10014))
|
||||
|
||||
|
||||
#define rWDTCON (*(volatile u_int32_t *)(WDT_BASE_ADDR + 0x00))
|
||||
#define rWDTCNT (*(volatile u_int32_t *)(WDT_BASE_ADDR + 0x04))
|
||||
|
||||
#endif /* __SAMSUNG_TIMER_H */
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_UART=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/uart.o
|
||||
@@ -0,0 +1,683 @@
|
||||
/*
|
||||
* Copyright (C) 2007-2009 Apple Inc. All rights reserved.
|
||||
* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
//#include <string.h>
|
||||
#include <arch.h>
|
||||
#include <debug.h>
|
||||
#include <cbuffer.h>
|
||||
#include <drivers/power.h>
|
||||
#include <drivers/uart.h>
|
||||
#include <platform.h>
|
||||
#include <platform/int.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/soc/hwisr.h>
|
||||
#include <sys.h>
|
||||
#include <sys/task.h>
|
||||
#if WITH_TARGET_CONFIG
|
||||
#include <target/uartconfig.h>
|
||||
#elif WITH_PLATFORM_UARTCONFIG
|
||||
#include <platform/uartconfig.h>
|
||||
#endif
|
||||
|
||||
#include "uart.h"
|
||||
|
||||
#ifndef UARTS_MASK
|
||||
#define UARTS_MASK ((1 << UARTS_COUNT) - 1)
|
||||
#endif
|
||||
|
||||
#ifndef UART_FLOWCONTROL_MASK
|
||||
#define UART_FLOWCONTROL_MASK (0x0E)
|
||||
#endif
|
||||
|
||||
|
||||
#define UART_RX_LEN 16
|
||||
|
||||
// defined in sys/debug.c
|
||||
extern int DebugUartReady;
|
||||
|
||||
static void uart_interrupt(void *);
|
||||
static int tx_fifo_count(int port);
|
||||
static int rx_fifo_count(int port);
|
||||
static void uart_dump_config(int port);
|
||||
static void uart_clear_rx(int port);
|
||||
static int uart_rx_complete(int port);
|
||||
static void uart_clear_tx(int port);
|
||||
static int uart_tx_complete(int port);
|
||||
static void drain_rx_fifo(int port);
|
||||
|
||||
typedef struct {
|
||||
volatile u_int32_t *ulcon;
|
||||
volatile u_int32_t *ucon;
|
||||
volatile u_int32_t *ufcon;
|
||||
volatile u_int32_t *umcon;
|
||||
volatile u_int32_t *utrstat;
|
||||
volatile u_int32_t *uerstat;
|
||||
volatile u_int32_t *ufstat;
|
||||
volatile u_int32_t *umstat;
|
||||
volatile u_int32_t *utxh;
|
||||
volatile u_int32_t *urxh;
|
||||
volatile u_int32_t *ubrdiv;
|
||||
volatile u_int32_t *uabrcnt;
|
||||
int clock;
|
||||
u_int32_t irq;
|
||||
} uart_regs_t;
|
||||
|
||||
static const uart_regs_t uart_regs[] = {
|
||||
#if UARTS_COUNT > 0
|
||||
{ &rULCON0, &rUCON0, &rUFCON0, &rUMCON0, &rUTRSTAT0, &rUERSTAT0, &rUFSTAT0, &rUMSTAT0, &rUTXH0, &rURXH0, &rUBRDIV0, &rUABRCNT0, CLK_UART0, INT_UART0 },
|
||||
#endif
|
||||
#if UARTS_COUNT > 1
|
||||
{ &rULCON1, &rUCON1, &rUFCON1, &rUMCON1, &rUTRSTAT1, &rUERSTAT1, &rUFSTAT1, &rUMSTAT1, &rUTXH1, &rURXH1, &rUBRDIV1, &rUABRCNT1, CLK_UART1, INT_UART1 },
|
||||
#endif
|
||||
#if UARTS_COUNT > 2
|
||||
{ &rULCON2, &rUCON2, &rUFCON2, &rUMCON2, &rUTRSTAT2, &rUERSTAT2, &rUFSTAT2, &rUMSTAT2, &rUTXH2, &rURXH2, &rUBRDIV2, &rUABRCNT2, CLK_UART2, INT_UART2 },
|
||||
#endif
|
||||
#if UARTS_COUNT > 3
|
||||
{ &rULCON3, &rUCON3, &rUFCON3, &rUMCON3, &rUTRSTAT3, &rUERSTAT3, &rUFSTAT3, &rUMSTAT3, &rUTXH3, &rURXH3, &rUBRDIV3, &rUABRCNT3, CLK_UART3, INT_UART3 },
|
||||
#endif
|
||||
#if UARTS_COUNT > 4
|
||||
{ &rULCON4, &rUCON4, &rUFCON4, &rUMCON4, &rUTRSTAT4, &rUERSTAT4, &rUFSTAT4, &rUMSTAT4, &rUTXH4, &rURXH4, &rUBRDIV4, &rUABRCNT4, CLK_UART4, INT_UART4 },
|
||||
#endif
|
||||
#if UARTS_COUNT > 5
|
||||
{ &rULCON5, &rUCON5, &rUFCON5, &rUMCON5, &rUTRSTAT5, &rUERSTAT5, &rUFSTAT5, &rUMSTAT5, &rUTXH5, &rURXH5, &rUBRDIV5, &rUABRCNT5, CLK_UART5, INT_UART5 },
|
||||
#endif
|
||||
#if UARTS_COUNT > 6
|
||||
{ &rULCON6, &rUCON6, &rUFCON6, &rUMCON6, &rUTRSTAT6, &rUERSTAT6, &rUFSTAT6, &rUMSTAT6, &rUTXH6, &rURXH6, &rUBRDIV6, &rUABRCNT6, CLK_UART6, INT_UART6 },
|
||||
#endif
|
||||
#if UARTS_COUNT > 7
|
||||
{ &rULCON7, &rUCON7, &rUFCON7, &rUMCON7, &rUTRSTAT7, &rUERSTAT7, &rUFSTAT7, &rUMSTAT7, &rUTXH7, &rURXH7, &rUBRDIV7, &rUABRCNT7, CLK_UART7, INT_UART7 },
|
||||
#endif
|
||||
#if UARTS_COUNT > 8
|
||||
{ &rULCON8, &rUCON8, &rUFCON8, &rUMCON8, &rUTRSTAT8, &rUERSTAT8, &rUFSTAT8, &rUMSTAT8, &rUTXH8, &rURXH8, &rUBRDIV8, &rUABRCNT8, CLK_UART8, INT_UART8 },
|
||||
#endif
|
||||
#if UARTS_COUNT > 9
|
||||
#error "Need to add more entries to uart_regs"
|
||||
#endif
|
||||
};
|
||||
|
||||
enum uart_mode {
|
||||
MODE_POLL,
|
||||
MODE_INT,
|
||||
};
|
||||
|
||||
enum uart_clk {
|
||||
PCLK,
|
||||
NCLK,
|
||||
SLOWCLK,
|
||||
};
|
||||
|
||||
static struct uart_status {
|
||||
int port;
|
||||
int baud;
|
||||
int sample_rate;
|
||||
bool flow_en;
|
||||
bool fifo_en;
|
||||
enum uart_mode mode;
|
||||
bool nclk; // false is pclk
|
||||
|
||||
/* Interrupt mode */
|
||||
CBUFFER rx_cbuf;
|
||||
|
||||
struct task_event rx_event;
|
||||
|
||||
/* completion flags */
|
||||
volatile int tx_complete;
|
||||
volatile int rx_complete;
|
||||
} uart_status[UARTS_COUNT];
|
||||
|
||||
static void uart_set_sample_rate(int port, int rate);
|
||||
static void uart_set_baud_rate(int port, u_int32_t baud_rate);
|
||||
static void uart_set_flow_control(int port, bool flow);
|
||||
static void uart_set_fifo_enable(int port, bool enable);
|
||||
static void uart_set_mode(int port, enum uart_mode mode);
|
||||
static void uart_set_clk(int port, enum uart_clk clk);
|
||||
|
||||
static int uart_read(int port, void *_buf, size_t len, bool wait);
|
||||
static int uart_write(int port, const void *_buf, size_t len, bool wait);
|
||||
|
||||
static const uart_regs_t *uregs(int port)
|
||||
{
|
||||
if (port < 0 || port >= UARTS_COUNT || !(UARTS_MASK & (1 << port)))
|
||||
panic("invalid uart\n");
|
||||
|
||||
return &uart_regs[port];
|
||||
}
|
||||
|
||||
static void uart_set_sample_rate(int port, int rate)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
|
||||
#if UART_VERSION == 0
|
||||
switch (rate) {
|
||||
case 4:
|
||||
*regs->ubrdiv = (*regs->ubrdiv & ~(3<<16)) | (2<<16);
|
||||
uart_status[port].sample_rate = 4;
|
||||
break;
|
||||
case 8:
|
||||
*regs->ubrdiv = (*regs->ubrdiv & ~(3<<16)) | (1<<16);
|
||||
uart_status[port].sample_rate = 8;
|
||||
break;
|
||||
case 16:
|
||||
*regs->ubrdiv = (*regs->ubrdiv & ~(3<<16)) | (0<<16);
|
||||
uart_status[port].sample_rate = 16;
|
||||
break;
|
||||
default:
|
||||
printf("uart_set_sample_rate: invalid rate %d\n", rate);
|
||||
return;
|
||||
}
|
||||
#else
|
||||
if ((rate < 4) || (rate > 16)) {
|
||||
printf("uart_set_sample_rate: invalid rate %d\n", rate);
|
||||
return;
|
||||
}
|
||||
*regs->ubrdiv = (*regs->ubrdiv & ~(0xF<<16)) | ((16 - rate)<<16);
|
||||
uart_status[port].sample_rate = rate;
|
||||
#endif
|
||||
|
||||
/* based on the new info, set the baud rate */
|
||||
uart_set_baud_rate(port, uart_status[port].baud);
|
||||
}
|
||||
|
||||
static void uart_set_clk(int port, enum uart_clk clk)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
|
||||
switch (clk) {
|
||||
case PCLK:
|
||||
uart_status[port].nclk = false;
|
||||
*regs->ucon &= ~(1<<10);
|
||||
break;
|
||||
case NCLK:
|
||||
uart_status[port].nclk = true;
|
||||
*regs->ucon |= (1<<10);
|
||||
break;
|
||||
default:
|
||||
panic("uart_set_clk: invalid clock\n");
|
||||
}
|
||||
|
||||
/* based on the new info, set the baud rate */
|
||||
uart_set_baud_rate(port, uart_status[port].baud);
|
||||
}
|
||||
|
||||
static void uart_set_baud_rate(int port, u_int32_t baud_rate)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
u_int32_t baud_low, actual_baud;
|
||||
int div;
|
||||
u_int32_t clk;
|
||||
|
||||
if (uart_status[port].nclk)
|
||||
clk = clock_get_frequency(CLK_NCLK);
|
||||
else
|
||||
clk = clock_get_frequency(CLK_PCLK);
|
||||
#if UART_CLOCK_SOURCE_OVERRIDE
|
||||
clk = UART_CLOCK_SOURCE_OVERRIDE;
|
||||
#endif
|
||||
if (uart_status[port].sample_rate == 0) {
|
||||
// sample_rate isn't set yet, can't calculate baud.
|
||||
return;
|
||||
}
|
||||
div = clk / (baud_rate * uart_status[port].sample_rate);
|
||||
|
||||
actual_baud = clk / ((div + 0) * uart_status[port].sample_rate);
|
||||
baud_low = clk / ((div + 1) * uart_status[port].sample_rate);
|
||||
|
||||
if ((baud_rate - baud_low) < (actual_baud - baud_rate)) {
|
||||
div++;
|
||||
actual_baud = baud_low;
|
||||
}
|
||||
|
||||
*regs->ubrdiv = (*regs->ubrdiv & ~0xFFFF) | (div - 1);
|
||||
|
||||
printf("uart_set_baud_rate: port %d, baud %d, sample %d, divider %d, actual baud %d\n",
|
||||
port, baud_rate, uart_status[port].sample_rate, div - 1, actual_baud);
|
||||
|
||||
uart_status[port].baud = baud_rate;
|
||||
}
|
||||
|
||||
static void uart_set_flow_control(int port, bool flow)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
|
||||
if (port == 0) {
|
||||
printf("%s: uart 0 does not support flow control\n", __FUNCTION__);
|
||||
return;
|
||||
}
|
||||
|
||||
if (flow) {
|
||||
*regs->umcon = 0x10; // set auto flow control
|
||||
} else {
|
||||
*regs->umcon = 0x01; // assert RTS
|
||||
}
|
||||
uart_status[port].flow_en = flow;
|
||||
}
|
||||
|
||||
static void uart_set_fifo_enable(int port, bool enable)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
|
||||
if (enable) {
|
||||
*regs->ufcon = 0x6; // reset both fifos
|
||||
*regs->ufcon = (0<<6)|(0<<4)|0x1; // enable fifo, tx trigger level 0, rx trigger level 4
|
||||
} else {
|
||||
*regs->ufcon = 0; // disable all fifos
|
||||
}
|
||||
uart_status[port].fifo_en = enable;
|
||||
}
|
||||
|
||||
static void uart_set_mode(int port, enum uart_mode mode)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
int old_mode;
|
||||
|
||||
printf("uart_set_mode: port %d, mode %d\n", port, mode);
|
||||
|
||||
old_mode = uart_status[port].mode;
|
||||
uart_status[port].mode = mode;
|
||||
|
||||
switch (mode) {
|
||||
case MODE_POLL: {
|
||||
// no interrupts in polled mode
|
||||
*regs->ucon &= ~((0xf<<11)|(1<<7));
|
||||
*regs->ucon = (*regs->ucon & ~0xf) | 0x5; // tx/rx polled/int mode
|
||||
break;
|
||||
}
|
||||
case MODE_INT: {
|
||||
// interrupt mode
|
||||
*regs->ucon = (*regs->ucon & ~(0xf<<11)) | ((0xb<<11)|(1<<7)); //enable read/error/timeout and disable write interrupt
|
||||
*regs->ucon = (*regs->ucon & ~0xf) | 0x5; // tx/rx polled/int mode
|
||||
break;
|
||||
}
|
||||
default:
|
||||
panic("uart_set_mode: unsupport modei\n ");
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static void uart_interrupt(void *arg)
|
||||
{
|
||||
/* to-do: the interrupt routine */
|
||||
int port = (int)arg;
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
u_int32_t utr_status;
|
||||
u_int32_t uer_status;
|
||||
|
||||
utr_status = *regs->utrstat;
|
||||
*regs->utrstat = utr_status;
|
||||
uer_status = *regs->uerstat;
|
||||
*regs->uerstat = uer_status;
|
||||
|
||||
if (utr_status & (1 << 6)) { // Error interrupt
|
||||
/* Error, eat up that byte and move on */
|
||||
volatile int hole;
|
||||
hole = *regs->urxh;
|
||||
}
|
||||
|
||||
if (utr_status & (3 << 3)) { // Rx or timeout interrupt
|
||||
CBUFFER *pcb = &uart_status[port].rx_cbuf;
|
||||
if (uart_status[port].fifo_en) {
|
||||
while ((rx_fifo_count(port) > 0) && cb_free_space(pcb)) {
|
||||
cb_putc_unsafe(pcb, *regs->urxh);
|
||||
}
|
||||
} else {
|
||||
if (utr_status & (1 << 0)) {
|
||||
cb_putc_unsafe(pcb, *regs->urxh);
|
||||
}
|
||||
}
|
||||
/* signal reader */
|
||||
event_signal(&uart_status[port].rx_event);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static void uart_dump_config(int port)
|
||||
{
|
||||
if (port >= UARTS_COUNT) return;
|
||||
|
||||
if (port < 0) {
|
||||
for (port = 0; port < UARTS_COUNT; port++) {
|
||||
uart_dump_config(port);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
printf("uart %d config: baud %d sample %d flow %d fifo %d ", port,
|
||||
uart_status[port].baud, uart_status[port].sample_rate,
|
||||
uart_status[port].flow_en, uart_status[port].fifo_en);
|
||||
switch (uart_status[port].mode) {
|
||||
case MODE_POLL:
|
||||
printf("polled ");
|
||||
break;
|
||||
case MODE_INT:
|
||||
printf("interrupt-mode");
|
||||
break;
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
static int uart_debug_reader_task(void *arg)
|
||||
{
|
||||
int port = (int)arg;
|
||||
u_int8_t port_mask = 0;
|
||||
|
||||
switch (port) {
|
||||
#if defined(DEBUG_SERIAL_PORT)
|
||||
case DEBUG_SERIAL_PORT : port_mask = kPowerNVRAMiBootDebugIAPSerial; break;
|
||||
#endif
|
||||
#if defined(DEBUG_SERIAL_PORT2)
|
||||
case DEBUG_SERIAL_PORT2 : port_mask = kPowerNVRAMiBootDebugAltSerial; break;
|
||||
#endif
|
||||
default: break;
|
||||
}
|
||||
|
||||
for(;;) {
|
||||
char c;
|
||||
int len;
|
||||
|
||||
/* use interrupt mode */
|
||||
len = uart_read(port, &c, 1, true);
|
||||
if ((len > 0) && ((DebugUartReady & port_mask) != 0)) {
|
||||
debug_pushchar(c);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int uart_init(void)
|
||||
{
|
||||
int port, oversample = 16;
|
||||
enum uart_clk clock = NCLK;
|
||||
const uart_regs_t *regs;
|
||||
|
||||
#ifdef UART_CLOCK_OVERRIDE
|
||||
clock = UART_CLOCK_OVERRIDE;
|
||||
#endif
|
||||
|
||||
#ifdef UART_OVERSAMPLE_OVERRIDE
|
||||
oversample = UART_OVERSAMPLE_OVERRIDE;
|
||||
#endif
|
||||
|
||||
for (port = 0; port < UARTS_COUNT; port++) {
|
||||
if (!(UARTS_MASK & (1 << port)))
|
||||
continue;
|
||||
|
||||
regs = uregs(port);
|
||||
|
||||
cb_create(&uart_status[port].rx_cbuf, UART_RX_LEN);
|
||||
|
||||
event_init(&uart_status[port].rx_event, EVENT_FLAG_AUTO_UNSIGNAL, false);
|
||||
|
||||
uart_status[port].port = port;
|
||||
uart_status[port].baud = 115200;
|
||||
|
||||
/* make sure the clock is on for this block */
|
||||
clock_gate(regs->clock, true);
|
||||
|
||||
/* put the uarts in a default state */
|
||||
*regs->ulcon = 0x03; /* 81N, not IR */
|
||||
*regs->ucon = 0x05; /*interrupt/polled mode, PCLK source, all ints disabled */
|
||||
|
||||
#if defined(HDQGAUGE_SERIAL_PORT)
|
||||
if (HDQGAUGE_SERIAL_PORT == port) {
|
||||
uart_status[port].baud = 57600;
|
||||
*regs->ulcon = 0x07; /* 82N */
|
||||
}
|
||||
#endif
|
||||
|
||||
uart_set_clk(port, clock);
|
||||
|
||||
/* Set sample rate to 16x to avoid issues with the lower ones*/
|
||||
uart_set_sample_rate(port, oversample);
|
||||
|
||||
uart_set_flow_control(port, UART_FLOWCONTROL_MASK & (1 << port));
|
||||
|
||||
uart_set_fifo_enable(port, true);
|
||||
|
||||
uart_set_mode(port, MODE_POLL);
|
||||
|
||||
/* register the interrupt handler */
|
||||
install_int_handler(regs->irq, &uart_interrupt, (void *)port);
|
||||
unmask_int(regs->irq);
|
||||
}
|
||||
|
||||
#if defined(DEBUG_SERIAL_PORT)
|
||||
if (DEBUG_SERIAL_PORT != 0)
|
||||
uart_set_flow_control(DEBUG_SERIAL_PORT, false);
|
||||
/* the fifo trigger level for Rx can not be zero -- 4 bytes is the lowest, so no fifo */
|
||||
uart_set_fifo_enable(DEBUG_SERIAL_PORT, false);
|
||||
uart_set_mode(DEBUG_SERIAL_PORT, MODE_INT);
|
||||
task_start(task_create("uart reader", uart_debug_reader_task, (void *)DEBUG_SERIAL_PORT, 0x200));
|
||||
#endif
|
||||
#if defined(DEBUG_SERIAL_PORT2)
|
||||
if (DEBUG_SERIAL_PORT2 != 0)
|
||||
uart_set_flow_control(DEBUG_SERIAL_PORT2, false);
|
||||
/* the fifo trigger level for Rx can not be zero -- 4 bytes is the lowest, so no fifo */
|
||||
uart_set_fifo_enable(DEBUG_SERIAL_PORT2, false);
|
||||
uart_set_mode(DEBUG_SERIAL_PORT2, MODE_INT);
|
||||
task_start(task_create("uart reader2", uart_debug_reader_task, (void *)DEBUG_SERIAL_PORT2, 0x200));
|
||||
#endif
|
||||
|
||||
#if DEBUG_UART_ENABLE_DEFAULT
|
||||
DebugUartReady |= kPowerNVRAMiBootDebugIAPSerial | kPowerNVRAMiBootDebugAltSerial;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int uart_hw_init_extended(u_int32_t port, u_int32_t baudrate, u_int32_t databits, enum uart_parity parity, u_int32_t stopbits)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
u_int32_t ulcon = 0;
|
||||
|
||||
uart_status[port].baud = baudrate;
|
||||
|
||||
switch (databits) {
|
||||
case 5: ulcon |= (0 << 0); break;
|
||||
case 6: ulcon |= (1 << 0); break;
|
||||
case 7: ulcon |= (2 << 0); break;
|
||||
case 8: ulcon |= (3 << 0); break;
|
||||
default: return -1;
|
||||
}
|
||||
|
||||
switch (parity) {
|
||||
case PARITY_NONE: ulcon |= (0 << 3); break;
|
||||
case PARITY_ODD: ulcon |= (4 << 3); break;
|
||||
case PARITY_EVEN: ulcon |= (5 << 3); break;
|
||||
default: return -1;
|
||||
}
|
||||
|
||||
switch(stopbits) {
|
||||
case 1: ulcon |= (0 << 2); break;
|
||||
case 2: ulcon |= (1 << 2); break;
|
||||
default: return -1;
|
||||
}
|
||||
|
||||
uart_set_fifo_enable(port, false);
|
||||
|
||||
*regs->ulcon = ulcon;
|
||||
|
||||
uart_set_baud_rate(port, uart_status[port].baud);
|
||||
|
||||
uart_set_fifo_enable(port, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int uart_hw_set_rx_buf(u_int32_t port, bool interrupt, size_t buffer_len)
|
||||
{
|
||||
/* Reconfigure a port for interrupt/polled and explicit buffer len */
|
||||
struct uart_status *st = &uart_status[port];
|
||||
*uregs(port)->ucon &= ~(1<<12); // disable interrupt
|
||||
if (cb_initialized(&st->rx_cbuf))
|
||||
cb_free(&st->rx_cbuf);
|
||||
cb_create(&st->rx_cbuf, buffer_len);
|
||||
uart_set_mode(port, interrupt ? MODE_INT : MODE_POLL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uart_write(int port, const void *_buf, size_t len, bool wait)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
const u_int8_t *buf = (const u_int8_t *)_buf;
|
||||
u_int32_t i;
|
||||
switch (uart_status[port].mode) {
|
||||
case MODE_INT:
|
||||
case MODE_POLL: {
|
||||
for (i=0; i < len; i++) {
|
||||
if (uart_status[port].fifo_en) {
|
||||
while ((*regs->ufstat) & 0x200) {
|
||||
}
|
||||
} else {
|
||||
while (!((*regs->utrstat) & 0x04))
|
||||
;
|
||||
}
|
||||
if (uart_status[port].flow_en) {
|
||||
while (((*regs->utrstat) & 4) == 0); // Wait Transmitter Empty
|
||||
while (((*regs->umstat) & 1) == 0); // Wait CTS Asserted
|
||||
}
|
||||
*regs->utxh = buf[i];
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
panic("uart_write: unhandled mode\n");
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static int tx_fifo_count(int port)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
int fifo_count = *regs->ufstat & ((1<<9)|(0xf<<4));
|
||||
fifo_count = ((fifo_count >> 4) & 0xf) | (fifo_count >> 5);
|
||||
return fifo_count;
|
||||
}
|
||||
|
||||
static int rx_fifo_count(int port)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
int fifo_count = *regs->ufstat & ((1<<8)|0xf);
|
||||
fifo_count = (fifo_count & 0xf) | (fifo_count >> 4);
|
||||
return fifo_count;
|
||||
}
|
||||
|
||||
static void drain_rx_fifo(int port)
|
||||
{
|
||||
volatile char hole;
|
||||
|
||||
if (uart_status[port].fifo_en) {
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
|
||||
while (rx_fifo_count(port) > 0) {
|
||||
hole = *regs->urxh;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int uart_read(int port, void *_buf, size_t len, bool wait)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
u_int8_t *buf = (u_int8_t *)_buf;
|
||||
u_int32_t i = 0;
|
||||
|
||||
switch (uart_status[port].mode) {
|
||||
case MODE_POLL: {
|
||||
volatile int hole;
|
||||
for (i=0; i < len; i++) {
|
||||
retry_polled_read:
|
||||
if (uart_status[port].fifo_en) {
|
||||
while (rx_fifo_count(port) == 0) {
|
||||
if (!wait)
|
||||
return i;
|
||||
task_yield();
|
||||
}
|
||||
} else {
|
||||
while (!((*regs->utrstat) & 0x01)) {
|
||||
if (!wait)
|
||||
return i;
|
||||
task_yield();
|
||||
}
|
||||
}
|
||||
if (*regs->uerstat) {
|
||||
/* some sort of error queued up, eat this character and move on */
|
||||
hole = *regs->urxh;
|
||||
goto retry_polled_read;
|
||||
}
|
||||
buf[i] = *regs->urxh;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case MODE_INT: {
|
||||
/* in interrupt mode, always wait */
|
||||
CBUFFER *pcb = &uart_status[port].rx_cbuf;
|
||||
retry_intr_read:
|
||||
if (wait && (!cb_readable_size(pcb)))
|
||||
event_wait(&uart_status[port].rx_event);
|
||||
|
||||
/* disable rx interrupt */
|
||||
*regs->ucon &= ~(1<<12);
|
||||
|
||||
i += cb_read_unsafe(pcb, buf + i, len - i);
|
||||
|
||||
/* enable rx interrupt */
|
||||
*regs->ucon |= (1<<12);
|
||||
|
||||
if ((i < len) && wait)
|
||||
goto retry_intr_read;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
panic("uart_read: unhandled mode\n");
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static int uart_rx_complete(int port)
|
||||
{
|
||||
return uart_status[port].rx_complete;
|
||||
}
|
||||
|
||||
int uart_putc(int port, char c)
|
||||
{
|
||||
return uart_write(port, &c, 1, true);
|
||||
}
|
||||
|
||||
int uart_puts(int port, const char *s)
|
||||
{
|
||||
int len = strlen(s);
|
||||
uart_write(port, s, len, true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int uart_getc(int port, bool wait) /* returns -1 if no data available */
|
||||
{
|
||||
char c;
|
||||
int len;
|
||||
|
||||
len = uart_read(port, &c, 1, wait);
|
||||
if (len == 0)
|
||||
return -1;
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
int uart_send_break(int port, bool enable)
|
||||
{
|
||||
const uart_regs_t *regs = uregs(port);
|
||||
if (enable)
|
||||
*regs->ucon |= (1 << 4);
|
||||
else
|
||||
*regs->ucon &= ~(1 << 4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,134 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Computer, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_UART_H
|
||||
#define __SAMSUNG_UART_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rULCON0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x00))
|
||||
#define rUCON0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x04))
|
||||
#define rUFCON0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x08))
|
||||
#define rUMCON0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x0C))
|
||||
#define rUTRSTAT0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x10))
|
||||
#define rUERSTAT0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x14))
|
||||
#define rUFSTAT0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x18))
|
||||
#define rUMSTAT0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x1C))
|
||||
#define rUBRDIV0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x28))
|
||||
#define rUABRCNT0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x2C))
|
||||
#define rUTXH0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x20))
|
||||
#define rURXH0 (*(volatile u_int32_t *)(UART0_BASE_ADDR + 0x24))
|
||||
|
||||
#define rULCON1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x00))
|
||||
#define rUCON1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x04))
|
||||
#define rUFCON1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x08))
|
||||
#define rUMCON1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x0C))
|
||||
#define rUTRSTAT1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x10))
|
||||
#define rUERSTAT1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x14))
|
||||
#define rUFSTAT1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x18))
|
||||
#define rUMSTAT1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x1C))
|
||||
#define rUBRDIV1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x28))
|
||||
#define rUABRCNT1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x2C))
|
||||
#define rUTXH1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x20))
|
||||
#define rURXH1 (*(volatile u_int32_t *)(UART1_BASE_ADDR + 0x24))
|
||||
|
||||
#define rULCON2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x00))
|
||||
#define rUCON2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x04))
|
||||
#define rUFCON2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x08))
|
||||
#define rUMCON2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x0C))
|
||||
#define rUTRSTAT2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x10))
|
||||
#define rUERSTAT2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x14))
|
||||
#define rUFSTAT2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x18))
|
||||
#define rUMSTAT2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x1C))
|
||||
#define rUBRDIV2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x28))
|
||||
#define rUABRCNT2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x2C))
|
||||
#define rUTXH2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x20))
|
||||
#define rURXH2 (*(volatile u_int32_t *)(UART2_BASE_ADDR + 0x24))
|
||||
|
||||
#define rULCON3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x00))
|
||||
#define rUCON3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x04))
|
||||
#define rUFCON3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x08))
|
||||
#define rUMCON3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x0C))
|
||||
#define rUTRSTAT3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x10))
|
||||
#define rUERSTAT3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x14))
|
||||
#define rUFSTAT3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x18))
|
||||
#define rUMSTAT3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x1C))
|
||||
#define rUBRDIV3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x28))
|
||||
#define rUABRCNT3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x2C))
|
||||
#define rUTXH3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x20))
|
||||
#define rURXH3 (*(volatile u_int32_t *)(UART3_BASE_ADDR + 0x24))
|
||||
|
||||
#define rULCON4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x00))
|
||||
#define rUCON4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x04))
|
||||
#define rUFCON4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x08))
|
||||
#define rUMCON4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x0C))
|
||||
#define rUTRSTAT4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x10))
|
||||
#define rUERSTAT4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x14))
|
||||
#define rUFSTAT4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x18))
|
||||
#define rUMSTAT4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x1C))
|
||||
#define rUBRDIV4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x28))
|
||||
#define rUABRCNT4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x2C))
|
||||
#define rUTXH4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x20))
|
||||
#define rURXH4 (*(volatile u_int32_t *)(UART4_BASE_ADDR + 0x24))
|
||||
|
||||
#define rULCON5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x00))
|
||||
#define rUCON5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x04))
|
||||
#define rUFCON5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x08))
|
||||
#define rUMCON5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x0C))
|
||||
#define rUTRSTAT5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x10))
|
||||
#define rUERSTAT5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x14))
|
||||
#define rUFSTAT5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x18))
|
||||
#define rUMSTAT5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x1C))
|
||||
#define rUBRDIV5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x28))
|
||||
#define rUABRCNT5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x2C))
|
||||
#define rUTXH5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x20))
|
||||
#define rURXH5 (*(volatile u_int32_t *)(UART5_BASE_ADDR + 0x24))
|
||||
|
||||
#define rULCON6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x00))
|
||||
#define rUCON6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x04))
|
||||
#define rUFCON6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x08))
|
||||
#define rUMCON6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x0C))
|
||||
#define rUTRSTAT6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x10))
|
||||
#define rUERSTAT6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x14))
|
||||
#define rUFSTAT6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x18))
|
||||
#define rUMSTAT6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x1C))
|
||||
#define rUBRDIV6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x28))
|
||||
#define rUABRCNT6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x2C))
|
||||
#define rUTXH6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x20))
|
||||
#define rURXH6 (*(volatile u_int32_t *)(UART6_BASE_ADDR + 0x24))
|
||||
|
||||
#define rULCON7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x00))
|
||||
#define rUCON7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x04))
|
||||
#define rUFCON7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x08))
|
||||
#define rUMCON7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x0C))
|
||||
#define rUTRSTAT7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x10))
|
||||
#define rUERSTAT7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x14))
|
||||
#define rUFSTAT7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x18))
|
||||
#define rUMSTAT7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x1C))
|
||||
#define rUBRDIV7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x28))
|
||||
#define rUABRCNT7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x2C))
|
||||
#define rUTXH7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x20))
|
||||
#define rURXH7 (*(volatile u_int32_t *)(UART7_BASE_ADDR + 0x24))
|
||||
|
||||
#define rULCON8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x00))
|
||||
#define rUCON8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x04))
|
||||
#define rUFCON8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x08))
|
||||
#define rUMCON8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x0C))
|
||||
#define rUTRSTAT8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x10))
|
||||
#define rUERSTAT8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x14))
|
||||
#define rUFSTAT8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x18))
|
||||
#define rUMSTAT8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x1C))
|
||||
#define rUBRDIV8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x28))
|
||||
#define rUABRCNT8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x2C))
|
||||
#define rUTXH8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x20))
|
||||
#define rURXH8 (*(volatile u_int32_t *)(UART8_BASE_ADDR + 0x24))
|
||||
|
||||
#endif /* __SAMSUNG_UART_H */
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Computer, Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Computer, Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_USBPHY=1
|
||||
|
||||
ALL_OBJS += $(LOCAL_DIR)/usbphy.o
|
||||
@@ -0,0 +1,304 @@
|
||||
/*
|
||||
* Copyright (C) 2007-2009 Apple Inc. All rights reserved.
|
||||
* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#include <debug.h>
|
||||
#include <platform.h>
|
||||
#include <platform/clocks.h>
|
||||
#include <platform/power.h>
|
||||
#include <platform/soc/hwclocks.h>
|
||||
#include <platform/usbconfig.h>
|
||||
#include <sys.h>
|
||||
|
||||
#include "usbphy.h"
|
||||
|
||||
static bool usb_phy_powered = false;
|
||||
|
||||
// <rdar://problem/10320827> Add support for multiple USB OTG controllers to iBoot
|
||||
// <rdar://problem/10304507> G1 USBBPHY USB OTG2 bit assignments are totally inconsistent
|
||||
#if WITH_CONJOINED_USB_PHYS
|
||||
|
||||
#if USBPHY_VERSION > 2
|
||||
#error "Conjoined USB PHYs not compatible with PHY version > 2"
|
||||
#endif
|
||||
|
||||
#define SELECTED_PHY (1)
|
||||
|
||||
#define SET_REG(reg, value) set_reg(reg, SELECTED_PHY, reg##_SHIFT, (value))
|
||||
#define SET_REG_BITS(reg, value, mask) set_reg_bits(reg, SELECTED_PHY, reg##_SHIFT, (value), (mask))
|
||||
#define GET_REG(reg) get_reg(reg, SELECTED_PHY, reg##_SHIFT)
|
||||
|
||||
static void set_reg(volatile u_int32_t *reg, int index, int shift, u_int32_t value)
|
||||
{
|
||||
u_int32_t mask = ((1 << shift) - 1) << (shift * index);
|
||||
*reg = (*reg & ~mask) | (value << (shift * index));
|
||||
}
|
||||
|
||||
static void set_reg_bits(volatile u_int32_t *reg, int index, int shift, u_int32_t value, u_int32_t mask)
|
||||
{
|
||||
mask = mask << (shift * index);
|
||||
*reg = (*reg & ~mask) | (value << (shift * index));
|
||||
}
|
||||
|
||||
static u_int32_t get_reg(volatile u_int32_t *reg, int index, int shift)
|
||||
{
|
||||
return (*reg >> shift) & ((1 << shift) - 1);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define SET_REG(reg, value) *(reg) = (value)
|
||||
#define SET_REG_BITS(reg, value, mask) *(reg) = (*(reg) & ~(mask)) | (value)
|
||||
#define GET_REG(reg) *(reg)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static void gate_clocks(bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
#if USBPHY_VERSION > 2
|
||||
clock_gate(CLK_UPERF, true);
|
||||
#endif
|
||||
|
||||
clock_gate(CLK_USBOTG, true);
|
||||
clock_gate(CLK_USBPHY, true);
|
||||
} else {
|
||||
clock_gate(CLK_USBOTG, false);
|
||||
clock_gate(CLK_USBPHY, false);
|
||||
|
||||
#if USBPHY_VERSION > 2
|
||||
clock_gate(CLK_UPERF, false);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// FUNCTION: usbphy_power_up
|
||||
//
|
||||
// DESCRIPTION: Does initial powering up to bring up the PHY
|
||||
//
|
||||
// RETURN: None
|
||||
//
|
||||
// NOTES: This should be one of the first things done upon startup.
|
||||
//---------------------------------------------------------------------------
|
||||
void usbphy_power_up(void)
|
||||
{
|
||||
u_int32_t clk_sel = 0;
|
||||
|
||||
if (usb_phy_powered) return;
|
||||
|
||||
platform_power_set_gate(PWRBIT_USB, true);
|
||||
spin(10*1000);
|
||||
|
||||
gate_clocks(true);
|
||||
|
||||
// Clear the StopPclk & GateHclk bits in the power and clock gating register
|
||||
*USB_PCGCCTL &= ~(PCGCCTL_StopPclk | PCGCCTL_GateHclk);
|
||||
|
||||
spin(100);
|
||||
|
||||
#if USBPHY_VERSION > 1
|
||||
*USB_USBHOSTSET = (1 << 9); // enable hsic, this will cause STB and DAT to stay low
|
||||
#endif
|
||||
|
||||
switch (clock_get_frequency(CLK_USBPHYCLK)) {
|
||||
case 12000000UL : clk_sel = 0; break;
|
||||
case 24000000UL : clk_sel = 1; break;
|
||||
case 48000000UL : clk_sel = 2; break;
|
||||
default : clk_sel = 3; break;
|
||||
}
|
||||
|
||||
#if USBPHY_VERSION > 0
|
||||
SET_REG(USB_PHYPWR, (0UL<<4) | // powerup analog block
|
||||
(0UL<<3) | // powerup OTG block
|
||||
(USBPHY_CLK_TYPE << 1) | // select the reference clock
|
||||
(0UL<<0)); // disable suspend signal for power save
|
||||
|
||||
SET_REG(USB_UVLDCON, (1 << 2)); // Set vbus_vld_ext_sel
|
||||
|
||||
#else
|
||||
*USB_PHYPWR = (0UL<<4) | // powerup analog block
|
||||
(0UL<<3) | // powerup XO block
|
||||
(USBPHY_CLK_TYPE << 2) | // select the reference for XO block
|
||||
(0UL<<1) | // powerup PLL
|
||||
(0UL<<0); // disable suspend signal for power save
|
||||
|
||||
/* Correct the field assinment for version 0 */
|
||||
clk_sel ^= 1;
|
||||
#endif
|
||||
|
||||
#ifdef USBPHY_UOTGTUNE1
|
||||
SET_REG(USB_UOTGTUNE1, USBPHY_UOTGTUNE1);
|
||||
#endif
|
||||
#ifdef USBPHY_UOTGTUNE2
|
||||
SET_REG(USB_UOTGTUNE2, USBPHY_UOTGTUNE2);
|
||||
#endif
|
||||
|
||||
spin(10);
|
||||
|
||||
#if WITH_CONJOINED_USB_PHYS
|
||||
// <rdar://problem/10491915> G1: Implement G1-specific USB PHY settings
|
||||
*USB_URSV |= (1 << 4);
|
||||
#endif
|
||||
|
||||
SET_REG_BITS(USB_PHYCON, clk_sel, 0x3);
|
||||
|
||||
// reset the PHY
|
||||
SET_REG_BITS(USB_URSTCON, 1, 1);
|
||||
spin(20); // need to assert for at least 10us
|
||||
SET_REG_BITS(USB_URSTCON, 0, 1);
|
||||
spin(1000); // need to wait for at least 805us
|
||||
|
||||
usb_phy_powered = true;
|
||||
}
|
||||
|
||||
void usbphy_enable_pullup(void)
|
||||
{
|
||||
if (!usb_phy_powered)
|
||||
return;
|
||||
|
||||
// Enable D+ PU
|
||||
SET_REG_BITS(USB_UVLDCON, (1 << 1), (1 << 1)); // Set vbus_vld_ext
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// FUNCTION: usbphy_power_down
|
||||
//
|
||||
// DESCRIPTION: Powers down the PHY upon USB shutdown
|
||||
//
|
||||
// RETURN: None
|
||||
//
|
||||
// NOTES: This should be one of the last things done upon shutdown.
|
||||
//---------------------------------------------------------------------------
|
||||
void usbphy_power_down(void)
|
||||
{
|
||||
platform_power_set_gate(PWRBIT_USB, true);
|
||||
gate_clocks(true);
|
||||
|
||||
// set bits 0-4 to 1 to power down the PHY
|
||||
SET_REG(USB_PHYPWR, (1UL<<5)-1);
|
||||
|
||||
#if USBPHY_VERSION == 0
|
||||
// assert S/W Reset for PHY_CLK and HCLK Domains
|
||||
SET_REG_BITS(USB_URSTCON, (1<<2)|(1<<1), (1<<2)|(1<<1));
|
||||
#endif
|
||||
|
||||
// assert S/W Reset for PHY
|
||||
SET_REG_BITS(USB_URSTCON, (1<<0), (1<<0));
|
||||
spin(1000);
|
||||
|
||||
#if USBPHY_VERSION > 0
|
||||
*USB_UVLDCON &= ~(1 << 1); // Clear vbus_vld_ext
|
||||
SET_REG_BITS(USB_UVLDCON, 0, (1<<1));
|
||||
#endif
|
||||
|
||||
gate_clocks(false);
|
||||
platform_power_set_gate(PWRBIT_USB, false);
|
||||
|
||||
usb_phy_powered = false;
|
||||
}
|
||||
|
||||
bool usbphy_is_cable_connected(void)
|
||||
{
|
||||
bool connected;
|
||||
|
||||
if (!usb_phy_powered) {
|
||||
#if USBPHY_VERSION > 2
|
||||
clock_gate(CLK_UPERF, true);
|
||||
#endif
|
||||
clock_gate(CLK_USBPHY, true);
|
||||
}
|
||||
|
||||
connected = (GET_REG(USB_UCONDET) & 1) != 0;
|
||||
|
||||
if (!usb_phy_powered) {
|
||||
#if USBPHY_VERSION > 2
|
||||
clock_gate(CLK_UPERF, false);
|
||||
#endif
|
||||
clock_gate(CLK_USBPHY, false);
|
||||
}
|
||||
|
||||
return connected;
|
||||
}
|
||||
|
||||
bool usbphy_set_dpdm_monitor(int select)
|
||||
{
|
||||
u_int32_t bits;
|
||||
|
||||
switch (select) {
|
||||
case kUSB_DP:
|
||||
bits = 1 << 1;
|
||||
break;
|
||||
case kUSB_DM:
|
||||
bits = 2 << 1;
|
||||
break;
|
||||
case kUSB_NONE:
|
||||
bits = 0 << 1;
|
||||
break;
|
||||
#if USBPHY_VERSION >= 4
|
||||
case kUSB_DCD:
|
||||
bits = (1 << 14) | (1 << 13) | (1 << 10) | (1 << 9) | (1 << 1);
|
||||
break;
|
||||
case kUSB_CP1:
|
||||
bits = (1 << 12) | (1 << 11) | (1 << 10) | (1 << 9) | (2 << 1);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return false;
|
||||
};
|
||||
|
||||
if (!usb_phy_powered) {
|
||||
#if USBPHY_VERSION > 2
|
||||
clock_gate(CLK_UPERF, true);
|
||||
#endif
|
||||
clock_gate(CLK_USBPHY, true);
|
||||
}
|
||||
|
||||
#if USBPHY_VERSION >= 4
|
||||
*USB_UPADCON = (*USB_UPADCON & ((0x3f << 3) | (1 << 0))) | bits;
|
||||
#else
|
||||
SET_REG_BITS(USB_UPADCON, bits, 3 << 1);
|
||||
#endif
|
||||
|
||||
if (!usb_phy_powered) {
|
||||
#if USBPHY_VERSION > 2
|
||||
clock_gate(CLK_UPERF, false);
|
||||
#endif
|
||||
clock_gate(CLK_USBPHY, false);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
void usbphy_update_device_tree(DTNode *node)
|
||||
{
|
||||
u_int32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
u_int32_t phy_tuning2_val;
|
||||
|
||||
phy_tuning2_val = 0;
|
||||
|
||||
#ifdef USBPHY_UOTGTUNE2
|
||||
phy_tuning2_val = USBPHY_UOTGTUNE2;
|
||||
#endif
|
||||
|
||||
// Fill in the phy-tuning-val property
|
||||
propName = "phy-tuning-val";
|
||||
if (FindProperty(node, &propName, &propData, &propSize)) {
|
||||
if (propSize >= sizeof(phy_tuning2_val)) {
|
||||
*(u_int32_t *)propData = phy_tuning2_val;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Computer, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_USBPHY_H
|
||||
#define __SAMSUNG_USBPHY_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
#include <sys/types.h>
|
||||
#include <drivers/usbphy.h>
|
||||
|
||||
// HW-OTG control registers
|
||||
#define USB_PCGCCTL ((volatile u_int32_t *)(USBOTG_BASE_ADDR + 0x0E00))
|
||||
|
||||
#define PCGCCTL_PhySuspended (1UL << 4)
|
||||
#define PCGCCTL_RstPdwnModule (1UL << 3)
|
||||
#define PCGCCTL_PwrClmp (1UL << 2)
|
||||
#define PCGCCTL_GateHclk (1UL << 1)
|
||||
#define PCGCCTL_StopPclk (1UL << 0)
|
||||
|
||||
// HS-OTG Phy control registers
|
||||
#define USB_PHYPWR ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0000))
|
||||
#define USB_PHYCON ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0004))
|
||||
#define USB_URSTCON ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0008))
|
||||
#define USB_UVLDCON ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x001C))
|
||||
#define USB_UCONDET ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0028))
|
||||
#define USB_URESCON ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0034))
|
||||
#define USB_UOTGTUNE1 ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0040))
|
||||
#define USB_UOTGTUNE2 ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0044))
|
||||
#define USB_UPADCON ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0048))
|
||||
#define USB_USBHOSTSET ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0060))
|
||||
#define USB_URSV ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0100))
|
||||
|
||||
// <rdar://problem/10320827> Add support for multiple USB OTG controllers to iBoot
|
||||
// <rdar://problem/10304507> G1 USBBPHY USB OTG2 bit assignments are totally inconsistent
|
||||
#define USB_PHYPWR_SHIFT 5
|
||||
#define USB_PHYCON_SHIFT 5
|
||||
#define USB_URSTCON_SHIFT 5
|
||||
#define USB_UVLDCON_SHIFT 9
|
||||
#define USB_UCONDET_SHIFT 10
|
||||
#define USB_UOTGTUNE1_SHIFT 11
|
||||
#define USB_UOTGTUNE2_SHIFT 13
|
||||
#define USB_UPADCON_SHIFT 3
|
||||
|
||||
#endif /* ! __SAMSUNG_USBPHY_H */
|
||||
Reference in new issue
Block a user