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/*
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* Copyright (C) 2009-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/display.h>
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#include <lib/paint.h>
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#include <platform/soc/hwclocks.h>
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#include <drivers/dither.h>
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#include "clcd_regs.h"
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#ifndef CLCD_VERSION
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#error CLCD_VERSION undefined
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#endif
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static void clcd_load_gamma_table(u_int32_t lut_id, u_int32_t *lut_data, uint32_t coeff);
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void clcd_enable_clocks(bool enable)
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{
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int device;
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if (CLCD_DISPLAYPIPE_BASE_ADDR == DISP0_BASE_ADDR)
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device = CLK_DISP0;
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else
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device = CLK_DISP1;
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// Enable/disable displaypipe and clcd clocks
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if (enable) {
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clock_gate(device, true);
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clock_gate(CLK_CLCD, true);
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}
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else {
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clock_gate(CLK_CLCD, false);
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clock_gate(device, false);
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}
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}
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void clcd_init(struct display_timing *timing)
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{
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rCLCD_STATUS = (1 << 8); // Reset CLCD
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while (rCLCD_STATUS & (1 << 8)); // Wait for reset complete...
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spin(1); // ... and wait some more: <rdar://problem/6090842>
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// Enable sync enable
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rCLCD_STATUS = (1 << 2);
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// Bypass and clock gate MIE
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rCLCD_CFG = (1 << 1) | (1 << 0);
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#if DITHER_VERSION == 1
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rCLCD_DITH_CFG = (1 << 31) | (1 << 0);
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// Set dithering constants
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rCLCD_DITH_CONST = (2 << 16) | (4 << 8) | (8 << 0);
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if (timing->display_depth <= 18) {
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#if CLCD_DITHER_BASE_ADDR
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rCLCD_DITHER_METHOD = (4 << 4) | (2 << 0);
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rCLCD_DITHER_ENABLE = 1;
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#else
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rCLCD_DITH_CFG |= (1 << 24) | (1 << 20) | (1 << 16);
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#endif
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}
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#endif
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#if DITHER_VERSION == 2
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//Need to force the bypass dithering in the clcd block
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rCLCD_DITH_CFG = (1 << 31) | (1 << 29) | (1 << 0);
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rCLCD_DITH_CONST = 0;
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dither_init(timing->display_depth);
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dither_set_enable(true);
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#endif
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rCLCD_OTF_CON1 = 0;
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rCLCD_OTF_CON2 = (timing->neg_vclk << 3) | (timing->neg_hsync << 2) | (timing->neg_vsync << 1) | (timing->neg_vden << 0);
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rCLCD_OTF_TCON1 = (CLCD_OTF_TCON1_VSPP |
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CLCD_OTF_TCON1_VBPD(timing->v_back_porch) |
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CLCD_OTF_TCON1_VFPD(timing->v_front_porch) |
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CLCD_OTF_TCON1_VSPW(timing->v_pulse_width));
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#if defined(TARGET_CLCD_VSPP) && (TARGET_CLCD_VSPP == 0)
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rCLCD_OTF_TCON1 &= ~CLCD_OTF_TCON1_VSPP;
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#endif
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rCLCD_OTF_TCON2 = (CLCD_OTF_TCON2_HBPD(timing->h_back_porch) |
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CLCD_OTF_TCON2_HFPD(timing->h_front_porch) |
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CLCD_OTF_TCON2_HSPW(timing->h_pulse_width));
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rCLCD_OTF_TCON3 = (CLCD_OTF_TCON3_HOZVAL(timing->h_active) |
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CLCD_OTF_TCON3_LINEVAL(timing->v_active));
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}
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bool clcd_get_enable_timing_generator(void)
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{
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return ((rCLCD_OTF_CON1 & 1) == 1);
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}
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void clcd_enable_timing_generator(bool enable)
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{
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if (enable) {
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rCLCD_OTF_CON1 |= 1; // Turn OTF on
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}
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else {
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rCLCD_OTF_CON1 &= ~1; // Turn off OTF
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while ((rCLCD_OTF_CON1 & (1 << 1)) == 0); // Wait for OTF off
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}
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}
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void clcd_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl)
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{
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RELEASE_ASSERT(red_lut != NULL);
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RELEASE_ASSERT(green_lut != NULL);
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RELEASE_ASSERT(blue_lut != NULL);
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RELEASE_ASSERT(wpcl != NULL);
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// Load the Gamma Correction Table
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clcd_load_gamma_table(CLCD_GM_COR_RED, red_lut, wpcl->red);
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clcd_load_gamma_table(CLCD_GM_COR_GREEN, green_lut, wpcl->green);
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clcd_load_gamma_table(CLCD_GM_COR_BLUE, blue_lut, wpcl->blue);
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#if CLCD_VERSION >= 1
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// Swap to the new Gamma Correction Table
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rCLCD_GM_CON = CLCD_GM_CON_GM_CO_TBL_UPDATED;
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// Wait for the swap to complete
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while ((rCLCD_GM_CON & CLCD_GM_CON_GM_CO_TBL_UPDATED) != 0);
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// Load the Alternate Gamma Correction Table
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clcd_load_gamma_table(CLCD_GM_COR_RED, red_lut, wpcl->red);
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clcd_load_gamma_table(CLCD_GM_COR_GREEN, green_lut, wpcl->green);
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clcd_load_gamma_table(CLCD_GM_COR_BLUE, blue_lut, wpcl->blue);
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#endif
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// Turn on Gamma Correction
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rCLCD_GM_CON = CLCD_GM_CON_GM_CO_ENABLE;
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}
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static void clcd_load_gamma_table(u_int32_t lut_id, u_int32_t *lut_data, uint32_t coeff)
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{
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u_int32_t cnt;
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u_int32_t lut_size = (lut_id == CLCD_GM_ENC) ? 225 : 256;
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u_int32_t lut_value, lut_value2;
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rCLCD_GM_TBL_ACC_CON = (1 << 16) | (lut_id << 12) | (0 << 0);
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for (cnt = 0; cnt < lut_size; cnt++) {
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lut_value = lut_data[cnt];
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switch (lut_id) {
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case CLCD_GM_DEC_RED :
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case CLCD_GM_DEC_GREEN :
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case CLCD_GM_DEC_BLUE :
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break;
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case CLCD_GM_COR_RED :
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case CLCD_GM_COR_GREEN :
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case CLCD_GM_COR_BLUE :
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lut_value2 = (lut_data[cnt + 1] * coeff) >> WpCl_Quotation_Denominator;
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lut_value = (lut_value * coeff) >> WpCl_Quotation_Denominator;
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lut_value = ((lut_value << 10) & 0x000FFC00) | (lut_value2 & 0x000003FF);
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break;
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case CLCD_GM_ENC :
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break;
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}
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rCLCD_GM_TBL_WDATA = (1 << 31) | lut_value;
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}
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rCLCD_GM_TBL_ACC_CON = 0;
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}
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@@ -0,0 +1,74 @@
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/*
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* Copyright (C) 2009-2012 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __SAMSUNG_CLCD_REGS_H
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#define __SAMSUNG_CLCD_REGS_H
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#include <platform/soc/hwregbase.h>
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#define rCLCD_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0000))
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#define rCLCD_CFG (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0004))
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#define rCLCD_INT_EN (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0008))
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#define rCLCD_INT_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x000C))
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#define rCLCD_VER (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0010))
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#define rCLCD_DITH_CFG (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0014))
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#define rCLCD_DITH_CONST (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0018))
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#define rCLCD_DPHSYNC_CTRL (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0020))
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#define rCLCD_DPVSYNC_CTRL (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0024))
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#define rCLCD_GM_CON (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x002C))
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#define CLCD_GM_CON_GM_CO_ENABLE (1 << 0)
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#define CLCD_GM_CON_GM_CO_TBL_UPDATED (1 << 6)
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#define rCLCD_GM_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0030))
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#define rCLCD_GM_TBL_ACC_CON (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0034))
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#define CLCD_GM_OFF (0)
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#define CLCD_GM_DEC_RED (1)
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#define CLCD_GM_DEC_GREEN (2)
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#define CLCD_GM_DEC_BLUE (3)
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#define CLCD_GM_COR_RED (4)
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#define CLCD_GM_COR_GREEN (5)
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#define CLCD_GM_COR_BLUE (6)
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#define CLCD_GM_ENC (7)
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#define rCLCD_GM_TBL_WDATA (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0038))
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#define rCLCD_GM_TBL_RDATA (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x003C))
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#define rCLCD_OTF_CON1 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0050))
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#define rCLCD_OTF_CON2 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0054))
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#define rCLCD_OTF_TCON1 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0058))
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#if (DISP_VERSION < 3)
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#define CLCD_OTF_TCON1_VSPP (1 << 24)
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#define CLCD_OTF_TCON1_VBPD(_l) (((_l)-1) << 16)
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#define CLCD_OTF_TCON1_VFPD(_l) (((_l)-1) << 8)
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#define CLCD_OTF_TCON1_VSPW(_l) (((_l)-1) << 0)
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#else
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#define CLCD_OTF_TCON1_VSPP (1 << 30)
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#define CLCD_OTF_TCON1_VBPD(_l) (((_l)-1) << 20)
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#define CLCD_OTF_TCON1_VFPD(_l) (((_l)-1) << 10)
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#define CLCD_OTF_TCON1_VSPW(_l) (((_l)-1) << 0)
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#endif
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#define rCLCD_OTF_TCON2 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x005C))
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#if (DISP_VERSION < 4)
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#define CLCD_OTF_TCON2_HBPD(_p) (((_p)-1) << 16)
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#define CLCD_OTF_TCON2_HFPD(_p) (((_p)-1) << 8)
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#define CLCD_OTF_TCON2_HSPW(_p) (((_p)-1) << 0)
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#else
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#define CLCD_OTF_TCON2_HBPD(_p) (((_p)-1) << 20)
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#define CLCD_OTF_TCON2_HFPD(_p) (((_p)-1) << 10)
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#define CLCD_OTF_TCON2_HSPW(_p) (((_p)-1) << 0)
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#endif
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#define rCLCD_OTF_TCON3 (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0060))
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#define CLCD_OTF_TCON3_HOZVAL(_p) (((_p)-1) << 16)
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#define CLCD_OTF_TCON3_LINEVAL(_p) (((_p)-1) << 0)
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#define rCLCD_OTF_INT_EN (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0064))
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#define rCLCD_OTF_INT_STATUS (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0068))
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#define rCLCD_MIE_SAT_CON (*(volatile u_int32_t *)(CLCD_BASE_ADDR + 0x0074))
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#define rCLCD_DITHER_ENABLE (*(volatile u_int32_t *)(CLCD_DITHER_BASE_ADDR + 0x0000))
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#define rCLCD_DITHER_METHOD (*(volatile u_int32_t *)(CLCD_DITHER_BASE_ADDR + 0x0004))
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#endif /* __SAMSUNG_CLCD_REGS_H */
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@@ -0,0 +1,20 @@
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/*
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* Copyright (C) 2012, 2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __SAMSUNG_CLCD_V2_H
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#define __SAMSUNG_CLCD_V2_H
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void clcd_enable_clocks(bool enable);
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void clcd_init(struct display_timing *timing);
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bool clcd_get_enable_timing_generator(void);
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void clcd_enable_timing_generator(bool enable);
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void clcd_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl);
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#endif /* __SAMSUNG_CLCD_V2_H */
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@@ -0,0 +1,19 @@
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# Copyright (C) 2012 Apple Inc. All rights reserved.
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#
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# This document is the property of Apple Inc.
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# It is considered confidential and proprietary.
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#
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# This document may not be reproduced or transmitted in any form,
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# in whole or in part, without the express written permission of
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# Apple Inc.
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#
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LOCAL_DIR := $(GET_LOCAL_DIR)
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OPTIONS += \
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DISPLAYPIPE_BASE_ADDR=CLCD_DISPLAYPIPE_BASE_ADDR \
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WITH_DBE_CLCD=1
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ALL_OBJS += \
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$(LOCAL_DIR)/clcd.o
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GLOBAL_INCLUDES += $(LOCAL_DIR)/include
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