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/*
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* Copyright (C) 2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/miu.h>
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#include <platform.h>
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#include <platform/chipid.h>
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#include <platform/clocks.h>
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#include <platform/gpio.h>
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#include <platform/soc/hwclocks.h>
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#include "drex.h"
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#if (TARGET_DREX_CLK_RATIO != 1) && (TARGET_DREX_CLK_RATIO != 2)
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#error "Invalid TARGET_DREX_CLK_RATIO"
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#endif
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static u_int32_t calc_sdram_refresh(u_int32_t tREFI, int clock);
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static uint8_t drex_mrr(uint8_t address)
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{
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uint32_t cmd_type = 9;
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uint32_t cmd_addr = ((address >> 6) & 0x3) | ((address & 0x7) << 10);
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uint32_t cmd_bank = (address >> 3) & 0x7;
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rDIRECTCMD = (cmd_type << 24) | (cmd_bank << 16) | (cmd_addr);
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spin(2);
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return rMRSTATUS;
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}
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static void drex_mrw(uint8_t address, uint8_t data)
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{
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uint32_t cmd_type = 0;
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uint32_t cmd_addr = (address >> 6) | (data << 2) | ((address & 0x7) << 10);
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uint32_t cmd_bank = (address >> 3) & 0x7;
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rDIRECTCMD = (cmd_type << 24) | (cmd_bank << 16) | (cmd_addr);
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spin(2);
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}
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int mcu_initialize_dram(bool resume)
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{
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#if !SUPPORT_FPGA
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// Change PhyZQControl.ctrl_zq_mode_dds to 4 for DDR2 400MHz. The default value, 7, is for DDR3 667MHz
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rPHYZQCONTROL = 0xE3855431;
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// Set ctrl_start_point and ctrl_inc, enable differential DQS.
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// Set ctrl_dll_on to activate the PHY DLL
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rPHYCONTROL0 = (0x10 << 16) | (0x10 << 8) | (0x1 << 3) | (0x1 << 1);
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// Set ctrl_shiftc = 5 (90 degree shift), ctrl_ref = 8
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rPHYCONTROL1 = (0x00 << 8) | (0x8 << 4) | 0x5;
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// Set ctrl_start
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rPHYCONTROL0 = (0x10 << 16) | (0x10 << 8) | (0x1 << 3) | (0x1 << 1) | 0x1;
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#endif
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rCONCONTROL = 0x0FFF30C0 | ((TARGET_DREX_CLK_RATIO - 1) << 1);
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rMEMCONTROL = 0x00202500;
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rMEMCONFIG = 0x00F01223;
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// Open page policy for all banks, maximum timeout before closing page
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rPRECHCONFIG = 0xFF000000;
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// Maximum timeout for going into self-refresh and dynamic power-down
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rPWRDNCONFIG = 0xFFFF00FF;
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rTIMINGAREF = TARGET_DREX_TIMING_AREF;
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rTIMINGROW = TARGET_DREX_TIMING_ROW;
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rTIMINGDATA = TARGET_DREX_TIMING_DATA;
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rTIMINGPOWER = TARGET_DREX_TIMING_POWER;
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#if !SUPPORT_FPGA
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// Wait for ctrl_locked to be set
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while ((rPHYSTATUS & (1 << 2)) == 0);
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// Prepare for the Force DLL resynchronization
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rPHYCONTROL1 = (0x00 << 8) | (0x8 << 4) | (0x0 << 3) | 0x5;
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// Force DLL resynchronization
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rPHYCONTROL1 = (0x00 << 8) | (0x8 << 4) | (0x1 << 3) | 0x5;
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// ZQ calibration
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// zq_start
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rPHYZQCONTROL |= (1 << 1);
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// wait for ctrl_zq_end
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while ((rPHYSTATUS & (1 << 16)) == 0);
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// fp_resync for ZQ result update
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rPHYCONTROL1 &= ~(1 << 3);
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rPHYCONTROL1 |= 1 << 3;
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rPHYCONTROL1 &= ~(1 << 3);
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// zq_stop
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rPHYZQCONTROL &= ~(1 << 1);
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#else
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spin(100000);
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#endif
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// NOP: exit from active/precharge power down or deep power down
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rDIRECTCMD = 0x07000000;
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spin(250);
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// MRW63: reset memory devices and do device auto-initialization
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drex_mrw(63, 0);
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spin(10);
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// RL = 6, WL = 3
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drex_mrw(2, 4);
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// Drive strength 48-ohm typical
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drex_mrw(3, 3);
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// Turn on auto-refresh counter
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rCONCONTROL |= (1 << 5);
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// Tunables for QoS, see radar 11065185
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rQOSTMDREX = TARGET_DREX_QOS_TIDEMARK;
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rQOSACDREX = TARGET_DREX_QOS_ACCESS;
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return 0;
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}
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void mcu_adjust_performance(void)
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{
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}
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uint64_t mcu_get_memory_size(void)
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{
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return chipid_get_memory_density() * chipid_get_memory_ranks() * (chipid_get_memory_width() / 32);
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}
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@@ -0,0 +1,42 @@
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/*
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* Copyright (C) 2011 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#ifndef __SAMSUNG_DREX_H
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#define __SAMSUNG_DREX_H
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#include <platform/soc/hwregbase.h>
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#define rCONCONTROL (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x000))
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#define rMEMCONTROL (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x004))
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#define rMEMCONFIG (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x008))
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#define rDIRECTCMD (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x010))
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#define rPRECHCONFIG (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x014))
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#define rPHYCONTROL0 (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x018))
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#define rPHYCONTROL1 (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x01C))
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#define rPHYCONTROL2 (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x020))
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#define rPHYCONTROL3 (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x024))
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#define rPWRDNCONFIG (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x028))
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#define rTIMINGPZQ (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x02C))
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#define rTIMINGAREF (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x030))
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#define rTIMINGROW (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x034))
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#define rTIMINGDATA (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x038))
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#define rTIMINGPOWER (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x03C))
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#define rPHYSTATUS (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x040))
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#define rPHYZQCONTROL (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x044))
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#define rCHIP0STATUS (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x048))
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#define rCHIP1STATUS (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x04C))
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#define rAREFSTATUS (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x050))
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#define rMRSTATUS (*(volatile u_int32_t *)(DREX_BASE_ADDR + 0x054))
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#define rQOSTMDREX (*(volatile u_int32_t *)(AXI_SPINE_BASE_ADDR + 0x400))
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#define rQOSACDREX (*(volatile u_int32_t *)(AXI_SPINE_BASE_ADDR + 0x404))
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#endif /* ! __SAMSUNG_DREX_H */
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@@ -0,0 +1,15 @@
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# Copyright (C) 2011 Apple Computer, Inc. All rights reserved.
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#
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# This document is the property of Apple Computer, Inc.
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# It is considered confidential and proprietary.
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#
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# This document may not be reproduced or transmitted in any form,
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# in whole or in part, without the express written permission of
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# Apple Computer, Inc.
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#
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LOCAL_DIR := $(GET_LOCAL_DIR)
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OPTIONS += \
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WITH_HW_DREX=1
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ALL_OBJS += $(LOCAL_DIR)/drex.o
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