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/*
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* Copyright (C) 2008-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/mipi.h>
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#include <platform.h>
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#include <platform/clocks.h>
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#include <platform/soc/hwclocks.h>
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#include <target/gpiodef.h>
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#include "dsim.h"
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#define DISPLAY_CONFIG_PLL_P(x) (((x) >> 26) & 0x03F)
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#define DISPLAY_CONFIG_PLL_M(x) (((x) >> 16) & 0x3FF)
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#define DISPLAY_CONFIG_PLL_S(x) (((x) >> 12) & 0x007)
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#define DISPLAY_CONFIG_PLL_B(x) (((x) >> 8) & 0x00F)
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#define DISPLAY_CONFIG_ESC_DIV(x) (((x) >> 4) & 0x00F)
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#define DISPLAY_CONFIG_LANES(x) (((x) >> 0) & 0x00F)
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#define DSIM_LANE_MASK ((1 << DSIM_LANE_COUNT) - 1)
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static u_int32_t lane_count;
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static u_int32_t lane_mask;
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static uint32_t esc_clock_div;
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static bool dsim_enabled;
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int mipi_dsim_init(struct display_timing *timing, enum colorspace color)
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{
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bool video_mode = true;
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u_int32_t tmp, pll_config, pix_format, afc_code = 0;
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u_int32_t config = rDSIM_CONFIG_HfpMode;
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bool afc_enable = false;
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uint32_t display_config;
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dprintf(DEBUG_CRITICAL, "mipi_dsim_init()\n");
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memcpy(&display_config, timing->display_config, sizeof(display_config));
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// Extract Lane configuration
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lane_count = DISPLAY_CONFIG_LANES(display_config);
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lane_mask = (1 << lane_count) - 1;
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// Extract PLL configuration
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pll_config = (rDSIM_PLLCTRL_P(DISPLAY_CONFIG_PLL_P(display_config)) |
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rDSIM_PLLCTRL_M(DISPLAY_CONFIG_PLL_M(display_config)) |
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rDSIM_PLLCTRL_S(DISPLAY_CONFIG_PLL_S(display_config)));
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// Extract Pixel Format
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if (timing->display_depth <= 18) pix_format = 5;
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else pix_format = 7;
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//Extract escape clock divisor
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esc_clock_div = DISPLAY_CONFIG_ESC_DIV(display_config);
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clock_gate(CLK_MIPI, true);
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// Configure clock selections
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rDSIM_CLKCTRL = (rDSIM_CLKCTRL_EscClkEn |
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((pll_config == 0) ? rDSIM_CLKCTRL_PllBypass : 0) |
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rDSIM_CLKCTRL_ByteClkSrc((pll_config == 0) ? 1 : 0) | // SOC or DSIM PLL
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rDSIM_CLKCTRL_EscPrescalar(DISPLAY_CONFIG_ESC_DIV(display_config)));
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// Select frequency band
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rDSIM_PLLCTRL = rDSIM_PLLCTRL_FreqBand(DISPLAY_CONFIG_PLL_B(display_config));
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#ifdef TARGET_DSIM_THS_PREPARE
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//Adjust tHS-PREPARE on the phy
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rDSIM_PLLCTRL |= rDSIM_PLLCTRL_PreprCtl(TARGET_DSIM_THS_PREPARE);
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#endif //TARGET_DSIM_THS_PREPARE
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// Configure PLL if needed
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if (pll_config != 0) {
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#if DSIM_VERSION == 1
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u_int32_t fin_pll;
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// Assume that AFC will be used
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afc_enable = true;
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// Set the AFC code in PHYACCHR
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fin_pll = clock_get_frequency(CLK_NCLK) / (1000000 * DISPLAY_CONFIG_PLL_P(display_config));
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// These code values are only for the 45nm PHY (i.e. DSIM_VERSION == 1)
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switch (fin_pll) {
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case 6: afc_code = 1; break;
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case 7: afc_code = 0; break;
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case 8: afc_code = 3; break;
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case 9: afc_code = 2; break;
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case 10: afc_code = 5; break;
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case 11: afc_code = 4; break;
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case 12: afc_code = 4; break;
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default : afc_enable = false; break;
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}
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#endif
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// If needed, enable AFC
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if (afc_enable) {
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rDSIM_PHYACCHR = rDSIM_PHYACCHR_AFC(afc_code) | rDSIM_PHYACCHR_AFC_ENABLE;
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}
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rDSIM_PLLTMR = 300000; // 1ms - HACK: assuming 300MHz hperf2
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rDSIM_PLLCTRL |= pll_config;
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rDSIM_PLLCTRL |= rDSIM_PLLCTRL_PllEn;
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while ((rDSIM_STATUS & rDSIM_STATUS_PllStable) == 0);
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}
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// Issue software reset
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rDSIM_SWRST = rDSIM_SWRST_SwRst;
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// If needed, enable AFC again
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if (afc_enable) {
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// PLL must be off to change AFC setting
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rDSIM_PLLCTRL &= ~rDSIM_PLLCTRL_PllEn;
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rDSIM_PHYACCHR = rDSIM_PHYACCHR_AFC(afc_code) | rDSIM_PHYACCHR_AFC_ENABLE;
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// Turn PLL back on
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rDSIM_PLLCTRL |= rDSIM_PLLCTRL_PllEn;
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}
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// Wait for software reset to complete
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while ((rDSIM_STATUS & rDSIM_STATUS_SwRstRls) == 0);
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#ifdef TARGET_DSIM_DPHYCTL
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rDSIM_PHYACCHR |= rDSIM_PHYACCHR_DPHYCTL(TARGET_DSIM_DPHYCTL);
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#endif // TARGET_DSIM_DPHYCTL
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#if TARGET_DSIM_DOWN_CODE
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rDSIM_PHYACCHR |= rDSIM_PHYACCHR_DOWN_CODE(TARGET_DSIM_DOWN_CODE);
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rDSIM_PHYACCHR2 |= rDSIM_PHYACCHR2_DOWN_CODE(TARGET_DSIM_DOWN_CODE);
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#endif // TARGET_DSIM_DOWN_CODE
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#ifdef TARGET_DSIM_UP_CODE
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rDSIM_PHYACCHR |= rDSIM_PHYACCHR_UP_CODE(TARGET_DSIM_UP_CODE);
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rDSIM_PHYACCHR2 |= rDSIM_PHYACCHR2_UP_CODE(TARGET_DSIM_UP_CODE);
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#endif // TARGET_DSIM_UP_CODE
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#ifdef TARGET_DSIM_SUPPRESS
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rDSIM_SUPPRESS |= TARGET_DSIM_SUPPRESS;
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#endif // TARGET_DSIM_SUPPRESS
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// Use the same resolution as CLCD
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rDSIM_MDRESOL = (rDSIM_MDRESOL_MainVResol(timing->v_active) |
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rDSIM_MDRESOL_MainHResol(timing->h_active));
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#ifdef TARGET_DISP_VIDEO_MODE
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video_mode = TARGET_DISP_VIDEO_MODE;
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#endif //TARGET_DISP_VIDEO_MODE
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if (video_mode) {
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// The vertical blanking settings are the same as the CLCD settings
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rDSIM_MVPORCH = (rDSIM_MVPORCH_CmdAllow(13) |
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rDSIM_MVPORCH_StableVfp(timing->v_front_porch) |
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rDSIM_MVPORCH_MainVbp(timing->v_back_porch));
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rDSIM_MSYNC = (timing->v_pulse_width << 22);
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// The horizontal blanking settings are constants which are
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// sufficent for all lane counts, frequencies and CLCD settings
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// Hfp = 15
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// Hbp = 14
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// Hsa = 1
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rDSIM_MHPORCH = (15 << 16) | (14 << 0);
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rDSIM_MSYNC |= (1 << 0);
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}
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#if DSIM_VERSION == 3
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else {
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rDSIM_I80_LPVALID_ST = (timing->h_active * 3) + 100;
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}
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#endif // DSIM_VERSION == 3
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rDSIM_SSCNT = 0xa;
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#ifdef TARGET_DSIM_CONFIG
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config = TARGET_DSIM_CONFIG;
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#endif
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rDSIM_CONFIG = (rDSIM_CONFIG_BurstMode |
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rDSIM_CONFIG_AutoMode |
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config |
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rDSIM_CONFIG_MainPixFormat(pix_format) |
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rDSIM_CONFIG_NumOfDatLane(DSIM_LANE_COUNT - 1) |
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rDSIM_CONFIG_LaneEn(DSIM_LANE_MASK) |
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rDSIM_CONFIG_LaneClkEn);
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if (video_mode) {
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rDSIM_CONFIG |= rDSIM_CONFIG_VideoMode;
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}
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#ifdef TARGET_NO_BURST_MODE
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if (TARGET_NO_BURST_MODE) {
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rDSIM_CONFIG &= ~rDSIM_CONFIG_BurstMode;
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}
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#endif
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rDSIM_CLKCTRL |= (rDSIM_CLKCTRL_ByteClkEn |
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rDSIM_CLKCTRL_LaneEscClkEn(DSIM_LANE_MASK) |
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rDSIM_CLKCTRL_LaneEscClkEnClk);
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rDSIM_FIFOCTRL = 0x1F;
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rDSIM_FIFOTHLD = 0x1FF;
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// Force Stop state on all lanes
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rDSIM_ESCMODE = (rDSIM_ESCMODE_CmdLpdt | rDSIM_ESCMODE_ForceStopstate);
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spin(1 * 1000);
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rDSIM_ESCMODE &= ~rDSIM_ESCMODE_ForceStopstate;
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// Wait for Stop state on all lanes
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tmp = rDSIM_STATUS_StopstateClk | rDSIM_STATUS_StopstateDat(DSIM_LANE_MASK);
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while ((rDSIM_STATUS & tmp) != tmp);
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// Request ULPS mode on all lanes
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rDSIM_ESCMODE = (rDSIM_ESCMODE_CmdLpdt | rDSIM_ESCMODE_TxUlpsClk | rDSIM_ESCMODE_TxUlpsDat);
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// Wait for ULPS mode on all lanes
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tmp = rDSIM_STATUS_UlpsClk | rDSIM_STATUS_UlpsDat(DSIM_LANE_MASK);
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while ((rDSIM_STATUS & tmp) != tmp);
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// Set the lane configuration
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rDSIM_CONFIG &= ~(rDSIM_CONFIG_NumOfDatLaneMsk | rDSIM_CONFIG_LaneEnMsk);
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rDSIM_CONFIG |= rDSIM_CONFIG_NumOfDatLane(lane_count - 1) | rDSIM_CONFIG_LaneEn(lane_mask);
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// Enable the configured lanes
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rDSIM_CLKCTRL &= ~rDSIM_CLKCTRL_LaneEscClkEnMsk;
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rDSIM_CLKCTRL |= rDSIM_CLKCTRL_LaneEscClkEn(lane_mask);
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// Request exit ULPS mode on configured lanes
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rDSIM_ESCMODE |= (rDSIM_ESCMODE_TxUlpsClkExit | rDSIM_ESCMODE_TxUlpsExit);
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// Wait for exit ULPS mode on configured lanes
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tmp = rDSIM_STATUS_UlpsClk | rDSIM_STATUS_UlpsDat(lane_mask);
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while ((rDSIM_STATUS & tmp) != 0);
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// Clear exit ULPS mode request and ULPS mode request
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rDSIM_ESCMODE &= ~(rDSIM_ESCMODE_TxUlpsClkExit | rDSIM_ESCMODE_TxUlpsExit);
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spin(1 * 1000);
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rDSIM_ESCMODE &= ~(rDSIM_ESCMODE_TxUlpsClk | rDSIM_ESCMODE_TxUlpsDat);
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// Wait for Stop state on configured lanes
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tmp = rDSIM_STATUS_StopstateClk | rDSIM_STATUS_StopstateDat(lane_mask);
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while ((rDSIM_STATUS & tmp) != tmp);
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#if DSIM_VERSION == 3
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if (!video_mode) {
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rDSIM_ULPSIN = TARGET_DSI_ULPS_IN_DELAY;
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rDSIM_ULPSEND = TARGET_DSI_ULPS_END_DELAY;
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rDSIM_ULPSOUT = TARGET_DSI_ULPS_OUT_DELAY;
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//<rdar://problem/18037708> SkiHillVail12S5356c: panic(cpu 0 caller 0x855223df): "_waitUntilPayloadFifoIsEmpty: Timeout Waiting for payload fifo to empty"
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rDSIM_ESCMODE |= rDSIM_ESCMODE_Auto_Ulps_Clk;
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}
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#endif //DSIM_VERSION == 3
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dsim_enabled = true;
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return 0;
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}
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int mipi_dsim_quiesce(void)
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{
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u_int32_t tmp, pllctrl, phyacchr;
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dprintf(DEBUG_CRITICAL, "mipi_dsim_quiesce()\n");
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if (!dsim_enabled) return 0;
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// Save the PLLCTRL and PHYACCHR settings before software reset
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pllctrl = rDSIM_PLLCTRL;
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phyacchr = rDSIM_PHYACCHR;
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// Issue software reset
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rDSIM_SWRST = rDSIM_SWRST_SwRst;
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// Turn off the PLL if it was on
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rDSIM_PLLCTRL = pllctrl & ~rDSIM_PLLCTRL_PllEn;
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// Restore PHYACCHR setting
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rDSIM_PHYACCHR = phyacchr;
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// If the PLL was on, turn it back on
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rDSIM_PLLCTRL = pllctrl;
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// Wait for reset to complete
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while ((rDSIM_STATUS & rDSIM_STATUS_SwRstRls) == 0);
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// Set the lane configuration
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rDSIM_CONFIG &= ~(rDSIM_CONFIG_NumOfDatLaneMsk | rDSIM_CONFIG_LaneEnMsk);
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rDSIM_CONFIG |= (rDSIM_CONFIG_NumOfDatLane(DSIM_LANE_COUNT - 1) |
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rDSIM_CONFIG_LaneEn(DSIM_LANE_MASK) |
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rDSIM_CONFIG_LaneClkEn);
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// Enable the configured lanes
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rDSIM_CLKCTRL &= ~(rDSIM_CLKCTRL_TxRequestHsClk | rDSIM_CLKCTRL_LaneEscClkEnMsk);
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rDSIM_CLKCTRL |= rDSIM_CLKCTRL_LaneEscClkEn(DSIM_LANE_MASK);
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// Force Stop state on all lanes
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rDSIM_ESCMODE = (rDSIM_ESCMODE_CmdLpdt | rDSIM_ESCMODE_ForceStopstate);
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spin(1 * 1000);
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rDSIM_ESCMODE &= ~rDSIM_ESCMODE_ForceStopstate;
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// Wait for Stop state on all lanes
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tmp = rDSIM_STATUS_StopstateClk | rDSIM_STATUS_StopstateDat(DSIM_LANE_MASK);
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while ((rDSIM_STATUS & tmp) != tmp);
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// Request ULPS mode on all lanes
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rDSIM_ESCMODE = (rDSIM_ESCMODE_CmdLpdt | rDSIM_ESCMODE_TxUlpsClk | rDSIM_ESCMODE_TxUlpsDat);
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// Wait for ULPS mode on all lanes
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tmp = rDSIM_STATUS_UlpsClk | rDSIM_STATUS_UlpsDat(DSIM_LANE_MASK);
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while ((rDSIM_STATUS & tmp) != tmp);
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// Turn off internal clocks
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rDSIM_CLKCTRL = 0x00000000;
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rDSIM_CONFIG = rDSIM_CONFIG_VideoMode;
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rDSIM_ESCMODE = 0x00000000;
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rDSIM_PLLCTRL = 0x00000000;
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clock_gate(CLK_MIPI, false);
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dsim_enabled = false;
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return 0;
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}
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void mipi_dsim_enable_high_speed(bool enable)
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{
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if (enable) {
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rDSIM_CLKCTRL |= rDSIM_CLKCTRL_TxRequestHsClk;
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while ((rDSIM_STATUS & rDSIM_STATUS_TxReadyHsClk) == 0);
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} else {
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rDSIM_CLKCTRL &= ~rDSIM_CLKCTRL_TxRequestHsClk;
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while ((rDSIM_STATUS & rDSIM_STATUS_TxReadyHsClk) != 0);
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}
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}
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void mipi_dsim_enable_video(bool enable)
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{
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if (enable) {
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rDSIM_MDRESOL |= rDSIM_MDRESOL_MainStandby;
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} else {
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rDSIM_MDRESOL &= ~rDSIM_MDRESOL_MainStandby;
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}
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}
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int mipi_dsim_send_short_command(u_int8_t cmd, u_int8_t data0, u_int8_t data1)
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{
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uint32_t escape_clock_period_us;
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uint32_t mipi_byte_clock_frequency;
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mipi_byte_clock_frequency = clock_get_frequency(CLK_MIPI)/ 8;
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escape_clock_period_us = (100000000 * esc_clock_div) /mipi_byte_clock_frequency;
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escape_clock_period_us = (escape_clock_period_us/100) < 1 ? 1 : (escape_clock_period_us/100);
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rDSIM_PKTHDR = (cmd & 0x3f) | (((u_int32_t)data0) << 8) | (((u_int32_t)data1) << 16);
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//10 ESC clocks before checking the status bit.
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spin (10 * escape_clock_period_us);
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//check for command header to have been sent
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while ((rDSIM_FIFOCTRL & rDSIM_FIFOCTRL_EmptyHSfr) == 0);
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//check for command payload to have been sent
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while ((rDSIM_FIFOCTRL & rDSIM_FIFOCTRL_EmptyLSfr) == 0);
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spin(22 + ((343 * 1000000 * esc_clock_div)/mipi_byte_clock_frequency));
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return 0;
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}
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int mipi_dsim_send_long_command(u_int8_t cmd, const u_int8_t *data, u_int32_t length)
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{
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u_int32_t cnt, payload = 0;
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for (cnt = 0; cnt < length; cnt++) {
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payload = (payload >> 8) | ((u_int32_t)data[cnt] << 24);
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if ((cnt & 3) == 3) {
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rDSIM_PAYLOAD = payload;
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payload = 0;
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}
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}
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if (payload) {
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payload >>= 32 - ((length & 3) * 8);
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rDSIM_PAYLOAD = payload;
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}
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for (cnt = 0; cnt < 5; cnt++) {
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rDSIM_PAYLOAD = 0;
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}
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length += 20;
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return mipi_dsim_send_short_command(cmd, length & 0xff, (length >> 8) & 0xff);
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}
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int mipi_dsim_read_short_command(u_int8_t cmd, u_int8_t *data)
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{
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u_int32_t tmp, i = 0;
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// Clear pending interrupts
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rDSIM_INTSRC = 0xffffffff;
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mipi_dsim_send_short_command(cmd, data[0], data[1]);
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while (1) {
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tmp = rDSIM_INTSRC;
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|
||||
if (tmp & rDSIM_INTSRC_RxAck) return -1;
|
||||
if (tmp & rDSIM_INTSRC_LpdrTout) return -1;
|
||||
// Ignore errors for now (not all drivers do ECC)
|
||||
// if (tmp & rDSIM_INTSRC_AnyError) return -1;
|
||||
|
||||
if (tmp & rDSIM_INTSRC_RxDatDone) break;
|
||||
|
||||
// Hardware timeout depends on having a receiver, and
|
||||
// completing BTA. This isn't guaranteed for dev boards.
|
||||
if (++i == 5) {
|
||||
dprintf(DEBUG_CRITICAL, "mipi: timing out\n");
|
||||
return -1;
|
||||
}
|
||||
spin(50 * 1000);
|
||||
}
|
||||
|
||||
while (rDSIM_FIFOCTRL & rDSIM_FIFOCTRL_EmptyRx);
|
||||
|
||||
tmp = rDSIM_RXFIFO;
|
||||
|
||||
switch (tmp & 0x3f) {
|
||||
case DSIM_RSP_READ_1B:
|
||||
case DSIM_RSP_DSC_READ_1B:
|
||||
data[0] = (tmp >> 8) & 0xff;
|
||||
data[1] = 0;
|
||||
break;
|
||||
case DSIM_RSP_READ_2B:
|
||||
case DSIM_RSP_DSC_READ_2B:
|
||||
data[0] = (tmp >> 8) & 0xff;
|
||||
data[1] = (tmp >> 16) & 0xff;
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mipi_dsim_read_long_command(u_int8_t cmd, u_int8_t *data, u_int32_t *length)
|
||||
{
|
||||
u_int32_t tmp, len, maxlen, i = 0;
|
||||
|
||||
maxlen = *length;
|
||||
|
||||
// Clear pending interrupts
|
||||
rDSIM_INTSRC = 0xffffffff;
|
||||
|
||||
mipi_dsim_send_short_command(cmd, data[0], data[1]);
|
||||
|
||||
while (1) {
|
||||
tmp = rDSIM_INTSRC;
|
||||
|
||||
if (tmp & rDSIM_INTSRC_RxAck) return -1;
|
||||
if (tmp & rDSIM_INTSRC_LpdrTout) return -1;
|
||||
// Ignore errors for now (not all drivers do ECC)
|
||||
// if (tmp & rDSIM_INTSRC_AnyError) return -1;
|
||||
|
||||
if (tmp & rDSIM_INTSRC_RxDatDone) break;
|
||||
|
||||
// Hardware timeout depends on having a receiver, and
|
||||
// completing BTA. This isn't guaranteed for dev boards.
|
||||
if (++i == 5) {
|
||||
dprintf(DEBUG_CRITICAL, "mipi: timing out\n");
|
||||
return -1;
|
||||
}
|
||||
spin(50 * 1000);
|
||||
}
|
||||
|
||||
while (rDSIM_FIFOCTRL & rDSIM_FIFOCTRL_EmptyRx);
|
||||
|
||||
tmp = rDSIM_RXFIFO;
|
||||
|
||||
switch (tmp & 0x3f) {
|
||||
case DSIM_RSP_LONG_READ:
|
||||
case DSIM_RSP_DSC_LONG_READ:
|
||||
break;
|
||||
default:
|
||||
dprintf(DEBUG_CRITICAL, "mipi: weird response %08x\n", tmp);
|
||||
return -1;
|
||||
}
|
||||
|
||||
len = (tmp >> 8) & 0xffff;
|
||||
if (len < maxlen)
|
||||
*length = len;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if ((i % 4) == 0) {
|
||||
while (rDSIM_FIFOCTRL & rDSIM_FIFOCTRL_EmptyRx);
|
||||
tmp = rDSIM_RXFIFO;
|
||||
}
|
||||
if (i < maxlen)
|
||||
data[i] = tmp & 0xff;
|
||||
tmp >>= 8;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,171 @@
|
||||
/*
|
||||
* Copyright (C) 2008-2012 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __SAMSUNG_DSIM_H
|
||||
#define __SAMSUNG_DSIM_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rDSIM_STATUS (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00))
|
||||
#define rDSIM_STATUS_PllStable (0x80000000)
|
||||
#define rDSIM_STATUS_SwRstRls (0x00100000)
|
||||
#define rDSIM_STATUS_Direction (0x00010000)
|
||||
#define rDSIM_STATUS_TxReadyHsClk (0x00000400)
|
||||
#define rDSIM_STATUS_UlpsClk (0x00000200)
|
||||
#define rDSIM_STATUS_StopstateClk (0x00000100)
|
||||
#define rDSIM_STATUS_UlpsDatMsk (0xf << 4)
|
||||
#define rDSIM_STATUS_UlpsDat(d) (((d) & 0xf) << 4)
|
||||
#define rDSIM_STATUS_StopstateDatMsk (0xf << 0)
|
||||
#define rDSIM_STATUS_StopstateDat(d) (((d) & 0xf) << 0)
|
||||
#define rDSIM_SWRST (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x04))
|
||||
#define rDSIM_SWRST_FuncRst (0x00010000)
|
||||
#define rDSIM_SWRST_SwRst (0x00000001)
|
||||
#define rDSIM_CLKCTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x08))
|
||||
#define rDSIM_CLKCTRL_TxRequestHsClk (0x80000000)
|
||||
#define rDSIM_CLKCTRL_EscClkEn (0x10000000)
|
||||
#define rDSIM_CLKCTRL_PllBypass (0x08000000)
|
||||
#define rDSIM_CLKCTRL_ByteClkSrcMsk (0x3 << 25)
|
||||
#define rDSIM_CLKCTRL_ByteClkSrc(d) (((d) & 0x3) << 25)
|
||||
#define rDSIM_CLKCTRL_ByteClkEn (0x01000000)
|
||||
#define rDSIM_CLKCTRL_LaneEscClkEnMsk (0xf << 20)
|
||||
#define rDSIM_CLKCTRL_LaneEscClkEn(d) (((d) & 0xf) << 20)
|
||||
#define rDSIM_CLKCTRL_LaneEscClkEnClk (0x00080000)
|
||||
#define rDSIM_CLKCTRL_EscPrescalar(d) ((d) & 0xffff)
|
||||
#define rDSIM_TIMEOUT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0C))
|
||||
#define rDSIM_CONFIG (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x10))
|
||||
#define rDSIM_CONFIG_DPDN_Test_En (0x80000000)
|
||||
#define rDSIM_CONFIG_TxTypeSfr (0x10000000)
|
||||
#define rDSIM_CONFIG_SyncInform (0x08000000)
|
||||
#define rDSIM_CONFIG_BurstMode (0x04000000)
|
||||
#define rDSIM_CONFIG_VideoMode (0x02000000)
|
||||
#define rDSIM_CONFIG_AutoMode (0x01000000)
|
||||
#define rDSIM_CONFIG_HseMode (0x00800000)
|
||||
#define rDSIM_CONFIG_HfpMode (0x00400000)
|
||||
#define rDSIM_CONFIG_HbpMode (0x00200000)
|
||||
#define rDSIM_CONFIG_HsaMode (0x00100000)
|
||||
#define rDSIM_CONFIG_MainVc(d) (((d) & 0x3) << 18)
|
||||
#define rDSIM_CONFIG_MainPixFormat(d) (((d) & 0x7) << 12)
|
||||
#define rDSIM_CONFIG_NumOfDatLaneMsk (0x3 << 5)
|
||||
#define rDSIM_CONFIG_NumOfDatLane(d) (((d) & 0x3) << 5)
|
||||
#define rDSIM_CONFIG_LaneEnMsk (0xf << 1)
|
||||
#define rDSIM_CONFIG_LaneEn(d) (((d) & 0xf) << 1)
|
||||
#define rDSIM_CONFIG_LaneClkEn (0x00000001)
|
||||
#define rDSIM_ESCMODE (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x14))
|
||||
#define rDSIM_ESCMODE_ForceStopstate (0x00100000)
|
||||
#define rDSIM_ESCMODE_ForceBTA (0x00010000)
|
||||
#if DSIM_VERSION == 3
|
||||
#define rDSIM_ESCMODE_Auto_Ulps_Data (1 << 9)
|
||||
#define rDSIM_ESCMODE_Auto_Ulps_Clk (1 << 8)
|
||||
#endif // DSIM_VERSION == 3
|
||||
#define rDSIM_ESCMODE_CmdLpdt (0x00000080)
|
||||
#define rDSIM_ESCMODE_TxLpdt (0x00000040)
|
||||
#define rDSIM_ESCMODE_TxTriggerRst (0x00000010)
|
||||
#define rDSIM_ESCMODE_TxUlpsDat (0x00000008)
|
||||
#define rDSIM_ESCMODE_TxUlpsExit (0x00000004)
|
||||
#define rDSIM_ESCMODE_TxUlpsClk (0x00000002)
|
||||
#define rDSIM_ESCMODE_TxUlpsClkExit (0x00000001)
|
||||
#define rDSIM_MDRESOL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x18))
|
||||
#define rDSIM_MDRESOL_MainStandby (0x80000000)
|
||||
#define rDSIM_MDRESOL_MainVResol(d) (((d) & 0x7ff) << 16)
|
||||
#define rDSIM_MDRESOL_MainHResol(d) ((d) & 0x7ff)
|
||||
#define rDSIM_MVPORCH (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x1C))
|
||||
#define rDSIM_MVPORCH_CmdAllow(d) (((d) & 0xf) << 28)
|
||||
#define rDSIM_MVPORCH_StableVfp(d) (((d) & 0x7ff) << 16)
|
||||
#define rDSIM_MVPORCH_MainVbp(d) ((d) & 0x7ff)
|
||||
#define rDSIM_MHPORCH (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x20))
|
||||
#define rDSIM_MSYNC (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x24))
|
||||
#define rDSIM_SSCNT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x28))
|
||||
#define rDSIM_INTSRC (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x2C))
|
||||
#define rDSIM_INTSRC_SwRstRelease (0x40000000)
|
||||
#define rDSIM_INTSRC_PllStable (0x80000000)
|
||||
#define rDSIM_INTSRC_LpdrTout (0x00200000)
|
||||
#define rDSIM_INTSRC_RxDatDone (0x00040000)
|
||||
#define rDSIM_INTSRC_RxAck (0x00010000)
|
||||
#define rDSIM_INTSRC_AnyError (0x0000ffff)
|
||||
#define rDSIM_INTMSK (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x30))
|
||||
#define rDSIM_PKTHDR (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x34))
|
||||
#define rDSIM_PAYLOAD (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x38))
|
||||
#define rDSIM_RXFIFO (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x3C))
|
||||
#define rDSIM_FIFOTHLD (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x40))
|
||||
#define rDSIM_FIFOCTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x44))
|
||||
#define rDSIM_FIFOCTRL_FullRx (0x02000000)
|
||||
#define rDSIM_FIFOCTRL_EmptyRx (0x01000000)
|
||||
#define rDSIM_FIFOCTRL_FullHSfr (0x00800000)
|
||||
#define rDSIM_FIFOCTRL_EmptyHSfr (0x00400000)
|
||||
#define rDSIM_FIFOCTRL_FullLSfr (0x00200000)
|
||||
#define rDSIM_FIFOCTRL_EmptyLSfr (0x00100000)
|
||||
#define rDSIM_FIFOCTRL_FullHI80 (0x00080000)
|
||||
#define rDSIM_FIFOCTRL_EmptyHI80 (0x00040000)
|
||||
#define rDSIM_FIFOCTRL_FullLI870 (0x00020000)
|
||||
#define rDSIM_FIFOCTRL_EmptyLI80 (0x00010000)
|
||||
#define rDSIM_FIFOCTRL_FullHMain (0x00000800)
|
||||
#define rDSIM_FIFOCTRL_EmptyHMain (0x00000400)
|
||||
#define rDSIM_FIFOCTRL_FullLMain (0x00000200)
|
||||
#define rDSIM_FIFOCTRL_EmptyLMain (0x00000100)
|
||||
#define rDSIM_FIFOCTRL_nInitRx (0x00000010)
|
||||
#define rDSIM_FIFOCTRL_nInitSfr (0x00000008)
|
||||
#define rDSIM_FIFOCTRL_nInitI80 (0x00000004)
|
||||
#define rDSIM_FIFOCTRL_nInitMain (0x00000001)
|
||||
#define rDSIM_MEMACCHR (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x48))
|
||||
#define rDSIM_PLLCTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x4C))
|
||||
#define rDSIM_PLLCTRL_HSzeroCtl(d) (((d) & 0xf) << 28)
|
||||
#define rDSIM_PLLCTRL_FreqBand(d) (((d) & 0xf) << 24)
|
||||
#define rDSIM_PLLCTRL_PllEn (0x00800000)
|
||||
#define rDSIM_PLLCTRL_PreprCtl(d) (((d) & 0x7) << 20)
|
||||
#if DSIM_VERSION == 0
|
||||
#define rDSIM_PLLCTRL_P(d) (((d) & 0x3f) << 14)
|
||||
#define rDSIM_PLLCTRL_M(d) (((d) & 0x3ff) << 4)
|
||||
#else
|
||||
#define rDSIM_PLLCTRL_P(d) (((d) & 0x3f) << 13)
|
||||
#define rDSIM_PLLCTRL_M(d) (((d) & 0x1ff) << 4)
|
||||
#endif
|
||||
#define rDSIM_PLLCTRL_S(d) (((d) & 0x7) << 1)
|
||||
#define rDSIM_PLLCTRL_DpDnSwap (0x00000001)
|
||||
#define rDSIM_PLLTMR (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x50))
|
||||
#define rDSIM_PHYACCHR (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x54))
|
||||
#if DSIM_VERSION < 2
|
||||
#define rDSIM_PHYACCHR_UP_CODE(d) (((d) & 0xc) << (26 - 2))
|
||||
#else
|
||||
#define rDSIM_PHYACCHR_UP_CODE(d) (0 << 0)
|
||||
#endif
|
||||
#define rDSIM_PHYACCHR_AFC_ENABLE (0x00004000)
|
||||
#define rDSIM_PHYACCHR_DPHYCTL(d) (((d) & 0x3f) << 8)
|
||||
#define rDSIM_PHYACCHR_AFC(d) (((d) & 0x7) << 5)
|
||||
#if DSIM_VERSION < 2
|
||||
#define rDSIM_PHYACCHR_DOWN_CODE(d) (((d) & 0x1) << (3 - 0))
|
||||
#else
|
||||
#define rDSIM_PHYACCHR_DOWN_CODE(d) (0 << 0) //NOOP
|
||||
#endif
|
||||
#define rDSIM_PHYACCHR2 (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x58))
|
||||
#if DSIM_VERSION < 2
|
||||
#define rDSIM_PHYACCHR2_UP_CODE(d) ((((d) & 0x2) << (17 - 1)) | (((d) & 0x1) << (8 - 0)))
|
||||
#define rDSIM_PHYACCHR2_DOWN_CODE(d) (0 << 0) //NOOP
|
||||
#else
|
||||
#define rDSIM_PHYACCHR2_UP_CODE(d) (((d) & 0x7) << 19)
|
||||
#define rDSIM_PHYACCHR2_DOWN_CODE(d) (((d) & 0x7) << 4)
|
||||
#endif
|
||||
#define rDSIM_PHYACCHR2_PrprCtlClk(d) (((d) & 0x7) << 16)
|
||||
|
||||
#if DSIM_VERSION == 3
|
||||
#define rDSIM_ULPSIN (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x60))
|
||||
#define rDSIM_ULPSOUT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x64))
|
||||
#define rDSIM_ULPSEND (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x68))
|
||||
#endif //DSIM_VERSION == 3
|
||||
|
||||
#define rDSIM_SUPPRESS (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x6C))
|
||||
#define rDSIM_SUPPRESS_Line_Timeout_Disable (0x00000001)
|
||||
|
||||
#if DSIM_VERSION == 3
|
||||
#define rDSIM_I80_LPVALID_ST (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x70))
|
||||
#endif //DSIM_VERSION == 3
|
||||
|
||||
#define rDSIM_VERINFO (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0C))
|
||||
|
||||
#endif /* __SAMSUNG_DSIM_H */
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (C) 2008 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_MIPI_DSIM=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/dsim.o
|
||||
Reference in new issue
Block a user