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@@ -0,0 +1,19 @@
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# Copyright (C) 2007 Apple Inc. All rights reserved.
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#
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# This document is the property of Apple Inc.
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# It is considered confidential and proprietary.
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#
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# This document may not be reproduced or transmitted in any form,
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# in whole or in part, without the express written permission of
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# Apple Inc.
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#
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LOCAL_DIR := $(GET_LOCAL_DIR)
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OPTIONS += \
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WITH_HW_SHA1=1
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MODULES += \
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drivers/sha1
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ALL_OBJS += \
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$(LOCAL_DIR)/sha1.o
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@@ -0,0 +1,212 @@
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/*
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* Copyright (C) 2007-2008 Apple Inc. All rights reserved.
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* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <arch.h>
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#include <debug.h>
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#include <platform/clocks.h>
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#include <platform/int.h>
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#include <platform/soc/hwclocks.h>
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#include <sys.h>
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#include <sys/task.h>
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#include "sha1.h"
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static const sha1_regs sha1_reg = {
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&rSHA1_ADDR_CONF, &rSHA1_ADDR_SWRESET, &rSHA1_ADDR_INT_SRC, &rSHA1_ADDR_INT_MASK,
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&rSHA1_ADDR_ENDIAN, &rSHA1_ADDR_CODE0, &rSHA1_ADDR_CODE1, &rSHA1_ADDR_CODE2,
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&rSHA1_ADDR_CODE3, &rSHA1_ADDR_CODE4, &rSHA1_ADDR_DATA0, &rSHA1_ADDR_DATA1,
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&rSHA1_ADDR_DATA2, &rSHA1_ADDR_DATA3, &rSHA1_ADDR_DATA4, &rSHA1_ADDR_DATA5,
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&rSHA1_ADDR_DATA6, &rSHA1_ADDR_DATA7, &rSHA1_ADDR_DATA8, &rSHA1_ADDR_DATA9,
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&rSHA1_ADDR_DATA10, &rSHA1_ADDR_DATA11, &rSHA1_ADDR_DATA12, &rSHA1_ADDR_DATA13,
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&rSHA1_ADDR_DATA14, &rSHA1_ADDR_DATA15, &rSHA1_MASTER_MODE, &rSHA1_MS_START_ADDR,
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&rSHA1_MS_SIZE };
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static sha1_status sha1Status = { 0, 0, 0 };
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static void sha1Run(u_int8_t *buf);
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static void Sha1NewInit(void);
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void Sha1NewAddEnd(u_int32_t dataLen, u_int32_t offset, u_int32_t startCmd);
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static void Sha1NewInit(void)
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{
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const sha1_regs *reg;
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reg = &sha1_reg;
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clock_gate(CLK_SHA1, true);
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/* wait for SHA-1 engine idle */
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while(*reg->con & (0x1<<0))
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;
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/* Software reset */
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*reg->swreset = 0x1;
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*reg->swreset = 0x0;
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/* Reset Configuration Register */
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*reg->con = 0x0;
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/* Always use slave mode */
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*reg->mode = 0x0;
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/* Always use twist / little endian */
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*reg->twist = 0x0;
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sha1Status.cmd = 1;
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sha1Status.offset = 0;
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sha1Status.length = 0;
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}
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/* Fill the frame buffer and send it out
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* the buffer size is always 64 bytes
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* Caller is responsible to set the End bit and 0 padding
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*/
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static void sha1Run(u_int8_t *buf)
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{
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const sha1_regs *reg;
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reg = &sha1_reg;
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/* Fill the buffer */
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for (int i = 0; i < 16; i++) {
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volatile u_int32_t *data;
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data = reg->data0;
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#if WITH_UNALIGNED_MEM
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*(data + i) = ((u_int32_t *)buf)[i];
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#else
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*(data + i) = (buf[i*4] << 0)|(buf[i*4+1] << 8)|(buf[i*4+2] << 16)|(buf[i*4+3] << 24);
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#endif
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}
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/* Run the SHA1 engine */
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if (sha1Status.cmd) {
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/* Start new hash code */
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*reg->con &= ~(1<<3);
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sha1Status.cmd = 0;
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} else {
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/* Continue hash code */
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*reg->con |= (1<<3);
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}
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*reg->con |= 1<<1;
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while(*reg->con & (1<<0))
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;
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}
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/************************************************************************
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* void sha1_hw_calculate(const void *buf, size_t len, u_int32_t *result)
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* -- We are using slave mode only so the code would be portable
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* between H1, H2, M1, M2.
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* -- Caller's responsibility to make sure buffer can hold 20 bytes
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* SHA1 code.
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************************************************************************/
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void sha1_hw_calculate(const void *buf, size_t len, u_int32_t *result)
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{
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u_int32_t length, counter;
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u_int8_t *frame;
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u_int64_t sha1TotalBits;
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u_int8_t sha1TotalLenAdd[8];
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const sha1_regs *reg;
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Sha1NewInit();
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reg = &sha1_reg;
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frame = (u_int8_t *)buf;
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length = len;
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counter =0;
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/* Prepare the 64 bits length */
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sha1TotalBits = len * 8;
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sha1TotalLenAdd[0] = ((sha1TotalBits >> 32) & (0xff << 24)) >> 24;
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sha1TotalLenAdd[1] = ((sha1TotalBits >> 32) & (0xff << 16)) >> 16;
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sha1TotalLenAdd[2] = ((sha1TotalBits >> 32) & (0xff << 8)) >> 8;
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sha1TotalLenAdd[3] = ((sha1TotalBits >> 32) & (0xff << 0)) >> 0;
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sha1TotalLenAdd[4] = (sha1TotalBits & (0xff << 24)) >> 24;
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sha1TotalLenAdd[5] = (sha1TotalBits & (0xff << 16)) >> 16;
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sha1TotalLenAdd[6] = (sha1TotalBits & (0xff << 8)) >> 8;
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sha1TotalLenAdd[7] = (sha1TotalBits & (0xff << 0)) >> 0;
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while (length > 64) {
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sha1Run(&frame[sha1Status.length]);
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sha1Status.length += 64;
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length -= 64;
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counter += 64;
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if (0x7FFFF < counter) {
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task_yield();
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counter = 0;
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}
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}
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if (length > 55) {
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/* Not enough space for the length bytes */
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u_int8_t frameBuf[64];
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for (u_int32_t i = 0; i < 64; i++) {
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if (length > i) {
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frameBuf[i] = frame[sha1Status.length++];
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} else if (length == i) {
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frameBuf[i] = 0x80;
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} else {
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frameBuf[i] = 0x0;
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}
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}
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sha1Run(frameBuf);
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/* Add End bit 0x80 if not added above */
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if (length == 64) {
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frameBuf[0] = 0x80;
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} else {
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frameBuf[0] = 0x0;
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}
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/* Start a new frame to hold the length */
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for (int j = 1; j < 56; j++) {
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frameBuf[j] = 0x0;
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}
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/* Now store the length */
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for (int k = 0; k < 8; k++) {
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frameBuf[56 + k] = sha1TotalLenAdd[k];
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}
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sha1Run(frameBuf);
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} else {
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/* Add End bit 0x80 and 0 padding */
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u_int8_t frameBuf[64];
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for (u_int32_t i = 0; i < 56; i++) {
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if (length > i) {
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frameBuf[i] = frame[sha1Status.length++];
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} else if (length == i) {
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frameBuf[i] = 0x80;
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} else {
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frameBuf[i] = 0x0;
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}
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}
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/* Now store the length */
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for (int j = 0; j < 8; j++) {
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frameBuf[56 + j] = sha1TotalLenAdd[j];
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}
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sha1Run(frameBuf);
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}
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/* Get the result */
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result[0] = *reg->code0;
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result[1] = *reg->code1;
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result[2] = *reg->code2;
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result[3] = *reg->code3;
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result[4] = *reg->code4;
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clock_gate(CLK_SHA1, false);
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}
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@@ -0,0 +1,98 @@
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/*
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* Copyright (C) 2007 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Computer, Inc.
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*/
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#ifndef __SAMSUNG_SHA1_H
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#define __SAMSUNG_SHA1_H
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#include <platform/soc/hwregbase.h>
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#define rSHA1_ADDR_CONF (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x00))
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#define rSHA1_ADDR_SWRESET (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x04))
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#define rSHA1_ADDR_INT_SRC (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x08))
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#define rSHA1_ADDR_INT_MASK (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x0C))
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#define rSHA1_ADDR_ENDIAN (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x10))
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#define rSHA1_ADDR_CODE0 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x20))
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#define rSHA1_ADDR_CODE1 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x24))
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#define rSHA1_ADDR_CODE2 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x28))
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#define rSHA1_ADDR_CODE3 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x2C))
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#define rSHA1_ADDR_CODE4 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x30))
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#define rSHA1_ADDR_DATA0 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x40))
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#define rSHA1_ADDR_DATA1 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x44))
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#define rSHA1_ADDR_DATA2 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x48))
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#define rSHA1_ADDR_DATA3 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x4C))
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#define rSHA1_ADDR_DATA4 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x50))
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#define rSHA1_ADDR_DATA5 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x54))
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#define rSHA1_ADDR_DATA6 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x58))
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#define rSHA1_ADDR_DATA7 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x5C))
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#define rSHA1_ADDR_DATA8 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x60))
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#define rSHA1_ADDR_DATA9 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x64))
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#define rSHA1_ADDR_DATA10 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x68))
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#define rSHA1_ADDR_DATA11 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x6C))
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#define rSHA1_ADDR_DATA12 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x70))
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#define rSHA1_ADDR_DATA13 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x74))
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#define rSHA1_ADDR_DATA14 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x78))
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#define rSHA1_ADDR_DATA15 (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x7C))
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#define rSHA1_MASTER_MODE (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x80))
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#define rSHA1_MS_START_ADDR (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x84))
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#define rSHA1_VERISON (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x88))
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#define rSHA1_MS_SIZE (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x8C))
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#define rSHA1_FIFO_PARAM (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x90))
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#define rSHA1_FIFO_CMD (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x94))
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#define rSHA1_TX_FIFO_STAT (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0x98))
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#define rSHA1_TX_FIFO (*(volatile u_int32_t *)(SHA1_BASE_ADDR + 0xA0))
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struct sha1_regs {
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volatile u_int32_t *con;
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volatile u_int32_t *swreset;
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volatile u_int32_t *int_src;
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volatile u_int32_t *int_mask;
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volatile u_int32_t *twist;
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volatile u_int32_t *code0;
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volatile u_int32_t *code1;
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volatile u_int32_t *code2;
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volatile u_int32_t *code3;
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volatile u_int32_t *code4;
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volatile u_int32_t *data0;
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volatile u_int32_t *data1;
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volatile u_int32_t *data2;
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volatile u_int32_t *data3;
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volatile u_int32_t *data4;
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volatile u_int32_t *data5;
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volatile u_int32_t *data6;
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volatile u_int32_t *data7;
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volatile u_int32_t *data8;
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volatile u_int32_t *data9;
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volatile u_int32_t *data10;
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volatile u_int32_t *data11;
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volatile u_int32_t *data12;
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volatile u_int32_t *data13;
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volatile u_int32_t *data14;
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volatile u_int32_t *data15;
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volatile u_int32_t *mode;
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volatile u_int32_t *start_addr;
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volatile u_int32_t *ms_size;
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};
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typedef struct sha1_regs sha1_regs;
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struct sha1_status {
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u_int32_t offset;
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u_int32_t cmd;
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u_int32_t length;
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};
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typedef struct sha1_status sha1_status;
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#endif /* __SAMSUNG_SHA1_H */
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