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@@ -0,0 +1,15 @@
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# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
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#
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# This document is the property of Apple Computer, Inc.
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# It is considered confidential and proprietary.
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#
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# This document may not be reproduced or transmitted in any form,
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# in whole or in part, without the express written permission of
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# Apple Computer, Inc.
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#
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LOCAL_DIR := $(GET_LOCAL_DIR)
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OPTIONS += \
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WITH_HW_TIMER=1
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ALL_OBJS += $(LOCAL_DIR)/timer.o
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@@ -0,0 +1,484 @@
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/*
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* Copyright (C) 2007-2009 Apple Inc. All rights reserved.
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* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <arch.h>
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#include <debug.h>
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#include <platform.h>
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#include <platform/clocks.h>
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#include <platform/int.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/hwisr.h>
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#include <sys.h>
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#include <sys/callout.h>
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#include "timer.h"
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/* 16-bit timers */
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#define TIMER_A 0
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#define TIMER_B 1
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#define TIMER_C 2
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#define TIMER_D 3
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/* 32-bit timers */
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#define TIMER_E 4
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#define TIMER_F 5
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#define TIMER_G 6
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#define TIMER_H 7
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/* 64-bit timer */
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#define TIMER_64 8
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#define INVALID_TIMER -1
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#ifndef TIMER_DEADLINE_TIMER
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# if TIMER_DEADLINE_USE16
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# define TIMER_DEADLINE_TIMER TIMER_D
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# else
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# define TIMER_DEADLINE_TIMER TIMER_E
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# endif
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#endif
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/* timer16/32 stuff */
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typedef struct {
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volatile u_int32_t *tcon;
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volatile u_int32_t *tcmd;
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volatile u_int32_t *tdata0;
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volatile u_int32_t *tdata1;
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volatile u_int32_t *tpre;
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volatile u_int32_t *tcnt;
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} timer_regs_t;
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static const timer_regs_t timer_regs_list[] = {
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{ &rTACON, &rTACMD, &rTADATA0, &rTADATA1, &rTAPRE, &rTACNT },
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{ &rTBCON, &rTBCMD, &rTBDATA0, &rTBDATA1, &rTBPRE, &rTBCNT },
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{ &rTCCON, &rTCCMD, &rTCDATA0, &rTCDATA1, &rTCPRE, &rTCCNT },
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{ &rTDCON, &rTDCMD, &rTDDATA0, &rTDDATA1, &rTDPRE, &rTDCNT },
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{ &rTECON, &rTECMD, &rTEDATA0, &rTEDATA1, &rTEPRE, &rTECNT },
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{ &rTFCON, &rTFCMD, &rTFDATA0, &rTFDATA1, &rTFPRE, &rTFCNT },
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{ &rTGCON, &rTGCMD, &rTGDATA0, &rTGDATA1, &rTGPRE, &rTGCNT },
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{ &rTHCON, &rTHCMD, &rTHDATA0, &rTHDATA1, &rTHPRE, &rTHCNT }
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};
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static const timer_regs_t *timer_regs(int timer);
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enum timer_clk {
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PCLK,
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NCLK,
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SLOWCLK,
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};
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typedef struct {
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/* configuration */
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enum timer_clk source_clk;
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uint32_t divider_bits;
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int prescalar;
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/* callout routine */
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void (*ovf_tick)(void);
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void (*mat0_tick)(void);
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void (*mat1_tick)(void);
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} timer_status_t;
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static timer_status_t timer_status[TIMER_H+1];
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enum timer_mode {
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MODE_INTERVAL = 0,
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MODE_PWM = 0x2,
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MODE_PDM = 0x3,
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MODE_ONESHOT_PWM = 0x4,
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MODE_ONESHOT_PDM = 0x5,
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MODE_CAPTURE = 0x6,
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};
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static void setup_timer(int timer, uint32_t data0, uint32_t data1, enum timer_mode mode, bool countdown, bool countdown_start, bool start_polarity);
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static void setup_timer_clk(int timer, enum timer_clk clk, int divider, int prescalar);
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static void start_stop_timer(int timer, bool start);
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static void timer_deadline(void);
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static void (* timer_deadline_func)(void);
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/* timer 64 stuff */
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static u_int64_t read_timer64(void);
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static int timer64_ticks_per_sec; // for system time
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static uint64_t timer64_scale;
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static void timer32_int(void *);
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static void timer16_int(void *);
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static u_int64_t read_timer64(void)
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{
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u_int32_t low, high;
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retry:
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high = rTM64_CNTH;
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low = rTM64_CNTL;
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if (high != rTM64_CNTH)
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goto retry;
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return (u_int64_t)high << 32 | low;
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}
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static u_int32_t read_timer(int timer)
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{
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const timer_regs_t *regs = timer_regs(timer);
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return *regs->tcnt;
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}
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static const timer_regs_t *timer_regs(int timer)
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{
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if (timer == TIMER_64)
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panic("timer_regs: asked for invalid timer registers\n");
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return &timer_regs_list[timer];
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}
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static void setup_timer_clk(int timer, enum timer_clk clk, int divider, int prescalar)
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{
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if (clk == SLOWCLK) {
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timer_status[timer].source_clk = PCLK;
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timer_status[timer].divider_bits = 6;
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} else {
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timer_status[timer].source_clk = clk;
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switch (divider) {
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case 2:
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timer_status[timer].divider_bits = 0;
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break;
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case 4:
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timer_status[timer].divider_bits = 1;
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break;
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case 16:
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timer_status[timer].divider_bits = 2;
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break;
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case 64:
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timer_status[timer].divider_bits = 3;
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break;
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case 1:
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timer_status[timer].divider_bits = 4;
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break;
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default:
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dprintf(DEBUG_CRITICAL, "setup_timer_clk: invalid divider %d\n", divider);
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}
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}
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timer_status[timer].prescalar = prescalar;
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}
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static void setup_timer(int timer, uint32_t data0, uint32_t data1, enum timer_mode mode, bool countdown, bool countdown_start, bool start_polarity)
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{
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start_stop_timer(timer, false);
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switch (timer) {
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case TIMER_A: case TIMER_B: case TIMER_C: case TIMER_D: {
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const timer_regs_t *regs = timer_regs(timer);
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/* setup timer (16 bit) */
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*regs->tcon = (start_polarity ? (1<<11) : 0) |
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(mode << 3) |
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(timer_status[timer].divider_bits<<8) | ((timer_status[timer].source_clk == NCLK) ? (1<<6) : 0) |
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(7<<12); // mode, upcount (no downcount feature), divider, clock source, enable all ints
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*regs->tpre = timer_status[timer].prescalar;
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*regs->tdata0 = data0;
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*regs->tdata1 = data1;
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*regs->tcmd = 2; // initialize the timer
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break;
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}
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case TIMER_E: case TIMER_F: case TIMER_G: case TIMER_H: {
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const timer_regs_t *regs = timer_regs(timer);
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/* setup timer (32 bit) */
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*regs->tcon = (countdown_start ? (1<<28) : 0) |
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(countdown ? (1<<24) : 0) |
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(start_polarity ? (1<<11) : 0) |
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(mode << 3) |
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(timer_status[timer].divider_bits<<8) | ((timer_status[timer].source_clk == NCLK) ? (1<<6) : 0) |
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(7<<12); // mode, downcount, pwm/pdm start bit, divider, clock source, enable all ints
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*regs->tpre = timer_status[timer].prescalar;
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*regs->tdata0 = data0;
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*regs->tdata1 = data1;
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*regs->tcmd = 2; // initialize the timer
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break;
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}
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default:
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panic("setup_timer: timer %d not supported\n", timer);
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}
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}
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static void start_stop_timer(int timer, bool start)
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{
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switch (timer) {
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case TIMER_A: case TIMER_B: case TIMER_C: case TIMER_D:
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case TIMER_E: case TIMER_F: case TIMER_G: case TIMER_H: {
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const timer_regs_t *regs = timer_regs(timer);
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if (start)
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*regs->tcmd = 1; // start it
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else
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*regs->tcmd = 0; // stop it
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break;
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}
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case TIMER_64:
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if (start)
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rTM64_CON &= ~0xf;
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else
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rTM64_CON |= 0xa;
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break;
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default:
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panic("start_stop_timer: timer %d not supported\n", timer);
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}
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}
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int timer_init(u_int32_t timer)
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{
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dprintf(DEBUG_SPEW, "timers_init()\n");
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#ifndef TIMER_NO_INIT
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clock_gate(CLK_TIMER, true);
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/* stop all timers */
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start_stop_timer(TIMER_A, false);
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start_stop_timer(TIMER_B, false);
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start_stop_timer(TIMER_C, false);
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start_stop_timer(TIMER_D, false);
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start_stop_timer(TIMER_E, false);
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start_stop_timer(TIMER_F, false);
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start_stop_timer(TIMER_G, false);
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start_stop_timer(TIMER_H, false);
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start_stop_timer(TIMER_64, false);
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setup_timer_clk(TIMER_A, NCLK, 2, 0);
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setup_timer_clk(TIMER_B, NCLK, 2, 0);
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setup_timer_clk(TIMER_C, NCLK, 2, 0);
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setup_timer_clk(TIMER_D, NCLK, 2, 0);
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setup_timer_clk(TIMER_E, NCLK, 2, 0);
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setup_timer_clk(TIMER_F, NCLK, 2, 0);
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setup_timer_clk(TIMER_G, NCLK, 2, 0);
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setup_timer_clk(TIMER_H, NCLK, 2, 0);
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/* set up the 64-bit timer */
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rTM64_CON = 0xa; // disable it
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rTM64_DATA0L = 0xffffffff;
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rTM64_DATA0H = 0xffffffff;
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rTM64_DATA1L = 0xffffffff;
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rTM64_DATA1H = 0xffffffff;
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rTM64_CON = (3<<15) | (1 << 4); // set nclk source, prescalar at /2, enable
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/* calculate how fast timer64 is running */
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timer64_ticks_per_sec = clock_get_frequency(CLK_NCLK) / 2;
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#else
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# ifndef TIMER_TICK_RATE
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# error TIMER_TICK_RATE not defined but we did not init the timebase
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# endif
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timer64_ticks_per_sec = TIMER_TICK_RATE;
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#endif
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// Precompute a 44.20 fixed-point representation of the microsecond to ticks conversion rate.
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// This limits the maximum number of microseconds that can be represented to 44 bits worth of ticks.
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timer64_scale = ((uint64_t)timer64_ticks_per_sec << 20) / (1000 * 1000);
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dprintf(DEBUG_SPEW, "timer64 running at %u Hz, will wrap around in %llu secs\n",
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timer64_ticks_per_sec, 0xffffffffffffffffULL / timer64_ticks_per_sec);
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dprintf(DEBUG_SPEW, "using 64-bit timer for system time\n");
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/* install interrupt handler */
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#if TIMER_DEADLINE_USE16
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install_int_handler(INT_TIMERIRQ, &timer16_int, (void *)1);
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unmask_int(INT_TIMERIRQ);
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#else
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install_int_handler(INT_TIMERFIQ, &timer32_int, (void *)1);
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unmask_int(INT_TIMERFIQ);
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#endif
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return 0;
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}
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void timer_gpio(int timer, int level)
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{
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setup_timer(timer, 0, 0, MODE_PWM, false, false, level);
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}
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static void timer_handle_int(int timer, u_int32_t status)
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{
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if (status & (1<<2)) {
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// overflow
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if (timer_status[timer].ovf_tick)
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timer_status[timer].ovf_tick();
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}
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if (status & (1<<1)) {
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// int1
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if (timer_status[timer].mat1_tick)
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timer_status[timer].mat1_tick();
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}
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if (status & (1<<0)) {
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// int0
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if (timer_status[timer].mat0_tick)
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timer_status[timer].mat0_tick();
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}
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}
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static void timer16_int(void *arg)
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{
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u_int32_t tcon;
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tcon = rTACON;
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if (tcon & (7<<16)) {
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timer_handle_int(TIMER_A, tcon >> 16);
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rTACON |= tcon & (7<<16);
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}
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tcon = rTBCON;
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if (tcon & (7<<16)) {
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timer_handle_int(TIMER_B, tcon >> 16);
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rTBCON |= tcon & (7<<16);
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}
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tcon = rTCCON;
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if (tcon & (7<<16)) {
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timer_handle_int(TIMER_C, tcon >> 16);
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rTCCON |= tcon & (7<<16);
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}
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tcon = rTDCON;
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if (tcon & (7<<16)) {
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timer_handle_int(TIMER_D, tcon >> 16);
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rTDCON |= tcon & (7<<16);
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}
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}
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static void timer32_int(void *arg)
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{
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u_int32_t tm32_status, tm32_ack, status, cnt;
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tm32_status = rTM32_INT;
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tm32_ack = 0;
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cnt = 0;
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#if TIMER_VERSION != 0
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status = (tm32_status >> (cnt * 8)) & 0x7;
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timer_handle_int(TIMER_H, status);
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tm32_ack |= (status << (cnt * 8));
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cnt++;
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#endif
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status = (tm32_status >> (cnt * 8)) & 0x7;
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timer_handle_int(TIMER_G, status);
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tm32_ack |= (status << (cnt * 8));
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cnt++;
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status = (tm32_status >> (cnt * 8)) & 0x7;
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timer_handle_int(TIMER_F, status);
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tm32_ack |= (status << (cnt * 8));
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cnt++;
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status = (tm32_status >> (cnt * 8)) & 0x7;
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timer_handle_int(TIMER_E, status);
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tm32_ack |= (status << (cnt * 8));
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cnt++;
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||||
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rTM32_INT = tm32_ack;
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}
|
||||
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||||
static void timer_deadline(void)
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{
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||||
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||||
// printf("deadline interrupt at %llu\n", read_timer64());
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/* stop the timer */
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start_stop_timer(TIMER_DEADLINE_TIMER, false);
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||||
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||||
/* call the handler */
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||||
if (timer_deadline_func)
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timer_deadline_func();
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}
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||||
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u_int64_t timer_get_ticks()
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{
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return read_timer64();
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}
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u_int32_t timer_get_tick_rate(void)
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{
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return timer64_ticks_per_sec;
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}
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||||
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utime_t timer_ticks_to_usecs(uint64_t ticks)
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{
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return (ticks * 1000 * 1000) / timer64_ticks_per_sec;
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}
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||||
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uint64_t timer_usecs_to_ticks(utime_t usecs)
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{
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return (usecs * timer64_scale) >> 20;
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}
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||||
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||||
void timer_stop_all(void)
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{
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#ifndef TIMER_NO_INIT
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/* stop all timers */
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start_stop_timer(TIMER_A, false);
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start_stop_timer(TIMER_B, false);
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start_stop_timer(TIMER_C, false);
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start_stop_timer(TIMER_D, false);
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||||
start_stop_timer(TIMER_E, false);
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||||
start_stop_timer(TIMER_F, false);
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||||
start_stop_timer(TIMER_G, false);
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||||
start_stop_timer(TIMER_H, false);
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start_stop_timer(TIMER_64, false);
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||||
#endif
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||||
}
|
||||
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||||
void timer_deadline_enter(uint64_t deadline, void (* callback)(void))
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||||
{
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||||
uint64_t ticks;
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||||
uint32_t decr;
|
||||
|
||||
timer_deadline_func = callback;
|
||||
if (callback != NULL) {
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||||
/* convert absolute deadline to relative time */
|
||||
ticks = read_timer64();
|
||||
if (deadline <= ticks) {
|
||||
// printf("setting deadline %llu before current time %llu\n", deadline, ticks);
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||||
deadline = 1;
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||||
} else {
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||||
// printf("setting deadline %llu (0x%llx away)\n", deadline, deadline - ticks);
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||||
deadline -= ticks;
|
||||
}
|
||||
|
||||
/* clamp the deadline to our maximum */
|
||||
#if TIMER_DEADLINE_USE16
|
||||
decr = (deadline > 0xffff) ? 0xffff : deadline;
|
||||
#else
|
||||
decr = (deadline > 0xffffffff) ? 0xffffffff : deadline;
|
||||
#endif
|
||||
// printf(" decr 0x%x\n", decr);
|
||||
|
||||
/*
|
||||
* Start the timer in interval mode. We will stop it when we handle the
|
||||
* interrupt, so it doesn't really matter as long as we get an interrupt after
|
||||
* (decr) ticks or so.
|
||||
*/
|
||||
timer_status[TIMER_DEADLINE_TIMER].mat0_tick = timer_deadline;
|
||||
setup_timer(TIMER_DEADLINE_TIMER, decr, 0, MODE_INTERVAL, false, false, 0);
|
||||
start_stop_timer(TIMER_DEADLINE_TIMER, true);
|
||||
} else {
|
||||
/* stop the timer */
|
||||
start_stop_timer(TIMER_DEADLINE_TIMER, false);
|
||||
}
|
||||
}
|
||||
|
||||
u_int32_t timer_get_entropy(void)
|
||||
{
|
||||
return arch_get_entropy(&rTM64_CNTL);
|
||||
}
|
||||
|
||||
void wdt_enable(void)
|
||||
{
|
||||
rWDTCON = (1 << 20) | (15 << 16) | (4 << 12) | (0xA << 8);
|
||||
}
|
||||
|
||||
void wdt_chip_reset(void)
|
||||
{
|
||||
rWDTCON = (1 << 20) | (0 << 16) | (0 << 15) | (0 << 12) | (0 << 8) | (0 << 0);
|
||||
}
|
||||
@@ -0,0 +1,121 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Computer, Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Computer, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __SAMSUNG_TIMER_H
|
||||
#define __SAMSUNG_TIMER_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
/**
|
||||
* Timer A
|
||||
*/
|
||||
#define rTACON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x0))
|
||||
#define rTACMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x4))
|
||||
#define rTADATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x8))
|
||||
#define rTADATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xC))
|
||||
#define rTAPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10))
|
||||
#define rTACNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x14))
|
||||
/**
|
||||
* Timer B
|
||||
*/
|
||||
#define rTBCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x20))
|
||||
#define rTBCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x24))
|
||||
#define rTBDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x28))
|
||||
#define rTBDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x2C))
|
||||
#define rTBPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x30))
|
||||
#define rTBCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x34))
|
||||
/**
|
||||
* Timer C
|
||||
*/
|
||||
#define rTCCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x40))
|
||||
#define rTCCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x44))
|
||||
#define rTCDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x48))
|
||||
#define rTCDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x4C))
|
||||
#define rTCPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x50))
|
||||
#define rTCCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x54))
|
||||
/**
|
||||
* Timer D
|
||||
*/
|
||||
#define rTDCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x60))
|
||||
#define rTDCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x64))
|
||||
#define rTDDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x68))
|
||||
#define rTDDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x6C))
|
||||
#define rTDPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x70))
|
||||
#define rTDCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x74))
|
||||
|
||||
//64-Bit Timer Register
|
||||
#define rTM64_CNTH (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x80))
|
||||
#define rTM64_CNTL (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x84))
|
||||
#define rTM64_CON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x88))
|
||||
|
||||
#define rTM64_DATA0H (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x8C))
|
||||
#define rTM64_DATA0L (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x90))
|
||||
#define rTM64_DATA1H (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x94))
|
||||
#define rTM64_DATA1L (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x98))
|
||||
/**
|
||||
* Timer E
|
||||
*/
|
||||
#define rTECON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xA0))
|
||||
#define rTECMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xA4))
|
||||
#define rTEDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xA8))
|
||||
#define rTEDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xAC))
|
||||
#define rTEPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xB0))
|
||||
#define rTECNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xB4))
|
||||
/**
|
||||
* Timer F
|
||||
*/
|
||||
#define rTFCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xC0))
|
||||
#define rTFCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xC4))
|
||||
#define rTFDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xC8))
|
||||
#define rTFDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xCC))
|
||||
#define rTFPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xD0))
|
||||
#define rTFCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xD4))
|
||||
/**
|
||||
* Timer G
|
||||
*/
|
||||
#define rTGCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xE0))
|
||||
#define rTGCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xE4))
|
||||
#define rTGDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xE8))
|
||||
#define rTGDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xEC))
|
||||
#define rTGPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xF0))
|
||||
#define rTGCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xF4))
|
||||
/**
|
||||
* Timer H
|
||||
*/
|
||||
#define rTHCON (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x100))
|
||||
#define rTHCMD (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x104))
|
||||
#define rTHDATA0 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x108))
|
||||
#define rTHDATA1 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10C))
|
||||
#define rTHPRE (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x100))
|
||||
#define rTHCNT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x104))
|
||||
|
||||
#if TIMER_VERSION == 0
|
||||
#define rTM32_INT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0xF8))
|
||||
#else
|
||||
#define rTM32_INT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x118))
|
||||
#endif
|
||||
|
||||
#define rTM_INT (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10000))
|
||||
/**
|
||||
* Timer counter register (RO)
|
||||
*/
|
||||
#define rTM32_CNT_E (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10004))
|
||||
#define rTM32_CNT_F (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10008))
|
||||
#define rTM32_CNT_G (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x1000C))
|
||||
|
||||
#define rTM64_CNTH2 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10010))
|
||||
#define rTM64_CNTL2 (*(volatile u_int32_t *)(TIMER_BASE_ADDR + 0x10014))
|
||||
|
||||
|
||||
#define rWDTCON (*(volatile u_int32_t *)(WDT_BASE_ADDR + 0x00))
|
||||
#define rWDTCNT (*(volatile u_int32_t *)(WDT_BASE_ADDR + 0x04))
|
||||
|
||||
#endif /* __SAMSUNG_TIMER_H */
|
||||
Reference in new issue
Block a user