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# Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
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#
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# This document is the property of Apple Computer, Inc.
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# It is considered confidential and proprietary.
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#
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# This document may not be reproduced or transmitted in any form,
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# in whole or in part, without the express written permission of
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# Apple Computer, Inc.
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#
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LOCAL_DIR := $(GET_LOCAL_DIR)
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OPTIONS += \
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WITH_HW_USBPHY=1
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ALL_OBJS += $(LOCAL_DIR)/usbphy.o
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/*
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* Copyright (C) 2007-2009 Apple Inc. All rights reserved.
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* Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <platform.h>
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#include <platform/clocks.h>
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#include <platform/power.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/usbconfig.h>
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#include <sys.h>
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#include "usbphy.h"
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static bool usb_phy_powered = false;
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// <rdar://problem/10320827> Add support for multiple USB OTG controllers to iBoot
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// <rdar://problem/10304507> G1 USBBPHY USB OTG2 bit assignments are totally inconsistent
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#if WITH_CONJOINED_USB_PHYS
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#if USBPHY_VERSION > 2
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#error "Conjoined USB PHYs not compatible with PHY version > 2"
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#endif
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#define SELECTED_PHY (1)
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#define SET_REG(reg, value) set_reg(reg, SELECTED_PHY, reg##_SHIFT, (value))
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#define SET_REG_BITS(reg, value, mask) set_reg_bits(reg, SELECTED_PHY, reg##_SHIFT, (value), (mask))
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#define GET_REG(reg) get_reg(reg, SELECTED_PHY, reg##_SHIFT)
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static void set_reg(volatile u_int32_t *reg, int index, int shift, u_int32_t value)
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{
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u_int32_t mask = ((1 << shift) - 1) << (shift * index);
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*reg = (*reg & ~mask) | (value << (shift * index));
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}
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static void set_reg_bits(volatile u_int32_t *reg, int index, int shift, u_int32_t value, u_int32_t mask)
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{
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mask = mask << (shift * index);
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*reg = (*reg & ~mask) | (value << (shift * index));
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}
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static u_int32_t get_reg(volatile u_int32_t *reg, int index, int shift)
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{
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return (*reg >> shift) & ((1 << shift) - 1);
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}
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#else
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#define SET_REG(reg, value) *(reg) = (value)
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#define SET_REG_BITS(reg, value, mask) *(reg) = (*(reg) & ~(mask)) | (value)
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#define GET_REG(reg) *(reg)
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#endif
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static void gate_clocks(bool enable)
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{
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if (enable) {
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#if USBPHY_VERSION > 2
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clock_gate(CLK_UPERF, true);
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#endif
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clock_gate(CLK_USBOTG, true);
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clock_gate(CLK_USBPHY, true);
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} else {
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clock_gate(CLK_USBOTG, false);
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clock_gate(CLK_USBPHY, false);
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#if USBPHY_VERSION > 2
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clock_gate(CLK_UPERF, false);
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#endif
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}
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}
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//---------------------------------------------------------------------------
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// FUNCTION: usbphy_power_up
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//
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// DESCRIPTION: Does initial powering up to bring up the PHY
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//
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// RETURN: None
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//
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// NOTES: This should be one of the first things done upon startup.
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//---------------------------------------------------------------------------
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void usbphy_power_up(void)
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{
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u_int32_t clk_sel = 0;
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if (usb_phy_powered) return;
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platform_power_set_gate(PWRBIT_USB, true);
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spin(10*1000);
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gate_clocks(true);
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// Clear the StopPclk & GateHclk bits in the power and clock gating register
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*USB_PCGCCTL &= ~(PCGCCTL_StopPclk | PCGCCTL_GateHclk);
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spin(100);
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#if USBPHY_VERSION > 1
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*USB_USBHOSTSET = (1 << 9); // enable hsic, this will cause STB and DAT to stay low
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#endif
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switch (clock_get_frequency(CLK_USBPHYCLK)) {
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case 12000000UL : clk_sel = 0; break;
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case 24000000UL : clk_sel = 1; break;
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case 48000000UL : clk_sel = 2; break;
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default : clk_sel = 3; break;
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}
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#if USBPHY_VERSION > 0
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SET_REG(USB_PHYPWR, (0UL<<4) | // powerup analog block
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(0UL<<3) | // powerup OTG block
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(USBPHY_CLK_TYPE << 1) | // select the reference clock
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(0UL<<0)); // disable suspend signal for power save
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SET_REG(USB_UVLDCON, (1 << 2)); // Set vbus_vld_ext_sel
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#else
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*USB_PHYPWR = (0UL<<4) | // powerup analog block
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(0UL<<3) | // powerup XO block
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(USBPHY_CLK_TYPE << 2) | // select the reference for XO block
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(0UL<<1) | // powerup PLL
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(0UL<<0); // disable suspend signal for power save
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/* Correct the field assinment for version 0 */
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clk_sel ^= 1;
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#endif
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#ifdef USBPHY_UOTGTUNE1
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SET_REG(USB_UOTGTUNE1, USBPHY_UOTGTUNE1);
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#endif
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#ifdef USBPHY_UOTGTUNE2
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SET_REG(USB_UOTGTUNE2, USBPHY_UOTGTUNE2);
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#endif
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spin(10);
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#if WITH_CONJOINED_USB_PHYS
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// <rdar://problem/10491915> G1: Implement G1-specific USB PHY settings
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*USB_URSV |= (1 << 4);
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#endif
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SET_REG_BITS(USB_PHYCON, clk_sel, 0x3);
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// reset the PHY
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SET_REG_BITS(USB_URSTCON, 1, 1);
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spin(20); // need to assert for at least 10us
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SET_REG_BITS(USB_URSTCON, 0, 1);
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spin(1000); // need to wait for at least 805us
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usb_phy_powered = true;
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}
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void usbphy_enable_pullup(void)
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{
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if (!usb_phy_powered)
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return;
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// Enable D+ PU
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SET_REG_BITS(USB_UVLDCON, (1 << 1), (1 << 1)); // Set vbus_vld_ext
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}
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//---------------------------------------------------------------------------
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// FUNCTION: usbphy_power_down
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//
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// DESCRIPTION: Powers down the PHY upon USB shutdown
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//
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// RETURN: None
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//
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// NOTES: This should be one of the last things done upon shutdown.
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//---------------------------------------------------------------------------
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void usbphy_power_down(void)
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{
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platform_power_set_gate(PWRBIT_USB, true);
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gate_clocks(true);
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// set bits 0-4 to 1 to power down the PHY
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SET_REG(USB_PHYPWR, (1UL<<5)-1);
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#if USBPHY_VERSION == 0
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// assert S/W Reset for PHY_CLK and HCLK Domains
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SET_REG_BITS(USB_URSTCON, (1<<2)|(1<<1), (1<<2)|(1<<1));
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#endif
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// assert S/W Reset for PHY
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SET_REG_BITS(USB_URSTCON, (1<<0), (1<<0));
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spin(1000);
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#if USBPHY_VERSION > 0
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*USB_UVLDCON &= ~(1 << 1); // Clear vbus_vld_ext
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SET_REG_BITS(USB_UVLDCON, 0, (1<<1));
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#endif
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gate_clocks(false);
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platform_power_set_gate(PWRBIT_USB, false);
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usb_phy_powered = false;
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}
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bool usbphy_is_cable_connected(void)
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{
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bool connected;
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if (!usb_phy_powered) {
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#if USBPHY_VERSION > 2
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clock_gate(CLK_UPERF, true);
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#endif
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clock_gate(CLK_USBPHY, true);
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}
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connected = (GET_REG(USB_UCONDET) & 1) != 0;
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if (!usb_phy_powered) {
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#if USBPHY_VERSION > 2
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clock_gate(CLK_UPERF, false);
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#endif
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clock_gate(CLK_USBPHY, false);
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}
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return connected;
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}
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bool usbphy_set_dpdm_monitor(int select)
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{
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u_int32_t bits;
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switch (select) {
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case kUSB_DP:
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bits = 1 << 1;
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break;
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case kUSB_DM:
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bits = 2 << 1;
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break;
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case kUSB_NONE:
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bits = 0 << 1;
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break;
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#if USBPHY_VERSION >= 4
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case kUSB_DCD:
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bits = (1 << 14) | (1 << 13) | (1 << 10) | (1 << 9) | (1 << 1);
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break;
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case kUSB_CP1:
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bits = (1 << 12) | (1 << 11) | (1 << 10) | (1 << 9) | (2 << 1);
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break;
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#endif
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default:
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return false;
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};
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if (!usb_phy_powered) {
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#if USBPHY_VERSION > 2
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clock_gate(CLK_UPERF, true);
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#endif
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clock_gate(CLK_USBPHY, true);
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}
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#if USBPHY_VERSION >= 4
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*USB_UPADCON = (*USB_UPADCON & ((0x3f << 3) | (1 << 0))) | bits;
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#else
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SET_REG_BITS(USB_UPADCON, bits, 3 << 1);
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#endif
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if (!usb_phy_powered) {
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#if USBPHY_VERSION > 2
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clock_gate(CLK_UPERF, false);
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#endif
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clock_gate(CLK_USBPHY, false);
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}
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return true;
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}
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#if WITH_DEVICETREE
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void usbphy_update_device_tree(DTNode *node)
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{
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u_int32_t propSize;
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char *propName;
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void *propData;
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u_int32_t phy_tuning2_val;
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phy_tuning2_val = 0;
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#ifdef USBPHY_UOTGTUNE2
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phy_tuning2_val = USBPHY_UOTGTUNE2;
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#endif
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// Fill in the phy-tuning-val property
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propName = "phy-tuning-val";
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if (FindProperty(node, &propName, &propData, &propSize)) {
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if (propSize >= sizeof(phy_tuning2_val)) {
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*(u_int32_t *)propData = phy_tuning2_val;
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}
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}
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}
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#endif
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@@ -0,0 +1,52 @@
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/*
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* Copyright (C) 2007 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Computer, Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Computer, Inc.
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*/
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#ifndef __SAMSUNG_USBPHY_H
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#define __SAMSUNG_USBPHY_H
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#include <platform/soc/hwregbase.h>
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#include <sys/types.h>
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#include <drivers/usbphy.h>
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// HW-OTG control registers
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#define USB_PCGCCTL ((volatile u_int32_t *)(USBOTG_BASE_ADDR + 0x0E00))
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#define PCGCCTL_PhySuspended (1UL << 4)
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#define PCGCCTL_RstPdwnModule (1UL << 3)
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#define PCGCCTL_PwrClmp (1UL << 2)
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#define PCGCCTL_GateHclk (1UL << 1)
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#define PCGCCTL_StopPclk (1UL << 0)
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// HS-OTG Phy control registers
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#define USB_PHYPWR ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0000))
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#define USB_PHYCON ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0004))
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#define USB_URSTCON ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0008))
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#define USB_UVLDCON ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x001C))
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#define USB_UCONDET ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0028))
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#define USB_URESCON ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0034))
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#define USB_UOTGTUNE1 ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0040))
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#define USB_UOTGTUNE2 ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0044))
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#define USB_UPADCON ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0048))
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#define USB_USBHOSTSET ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0060))
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#define USB_URSV ((volatile u_int32_t *)(USBPHY_BASE_ADDR + 0x0100))
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// <rdar://problem/10320827> Add support for multiple USB OTG controllers to iBoot
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// <rdar://problem/10304507> G1 USBBPHY USB OTG2 bit assignments are totally inconsistent
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#define USB_PHYPWR_SHIFT 5
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#define USB_PHYCON_SHIFT 5
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#define USB_URSTCON_SHIFT 5
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#define USB_UVLDCON_SHIFT 9
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#define USB_UCONDET_SHIFT 10
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#define USB_UOTGTUNE1_SHIFT 11
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#define USB_UOTGTUNE2_SHIFT 13
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#define USB_UPADCON_SHIFT 3
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#endif /* ! __SAMSUNG_USBPHY_H */
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