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/*
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* Copyright (C) 2013-2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <assert.h>
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#include <drivers/mipi.h>
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#include <drivers/mipi/mipi.h>
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#include <platform.h>
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#include <platform/clocks.h>
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#include <platform/soc/hwclocks.h>
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#include <platform/soc/chipid.h>
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#include <target/gpiodef.h>
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#include "dsim.h"
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#define CEIL_DIV(a,b) (((a)/(b)) + (((a) % (b)) ? 1 : 0))
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static u_int32_t lane_count;
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static struct phy_settings *phy_settings_info;
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static void mipi_program_phy_test_codes(struct phy_settings *phy_settings_info);
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static void mipi_program_phy_hsfreqrange(struct phy_settings *phy_settings_info);
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static void mipi_phy_write(uint32_t address, uint8_t *data, uint32_t length);
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static void mipi_phy_read_mod_write(uint32_t address, uint8_t mask, uint8_t shift, uint8_t val);
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static void mipi_phy_test_reset(bool reset);
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static void mipi_phy_toggle_shutdownz(void);
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static bool mipi_is_interface_enabled();
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/*
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* The Programming sequences of MIPI DSI can be broken down in the following parts:
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* Static configurations
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* Main sequence
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* Sequence for generic packets
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*/
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int mipi_dsim_init(struct display_timing *timing, enum colorspace color)
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{
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const char *env;
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uint32_t dpi_color_coding, vid_size, bytes_per_pixel;
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uint64_t lane_byte_clock_period, lane_byte_clock, pixel_clock;
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uint64_t esc_clock;
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uint32_t total_pixels_per_line;
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uint32_t status_mask;
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uint32_t cmd_mode;
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uint32_t outvact_lpcmd_time, invact_lpcmd_time;
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uint32_t hsa_time, hbp_time, hline_time, hss_time;
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uint64_t time_calculation;
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uint64_t hline_time_ns;
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uint32_t max_rd_time;
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uint32_t pll_config;
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uint32_t hs_freq_range;
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mipi_t *display_config;
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dprintf(DEBUG_CRITICAL, "mipi_dsim_init()\n");
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env = env_get("display-timing");
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if (env == 0) env = "";
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pll_config = 0;
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hs_freq_range = 0;
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display_config = (mipi_t *)(timing->display_config);
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assert(display_config != NULL);
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phy_settings_info = &display_config->target_phy_settings;
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if (phy_settings_info == 0) {
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panic("Failed to find display timing info");
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}
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// Extract Lane configuration
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lane_count = display_config->lanes;
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#if DSIM_VERSION > 1
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// Extract PLL configuration
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pll_config = DSIM_TOP_PLL_PARAM_P(display_config->pll_p);
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pll_config |= DSIM_TOP_PLL_PARAM_M(display_config->pll_m);
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pll_config |= DSIM_TOP_PLL_PARAM_N(display_config->pll_n);
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dprintf(DEBUG_CRITICAL,"pll_config 0x%x\n", pll_config);
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// Extract frequence range
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hs_freq_range = display_config->hsfreq;
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#endif //DSIM_VERSION
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switch (timing->display_depth){
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case 16:
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dpi_color_coding = DPI_COLOR_CODING_BIT16_CONF1;
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vid_size = timing->h_active;
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break;
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case 18:
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dpi_color_coding = DPI_COLOR_CODING_BIT18_CONF1;
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vid_size = timing->h_active & ~3;
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break;
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case 24:
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dpi_color_coding = DPI_COLOR_CODING_BIT24;
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vid_size = timing->h_active & ~1;
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break;
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case 30:
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dpi_color_coding = DPI_COLOR_CODING_BIT30;
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vid_size = timing->h_active;
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break;
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default:
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panic("unexpected display depth");
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}
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bytes_per_pixel = timing->display_depth / 8;
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clock_gate(CLK_MIPI, true);
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#if DSIM_VERSION > 1
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rDSIM_TOP_PLL_CTRL = DSIM_TOP_PLL_CTRL_PLL_CFG_SEL_PHY;
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#endif //DSIM_VERSION
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//Reset the block if we detect HW errors
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uint32_t tmp = rDSIM_CORE_INT_ST1;
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if ((tmp & DSIM_CORE_INT_ST1_ERRORS) != 0) {
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clock_reset_device(CLK_MIPI);
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}
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rDSIM_CORE_INT_MSK0 = 0;
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rDSIM_CORE_INT_MSK1 = 0;
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//Configure byte clock dividers
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rDSIM_CORE_CLKMGR_CFG = (DSIM_CORE_CLKMGR_CFG_TO_CLK_DIVISION(1) | DSIM_CORE_CLKMGR_CFG_TX_ESC_CLK_DIVISION(display_config->esc_div));
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rDSIM_CORE_MODE_CFG = DSIM_CORE_MODE_CFG_COMMAND_MODE;
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#ifndef TARGET_PHY_STOP_WAIT_TIME
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#define TARGET_PHY_STOP_WAIT_TIME 0xf
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#endif //TARGET_PHY_STOP_WAIT_TIME
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//Configure PHY lanes
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rDSIM_CORE_PHY_IF_CFG = DSIM_CORE_PHY_IF_CFG_PHY_STOP_WAIT_TIME(TARGET_PHY_STOP_WAIT_TIME) | DSIM_CORE_PHY_IF_CFG_N_LANES(lane_count - 1);
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//Configure packet handler
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rDSIM_CORE_PCKHDL_CFG = DSIM_CORE_PCKHDL_CFG_BTA_EN | DSIM_CORE_PCKHDL_CFG_ECC_RX_EN | DSIM_CORE_PCKHDL_CFG_CRC_RX_EN;
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//Don't support virtual channels
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rDSIM_CORE_DPI_VCID = 0;
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//Configure pixel map
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rDSIM_CORE_DPI_COLOR_CODING = dpi_color_coding;
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rDSIM_TOP_PIXEL_REMAP = dpi_color_coding;
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//rDSIM_CORE_DPI_CFG_POL = (timing->neg_hsync << 2) | (timing->neg_vsync << 1) | (timing->neg_vden << 0);
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rDSIM_CORE_DPI_CFG_POL = 0;
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//Configure low power mode
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rDSIM_CORE_VID_MODE_CFG = (DSIM_CORE_VID_MODE_CFG_LP_CMD_EN | DSIM_CORE_VID_MODE_CFG_LP_VFP_EN | DSIM_CORE_VID_MODE_CFG_LP_VACT_EN | DSIM_CORE_VID_MODE_CFG_LP_HFP_EN | DSIM_CORE_VID_MODE_CFG_LP_HBP_EN);
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#if DSIM_VERSION > 1
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rDSIM_CORE_VID_MODE_CFG |= (DSIM_CORE_VID_MODE_CFG_LP_VBP_EN | DSIM_CORE_VID_MODE_CFG_LP_VSA_EN);
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#endif
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rDSIM_CORE_VID_MODE_CFG |= DSIM_CORE_VID_MODE_CFG_VID_MODE_TYPE_HORIZONTALEXPANSION;
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//Configure video packetizing
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rDSIM_CORE_VID_PKT_SIZE = timing->h_active;
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// LEAVE DEFAULT VID_NUM_CHUNKS VID_NULL_SIZE;
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//Configure video timing
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pixel_clock = clock_get_frequency(CLK_VCLK0);
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lane_byte_clock = CEIL_DIV(clock_get_frequency(CLK_MIPI), 8);
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lane_byte_clock_period = CEIL_DIV(1000000000, lane_byte_clock);
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total_pixels_per_line = timing->h_active + timing->h_front_porch + timing->h_pulse_width + timing->h_back_porch;
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time_calculation = (timing->h_pulse_width * lane_byte_clock);
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time_calculation = CEIL_DIV(time_calculation, pixel_clock);
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hsa_time = time_calculation & UINT32_MAX;
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time_calculation = (timing->h_back_porch * lane_byte_clock);
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time_calculation = CEIL_DIV(time_calculation, pixel_clock);
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hbp_time = time_calculation & UINT32_MAX;
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time_calculation = (total_pixels_per_line * lane_byte_clock);
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time_calculation = CEIL_DIV(time_calculation, pixel_clock);
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hline_time = time_calculation & UINT32_MAX;
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rDSIM_CORE_VID_HSA_TIME = hsa_time;
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rDSIM_CORE_VID_HBP_TIME = hbp_time;
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rDSIM_CORE_VID_HLINE_TIME = hline_time;
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rDSIM_CORE_VID_VSA_LINES = timing->v_pulse_width;
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rDSIM_CORE_VID_VBP_LINES = timing->v_back_porch;
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rDSIM_CORE_VID_VACTIVE_LINES = timing->v_active;
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// Configure LP time to send commands
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//<rdar://problem/15320588> Synopsys Mipi dsi: outvact_lpcmd_time programming recommendation seems incorrect
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//The synopsys recommended values do not support sending commands while video is active. SEG has provided a WA as explained on the above
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//radar
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hline_time_ns = CEIL_DIV(pixel_clock, 1000);
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hline_time_ns = CEIL_DIV(1000000000, hline_time_ns);
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hline_time_ns *= total_pixels_per_line;
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hline_time_ns = CEIL_DIV(hline_time_ns, 1000); //ns
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esc_clock = lane_byte_clock_period * display_config->esc_div;
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hss_time = 4 * lane_byte_clock_period;
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outvact_lpcmd_time = (hline_time_ns) - hss_time - (TARGET_HS_2_LP_DATA_TIME * lane_byte_clock_period)
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- (TARGET_LP_2_HS_DATA_TIME * lane_byte_clock_period) - (22 * esc_clock) - (2 * esc_clock);
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outvact_lpcmd_time = CEIL_DIV(outvact_lpcmd_time, (2 * 8 * esc_clock));
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rDSIM_CORE_VID_VFP_LINES = timing->v_front_porch - CEIL_DIV(256, outvact_lpcmd_time);
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max_rd_time = hline_time;
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//Set outvact_lpcmd_time to 0 to force sending the command on the last line
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outvact_lpcmd_time = 0;
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invact_lpcmd_time = 0;
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rDSIM_CORE_DPI_LP_CMD_TIM = (outvact_lpcmd_time << 16) | (invact_lpcmd_time << 0);
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//Disable 3D capabilities
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rDSIM_CORE_SDF_3D = 0;
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rDSIM_CORE_LPCLK_CTRL = 0;
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//Configure PHY timing
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rDSIM_CORE_PHY_TMR_CFG = ((TARGET_HS_2_LP_DATA_TIME & 0xFF) << 24) | ((TARGET_LP_2_HS_DATA_TIME & 0xFF) << 16) | max_rd_time;
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rDSIM_CORE_PHY_TMR_LPCLK_CFG = (TARGET_HS_2_LP_CLOCK_TIME << 16) | (TARGET_LP_2_HS_CLOCK_TIME << 0);
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//Configure packet transmission type
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cmd_mode = DSIM_CORE_CMD_MODE_CFG_GEN_LW_TX_LP |
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DSIM_CORE_CMD_MODE_CFG_GEN_SR_2P_TX_LP |
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DSIM_CORE_CMD_MODE_CFG_GEN_SR_1P_TX_LP |
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DSIM_CORE_CMD_MODE_CFG_GEN_SR_0P_TX_LP |
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DSIM_CORE_CMD_MODE_CFG_GEN_SW_2P_TX_LP |
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DSIM_CORE_CMD_MODE_CFG_GEN_SW_1P_TX_LP |
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DSIM_CORE_CMD_MODE_CFG_GEN_SW_0P_TX_LP;
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#if DSIM_VERSION == 1
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cmd_mode |= DSIM_CORE_CMD_MODE_CFG_MAX_RD_PKT_SIZE_LP |
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DSIM_CORE_CMD_MODE_CFG_DCS_LW_TX_LP |
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DSIM_CORE_CMD_MODE_CFG_DCS_SR_0P_TX_LP |
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DSIM_CORE_CMD_MODE_CFG_DCS_SW_1P_TX_LP |
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DSIM_CORE_CMD_MODE_CFG_DCS_SW_0P_TX_LP;
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#endif //DSIM_VERSION
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rDSIM_CORE_CMD_MODE_CFG = cmd_mode;
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#if DSIM_VERSION == 1
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//PHY power up
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rDSIM_CORE_PWR_UP = DSIM_CORE_PWR_UP_SHUTDOWNZ;
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#endif
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mipi_phy_test_reset( false );
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mipi_phy_test_reset( false );
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mipi_phy_test_reset( true );
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#if DSIM_VERSION > 1
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// Configure PLL if needed
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if (pll_config != 0) {
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rDSIM_TOP_PLL_CTRL |= DSIM_TOP_PLL_CTRL_SEQ_OW_ON;
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//PHY power up
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rDSIM_CORE_PWR_UP = DSIM_CORE_PWR_UP_SHUTDOWNZ;
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//PHY reset
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rDSIM_CORE_PHY_RSTZ = DSIM_CORE_PHY_RSTZ_PHY_ENABLECLK;
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rDSIM_TOP_PLL_CTRL |= DSIM_TOP_PLL_CTRL_CLKSELPLL_PLLCLK | DSIM_TOP_PLL_CTRL_HSFREQRANGE(hs_freq_range);
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rDSIM_TOP_PLL_CTRL |= DSIM_TOP_PLL_CTRL_SHADOW_CLEAR;
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//typically becomes 0 in the first read
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while ((rDSIM_TOP_PLL_CTRL & DSIM_TOP_PLL_CTRL_SHADOW_CLEAR) != 0);
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rDSIM_TOP_PLL_PARAM = DSIM_TOP_PLL_PARAM_VCOCAP(TARGET_PLL_VCO_CAP) |
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DSIM_TOP_PLL_PARAM_VCORANGE(TARGET_VCO_RANGE) |
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DSIM_TOP_PLL_PARAM_LPFCTRL(TARGET_LPF_CTRL) |
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DSIM_TOP_PLL_PARAM_ICPCTRL(TARGET_ICP_CTR) |
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pll_config;
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//wait at least one microsecond (requirement between shadow_clear and updatepll)
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spin(2);
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rDSIM_TOP_PLL_CTRL |= DSIM_TOP_PLL_CTRL_UPDATEPLL_ON;
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// wait at least 200 nanoseconds (for updatepll to remain asserted at least four 24 MHz cycles) 8) clear MIPI_DSI_TOP_PLL_CTRL.updatepll
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// wait at least 200 nanoseconds (for phylock_hw to clear)
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spin(1);
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rDSIM_TOP_PLL_CTRL &= ~DSIM_TOP_PLL_CTRL_UPDATEPLL_ON;
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spin(1);
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#if WITH_HW_AGC_MIPI_V2
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rDSIM_TOP_AGILE_SEQ1 = TARGET_AGILE_SEQ1;
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rDSIM_TOP_AGILE_SEQ2 = TARGET_AGILE_SEQ2;
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rDSIM_TOP_PLL_CTRL &= ~DSIM_TOP_PLL_CTRL_SEQ_OW_ON;
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//set up agilie clocking constants
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//<rdar://problem/22524373> Maui/Malta MIPI-DSI screen shift due to first first agile command after display on
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rDSIM_TOP_AGILE_LINECOUNT |= DSIM_TOP_AGILE_LINECOUNT_CONFIG_MAX;
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rDSIM_TOP_AGILE_CTRL &= ~((0x3 << 18) | (0x3 << 16)); //VFRONT
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rDSIM_TOP_AGILE_CTRL |= DSIM_TOP_AGILE_CTRL_ENABLE;
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#endif //WITH_HW_AGC_MIPI_V2
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}
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#endif //DSIM_VERSION
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rDSIM_CORE_PHY_RSTZ = DSIM_CORE_PHY_RSTZ_PHY_FORCEPLL | DSIM_CORE_PHY_RSTZ_PHY_ENABLECLK | DSIM_CORE_PHY_RSTZ_PHY_SHUTDOWNZ;
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spin(5);
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rDSIM_CORE_PHY_RSTZ = DSIM_CORE_PHY_RSTZ_PHY_FORCEPLL | DSIM_CORE_PHY_RSTZ_PHY_ENABLECLK | DSIM_CORE_PHY_RSTZ_PHY_SHUTDOWNZ | DSIM_CORE_PHY_RSTZ_PHY_RSTZ;
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#if DSIM_VERSION > 1
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while ((rDSIM_GENERAL_CTRL & DSIM_GENERAL_CTRL_PHYLOCK_HW_LOCK) == 0);
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#endif //DSIM_VERSION
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#if DSIM_VERSION == 1
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//Program PHY hsfreqrange registers
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mipi_program_phy_hsfreqrange(phy_settings_info);
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#endif //DSIM_VERSION
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rDSIM_CORE_LP_RD_TO_CNT = 0x19;
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rDSIM_CORE_BTA_TO_CNT = 0x19;
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//Monitor PHY status
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status_mask = (DSIM_CORE_PHY_STATUS_PHY_STOPSTATECLKLANE | DSIM_CORE_PHY_STATUS_PHY_STOPSTATE0LANE);
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status_mask |= (lane_count >= 2) ? DSIM_CORE_PHY_STATUS_PHY_STOPSTATE1LANE : 0;
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status_mask |= (lane_count >= 3) ? DSIM_CORE_PHY_STATUS_PHY_STOPSTATE2LANE : 0;
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status_mask |= (lane_count == 4) ? DSIM_CORE_PHY_STATUS_PHY_STOPSTATE3LANE : 0;
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while ((rDSIM_CORE_PHY_STATUS & status_mask) != status_mask);
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return 0;
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}
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int mipi_dsim_quiesce(void)
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{
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dprintf(DEBUG_CRITICAL, "mipi_dsim_quiesce()\n");
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if (!mipi_is_interface_enabled()) return 0;
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//Disable interrupts
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rDSIM_CORE_INT_MSK0 = 0x1FFFFF;
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rDSIM_CORE_INT_MSK1 = 0x1FFF;
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//Need to shutdown core before the phy
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// Power off the core
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rDSIM_CORE_PWR_UP = 0;
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// Power off PHY
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mipi_phy_test_reset( true );
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rDSIM_CORE_PHY_RSTZ &= ~(DSIM_CORE_PHY_RSTZ_PHY_FORCEPLL | DSIM_CORE_PHY_RSTZ_PHY_SHUTDOWNZ | DSIM_CORE_PHY_RSTZ_PHY_ENABLECLK);
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// Delay from SHUTDOWNZ assertion to RSTZ assertion (T4)
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spin( 5 );
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rDSIM_CORE_PHY_RSTZ &= ~(DSIM_CORE_PHY_RSTZ_PHY_RSTZ);
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clock_gate(CLK_MIPI, false);
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return 0;
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}
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void mipi_dsim_enable_high_speed(bool enable)
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{
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if (!mipi_is_interface_enabled()) return;
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if (enable) {
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//Enable MIPI operation
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rDSIM_CORE_LPCLK_CTRL |= DSIM_CORE_LPCLK_CTRL_PHY_TXREQUESTCLKHS;
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#if DSIM_VERSION == 1
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//Program PHY test registers
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||||
mipi_program_phy_test_codes(phy_settings_info);
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||||
//handle termination
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mipi_phy_read_mod_write(0x21, 0x1f, 2, 2);
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#endif
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} else {
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rDSIM_CORE_LPCLK_CTRL &= ~DSIM_CORE_LPCLK_CTRL_PHY_TXREQUESTCLKHS;
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}
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}
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void mipi_dsim_enable_video(bool enable)
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{
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#if DSIM_VERSION == 1
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uint32_t status_mask;
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||||
#endif
|
||||
|
||||
if (!mipi_is_interface_enabled()) return;
|
||||
|
||||
if (enable) {
|
||||
#if DSIM_VERSION == 1
|
||||
//<rdar://problem/15548340> [N61/N56] Fiji MIPI DSI PHY requires shutdownz toggle during power up sequence
|
||||
//validate no commands are in flight
|
||||
status_mask = DSIM_CORE_PHY_STATUS_PHY_STOPSTATE0LANE;
|
||||
status_mask |= (lane_count >= 2) ? DSIM_CORE_PHY_STATUS_PHY_STOPSTATE1LANE : 0;
|
||||
status_mask |= (lane_count >= 3) ? DSIM_CORE_PHY_STATUS_PHY_STOPSTATE2LANE : 0;
|
||||
status_mask |= (lane_count == 4) ? DSIM_CORE_PHY_STATUS_PHY_STOPSTATE3LANE : 0;
|
||||
|
||||
while ((rDSIM_CORE_PHY_STATUS & status_mask) != status_mask);
|
||||
|
||||
mipi_phy_toggle_shutdownz();
|
||||
#endif
|
||||
|
||||
//Set Video Mode
|
||||
rDSIM_CORE_MODE_CFG = DSIM_CORE_MODE_CFG_VIDEO_MODE;
|
||||
} else {
|
||||
//Set Video Mode
|
||||
rDSIM_CORE_MODE_CFG = DSIM_CORE_MODE_CFG_COMMAND_MODE;
|
||||
}
|
||||
}
|
||||
|
||||
//Programming of generic packets
|
||||
int mipi_dsim_send_short_command(u_int8_t cmd, u_int8_t data0, u_int8_t data1)
|
||||
{
|
||||
if (!mipi_is_interface_enabled()) return 0;
|
||||
|
||||
//Write packet header
|
||||
rDSIM_CORE_GEN_HDR = DSIM_CORE_GEN_HDR_GEN_DT(cmd) | DSIM_CORE_GEN_HDR_GEN_WC_LSBYTE(data0) | DSIM_CORE_GEN_HDR_GEN_WC_MSBYTE(data1);
|
||||
|
||||
//Read queue status
|
||||
while (!(rDSIM_CORE_CMD_PKT_STATUS & DSIM_CORE_CMD_PKT_STATUS_GEN_CMD_EMPTY));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mipi_dsim_send_long_command(u_int8_t cmd, const u_int8_t *data, u_int32_t length)
|
||||
{
|
||||
u_int32_t cnt, payload = 0;
|
||||
|
||||
if (!mipi_is_interface_enabled()) return 0;
|
||||
|
||||
for (cnt = 0; cnt < length; cnt++) {
|
||||
payload = (payload >> 8) | ((u_int32_t)data[cnt] << 24);
|
||||
if ((cnt & 3) == 3) {
|
||||
//Write packet data
|
||||
rDSIM_CORE_GEN_PLD_DATA = payload;
|
||||
payload = 0;
|
||||
}
|
||||
}
|
||||
if (payload) {
|
||||
payload >>= 32 - ((length & 3) * 8);
|
||||
}
|
||||
|
||||
//Need to write to the fifo even if the values are 0's
|
||||
if (length % 4)
|
||||
rDSIM_CORE_GEN_PLD_DATA = payload;
|
||||
|
||||
return mipi_dsim_send_short_command(cmd, length & 0xff, (length >> 8) & 0xff);
|
||||
}
|
||||
|
||||
int mipi_dsim_read_short_command(u_int8_t cmd, u_int8_t *data)
|
||||
{
|
||||
uint32_t tmp, i = 0, status_mask;
|
||||
|
||||
if (!mipi_is_interface_enabled()) return 0;
|
||||
|
||||
// Clear pending interrupts
|
||||
rDSIM_CORE_INT_ST1 = 0x1FFF;
|
||||
|
||||
mipi_dsim_send_short_command(cmd, data[0], data[1]);
|
||||
|
||||
while (1) {
|
||||
tmp = rDSIM_CORE_INT_ST1;
|
||||
|
||||
if ((tmp & DSIM_CORE_INT_ST1_ERRORS) != 0) {
|
||||
dprintf(DEBUG_CRITICAL, "mipi cmd error 0x%x\n", tmp);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((tmp & DSIM_CORE_INT_ST1_TO_LP_RX) || (tmp & DSIM_CORE_INT_ST1_TO_HS_TX)) {
|
||||
dprintf(DEBUG_CRITICAL, "mipi: timing out\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
tmp = rDSIM_CORE_CMD_PKT_STATUS;
|
||||
status_mask = DSIM_CORE_CMD_PKT_STATUS_GEN_PLD_R_EMPTY | DSIM_CORE_CMD_PKT_STATUS_GEN_PLD_W_EMPTY |
|
||||
DSIM_CORE_CMD_PKT_STATUS_GEN_CMD_EMPTY;
|
||||
if (tmp == status_mask) {
|
||||
break;
|
||||
}
|
||||
|
||||
// Hardware timeout depends on having a receiver, and
|
||||
// completing BTA. This isn't guaranteed for dev boards.
|
||||
if (++i == 5) {
|
||||
dprintf(DEBUG_CRITICAL, "mipi: timing out\n");
|
||||
return -1;
|
||||
}
|
||||
spin(50 * 1000);
|
||||
}
|
||||
|
||||
// Wait for the read data
|
||||
while ((rDSIM_CORE_CMD_PKT_STATUS & DSIM_CORE_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) != DSIM_CORE_CMD_PKT_STATUS_GEN_RD_CMD_BUSY);
|
||||
|
||||
|
||||
tmp = rDSIM_CORE_GEN_PLD_DATA;
|
||||
|
||||
data[0] = (tmp >> 0) & 0xff;
|
||||
data[1] = (tmp >> 8) & 0xff;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mipi_dsim_read_long_command(u_int8_t cmd, u_int8_t *data, u_int32_t *length)
|
||||
{
|
||||
u_int32_t tmp, maxlen, i = 0;
|
||||
|
||||
if (!mipi_is_interface_enabled()) return 0;
|
||||
|
||||
maxlen = *length;
|
||||
|
||||
// Clear pending interrupts
|
||||
rDSIM_CORE_INT_ST1 = 0x1FFF;
|
||||
|
||||
mipi_dsim_send_short_command(cmd, data[0], data[1]);
|
||||
|
||||
while (1) {
|
||||
tmp = rDSIM_CORE_INT_ST1;
|
||||
|
||||
if ((tmp & DSIM_CORE_INT_ST1_ERRORS) != 0) {
|
||||
dprintf(DEBUG_CRITICAL, "mipi cmd error 0x%x\n", tmp);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((tmp & DSIM_CORE_INT_ST1_TO_LP_RX) || (tmp & DSIM_CORE_INT_ST1_TO_HS_TX)) {
|
||||
dprintf(DEBUG_CRITICAL, "mipi: timing out\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
// rd_cmd_busy should go low indicating the data is ready
|
||||
if ( !(rDSIM_CORE_CMD_PKT_STATUS & DSIM_CORE_CMD_PKT_STATUS_GEN_RD_CMD_BUSY))
|
||||
break;
|
||||
|
||||
// Hardware timeout depends on having a receiver, and
|
||||
// completing BTA. This isn't guaranteed for dev boards.
|
||||
if (++i == 5) {
|
||||
dprintf(DEBUG_CRITICAL, "mipi_dsim_read_long_command: timing out\n");
|
||||
return -1;
|
||||
}
|
||||
spin(50 * 1000);
|
||||
}
|
||||
|
||||
//Unlike other IPs, the FIJI IP strips the response packet header. SW determines how many bytes were
|
||||
//sent by checking when the FIFO is emtpy and returning how many bytes were read
|
||||
for (i = 0; i < maxlen; i++) {
|
||||
if (rDSIM_CORE_CMD_PKT_STATUS & DSIM_CORE_CMD_PKT_STATUS_GEN_PLD_R_EMPTY)
|
||||
break;
|
||||
|
||||
if (!(i % 4)) {
|
||||
tmp = rDSIM_CORE_GEN_PLD_DATA;
|
||||
}
|
||||
data[i] = tmp & 0xff;
|
||||
tmp >>= 8;
|
||||
}
|
||||
|
||||
|
||||
while (!(rDSIM_CORE_CMD_PKT_STATUS & DSIM_CORE_CMD_PKT_STATUS_GEN_PLD_R_EMPTY)){
|
||||
//empty the fifo
|
||||
tmp = rDSIM_CORE_GEN_PLD_DATA;
|
||||
}
|
||||
|
||||
if (i < maxlen)
|
||||
*length = i;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mipi_program_phy_hsfreqrange(struct phy_settings *phy_settings_info)
|
||||
{
|
||||
struct phy_setting_vals *phy_setting_value_ptr;
|
||||
uint32_t num_of_values;
|
||||
|
||||
num_of_values = 1;
|
||||
|
||||
phy_setting_value_ptr = &(phy_settings_info->phy_setting_values[0]);
|
||||
mipi_phy_write(phy_setting_value_ptr->test_code, phy_setting_value_ptr->test_data, phy_setting_value_ptr->num_of_data);
|
||||
}
|
||||
|
||||
static void mipi_program_phy_test_codes(struct phy_settings *phy_settings_info)
|
||||
{
|
||||
struct phy_setting_vals *phy_setting_value_ptr;
|
||||
uint32_t num_of_values, cnt;
|
||||
|
||||
num_of_values = phy_settings_info->num_of_values;
|
||||
|
||||
//skip first element as it was programmed in the hsfreqrange
|
||||
for(cnt = 1; cnt < num_of_values; cnt++) {
|
||||
phy_setting_value_ptr = &(phy_settings_info->phy_setting_values[cnt]);
|
||||
mipi_phy_write(phy_setting_value_ptr->test_code, phy_setting_value_ptr->test_data, phy_setting_value_ptr->num_of_data);
|
||||
}
|
||||
}
|
||||
|
||||
static void mipi_phy_write(uint32_t address, uint8_t *data, uint32_t length)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
// Clock High
|
||||
rDSIM_CORE_PHY_TST_CTRL0 = DSIM_CORE_PHY_TST_CTRL0_PHY_TESTCLK;
|
||||
|
||||
//register address
|
||||
rDSIM_CORE_PHY_TST_CTRL1 = DSIM_CORE_PHY_TST_CTRL1_PHY_TESTDIN(address);
|
||||
|
||||
// Mark this tx as an AddressWrite
|
||||
rDSIM_CORE_PHY_TST_CTRL1 |= DSIM_CORE_PHY_TST_CTRL1_PHY_TESTEN;
|
||||
|
||||
//Wait 5ns
|
||||
spin(5);
|
||||
|
||||
// Latch address
|
||||
rDSIM_CORE_PHY_TST_CTRL0 &= ~DSIM_CORE_PHY_TST_CTRL0_PHY_TESTCLK;
|
||||
|
||||
spin(10);
|
||||
//Get ready for the Write Data
|
||||
rDSIM_CORE_PHY_TST_CTRL1 &= ~DSIM_CORE_PHY_TST_CTRL1_PHY_TESTEN;
|
||||
|
||||
for (i = 0; i < length; i++) {
|
||||
rDSIM_CORE_PHY_TST_CTRL1 &= ~DSIM_CORE_PHY_TST_CTRL1_PHY_TESTDIN(0xFF);
|
||||
rDSIM_CORE_PHY_TST_CTRL1 |= DSIM_CORE_PHY_TST_CTRL1_PHY_TESTDIN(data[i]);
|
||||
spin(2);
|
||||
rDSIM_CORE_PHY_TST_CTRL0 |= DSIM_CORE_PHY_TST_CTRL0_PHY_TESTCLK;
|
||||
spin(10);
|
||||
rDSIM_CORE_PHY_TST_CTRL0 &= ~DSIM_CORE_PHY_TST_CTRL0_PHY_TESTCLK;
|
||||
}
|
||||
}
|
||||
|
||||
static void mipi_phy_read_mod_write(uint32_t address, uint8_t mask, uint8_t shift, uint8_t val)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
// Clock High
|
||||
rDSIM_CORE_PHY_TST_CTRL0 = DSIM_CORE_PHY_TST_CTRL0_PHY_TESTCLK;
|
||||
|
||||
//register address
|
||||
rDSIM_CORE_PHY_TST_CTRL1 = DSIM_CORE_PHY_TST_CTRL1_PHY_TESTDIN(address);
|
||||
|
||||
// Mark this tx as an AddressWrite
|
||||
rDSIM_CORE_PHY_TST_CTRL1 |= DSIM_CORE_PHY_TST_CTRL1_PHY_TESTEN;
|
||||
|
||||
//Wait 5ns
|
||||
spin(5);
|
||||
|
||||
// Latch address
|
||||
rDSIM_CORE_PHY_TST_CTRL0 &= ~DSIM_CORE_PHY_TST_CTRL0_PHY_TESTCLK;
|
||||
|
||||
spin(10);
|
||||
|
||||
//Get ready for the Write Data
|
||||
rDSIM_CORE_PHY_TST_CTRL1 &= ~DSIM_CORE_PHY_TST_CTRL1_PHY_TESTEN;
|
||||
|
||||
// From Fiji | MIPI DSI PHY Required test code settings & impact:
|
||||
// Once the termination resistance is calibrated, read out the calibrated
|
||||
// value (bit[4:0]) and then force these values thereafter by writing them
|
||||
// back to bits[6:2] with bits[1:0] = 10 (0x2). This prevents clock lanes
|
||||
// from recalibrating termination during each PHY reset.
|
||||
reg = rDSIM_CORE_PHY_TST_CTRL1;
|
||||
reg = DSIM_CORE_PHY_TST_CTRL1_PHY_TESTDOUT(reg);
|
||||
reg &= mask;
|
||||
reg = (reg << shift) | val;
|
||||
|
||||
// DataWrite
|
||||
rDSIM_CORE_PHY_TST_CTRL1 &= ~DSIM_CORE_PHY_TST_CTRL1_PHY_TESTEN;
|
||||
|
||||
rDSIM_CORE_PHY_TST_CTRL1 &= ~DSIM_CORE_PHY_TST_CTRL1_PHY_TESTDIN(0xFF);
|
||||
rDSIM_CORE_PHY_TST_CTRL1 |= DSIM_CORE_PHY_TST_CTRL1_PHY_TESTDIN(reg);
|
||||
|
||||
spin(2);
|
||||
|
||||
// Pulse clock to latch data
|
||||
rDSIM_CORE_PHY_TST_CTRL0 |= DSIM_CORE_PHY_TST_CTRL0_PHY_TESTCLK;
|
||||
|
||||
spin(10);
|
||||
|
||||
reg = rDSIM_CORE_PHY_TST_CTRL1;
|
||||
|
||||
rDSIM_CORE_PHY_TST_CTRL0 &= ~DSIM_CORE_PHY_TST_CTRL0_PHY_TESTCLK;
|
||||
|
||||
spin(2);
|
||||
}
|
||||
|
||||
static void mipi_phy_test_reset(bool reset)
|
||||
{
|
||||
rDSIM_CORE_PHY_TST_CTRL0 = reset ? DSIM_CORE_PHY_TST_CTRL0_PHY_TESTCLR : 0;
|
||||
|
||||
spin(5);
|
||||
}
|
||||
|
||||
static void mipi_phy_toggle_shutdownz(void)
|
||||
{
|
||||
rDSIM_CORE_PHY_RSTZ &= ~DSIM_CORE_PHY_RSTZ_PHY_SHUTDOWNZ;
|
||||
spin(1);
|
||||
rDSIM_CORE_PHY_RSTZ |= DSIM_CORE_PHY_RSTZ_PHY_SHUTDOWNZ;
|
||||
}
|
||||
|
||||
|
||||
static bool mipi_is_interface_enabled()
|
||||
{
|
||||
clock_gate(CLK_MIPI, true);
|
||||
|
||||
if (rDSIM_CORE_PWR_UP == DSIM_CORE_PWR_UP_SHUTDOWNZ)
|
||||
return true;
|
||||
|
||||
clock_gate(CLK_MIPI, false);
|
||||
return false;
|
||||
}
|
||||
|
||||
#if WITH_DEVICETREE
|
||||
|
||||
#include <lib/devicetree.h>
|
||||
|
||||
int mipi_update_device_tree(DTNode *mipi_node)
|
||||
{
|
||||
uint32_t propSize;
|
||||
char *propName;
|
||||
void *propData;
|
||||
uint32_t sizeofData;
|
||||
uint32_t cnt;
|
||||
struct phy_setting_vals *phy_settings_ptr;
|
||||
struct phy_setting_vals *propdata_phy_settings;
|
||||
uint32_t size_phy_settings;
|
||||
|
||||
if (phy_settings_info == NULL) {
|
||||
printf("something is seriously bad\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
size_phy_settings = sizeof(struct phy_setting_vals);
|
||||
|
||||
propName = "phy-test-num";
|
||||
if (FindProperty(mipi_node, &propName, &propData, &propSize)) {
|
||||
((u_int32_t *)propData)[0] = phy_settings_info->num_of_values;
|
||||
}
|
||||
|
||||
propName = "phy-test";
|
||||
if (FindProperty(mipi_node, &propName, &propData, &propSize)) {
|
||||
sizeofData = sizeof(struct phy_setting_vals) * phy_settings_info->num_of_values;
|
||||
if (propSize < sizeofData) {
|
||||
printf("device tree doesn't have enough space for data: propSize %d sizeofData %d\n", propSize, sizeofData);
|
||||
return -1;
|
||||
}
|
||||
for (cnt = 0; cnt < phy_settings_info->num_of_values; cnt++) {
|
||||
|
||||
|
||||
phy_settings_ptr = &(phy_settings_info->phy_setting_values[cnt]);
|
||||
propdata_phy_settings = (struct phy_setting_vals *)propData + (cnt * size_phy_settings);
|
||||
memcpy(propData + (cnt * size_phy_settings), phy_settings_ptr, size_phy_settings);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,300 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Apple Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __SYNOPSYS_DSIM_H
|
||||
#define __SYNOPSYS_DSIM_H
|
||||
|
||||
#include <platform/soc/hwregbase.h>
|
||||
|
||||
#define rDSIM_CORE_VERSION (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00000))
|
||||
#define rDSIM_CORE_PWR_UP (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00004))
|
||||
#define DSIM_CORE_PWR_UP_SHUTDOWNZ (1 << 0)
|
||||
#define rDSIM_CORE_CLKMGR_CFG (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00008))
|
||||
#define DSIM_CORE_CLKMGR_CFG_TO_CLK_DIVISION(n) ((n) << 8)
|
||||
#define DSIM_CORE_CLKMGR_CFG_TX_ESC_CLK_DIVISION(n) ((n) << 0)
|
||||
#define rDSIM_CORE_DPI_VCID (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0000C))
|
||||
#define rDSIM_CORE_DPI_COLOR_CODING (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00010))
|
||||
#define DPI_COLOR_CODING_BIT16_CONF1 (0x0)
|
||||
#define DPI_COLOR_CODING_BIT16_CONF2 (0x1)
|
||||
#define DPI_COLOR_CODING_BIT16_CONF3 (0x2)
|
||||
#define DPI_COLOR_CODING_BIT18_CONF1 (0x3)
|
||||
#define DPI_COLOR_CODING_BIT18_CONF2 (0x4)
|
||||
#define DPI_COLOR_CODING_BIT24 (0x5)
|
||||
#define DPI_COLOR_CODING_BIT20_422_LOOSELY (0x6)
|
||||
#define DPI_COLOR_CODING_BIT24_422 (0x7)
|
||||
#define DPI_COLOR_CODING_BIT16_422 (0x8)
|
||||
#define DPI_COLOR_CODING_BIT30 (0x9)
|
||||
#define DPI_COLOR_CODING_BIT36 (0xA)
|
||||
#define DPI_COLOR_CODING_BIT12_420 (0xB)
|
||||
#define DPI_COLOR_CODING_BIT12_420_SAME (0xC)
|
||||
#define DPI_COLOR_CODING_BIT12_420_SAME2 (0xD)
|
||||
#define DPI_COLOR_CODING_BIT12_420_SAME3 (0xE)
|
||||
#define DPI_COLOR_CODING_BIT12_420_SAME4 (0xF)
|
||||
#define rDSIM_CORE_DPI_CFG_POL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00014))
|
||||
#define rDSIM_CORE_DPI_LP_CMD_TIM (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00018))
|
||||
#define rDSIM_CORE_PCKHDL_CFG (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0002C))
|
||||
#define DSIM_CORE_PCKHDL_CFG_CRC_RX_EN (1 << 4)
|
||||
#define DSIM_CORE_PCKHDL_CFG_ECC_RX_EN (1 << 3)
|
||||
#define DSIM_CORE_PCKHDL_CFG_BTA_EN (1 << 2)
|
||||
#define DSIM_CORE_PCKHDL_CFG_EOTP_RX_EN (1 << 1)
|
||||
#define DSIM_CORE_PCKHDL_CFG_EOTP_TX_EN (1 << 0)
|
||||
#define rDSIM_CORE_GEN_VCID (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00030))
|
||||
#define rDSIM_CORE_MODE_CFG (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00034))
|
||||
#define DSIM_CORE_MODE_CFG_VIDEO_MODE (0 << 0)
|
||||
#define DSIM_CORE_MODE_CFG_COMMAND_MODE (1 << 0)
|
||||
#define rDSIM_CORE_VID_MODE_CFG (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00038))
|
||||
#define DSIM_CORE_VID_MODE_CFG_LP_CMD_EN (1 << 15)
|
||||
#define DSIM_CORE_VID_MODE_CFG_FRAME_BTA_ACK_EN (1 << 14)
|
||||
#define DSIM_CORE_VID_MODE_CFG_LP_HFP_EN (1 << 13)
|
||||
#define DSIM_CORE_VID_MODE_CFG_LP_HBP_EN (1 << 12)
|
||||
#define DSIM_CORE_VID_MODE_CFG_LP_VACT_EN (1 << 11)
|
||||
#define DSIM_CORE_VID_MODE_CFG_LP_VFP_EN (1 << 10)
|
||||
#define DSIM_CORE_VID_MODE_CFG_LP_VBP_EN (1 << 9)
|
||||
#define DSIM_CORE_VID_MODE_CFG_LP_VSA_EN (1 << 8)
|
||||
#define DSIM_CORE_VID_MODE_CFG_VID_MODE_TYPE_NONBURSTSYNCPULSE (0 << 0)
|
||||
#define DSIM_CORE_VID_MODE_CFG_VID_MODE_TYPE_NONBURSTSYNCEVENT (1 << 0)
|
||||
#define DSIM_CORE_VID_MODE_CFG_VID_MODE_TYPE_BURSTMODE (2 << 0)
|
||||
#define DSIM_CORE_VID_MODE_CFG_VID_MODE_TYPE_HORIZONTALEXPANSION (3 << 0)
|
||||
#define rDSIM_CORE_VID_PKT_SIZE (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0003C))
|
||||
#define rDSIM_CORE_VID_NUM_CHUNKS (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00040))
|
||||
#define rDSIM_CORE_VID_NULL_SIZE (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00044))
|
||||
#define rDSIM_CORE_VID_HSA_TIME (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00048))
|
||||
#define rDSIM_CORE_VID_HBP_TIME (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0004C))
|
||||
#define rDSIM_CORE_VID_HLINE_TIME (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00050))
|
||||
#define rDSIM_CORE_VID_VSA_LINES (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00054))
|
||||
#define rDSIM_CORE_VID_VBP_LINES (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00058))
|
||||
#define rDSIM_CORE_VID_VFP_LINES (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0005C))
|
||||
#define rDSIM_CORE_VID_VACTIVE_LINES (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00060))
|
||||
#define rDSIM_CORE_CMD_MODE_CFG (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00068))
|
||||
|
||||
#if DSIM_VERSION == 1
|
||||
#define DSIM_CORE_CMD_MODE_CFG_MAX_RD_PKT_SIZE_LP (1 << 24)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_DCS_LW_TX_LP (1 << 19)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_DCS_SR_0P_TX_LP (1 << 18)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_DCS_SW_1P_TX_LP (1 << 17)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_DCS_SW_0P_TX_LP (1 << 16)
|
||||
#endif //DSIM_VERSION == 1
|
||||
|
||||
#define DSIM_CORE_CMD_MODE_CFG_GEN_LW_TX_LP (1 << 14)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_GEN_SR_2P_TX_LP (1 << 13)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_GEN_SR_1P_TX_LP (1 << 12)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_GEN_SR_0P_TX_LP (1 << 11)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_GEN_SW_2P_TX_LP (1 << 10)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_GEN_SW_1P_TX_LP (1 << 9)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_GEN_SW_0P_TX_LP (1 << 8)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_ACK_RQST_EN (1 << 1)
|
||||
#define DSIM_CORE_CMD_MODE_CFG_TEAR_FX_EN (1 << 0)
|
||||
#define rDSIM_CORE_GEN_HDR (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0006C))
|
||||
#define DSIM_CORE_GEN_HDR_GEN_WC_MSBYTE(n) ((n) << 16)
|
||||
#define DSIM_CORE_GEN_HDR_GEN_WC_LSBYTE(n) ((n) << 8)
|
||||
#define DSIM_CORE_GEN_HDR_GEN_VC(n) ((n) << 6)
|
||||
#define DSIM_CORE_GEN_HDR_GEN_DT(n) ((n) << 0)
|
||||
#define rDSIM_CORE_GEN_PLD_DATA (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00070))
|
||||
#define rDSIM_CORE_CMD_PKT_STATUS (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00074))
|
||||
#define DSIM_CORE_CMD_PKT_STATUS_GEN_RD_CMD_BUSY (1 << 6)
|
||||
#define DSIM_CORE_CMD_PKT_STATUS_GEN_PLD_R_FULL (1 << 5)
|
||||
#define DSIM_CORE_CMD_PKT_STATUS_GEN_PLD_R_EMPTY (1 << 4)
|
||||
#define DSIM_CORE_CMD_PKT_STATUS_GEN_PLD_W_FULL (1 << 3)
|
||||
#define DSIM_CORE_CMD_PKT_STATUS_GEN_PLD_W_EMPTY (1 << 2)
|
||||
#define DSIM_CORE_CMD_PKT_STATUS_GEN_CMD_FULL (1 << 1)
|
||||
#define DSIM_CORE_CMD_PKT_STATUS_GEN_CMD_EMPTY (1 << 0)
|
||||
#define rDSIM_CORE_TO_CNT_CFG (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00078))
|
||||
#define rDSIM_CORE_HS_RD_TO_CNT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0007C))
|
||||
#define rDSIM_CORE_LP_RD_TO_CNT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00080))
|
||||
#define rDSIM_CORE_HS_WR_TO_CNT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00084))
|
||||
#define rDSIM_CORE_LP_WR_TO_CNT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00088))
|
||||
#define rDSIM_CORE_BTA_TO_CNT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0008C))
|
||||
#define rDSIM_CORE_SDF_3D (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00090))
|
||||
#define rDSIM_CORE_LPCLK_CTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00094))
|
||||
#define DSIM_CORE_LPCLK_CTRL_AUTO_CLKLANE_CTRL (1 << 1)
|
||||
#define DSIM_CORE_LPCLK_CTRL_PHY_TXREQUESTCLKHS (1 << 0)
|
||||
#define rDSIM_CORE_PHY_TMR_LPCLK_CFG (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x00098))
|
||||
#define DSIM_CORE_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME(n) ((n) << 16)
|
||||
#define DSIM_CORE_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME(n) ((n) << 0)
|
||||
#define rDSIM_CORE_PHY_TMR_CFG (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x0009C))
|
||||
#define DSIM_CORE_PHY_TMR_CFG_PHY_HS2LP_TIME(n) ((n) << 24)
|
||||
#define DSIM_CORE_PHY_TMR_CFG_PHY_LP2HS_TIME(n) ((n) << 16)
|
||||
#define DSIM_CORE_PHY_TMR_CFG_MAX_RD_TIME(n) ((n) << 0)
|
||||
#define rDSIM_CORE_PHY_RSTZ (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000A0))
|
||||
#define DSIM_CORE_PHY_RSTZ_PHY_FORCEPLL (1 << 3)
|
||||
#define DSIM_CORE_PHY_RSTZ_PHY_ENABLECLK (1 << 2)
|
||||
#define DSIM_CORE_PHY_RSTZ_PHY_RSTZ (1 << 1)
|
||||
#define DSIM_CORE_PHY_RSTZ_PHY_SHUTDOWNZ (1 << 0)
|
||||
#define rDSIM_CORE_PHY_IF_CFG (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000A4))
|
||||
#define DSIM_CORE_PHY_IF_CFG_PHY_STOP_WAIT_TIME(n) ((n) << 8)
|
||||
#define DSIM_CORE_PHY_IF_CFG_N_LANES(n) ((n) << 0)
|
||||
#define rDSIM_CORE_PHY_ULPS_CTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000A8))
|
||||
#define rDSIM_CORE_PHY_TX_TRIGGERS (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000AC))
|
||||
#define rDSIM_CORE_PHY_STATUS (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000B0))
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_ULPSACTIVENOT3LANE (1 << 12)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_STOPSTATE3LANE (1 << 11)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_ULPSACTIVENOT2LANE (1 << 10)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_STOPSTATE2LANE (1 << 9)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_ULPSACTIVENOT1LANE (1 << 8)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_STOPSTATE1LANE (1 << 7)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_RXULPSESC0LANE (1 << 6)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_ULPSACTIVENOT0LANE (1 << 5)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_STOPSTATE0LANE (1 << 4)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_ULPSACTIVENOTCLK (1 << 3)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_STOPSTATECLKLANE (1 << 2)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_DIRECTION (1 << 1)
|
||||
#define DSIM_CORE_PHY_STATUS_PHY_LOCK (1 << 0)
|
||||
#define rDSIM_CORE_PHY_TST_CTRL0 (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000B4))
|
||||
#define DSIM_CORE_PHY_TST_CTRL0_PHY_TESTCLK (1 << 1)
|
||||
#define DSIM_CORE_PHY_TST_CTRL0_PHY_TESTCLR (1 << 0)
|
||||
#define rDSIM_CORE_PHY_TST_CTRL1 (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000B8))
|
||||
#define DSIM_CORE_PHY_TST_CTRL1_PHY_TESTEN (1 << 16)
|
||||
#define DSIM_CORE_PHY_TST_CTRL1_PHY_TESTDOUT(n)(((n) >> 8) & 0xff)
|
||||
#define DSIM_CORE_PHY_TST_CTRL1_PHY_TESTDIN(n) ((n) << 0)
|
||||
#define rDSIM_CORE_INT_ST0 (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000BC))
|
||||
#define DSIM_CORE_INT_ST0_DPHY_ERRORS_4 (1 << 20)
|
||||
#define DSIM_CORE_INT_ST0_PHY_ERRORS_3 (1 << 19)
|
||||
#define DSIM_CORE_INT_ST0_PHY_ERRORS_1 (1 << 17)
|
||||
#define DSIM_CORE_INT_ST0_PHY_ERRORS_0 (1 << 16)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_15 (1 << 15)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_14 (1 << 14)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_13 (1 << 13)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_12 (1 << 12)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_11 (1 << 11)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_10 (1 << 10)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_9 (1 << 9)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_8 (1 << 8)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_7 (1 << 7)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_6 (1 << 6)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_5 (1 << 5)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_4 (1 << 4)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_3 (1 << 3)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_2 (1 << 2)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_1 (1 << 1)
|
||||
#define DSIM_CORE_INT_ST0_ACK_WITH_ERR_0 (1 << 0)
|
||||
#define rDSIM_CORE_INT_ST1 (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000C0))
|
||||
#define DSIM_CORE_INT_ST1_GEN_PLD_RECEV_ERR (1 << 12)
|
||||
#define DSIM_CORE_INT_ST1_GEN_PLD_RD_ERR (1 << 11)
|
||||
#define DSIM_CORE_INT_ST1_GEN_PLD_SEND_ERR (1 << 10)
|
||||
#define DSIM_CORE_INT_ST1_GEN_PLD_WR_ERR (1 << 9)
|
||||
#define DSIM_CORE_INT_ST1_GEN_CMD_WR_ERR (1 << 8)
|
||||
#define DSIM_CORE_INT_ST1_DPI_PLD_WR_ERR (1 << 7)
|
||||
#define DSIM_CORE_INT_ST1_EOPT_ERR (1 << 6)
|
||||
#define DSIM_CORE_INT_ST1_PKT_SIZE_ERR (1 << 5)
|
||||
#define DSIM_CORE_INT_ST1_CRC_ERR (1 << 4)
|
||||
#define DSIM_CORE_INT_ST1_ECC_MILTI_ERR (1 << 3)
|
||||
#define DSIM_CORE_INT_ST1_ECC_SINGLE_ERR (1 << 2)
|
||||
#define DSIM_CORE_INT_ST1_TO_LP_RX (1 << 1)
|
||||
#define DSIM_CORE_INT_ST1_TO_HS_TX (1 << 0)
|
||||
#define DSIM_CORE_INT_ST1_ERRORS (DSIM_CORE_INT_ST1_GEN_PLD_RECEV_ERR | \
|
||||
DSIM_CORE_INT_ST1_GEN_PLD_RD_ERR | \
|
||||
DSIM_CORE_INT_ST1_GEN_PLD_SEND_ERR | \
|
||||
DSIM_CORE_INT_ST1_GEN_PLD_WR_ERR | \
|
||||
DSIM_CORE_INT_ST1_GEN_CMD_WR_ERR | \
|
||||
DSIM_CORE_INT_ST1_DPI_PLD_WR_ERR | \
|
||||
DSIM_CORE_INT_ST1_EOPT_ERR | \
|
||||
DSIM_CORE_INT_ST1_PKT_SIZE_ERR | \
|
||||
DSIM_CORE_INT_ST1_CRC_ERR | \
|
||||
DSIM_CORE_INT_ST1_ECC_MILTI_ERR | \
|
||||
DSIM_CORE_INT_ST1_ECC_SINGLE_ERR)
|
||||
#define rDSIM_CORE_INT_MSK0 (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000C4))
|
||||
#define rDSIM_CORE_INT_MSK1 (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000C8))
|
||||
#define rDSIM_CORE_VID_VBP_HS_LINES (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000D0))
|
||||
#define rDSIM_CORE_VID_VFP_HS_LINES (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x000D4))
|
||||
|
||||
//TOP
|
||||
#define rDSIM_VERSION (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80000))
|
||||
|
||||
#define rDSIM_GENERAL_CTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80004))
|
||||
#define DSIM_GENERAL_CTRL_HSYNC_MASK_STATUS_ON (1 << 28)
|
||||
#define DSIM_GENERAL_CTRL_HSYNC_MASK_ENABLE (1 << 27)
|
||||
#define DSIM_GENERAL_CTRL_VID_HTIME_AUTO_TIMER(n) ((n) << 12)
|
||||
#define DSIM_GENERAL_CTRL_VID_HTIME_AUTO_DYN (1 << 11)
|
||||
#define DSIM_GENERAL_CTRL_VID_HTIME_AUTO_OFFSET(n) ((n) << 9)
|
||||
#define DSIM_GENERAL_CTRL_VID_HTIME_AUTO_ROUND_TOL0 (0 << 7)
|
||||
#define DSIM_GENERAL_CTRL_VID_HTIME_AUTO_ROUND_TOL1 (1 << 7)
|
||||
#define DSIM_GENERAL_CTRL_VID_HTIME_AUTO_ROUND_TOL2 (2 << 7)
|
||||
#define DSIM_GENERAL_CTRL_VID_HTIME_AUTO_ROUND_TOL3 (3 << 7)
|
||||
#define DSIM_GENERAL_CTRL_VID_HTIME_AUTO_VALID (1 << 6)
|
||||
#define DSIM_GENERAL_CTRL_VID_HTIME_AUTO_SEL (1 << 5)
|
||||
#define DSIM_GENERAL_CTRL_PHYLOCK_HW_LOCK (1 << 4)
|
||||
#define DSIM_GENERAL_CTRL_PHYLOCK_SW_LOCK (1 << 3)
|
||||
#define DSIM_GENERAL_CTRL_DPISHUTDN (1 << 2)
|
||||
#define DSIM_GENERAL_CTRL_DPICOLORM_REDUCED (1 << 1)
|
||||
#define DSIM_GENERAL_CTRL_DPIHALT_HALT (1 << 0)
|
||||
|
||||
#define rDSIM_LANE_SWAP (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80008))
|
||||
#define rDSIM_TOP_PIXEL_REMAP (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x8000C))
|
||||
#define rDSIM_PIXEL_SWAP (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80010))
|
||||
#define rDSIM_TEST_COLOR (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80014))
|
||||
#define rDSIM_VID_HSA_TIME (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80018))
|
||||
#define rDSIM_VID_HBP_TIME (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x8001C))
|
||||
#define rDSIM_VID_HLINE_TIME (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80020))
|
||||
|
||||
#if DSIM_VERSION > 1
|
||||
#define rDSIM_TOP_AGILE_CTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80024))
|
||||
#define DSIM_TOP_AGILE_CTRL_HS_PACKET_LATENCY(n) ((n) << 24)
|
||||
#define DSIM_TOP_AGILE_CTRL_HS_PACKET_STATUS_HS (1 << 23)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_ENABLE_STATUS (1 << 22)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_RESET (1 << 21)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_TRIGGER (1 << 20)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_FINISH(n) ((n) << 18)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_FINISH_VFRONT DSIM_TOP_AGILE_CTRL_LINECOUNT_FINISH(0x0)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_FINISH_VSYNC DSIM_TOP_AGILE_CTRL_LINECOUNT_FINISH(0x1)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_FINISH_VBACK DSIM_TOP_AGILE_CTRL_LINECOUNT_FINISH(0x2)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_FINISH_VACTIVE DSIM_TOP_AGILE_CTRL_LINECOUNT_FINISH(0x3)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_START(n) ((n) << 16)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_START_VFRONT DSIM_TOP_AGILE_CTRL_LINECOUNT_START(0x0)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_START_VSYNC DSIM_TOP_AGILE_CTRL_LINECOUNT_START(0x1)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_START_VBACK DSIM_TOP_AGILE_CTRL_LINECOUNT_START(0x2)
|
||||
#define DSIM_TOP_AGILE_CTRL_LINECOUNT_START_VACTIVE DSIM_TOP_AGILE_CTRL_LINECOUNT_START(0x3)
|
||||
#define DSIM_TOP_AGILE_CTRL_TIMEBASE(n) ((n) << 8)
|
||||
#define DSIM_TOP_AGILE_CTRL_STATE(n) ((n) << 4)
|
||||
#define DSIM_TOP_AGILE_CTRL_ENABLE (1 << 3)
|
||||
#define DSIM_TOP_AGILE_CTRL_USE_TEMP_CLK (1 << 2)
|
||||
#define DSIM_TOP_AGILE_CTRL_IDLE_FRAME (1 << 1)
|
||||
#define DSIM_TOP_AGILE_CTRL_VBLANK_ON (1 << 0)
|
||||
|
||||
#define rDSIM_TOP_AGILE_LINECOUNT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80028))
|
||||
#define DSIM_TOP_AGILE_LINECOUNT_CONFIG_MAX (0xFFFF)
|
||||
|
||||
#define rDSIM_TOP_AGILE_SEQ1 (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x8002c))
|
||||
#define rDSIM_TOP_AGILE_SEQ2 (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80030))
|
||||
|
||||
#define rDSIM_TOP_PLL_CTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80034))
|
||||
#define DSIM_TOP_PLL_CTRL_PLL_CFG_SEL_PHY (1 << 31)
|
||||
#define DSIM_TOP_PLL_CTRL_PLL_SHADOW_CONTROL_PHY (1 << 30)
|
||||
#define DSIM_TOP_PLL_CTRL_PLL_SHADOW_CONTROL_OBS_PHY (1 << 29)
|
||||
#define DSIM_TOP_PLL_CTRL_SEQ_OW_ON (1 << 28)
|
||||
#define DSIM_TOP_PLL_CTRL_UPDATEPLL_ON (1 << 27)
|
||||
#define DSIM_TOP_PLL_CTRL_CLKSELPLL_MASK (3 << 25)
|
||||
#define DSIM_TOP_PLL_CTRL_CLKSELPLL_PLLCLK (1 << 25)
|
||||
#define DSIM_TOP_PLL_CTRL_CLKSELPLL_TEMPCLK (2 << 25)
|
||||
#define DSIM_TOP_PLL_CTRL_TEMP_MIPI_DSI_CLK_REQ (1 << 24)
|
||||
#define DSIM_TOP_PLL_CTRL_TEMP_MIPI_DSI_CLK_ACK_ON (1 << 23)
|
||||
#define DSIM_TOP_PLL_CTRL_CSI_SEL_CSI2 (1 << 10
|
||||
#define DSIM_TOP_PLL_CTRL_HSFREQRANGE(n) ((n) << 4)
|
||||
#define DSIM_TOP_PLL_CTRL_FORCEPLL_ON (1 << 3)
|
||||
#define DSIM_TOP_PLL_CTRL_SHADOW_CLEAR (1 << 2)
|
||||
#define DSIM_TOP_PLL_CTRL_FORCE_LOCK (1 << 1)
|
||||
#define DSIM_TOP_PLL_CTRL_ONPLL_PWRUP (1 << 0)
|
||||
|
||||
#define rDSIM_TOP_PLL_PARAM (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80038))
|
||||
#define DSIM_TOP_PLL_PARAM_VCOCAP(n) ((n) << 27)
|
||||
#define DSIM_TOP_PLL_PARAM_VCORANGE(n) ((n) << 25)
|
||||
#define DSIM_TOP_PLL_PARAM_LPFCTRL(n) ((n) << 19)
|
||||
#define DSIM_TOP_PLL_PARAM_ICPCTRL(n) ((n) << 15)
|
||||
#define DSIM_TOP_PLL_PARAM_P(n) ((n) << 14)
|
||||
#define DSIM_TOP_PLL_PARAM_M(n) ((n) << 4)
|
||||
#define DSIM_TOP_PLL_PARAM_N(n) ((n) << 0)
|
||||
|
||||
#define rDSIM_TOP_PLL_PARAM_OBS (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x8003c))
|
||||
#define rDSIM_TOP_PLL_LOCK (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80040))
|
||||
#define rDSIM_TOP_PLL_TEST (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80044))
|
||||
#define rDSIM_TOP_BIST_CTRL (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x80048))
|
||||
#define rDSIM_TOP_HSYNC_PREDICT (*(volatile u_int32_t *)(DSIM_BASE_ADDR + 0x8004c))
|
||||
#endif //DSIM_VERSION
|
||||
|
||||
#endif /* __SYNOPSYS_DSIM_H */
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Apple Computer, Inc. All rights reserved.
|
||||
*
|
||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
|
||||
*/
|
||||
#ifndef __MIPI_DISPLAY_H
|
||||
#define __MIPI_DISPLAY_H
|
||||
|
||||
#include <sys/types.h>
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
#define MAX_PHY_VALUES 9
|
||||
#define MAX_NUM_OF_TEST_DATA 6
|
||||
|
||||
struct phy_setting_vals {
|
||||
uint8_t test_code;
|
||||
uint8_t num_of_data;
|
||||
uint8_t test_data[MAX_NUM_OF_TEST_DATA];
|
||||
};
|
||||
|
||||
struct phy_settings {
|
||||
uint8_t num_of_values;
|
||||
struct phy_setting_vals phy_setting_values[MAX_PHY_VALUES];
|
||||
};
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t lanes : 4; // 3:0
|
||||
uint32_t esc_div : 4; // 7:4
|
||||
uint32_t pll_n : 3; // 10:8
|
||||
uint32_t resvd0 : 1; // 11
|
||||
uint32_t pll_m : 10; // 21:12
|
||||
uint32_t pll_p : 1; // 22
|
||||
uint32_t resvd1 : 1; // 23
|
||||
uint32_t hsfreq : 8; // 31:24
|
||||
struct phy_settings target_phy_settings;
|
||||
} mipi_t;
|
||||
|
||||
__END_DECLS
|
||||
|
||||
#endif /* __MIPI_DISPLAY_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (C) 2008-2015 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
OPTIONS += \
|
||||
WITH_HW_MIPI_DSIM=1
|
||||
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/dsim.o
|
||||
|
||||
GLOBAL_INCLUDES += $(LOCAL_DIR)/include
|
||||
Reference in new issue
Block a user