first and last commit

include/drivers/aes.h

@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2007-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_AES_H
+#define __DRIVERS_AES_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+#define AES_CMD_ENC		(0x00000000)
+#define AES_CMD_DEC		(0x00000001)
+#define AES_CMD_DIR_MASK	(0x0000000F)
+#define AES_CMD_ECB		(0x00000000)
+#define AES_CMD_CBC		(0x00000010)
+#define AES_CMD_MODE_MASK	(0x000000F0)
+
+#define AES_KEY_TYPE_USER	(0x00000000)
+#define AES_KEY_TYPE_UID0	(0x00000100)
+#define AES_KEY_TYPE_GID0	(0x00000200)
+#define AES_KEY_TYPE_GID1	(0x00000201)
+#define AES_KEY_TYPE_MASK	(0x00000FFF)
+
+#define AES_KEY_SIZE_128	(0x00000000)
+#define AES_KEY_SIZE_192	(0x10000000)
+#define AES_KEY_SIZE_256	(0x20000000)
+#define AES_KEY_SIZE_MASK	(0xF0000000)
+
+#define AES_BLOCK_SIZE		(16)
+
+/*
+ *  aes_crypto_cmd - provides access to AES functions
+ *
+ *    cmd  - operation mode: ENC or DEC and EBC or CBC
+ *    src  - source buffer and destination buffer for in place operations
+ *    dst  - desination buffer, or NULL for in place operations
+ *    len  - size in bytes of the operation
+ *    opts - key type and size
+ *    key  - key buffer or NULL for non USER key types
+ *    iv   - iv buffer or NULL if iv should be all zeros
+ *
+ * AES operations may return an error if the requested operation depends
+ * on hardware resources that are not available.
+ *
+ * Bad arguments passed to AES operations will result in a panic.
+ */
+int aes_crypto_cmd(u_int32_t cmd, void *src, void *dst, size_t len, u_int32_t opts, const void *key, void *iv);
+
+#define aes_cbc_encrypt(src, dst, len, opts, key, iv) \
+		aes_crypto_cmd(AES_CMD_ENC | AES_CMD_CBC, src, dst, len, opts, key, iv)
+#define aes_cbc_decrypt(src, dst, len, opts, key, iv) \
+		aes_crypto_cmd(AES_CMD_DEC | AES_CMD_CBC, src, dst, len, opts, key, iv)
+
+/* exported interface from hardware AES driver */
+int aes_hw_crypto_cmd(u_int32_t cmd, void *src, void *dst, size_t len, u_int32_t opts, const void *key, void *iv);
+
+/* old AES hardware driver protocol, not for new platforms */
+enum aes_key_type {
+	AES_KEY_TYPE_REGISTER = 0,
+	AES_KEY_TYPE_GLOBAL,
+	AES_KEY_TYPE_CHIP
+};
+
+int AES_CBC_DecryptInPlace(u_int8_t* pAddr, u_int32_t u32Len, u_int32_t keyType, u_int8_t* pKey, u_int8_t* pIv);
+bool AES_CBC_EncryptInPlace(u_int8_t* pAddr, u_int32_t u32Len, u_int32_t keyType, u_int8_t* pKey, u_int8_t* pIv);
+
+__END_DECLS
+
+#endif /* __DRIVERS_AES_H */

include/drivers/anc_boot.h

@@ -0,0 +1,24 @@
+/*                                                                              
+ * Copyright (c) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef ANC_BOOT_H
+#define ANC_BOOT_H
+
+#define ANC_BOOT_MODE_RESET_ALL_CONTROLLERS			0
+#define ANC_BOOT_MODE_RESET_ONE_CONTROLLER			1
+#define ANC_MIN_ALIGNMENT					16
+
+extern bool anc_reset(int resetMode);
+extern bool anc_firmware_init(void);
+extern size_t anc_read_llb(void* data, size_t size);
+
+#endif
+

include/drivers/apcie.h

@@ -0,0 +1,56 @@
+/*                                                                              
+ * Copyright (c) 2012-2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef APCIE_INIT_H
+#define APCIE_INIT_H
+
+#include <lib/devicetree.h>
+#include <drivers/pci.h>
+#include <sys/types.h>
+
+// 10 second timeout when enabling a link
+#define APCIE_ENABLE_TIMEOUT	10000000
+
+struct apcie_link_config {
+	uint32_t	perst_gpio;
+	uint32_t	clkreq_gpio;
+	unsigned int	dart_id;
+	utime_t		t_perst_delay;
+	utime_t		t_boot_to_perst;
+	utime_t		t_refclk_to_perst;
+};
+
+struct apcie_link_status {
+	bool		enabled;
+};
+
+void apcie_init(void);
+void apcie_use_external_refclk(bool use);
+void apcie_set_s3e_mode(bool reset_on_enable);
+
+void apcie_config_read_raw(void *dst, uint32_t bdfo, int size);
+void apcie_config_write_raw(const void *src, uint32_t bdfo, int size);
+
+bool apcie_enable_link(uint32_t link);
+void apcie_disable_link(uint32_t link);
+void apcie_disable_all(void);
+uint32_t apcie_get_link_enable_count(void);
+void apcie_setup_root_port_bridge(uint32_t link, struct apcie_link_config *config);
+void apcie_update_devicetree(DTNode *apcie_node);
+pci_device_t apcie_get_port_bridge(uint32_t link);
+void apcie_free_port_bridge(uint32_t link);
+
+extern struct apcie_link_config platform_apcie_link_configs[];
+extern struct apcie_link_status apcie_link_statuses[];
+extern struct apcie_link_config *apcie_link_configs;
+
+#endif
+

include/drivers/asp.h

@@ -0,0 +1,9 @@
+#ifndef _ASP_INIT_H
+#define _ASP_INIT_H
+
+int asp_init(void);
+int asp_nand_open(void);
+int asp_set_default_dies_in_parallel(void);
+int asp_disable_uid(void);
+
+#endif // _ASP_INIT_H

include/drivers/buttons.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_BUTTONS_H
+#define __DRIVERS_BUTTONS_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+enum buttons {
+	MENU_KEY,
+	VOLUP_KEY,
+	VOLDOWN_KEY,
+};
+
+typedef void (*button_callback)(bool state);
+
+int buttons_init(void);
+
+/* Callback is executed in interrupt context */
+void button_callback_register(enum buttons button, button_callback callback);
+void button_callback_unregister(enum buttons button, button_callback callback);
+
+__END_DECLS
+
+#endif /* __DRIVERS_BUTTONS_H */

include/drivers/charger.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_CHARGER_H
+#define __DRIVERS_CHARGER_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+void charger_early_init(void);
+void charger_clear_alternate_usb_current_limit(void);
+bool charger_has_usb(int dock);
+bool charger_has_firewire(int dock);
+bool charger_has_external(int dock);
+bool charger_check_usb_change(int dock, bool expected);
+void charger_set_charging(int dock, uint32_t input_current_ma, uint32_t *charge_current_ma);
+void charger_clear_usb_state(void);
+bool charger_set_usb_brick_detect(int dock, int select);
+bool charger_charge_done(int dock);
+bool charger_has_batterypack(int dock);
+uint32_t charger_get_max_charge_current(int dock);
+int charger_read_battery_temperature(int *centiCelsiusTemperature);
+int charger_read_battery_level(uint32_t *milliVolts);
+int charger_set_gasgauge_interface(bool enabled);
+void charger_print_status(void);
+
+__END_DECLS
+
+#endif /* __DRIVERS_CHARGER_H */
+

include/drivers/consistent_debug.h

@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_CONSISTENT_DEBUG__H
+#define __DRIVERS_CONSISTENT_DEBUG__H
+
+
+#include <consistent_debug/consistent_debug_registry.h>
+#include <consistent_debug/consistent_debug_helper_fns.h>
+
+// Functions
+
+// Restores consistent debug state on resume from sleep.
+int consistent_debug_resume(void);
+
+// Set up consistent debug region on cold boot.
+int consistent_debug_init(void);
+
+
+/**
+ * Returns the location of the Consistent Debug Registry
+ * 
+ * @author jdong (1/25/2013)
+ * 
+ * @return A pointer to the debug registry if it exists. NULL if 
+ *         not yet initialized.
+ */
+dbg_registry_t* consistent_debug_get_registry(void);
+
+/**
+ * Attempt to register a header with the supplied information. 
+ * 
+ * @author jdong (12/10/2012)
+ * 
+ * @param hdr: A filled-out header. The debug registry will be 
+ *           filled in with this information.
+ * 
+ * @return dbg_record_header_t*: NULL if unsuccessful. 
+ *         Otherwise, a pointer to the entry in the debug
+ *         registry. It's already filled out, so in the general
+ *         case one would just check if it's non-NULL.
+ */
+dbg_record_header_t* consistent_debug_register_header(dbg_record_header_t hdr);
+
+
+/**
+ * Attempt to deregister a consistent debug header. This might 
+ * have to be done when handing off from a bootloader to an OS, 
+ * or when powering down / resetting a coprocessor. It ensures 
+ * that consumers of a debug region are given a chance to clean 
+ * up before it is no longer valid. 
+ *  
+ * Note the return value. One should initially check that a call 
+ * returns "0" indicating an entry is valid and has been marked 
+ * as being freed. Then, one should poll by calling again with 
+ * the same argument until the return value is 1. 
+ * 
+ * @author jdong (12/14/2012)
+ * 
+ * @param hdr A pointer to a debug header returned by 
+ *            consistent_debug_register_header()
+ * 
+ * @return -1: Error has occurred. Most likely the value passed 
+ *         is not an in-use debug registry header.
+ *          0: Record is marked as being freed -- waiting for
+ *          the other end to acknowledge it. Check again later.
+ *          1: Record has been freed and is now unused.
+ */
+int consistent_debug_unregister_header(dbg_record_header_t *hdr);
+
+
+
+
+/**
+ * Update the AP's Progress Report with the given state and 
+ * state argument. 
+ * 
+ */
+void consistent_debug_update_ap_cpr(cp_state_t state, int arg);
+
+#endif

include/drivers/csi.h

@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __CSI_H
+#define __CSI_H
+
+#include <sys/task.h>
+#include <sys/boot.h>
+
+//
+// Public API
+//
+
+typedef enum {
+  CSI_COPROC_ANS = 0,
+  CSI_COPROC_SEP,
+  CSI_COPROC_ISP,
+  CSI_COPROC_SIO,
+  CSI_COPROC_MAX
+} csi_coproc_t;
+
+#define IOP_NAME(coproc) \
+    (((coproc)==CSI_COPROC_ANS) ? "ANS" : \
+      (((coproc)==CSI_COPROC_SEP) ? "SEP" : \
+        (((coproc)==CSI_COPROC_ISP) ? "ISP" : \
+          (((coproc)==CSI_COPROC_SIO) ? "SIO" : "???"))))
+
+#define KFW(coproc) \
+    (((coproc)==CSI_COPROC_ANS) ? KFW_ANS : \
+      (((coproc)==CSI_COPROC_SEP) ? KFW_SEP : \
+        (((coproc)==CSI_COPROC_ISP) ? 0 : \
+          (((coproc)==CSI_COPROC_SIO) ? KFW_SIO : 0))))
+
+typedef enum {
+  CSI_STATUS_OK = 0,
+  CSI_STATUS_UNSUPPORTED,
+  CSI_STATUS_UNAVAILABLE,
+  CSI_STATUS_ERROR,
+  CSI_STATUS_NO_FIRMWARE,
+  CSI_STATUS_BAD_FIRMWARE,
+  CSI_STATUS_TIMEOUT,
+  CSI_STATUS_PANIC_RECOVER,
+  CSI_STATUS_OUT_OF_RESSOURCES,
+} csi_status_t;
+
+#define CSI_STATUS_STR(status) \
+    (((status)==CSI_STATUS_OK)                      ? "OK" : \
+      (((status)==CSI_STATUS_UNSUPPORTED)           ? "UNSUPPORTED" : \
+        (((status)==CSI_STATUS_UNAVAILABLE)         ? "UNAVAILABLE" : \
+          (((status)==CSI_STATUS_ERROR)             ? "ERROR" : \
+            (((status)==CSI_STATUS_NO_FIRMWARE)     ? "NO_FIRMWARE" : \
+              (((status)==CSI_STATUS_BAD_FIRMWARE)  ? "BAD_FIRMWARE" : \
+                (((status)==CSI_STATUS_TIMEOUT)     ? "TIMEOUT" : "???")))))))
+
+
+typedef uint64_t msg_payload_t;
+
+
+csi_status_t csi_init (csi_coproc_t which_coproc);
+csi_status_t csi_late_init (void);
+
+csi_status_t csi_quiesce (enum boot_target target);
+
+csi_status_t csi_register_endpoint (csi_coproc_t which_coproc, uint32_t ep, struct task_event *event, void **csi_token, const char **name);
+
+void*        csi_allocate_shared_memory (void *csi_token, uint32_t capacity);
+void         csi_free_shared_memory     (void *sm);
+
+csi_status_t csi_receive_message (void *csi_token, msg_payload_t *msg_payload);
+csi_status_t csi_send_message    (void *csi_token, msg_payload_t msg_payload);
+
+//
+// coprocessor feature and status
+//
+
+#define COPROC_FEATURE_NONE                  (0x0000UL)
+#define COPROC_FEATURE_SHUTDOWN_IN_PROGRESS  (0x0001UL)
+#define COPROC_FEATURE_PANIC_RECOVERY        (0x0002UL)
+#define COPROC_FEATURE_ALL                   (0xFFFFFFFFUL)
+
+typedef uint32_t coproc_feature_t;
+
+coproc_feature_t csi_get_feature (csi_coproc_t which_coproc);
+
+static inline bool csi_is_panic_recovery (csi_coproc_t which_coproc)
+{
+  return (csi_get_feature(which_coproc) & COPROC_FEATURE_PANIC_RECOVERY);
+}
+
+static inline bool csi_is_shutdown_in_progress (csi_coproc_t which_coproc)
+{
+  return (csi_get_feature(which_coproc) & COPROC_FEATURE_SHUTDOWN_IN_PROGRESS);
+}
+
+#endif /* !defined(__CSI_H) */

include/drivers/dart.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef _DART_H
+#define _DART_H
+
+#include <sys/types.h>
+
+#define DART_PAGE_SIZE	(4096)
+
+typedef uint32_t	dart_iovm_addr_t;
+
+void dart_init(unsigned int dart_id);
+void dart_enable_translation(unsigned int dart_id);
+void dart_disable_translation(unsigned int dart_id);
+void dart_map_page_range(unsigned int dart_id, uintptr_t paddr, dart_iovm_addr_t vaddr, uint32_t pages, bool write_protect);
+void dart_unmap_page_range(unsigned int dart_id, dart_iovm_addr_t vaddr, uint32_t pages);
+void dart_write_protect_page_range(unsigned int dart_id, dart_iovm_addr_t vaddr, uint32_t pages, bool write_protect);
+void dart_assert_unmapped(unsigned int dart_id);
+
+#endif

include/drivers/display.h

@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2007-2015 Apple Inc. All rights reserved.
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_DISPLAY_H
+#define __DRIVERS_DISPLAY_H
+
+#include <sys/types.h>
+#include <lib/paint.h>
+
+__BEGIN_DECLS
+
+struct display_window {
+	bool active;
+	enum colorspace cs;
+	uint32_t depth;
+	uint32_t pos_x, pos_y;
+	uint32_t width, height;
+	uint32_t stride;
+	struct canvas c;
+	void *ptr; // device specific data
+};
+
+#define kGammaChannelBufferSize (72)
+#define kGammaBufferSize (kGammaChannelBufferSize * 3)
+
+struct display_gamma_table {
+	uint32_t display_id;
+	uint32_t display_id_mask;
+	uint8_t  display_gamma_data[kGammaBufferSize];
+};
+typedef struct display_gamma_table display_gamma_table;
+
+struct syscfg_glcl {
+	uint8_t	minor_vers;
+	uint8_t	major_vers;
+	uint8_t reserved[2];
+	uint8_t	gamma_data[kGammaBufferSize];
+};
+
+int display_init(void);
+int display_quiesce(bool clear_display);
+void display_clear(void);
+
+bool display_get_enable(void);
+void display_set_enable(bool enable, uint32_t *color);
+bool display_set_rotation(bool rotate180);
+void display_delay_frames(uint32_t frames);
+void display_set_background_color(uint32_t color);
+
+struct display_window *display_create_window(uint32_t x, uint32_t y, uint32_t width, uint32_t height, enum colorspace color);
+void display_destroy_window(struct display_window *win);
+void display_move_window(struct display_window *win, uint32_t x, uint32_t y);
+void display_activate_window(struct display_window *win);
+void display_deactivate_window(struct display_window *win);
+void display_set_window_fb(struct display_window *win, void *fb);
+
+struct display_info {
+	addr_t   framebuffer;
+	uint32_t width;
+	uint32_t height;
+	uint32_t stride;
+	uint32_t depth;
+};
+
+/* after the fact get the information about the current display */
+int display_get_info(struct display_info *info);
+
+struct display_timing
+{
+	const char	*display_name;
+
+	uint32_t	host_clock_id;
+	uint32_t	pixel_clock;
+
+	uint32_t	dot_pitch;
+
+	uint32_t	h_active;
+	uint32_t	h_back_porch;
+	uint32_t	h_front_porch;
+	uint32_t	h_pulse_width;
+	uint32_t	v_active;
+	uint32_t	v_back_porch;
+	uint32_t	v_front_porch;
+	uint32_t	v_pulse_width;
+
+	bool		neg_vclk;
+	bool		neg_hsync;
+	bool		neg_vsync;
+	bool		neg_vden;
+
+	uint32_t	display_depth;
+	uint32_t	display_type;
+	void		*display_config;
+};
+
+#define DISPLAY_TYPE_DUMB	(0)
+#define DISPLAY_TYPE_SMART	(1)
+#define DISPLAY_TYPE_MERLOT	(2)
+#define DISPLAY_TYPE_PINOT	(3)
+#define DISPLAY_TYPE_TMDS	(4)
+#define DISPLAY_TYPE_DP 	(5)
+#define DISPLAY_TYPE_EDP 	(6)
+#define DISPLAY_TYPE_HDMI	(7)
+#define	DISPLAY_TYPE_SUMMIT	(8)
+
+__END_DECLS
+
+#endif /* __DRIVERS_DISPLAY_H */

include/drivers/displayAV.h

@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2012-2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef DRIVERS_DISPLAYAV_H
+#define DRIVERS_DISPLAYAV_H	1
+
+
+enum {
+        kDisplayAxisTypeHorizontal,
+        kDisplayAxisTypeVertical,
+        kDisplayAxisCount
+};
+
+enum {
+        kDisplayColorSpacesRGB,
+        kDisplayColorSpacesYCbCr422,
+        kDisplayColorSpacesYCbCr444
+};
+
+enum {
+	kDisplayColorDynamicRangeFull,
+	kDisplayColorDynamicRangeLimited,
+	kDisplayColorDynamicRangeVESA   = kDisplayColorDynamicRangeFull,
+	kDisplayColorDynamicRangeCEA    = kDisplayColorDynamicRangeLimited
+};
+
+enum {
+        kDisplayColorCoefficientITU601,               
+        kDisplayColorCoefficientITU709
+};
+
+enum {
+    kDisplayTestModeOff,
+    kDisplayTestModeColorRamp,
+    kDisplayTestModeBlackWhiteVLines,
+    kDisplayTestModeColorSquare,
+    kDisplayTestModeInvalid,
+    kDisplayTestModeColorBar32,
+    kDisplayTestModeColorBar64,
+    kDisplayTestModeWhiteGrayBlackBar32,
+    kDisplayTestModeWhiteGrayBlackBar64,
+    kDisplayTestModeMobileWhiteBar32,
+    kDisplayTestModeMobileWhiteBar64    
+};
+
+enum {
+    kDisplayColorRGBQuantizationRangeDefault,
+    kDisplayColorRGBQuantizationRangeLimited,
+    kDisplayColorRGBQuantizationRangeFull
+};
+
+struct video_color_data {
+        u_int32_t           depth;
+        u_int32_t           space; 
+        u_int32_t           range; 
+        u_int32_t           coefficient;
+};
+
+struct video_timing_axis {
+        uint32_t            total;
+        uint32_t            active;
+        uint32_t            sync_width;
+        uint32_t            back_porch;
+        uint32_t            front_porch;
+        int32_t             sync_rate;
+        uint32_t            sync_polarity;        
+};
+
+struct video_timing_data {
+        bool                                interlaced;
+        struct video_timing_axis         axis[kDisplayAxisCount];    
+};
+
+struct video_link_data {
+        bool                            mirror_mode;
+        u_int32_t                       test_mode;
+        struct video_color_data		color;
+        struct video_timing_data	timing;
+};
+
+
+typedef enum {
+	kDisplayInfoFrameTypeReserved              = 0x80,
+	kDisplayInfoFrameTypeVendorSpecific        = 0x81,
+	kDisplayInfoFrameTypeAVI                   = 0x82,
+	kDisplayInfoFrameTypeProductDescription    = 0x83,
+	kDisplayInfoFrameTypeAudio                 = 0x84,
+	kDisplayInfoFrameTypeMPEG                  = 0x85,
+	kDisplayInfoFrameTypeMin                   = kDisplayInfoFrameTypeReserved,
+	kDisplayInfoFrameTypeMax                   = kDisplayInfoFrameTypeMPEG,
+	kDisplayInfoFrameTypeCount                 = 1 + (kDisplayInfoFrameTypeMax - kDisplayInfoFrameTypeMin)
+} display_infoframe_type;
+
+struct display_infoframe {
+	display_infoframe_type   type;
+	uint8_t             version;
+	uint8_t             length;
+	uint8_t             checksum;
+	uint8_t             data[28];
+};
+
+#endif

include/drivers/display_pmu.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef DRIVERS_DISPLAY_PMU_H
+#define DRIVERS_DISPLAY_PMU_H	1
+
+#if WITH_HW_CHESTNUT
+#define DISPLAY_PMU_LDO(n)	(((n) + 1) << 2)
+#endif
+
+int display_pmu_init(void);
+int display_pmu_quiesce(void);
+void display_pmu_update_device_tree(const char *node);
+
+#endif /* DRIVERS_DISPLAY_PMU_H */
+

include/drivers/displayport.h

@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2010-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef DRIVERS_DISPLAYPORT_H
+#define DRIVERS_DISPLAYPORT_H	1
+
+#include <drivers/display.h>
+#include <drivers/displayAV.h>
+
+#define kDPMaxLanes 4
+
+
+enum {
+	kLinkRate000Gbps	= 0x0,
+	kLinkRate162Gbps	= 0x6,
+	kLinkRate270Gbps	= 0xa,
+	kLinkRate324Gbps	= 0x0c,
+	kLinkRate540Gbps	= 0x14
+};
+
+enum {
+        kDPVoltageLevel0,
+        kDPVoltageLevel1,
+        kDPVoltageLevel2,
+        kDPVoltageLevel3,
+        kDPVoltageLevelMin = kDPVoltageLevel0,
+        kDPVoltageLevelMax = kDPVoltageLevel3
+};
+
+enum {
+        kDPEQLevel0,
+        kDPEQLevel1,
+        kDPEQLevel2,
+        kDPEQLevel3,
+        kDPEQLevelMin = kDPEQLevel0,
+        kDPEQLevelMax = kDPEQLevel3
+};
+
+enum {
+        kDPTrainingPatternNone,
+        kDPTrainingPattern1,
+        kDPTrainingPattern2,
+        kDPTrainingPattern3
+};
+
+enum {
+        kDPLaneStatusFlagClockRecoveryDone      = (1<<0),
+        kDPLaneStatusFlagsEQDone                = (1<<1),
+        kDPLaneStatusFlagsSymbolLocked          = (1<<2),
+        kDPLaneStatusFlagsMask                  = (0x7)
+};
+
+enum {
+    kDPAlignmentStatusFlagsDone               = (1<<0),
+    kDPAlignmentStatusFlagsDownstreamChanged  = (1<<6),
+    kDPAlignmentStatusFlagsLinkUpdated        = (1<<7),
+};
+
+enum {
+    kDPDownstreamTypeDP,
+    kDPDownstreamTypeVGA,
+    kDPDownstreamTypeDVI,
+    kDPDownstreamTypeHDMI,
+    kDPDownstreamTypeOther,
+    kDPDownstreamTypeCount
+};
+
+struct dp_link_training_lane_data {
+        u_int32_t       voltage;
+        u_int32_t       eq;
+};
+
+struct dp_link_train_data {
+    bool        enhanced_mode;
+    bool	assr;
+    bool        downspread;
+    bool        fast;
+    u_int32_t   lane_count;
+    u_int32_t   link_rate;
+    struct dp_link_training_lane_data lane[kDPMaxLanes];
+};
+
+
+// controller config flags
+
+enum {
+	kDPControllerMode_Master = 0,
+	kDPControllerMode_Slave
+};
+#define kDPControllerMode_Mask		0xf
+#define kDPControllerMode_Shift		4
+
+enum {
+	kDPControllerType_DP = 0,
+	kDPControllerType_EDP
+};
+#define kDPControllerType_Mask		0xf
+#define kDPControllerType_Shift		0
+
+#include <drivers/display.h>
+
+// global
+int displayport_init(dp_t *dp);
+int displayport_init_with_timing_info(struct display_timing *timing_info);
+int displayport_set_timings(struct display_timing *timing_info);
+int displayport_start_video(void);
+int displayport_enable_alpm(bool enable);
+bool displayport_video_configured();
+void displayport_quiesce();			
+
+// eDP support
+#if WITH_HW_DISPLAY_EDP
+#define kEDPRawPanelIdLength	16
+
+int displayport_get_raw_panel_id(u_int8_t *raw_panel_id);
+#endif // WITH_HW_DISPLAY_EDP
+
+// controller
+int dp_controller_start(dp_t *);
+void dp_controller_stop();
+int dp_controller_validate_video(struct video_timing_data *data);
+int dp_controller_read_bytes_dpcd(u_int32_t addr, u_int8_t *data, u_int32_t length);
+int dp_controller_read_bytes_i2c(u_int32_t device_addr, u_int32_t addr, u_int8_t *data, u_int32_t length);
+int dp_controller_write_bytes_dpcd(u_int32_t addr, u_int8_t *data, u_int32_t length);
+int dp_controller_write_bytes_i2c(u_int32_t device_addr, u_int32_t addr, u_int8_t *data, u_int32_t length);
+int dp_controller_train_link(struct dp_link_train_data *data);
+int dp_controller_get_adjustment_levels(u_int32_t lane, u_int32_t *voltage_swing, u_int32_t *eq);
+int dp_controller_set_adjustment_levels(u_int32_t lane, u_int32_t voltage_swing, u_int32_t eq, 
+                                      bool *voltage_max_reached, bool *eq_max_reached);
+int dp_controller_set_training_pattern(u_int32_t value, bool scramble);
+int dp_controller_get_training_pattern(u_int32_t *value, bool *scramble);
+int dp_controller_set_link_rate(u_int32_t link_rate);
+int dp_controller_get_link_rate(u_int32_t *link_rate);
+int dp_controller_set_lane_count(uint32_t lane_count);
+int dp_controller_get_lane_count(uint32_t * lane_count);
+int dp_controller_set_enhanced_mode(bool mode);
+int dp_controller_get_enhanced_mode(bool * mode);
+int dp_controller_set_ASSR(bool mode);
+int dp_controller_get_ASSR(bool * mode);
+int dp_controller_set_downspread(bool state);
+int dp_controller_get_downspread(bool *state);
+int dp_controller_start_video(struct video_link_data *data);
+int dp_controller_stop_video();
+u_int32_t dp_controller_get_max_lane_count();
+u_int32_t dp_controller_get_max_link_rate();
+u_int32_t dp_controller_get_min_lane_count();
+u_int32_t dp_controller_get_min_link_rate();
+bool dp_controller_get_supports_downspread();
+bool dp_controller_get_supports_fast_link_training();
+bool dp_controller_get_supports_alpm();
+int dp_controller_enable_alpm(bool enable, struct video_link_data *data);
+
+bool dp_controller_video_configured();
+bool dp_controller_wait_for_edp_hpd(utime_t *hpd_time);
+void dp_controller_wait_for_HPD_to_BL(utime_t hpd_time);
+
+void dp_controller_wait_phy_locked(void);
+
+// device
+
+int dp_device_start(bool edp_panel);
+int dp_device_wait_started(utime_t timeout);
+void dp_device_stop();
+int dp_device_get_alignment_status_mask(u_int32_t *mask);
+int dp_device_get_lane_status_mask(uint32_t lane, uint32_t *mask);
+int dp_device_get_training_pattern(uint32_t *value, bool *scramble);
+int dp_device_set_training_pattern(uint32_t value, bool scramble);
+int dp_device_get_requested_adjustment_levels(uint32_t lane, u_int32_t *voltage, u_int32_t *eq);
+int dp_device_set_adjustment_levels(uint32_t lane, u_int32_t voltage_swing, u_int32_t eq, 
+                                bool voltage_max_reached, bool eq_max_reached);
+int dp_device_get_enhanced_mode(bool * value);
+int dp_device_set_enhanced_mode(bool value);
+int dp_device_get_ASSR(bool * value);
+int dp_device_set_ASSR(bool value);
+int dp_device_get_downspread(bool * value);
+int dp_device_set_downspread(bool value);
+int dp_device_get_lane_count(uint32_t * value);
+int dp_device_set_lane_count(uint32_t value);
+int dp_device_get_link_rate(u_int32_t * value);
+int dp_device_set_link_rate(u_int32_t value);
+int dp_device_hdcp_enable(bool enable);
+int dp_device_get_downstream_port_type(int *ret_value);
+int dp_device_get_raw_panel_id(u_int8_t *raw_panel_id);
+int dp_device_get_sink_count(uint8_t * value);
+
+bool dp_device_get_supports_fast_link_training();
+bool dp_device_get_supports_alpm();
+int dp_device_enable_alpm(bool enable);
+bool dp_device_is_alpm_enabled();
+bool dp_device_get_supports_enhanced_mode();
+bool dp_device_get_supports_assr();
+bool dp_device_get_supports_downspread();
+u_int32_t dp_device_get_revision();
+u_int32_t dp_device_get_max_lane_count();
+u_int32_t dp_device_get_max_link_rate();
+
+
+
+#endif

include/drivers/dither.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_DITHER_H
+#define __DRIVERS_DITHER_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+#define	DITHER_NONE		(0 << 0)
+#define	DITHER_BLUE_NOISE	(1 << 0)
+#define	DITHER_SPATIO_TEMPORAL	(1 << 1)
+#define DITHER_ERROR_DIFFUSION	(1 << 2)
+
+#if DITHER_VERSION == 4
+void dither_init(uint32_t display_width, uint32_t display_height, uint32_t display_depth);
+#else
+void dither_init(uint32_t display_depth);
+#endif
+void dither_set_enable(bool enable);
+
+__END_DECLS
+
+#endif /* __DRIVERS_DITHER_H */

include/drivers/dma.h

@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2008 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_DMA_H
+#define __DRIVERS_DMA_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+#define DMA_CMD_DIR_MEM		(0x00000000)
+#define DMA_CMD_DIR_TX		(0x00000001)
+#define DMA_CMD_DIR_RX		(0x00000002)
+#define DMA_CMD_DIR_MASK	(0x00000003)
+
+void dma_init(void);
+
+/*
+ *  dma_execute_cmd - simple DMA operation
+ *
+ *    cmd         - operation mode: MEM (MEMORY-MEMORY), TX (MEMORY-DEVICE) or RX (DEVICE-MEMORY)
+ *    dma_channel - dma channel number
+ *    src         - source buffer or fifo
+ *    dst         - desination buffer or fifo
+ *    length      - size in bytes of the operation
+ *    word_size   - size in bytes of each word
+ *    burst_size  - size in words of each burst
+ *
+ *    Returns 0 on success or -1 on failure
+ */
+int dma_execute_cmd(u_int32_t cmd, int dma_channel,
+		    void *src, void *dst, u_int32_t length,
+		    u_int32_t word_size, u_int32_t burst_size);
+
+
+/*
+ * dma_execute_async - complex async DMA operation
+ *
+ *    cmd            - operation mode: MEM (MEMORY-MEMORY), TX (MEMORY-DEVICE) or RX (DEVICE-MEMORY)
+ *    dma_channel    - dma channel number
+ *    sgl            - memory scatter/gather list
+ *    fifo           - device fifo address
+ *    length         - size in bytes of the operation
+ *    word_size      - size in bytes of each word
+ *    burst_size     - size in words of each burst
+ *    completion     - completion callback
+ *    completion_arg - argument passed to callback
+ *
+ *    Returns 0 on success or -1 on failure
+ *
+ */
+
+struct dma_segment {
+	u_int32_t	paddr;
+	u_int32_t	length;
+};
+
+typedef void	(* dma_completion_function)(void *);
+
+int dma_execute_async(u_int32_t cmd, int dma_channel,
+		      struct dma_segment *sgl, void *fifo, u_int32_t length, 
+		      u_int32_t word_size, u_int32_t burst_size,
+		      dma_completion_function completion, void *completion_arg);
+
+void dma_use_int(int dma_channel, bool use);
+
+bool dma_poll(int dma_channel);
+
+/*
+ * dma_cancel - cancel DMA operation on a given channel.
+ *
+ * When this returns, the numbered DMA channel is guaranteed to be idle.
+ */
+
+void dma_cancel(int dma_channel);
+
+/*
+ * DMA channel encryption
+ *
+ * A channel is configured to perform AES en/decryption by calling dma_set_aes()
+ * with a dma_aes_config structure.  If NULL is passed as an argument, encryption
+ * is disabled for the channel; the en/decryption state is also reset at the completion
+ * or aborting of the transaction.
+ *
+ * The caller is responsible for ensuring the dma_aes_config structure remains valid
+ * for the duration of the operation.
+ *
+ * A constant key is used for a given DMA operation, however the caller may specify
+ * that a transfer should be broken into constant-sized chunks.  For each chunk, the
+ * iv_func hook will be invoked with the chunk index (offset from 0 at the start of
+ * the transaction).
+ * 
+ */
+
+struct dma_aes_config {
+	/* AES configuration */
+	u_int32_t	command;	/* AES_CMD bits from <drivers/aes.h> */
+	u_int32_t	keying;		/* AES_KEY bits from <drivers/aes.h> */
+	void		*key;		/* AES key for AES_KEY_TYPE_USER */
+
+	/* IV generation */
+	u_int32_t	chunk_size;	/* AES chunk size */
+	void		(* iv_func)(void *arg, u_int32_t chunk_index, void *iv_buffer);
+	void		*iv_func_arg;
+};
+
+int dma_set_aes(int dma_channel, struct dma_aes_config *config);
+
+
+__END_DECLS
+
+#endif /* __DRIVERS_DMA_H */

include/drivers/dpb.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_DPB_H
+#define __DRIVERS_DPB_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+#if DPB_VERSION < 2
+void dpb_init(void);
+#else
+void dpb_init(uint32_t display_width, uint32_t display_height);
+#endif
+void dpb_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl);
+
+__END_DECLS
+
+#endif /* __DRIVERS_DPB_H */

include/drivers/dram.h

@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2010-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __JEDEC_H
+#define __JEDEC_H
+
+/* Based on JEDEC LPDDR2 spec */
+
+enum {
+        JEDEC_MANUF_ID_RSVD0   = 0,
+        JEDEC_MANUF_ID_SAMSUNG,
+        JEDEC_MANUF_ID_QIMONDA,
+        JEDEC_MANUF_ID_ELPIDA,
+        JEDEC_MANUF_ID_ETRON,
+        JEDEC_MANUF_ID_NANYA,
+        JEDEC_MANUF_ID_HYNIX,
+        JEDEC_MANUF_ID_MOSEL,
+        JEDEC_MANUF_ID_WINBOND,
+        JEDEC_MANUF_ID_ESMT,
+        JEDEC_MANUF_ID_RSVD1,
+        JEDEC_MANUF_ID_SPANSION,
+        JEDEC_MANUF_ID_SST,
+        JEDEC_MANUF_ID_ZMOS,
+        JEDEC_MANUF_ID_INTEL,
+        JEDEC_MANUF_ID_NUMONYX,
+        JEDEC_MANUF_ID_MICRON,
+        JEDEC_MANUF_ID_RSVD2,
+	JEDEC_NUM_MANUF_IDS
+};
+
+// LPDDR4 vendor ids
+#define JEDEC_LPDDR4_MANUF_ID_SAMSUNG		JEDEC_MANUF_ID_SAMSUNG
+#define JEDEC_LPDDR4_MANUF_ID_HYNIX		JEDEC_MANUF_ID_HYNIX
+#define JEDEC_LPDDR4_MANUF_ID_MICRON		0xFF
+#define JEDEC_LPDDR4_MANUF_ID_ELPIDA		JEDEC_LPDDR4_MANUF_ID_MICRON
+
+enum {
+	JEDEC_TYPE_S4_SDRAM = 0,
+	JEDEC_TYPE_S2_SDRAM
+};
+
+enum {
+	JEDEC_IO_WIDTH_32 = 0,
+	JEDEC_IO_WIDTH_16,
+	JEDEC_IO_WIDTH_8
+};
+
+enum {
+	JEDEC_DENSITY_64Mb = 0,
+	JEDEC_DENSITY_128Mb,
+	JEDEC_DENSITY_256Mb,
+	JEDEC_DENSITY_512Mb,
+	JEDEC_DENSITY_1Gb,
+	JEDEC_DENSITY_2Gb,
+	JEDEC_DENSITY_4Gb,
+	JEDEC_DENSITY_8Gb,
+	JEDEC_DENSITY_16Gb,
+	JEDEC_DENSITY_32Gb
+};
+
+enum {
+	JEDEC_LPDDR4_DENSITY_4Gb = 0,
+	JEDEC_LPDDR4_DENSITY_6Gb,
+	JEDEC_LPDDR4_DENSITY_8Gb,
+	JEDEC_LPDDR4_DENSITY_12Gb,
+	JEDEC_LPDDR4_DENSITY_16Gb,
+	JEDEC_LPDDR4_DENSITY_24Gb,
+	JEDEC_LPDDR4_DENSITY_32Gb
+};
+
+	
+#define JEDEC_MR8_TYPE_SHIFT	(0)
+#define JEDEC_MR8_TYPE_MASK	(0x3)
+#define JEDEC_MR8_DENSITY_SHIFT	(2)
+#define JEDEC_MR8_DENSITY_MASK	(0xF)
+#define JEDEC_MR8_WIDTH_SHIFT	(6)
+#define JEDEC_MR8_WIDTH_MASK	(0x3)
+
+#endif // __JEDEC_H

include/drivers/edgeic.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2007 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+
+#ifndef __DRIVERS_EDGEIC_H
+#define __DRIVERS_EDGEIC_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+void edgeic_reset(void);
+void edgeic_select_edge(u_int32_t vector, bool edge);
+void edgeic_clear_interrupt(u_int32_t vector);
+
+__END_DECLS
+
+#endif /* __DRIVERS_EDGEIC_H */

include/drivers/ethernet.h

@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_ETHERNET_H
+#define __DRIVERS_ETHERNET_H
+
+#include <sys/types.h>
+#include <lib/net/mbuf.h>
+
+__BEGIN_DECLS
+
+typedef struct ethq {
+	int read,write;
+	int numentries;
+	int queue_len;
+	int queue_len_mask;
+
+	mymbuf_t **packets; // pointer to an array of pointers to mbufs
+} ethqueue_t;
+
+typedef struct ethdstats {
+	int rxerrors; //Sum of all errors
+	int txerrors; //Sum of all errors
+	int runt; //?
+	int extra; //?
+	int crc; // crc error
+	int dribble; //?
+	int rxmissed;
+	int txcollisions;
+	int rxpktok;
+	int txpktok;
+	int rxbytes;
+	int txbytes;
+} ethdstats_t;
+
+
+typedef struct ethpriv
+{
+	ethdstats_t dstats;
+	ethqueue_t rxqueue;
+	ethqueue_t txqueue;
+	char macaddr[6];
+} ethstat_t;
+
+//Function declarations
+//
+//eth_init()
+//NULL on failure, ptr private data otherwise.
+int eth_init(void);
+
+int eth_start(ethstat_t *);
+
+int eth_stop(ethstat_t *);
+
+ethstat_t *eth_get_handle(void);
+
+int eth_printstatus(ethstat_t *);
+
+int eth_getpkt(ethstat_t *,char *buffer,int *len);
+
+int eth_output_packet(ethstat_t *d, const char *pkt,int len,int flag);
+
+void eth_setmacaddr(ethstat_t *data, const char macaddr[6]);
+
+void eth_getmacaddr(ethstat_t *data,char *buf);
+
+void eth_uninit(ethstat_t *data);
+
+#if WITH_HW_ETHERNET_SWITCH
+int eth_switch_init(void);
+#endif
+
+
+
+__END_DECLS
+
+#endif /* __DRIVERS_ETHERNET_H */
+

include/drivers/flash_nand.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_FLASH_NAND_H
+#define __DRIVERS_FLASH_NAND_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+int 	flash_nand_init(void);
+int 	flash_nand_id(void);
+
+#if WITH_HW_BOOTROM_NAND
+/* page offset into block zero from which the bootblock should be read */
+#define NAND_BOOTBLOCK_OFFSET	2
+
+int	nand_read_bootblock(u_int8_t interface, u_int8_t cs, void *buffer, size_t *size);
+#endif
+
+__END_DECLS
+
+#endif /* __DRIVERS_FLASH_NAND_H */

include/drivers/flash_nor.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ * Copyright (C) 2007-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_FLASH_NOR_H
+#define __DRIVERS_FLASH_NOR_H
+
+#include <sys/types.h>
+#include <lib/blockdev.h>
+
+__BEGIN_DECLS
+
+struct nor_blockdev {
+	struct blockdev bdev;
+
+	uintptr_t handle;
+
+	int (* readRange)(uintptr_t handle, uint8_t *ptr, uint32_t offset, uint32_t length);
+	int (* writeRange)(uintptr_t handle, const uint8_t *ptr, uint32_t offset, uint32_t length);
+	int (* eraseRange)(uintptr_t handle, uint32_t offset, uint32_t length);
+};
+
+/* pass -1 for which_device to use the target-defined default device */
+int flash_nor_init(int which_device);
+int flash_nor_register(struct nor_blockdev *nor_bdev, const char *name, uint64_t len, uint32_t block_size);
+
+__END_DECLS
+
+#endif /* __DRIVERS_FLASH_NOR_H */

include/drivers/gasgauge.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2009 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_GASGAUGE_H
+#define __DRIVERS_GASGAUGE_H
+
+#include <sys/types.h>
+#include <drivers/power.h>
+
+__BEGIN_DECLS
+
+void gasgauge_init(void);
+void gasgauge_late_init(void);
+void gasgauge_print_status(void);
+
+#define GG_NEEDS_PRECHARGE (1<<0)
+#define GG_NEEDS_RESET     (1<<1)
+#define GG_COMMS_WD        (1<<2)
+
+int gasgauge_needs_precharge(int debug_print_level, bool debug_show_target);
+void gasgauge_will_shutdown(void);
+bool gasgauge_full(void);
+int gasgauge_get_battery_id(u_int8_t *buf, int size);
+bool gasgauge_check_health(unsigned int vbat_mv);
+bool gasgauge_read_charge_table(struct power_charge_limits *table, size_t num_elems);
+
+// gasgauge_read_temperature: returns 0 on success 
+int gasgauge_read_temperature(int *centiCelsiusTemperature);
+// gasgauge_read_voltage: returns 0 on success 
+int gasgauge_read_voltage(unsigned int *milliVolt);
+int gasgauge_read_design_capacity(unsigned int *milliAmpHours);
+int gasgauge_read_soc(unsigned int *soc);
+int gasgauge_reset_timer(int debug_print_level, unsigned int timeout);
+
+// Gas Gauge Flags
+enum {
+    kHDQRegFlagsMaskOTC			= (1 << 15),
+    kHDQRegFlagsMaskOTD			= (1 << 14),
+    kHDQRegFlagsMaskCHG_INH		= (1 << 11),
+    kHDQRegFlagsMaskXCHG		= (1 << 10),
+
+    kHDQRegFlagsMaskIMAXOK		= (1 << 13),    // Aquarius
+    kHDQRegFlagsMaskTC2			= (1 << 11),    // 0x800 Aquarius
+    kHDQRegFlagsMaskTC1			= (1 << 10),    // 0x400 Aquarius
+
+    kHDQRegFlagsMaskFC			= (1 << 9),
+    kHDQRegFlagsMaskCHG			= (1 << 8),
+    kHDQRegFlagsMaskCCA_REQ		= (1 << 5),	// Aquarius
+    kHDQRegFlagsMaskLOWV		= (1 << 4),	// A4
+    kHDQRegFlagsMaskSOC1		= (1 << 2),
+    kHDQRegFlagsMaskSOCF		= (1 << 1),
+    kHDQRegFlagsMaskDSG			= (1 << 0),
+};
+
+__END_DECLS
+
+#if (WITH_HW_GASGAUGE && DEBUG_BUILD)
+// define BATTERY_TRAP_DEBUG for full gas gauge register dump in gasgauge_needs_precharge
+#define BATTERY_TRAP_DEBUG
+#endif
+#endif /* __DRIVERS_GAUGE_H */
+

include/drivers/hdc.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_HDC_H
+#define __DRIVERS_HDC_H
+
+#include <sys/types.h>
+#include <lib/blockdev.h>
+
+__BEGIN_DECLS
+
+/* Generic Device defines */
+#define HDC_BLOCK_SIZE		512
+
+#define HDC_CMD_READ		0x01
+#define HDC_CMD_WRITE		0x02
+#define HDC_CMD_INT		0x80
+#define HDC_CMD_MASK		0x7F
+
+#define HDC_ST_READY		0x0
+#define HDC_ST_BUSY		0x1
+#define HDC_ST_DONE		0x2
+#define HDC_ST_ERROR		0x3
+
+#define HDC_SET_CMD_CMD(r,c)	((r) | (((c) & 0xff) << 24))
+#define HDC_SET_CMD_DISK(r,c)	((r) | (((c) & 0xff) << 16))
+#define HDC_SET_CMD_LEN(r,c)	((r) | (((c) & 0xff) <<  0))
+
+#define HDC_GET_STATUS_ST(r)	(((r) >> 24) & 0xff)
+#define HDC_GET_STATUS_DISK(r)	(((r) >> 16) & 0xff)
+#define HDC_GET_STATUS_CNT(r)	(((r) >>  0) & 0xffff)
+
+
+int hdc_init(void);
+
+__END_DECLS
+
+#endif /* __DRIVERS_HDC_H */

include/drivers/hdmi.h

@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef DRIVERS_HDMI_H
+#define DRIVERS_HDMI_H	1
+
+#include <drivers/displayAV.h>
+#include <drivers/display.h>
+
+// Color component limits for limited range color
+#define kVideoColorLimitedRangeYMin     16     // Also used for RGB
+#define kVideoColorLimitedRangeYMax     235    // Also used for RGB
+#define kVideoColorLimitedRangeCMin     16
+#define kVideoColorLimitedRangeCMax     240
+
+// Timing Generator Limits (max value + 1)
+#define kHorizontalTotalLimit           8192u
+#define kHorizontalActiveLimit          4096u
+#define kHorizontalBlankLimit           4096u
+#define kVerticalTotalLimit             2048u
+#define kVerticalActiveLimit            2048u
+#define kVerticalBlankLimit             2048u
+
+#define kPHYReadyPollIntervalMS         10
+#define kVideoStabilizationIntervalMS   60
+
+// controller config flags
+
+enum {
+	kHDMIControllerMode_Master = 0,
+	kHDMIControllerMode_Slave
+};
+#define kHDMIControllerMode_Mask		0xf
+#define kHDMIControllerMode_Shift		4
+
+enum {
+	kHDMIControllerType_HDMI	= 0,
+};
+#define kHDMIControllerType_Mask		0xf
+#define kHDMIControllerType_Shift		0
+
+enum {
+	kHDMI_tx_mode_None = 0,
+	kHDMI_tx_mode_HDMI = 1,
+	kHDMI_tx_mode_DVI = 2,
+} TX_Mode;
+
+struct pixel {
+	uint16_t    r;  // R or Cr
+	uint16_t    g;  // G or Y
+	uint16_t    b;  // B or Cb
+};
+
+// global
+int hdmi_init();
+int hdmi_init_with_timing_info(struct display_timing *timing_info);
+int hdmi_set_timings(struct display_timing *timing_info);
+int hdmi_start_video(void);
+bool hdmi_video_configured();
+void hdmi_quiesce();			
+
+// controller
+int hdmi_controller_start(u_int8_t type, u_int8_t mode);
+void hdmi_controller_stop();
+int hdmi_controller_validate_video(struct video_timing_data *data);
+int hdmi_controller_read_bytes_i2c(u_int32_t device_addr, u_int8_t addr, u_int8_t *data, u_int32_t length);
+int hdmi_controller_write_bytes_i2c(u_int32_t device_addr, u_int32_t addr, u_int8_t *data, u_int32_t length);
+int hdmi_controller_start_video(struct video_link_data *data, uint32_t pixel_clock);
+int hdmi_controller_stop_video();
+
+uint8_t hdmi_read_reg(uint32_t offset);
+void hdmi_write_reg(uint32_t offset, uint8_t value);
+
+bool hdmi_controller_video_configured();
+
+// device
+
+int hdmi_device_start();
+int hdmi_device_wait_started();
+void hdmi_device_stop();
+#endif

include/drivers/iic.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2007-2008 Apple Inc. All rights reserved.
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_IIC_H
+#define __DRIVERS_IIC_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+typedef enum {
+	IIC_NORMAL = 1,
+	IIC_COMBINED = 2,
+} iic_fmt_t;
+
+void iic_init(void);
+void iic_set_filter(int iic, uint32_t value);
+void iic_set_frequency(int iic, u_int32_t frequency);
+int iic_read(int iic, uint8_t address, const void *send_data, size_t send_len, void *data, size_t len, iic_fmt_t fmt);
+int iic_write(int iic, uint8_t address, const void *data, size_t len);
+
+bool iic_probe(int iic, uint8_t address);
+
+__END_DECLS
+
+#endif /* __DRIVERS_IIC_H */

include/drivers/iis.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_IIS_H
+#define __DRIVERS_IIS_H
+
+#include <sys/types.h>
+#include <sys.h>
+#include <platform.h>
+
+__BEGIN_DECLS
+
+void iis_set_master(int iis, bool master);
+int iis_set_bcpf(int iis, int bcpf);
+int iis_set_usb(int iis, bool usb);
+void iis_set_bclk_scaler(int iis, int bclk_scaler);
+
+void iis_tx(int iis, void *buf, size_t len);
+
+bool iis_is_done(int iis);
+bool iis_wait_done(int iis, int ms);
+
+__END_DECLS
+
+#endif /* __DRIVERS_IIS_H */

include/drivers/ipipe.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef IPIPE_H
+#define IPIPE_H
+
+#include <stdint.h>
+
+typedef struct ipipe ipipe_t;
+
+typedef void (ipipe_tx_callback_t)(void *priv, const uint8_t *packet, uint32_t bytes);
+
+ipipe_t *ipipe_init(uint32_t max_packet_size, ipipe_tx_callback_t *tx_callback, void *priv);
+void ipipe_quiesce_and_free(ipipe_t *ipipe);
+void ipipe_handle_packet(ipipe_t *ipipe, const uint8_t *packet, uint32_t bytes);
+
+#endif

include/drivers/mcu.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2010 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_MCU_H
+#define __DRIVERS_MCU_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+int mcu_init(void);
+int mcu_start_recover(void);
+int mcu_start_boot(void);
+int mcu_set_passthrough_mode(bool on);
+int mcu_send_info_frames(bool on);
+int mcu_quiesce_uart(void);
+
+__END_DECLS
+
+#endif /* __DRIVERS_MCU_H */
+

include/drivers/mipi.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2008 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_MIPI_H
+#define __DRIVERS_MIPI_H
+
+#include <drivers/display.h>
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+int  mipi_dsim_init(struct display_timing *timing, enum colorspace color);
+void mipi_dsim_enable_high_speed(bool enable);
+void mipi_dsim_enable_video(bool enable);
+int  mipi_dsim_quiesce(void);
+int  mipi_dsim_send_short_command(u_int8_t cmd, u_int8_t data0, u_int8_t data1);
+int  mipi_dsim_send_long_command(u_int8_t cmd, const u_int8_t *data, u_int32_t length);
+int  mipi_dsim_read_short_command(u_int8_t cmd, u_int8_t *data);
+int  mipi_dsim_read_long_command(u_int8_t cmd, u_int8_t *data, u_int32_t *length);
+
+/* DSIM command types */
+#define DSIM_TYPE_DSC_WRITE		0x05
+#define DSIM_TYPE_DSC_READ		0x06
+#define DSIM_TYPE_GEN_READ_1P		0x14
+#define DSIM_TYPE_DSC_WRITE_1P		0x15
+#define DSIM_TYPE_DSC_READ_2P		0x24
+#define DSIM_TYPE_GEN_LONG_WRITE	0x29
+#define DSIM_TYPE_GEN_LUT_WRITE		0x39
+
+/* DSIM response types */
+#define DSIM_RSP_READ_1B		0x11
+#define DSIM_RSP_READ_2B		0x12
+#define DSIM_RSP_LONG_READ		0x1A
+#define DSIM_RSP_DSC_LONG_READ		0x1C
+#define DSIM_RSP_DSC_READ_1B		0x21
+#define DSIM_RSP_DSC_READ_2B		0x22
+
+/* DSIM commands / registers */
+#define DSIM_CMD_NOP			0x00
+#define DSIM_CMD_ENTER_SLEEP		0x10
+#define DSIM_CMD_EXIT_SLEEP		0x11
+#define DSIM_CMD_INVERT_OFF		0x20
+#define DSIM_CMD_INVERT_ON		0x21
+#define DSIM_CMD_DISPLAY_OFF		0x28
+#define DSIM_CMD_DISPLAY_ON		0x29
+#define DSIM_CMD_ADDRESS_MODE		0x36
+#define DSIM_CMD_DEVICE_ID		0xb1
+
+__END_DECLS
+
+#endif /* ! __DRIVERS_MIPI_H */

include/drivers/miu.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2007-2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_MIU_H
+#define __DRIVERS_MIU_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+int  mcu_initialize_dram(bool resume);
+int  mcu_suspend_dram(void);
+void mcu_adjust_performance(void);
+u_int64_t mcu_get_memory_size(void);
+
+__END_DECLS
+
+#endif /* __DRIVERS_MIU_H */

include/drivers/nand_boot.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef _NAND_BOOT_H
+#define _NAND_BOOT_H
+#if WITH_NAND_BOOT
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+int nand_boot_init(void);
+
+__END_DECLS
+
+#endif /* WITH_NAND_BOOT */
+#endif /* ! _NAND_BOOT_H */

include/drivers/nand_device_tree.h

@@ -0,0 +1,19 @@
+// Copyright (C) 2009 Apple, Inc. All rights reserved.
+//
+// This document is the property of Apple, Inc.
+// It is considered confidential and proprietary.
+//
+// This document may not be reproduced or transmitted in any form,
+// in whole or in part, without the express written permission of
+// Apple, Inc.
+//
+
+#include <lib/devicetree.h>
+
+#ifndef _NAND_DEVICETREE_H_
+
+// Add required NAND properties to the given device-tree node
+
+void fillNandConfigProperties(DTNode *node);
+
+#endif //_NAND_DEVICETREE_H_

include/drivers/nand_syscfg.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef _NAND_SYSCFG_H
+#define _NAND_SYSCFG_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+int nand_syscfg_init(NandPartInterface * npi);
+
+__END_DECLS
+
+#endif /* ! _NAND_SYSCFG_H */

include/drivers/nvme.h

@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef DRIVERS_NVME_H
+#define DRIVERS_NVME_H
+
+#include <sys/types.h>
+#include <drivers/pci.h>
+#if WITH_DEVICETREE
+#include <lib/devicetree.h>
+#endif
+
+// NVMe for iOS says we can assume IDENTIFY.MDTS >= 8, which translates to 256 blocks
+#define NVME_BOOT_MAX_TRANSFER_BLOCKS	(256)
+
+#define NVME_NAMESPACE_NAND		1
+#define NVME_NAMESPACE_FIRMWARE		2
+#define NVME_NAMESPACE_SYSCFG		3
+#define NVME_NAMESPACE_NVRAM		5
+#define NVME_NAMESPACE_EFFACEABLE	6
+#define NVME_NAMESPACE_PANICLOG		7
+
+#define NVME_BLOCK_SIZE			(1<<12)
+
+#define NVME_SUCCESS			(0)
+// Error codes from -1 to -4095 are reserved for NVMe errors
+//     - Bits 7:0 get the SC field from the completion
+//     - Bits 11:8 get the SCT field from the completion
+//     - See the NVMe spec for details on errors from -1 to -4095
+// Error codes from 5000 to 5999 for PCI errors
+#define NVME_ERR_PROBE_FAILED		(-5000)
+#define NVME_ERR_INVALID_CLASS_CODE	(-5001)
+#define NVME_ERR_INVALID_BAR		(-5002)
+#define NVME_ERR_INVALID_REG		(-5003)
+// Error codes from 6000 to 6999 for controller initialization errors
+#define NVME_ERR_DISABLE_TIMEOUT	(-6000)
+#define NVME_ERR_ENABLE_TIMEOUT		(-6001)
+#define NVME_ERR_SHUTDOWN_TIMEOUT	(-6002)
+#define NVME_ERR_CFS			(-6003)
+#define NVME_ERR_POLL_REG_TIMEOUT	(-6004)
+#define NVME_ERR_INVALID_DSTRD		(-6100)
+#define NVME_ERR_INVALID_MPSMIN		(-6101)
+#define NVME_ERR_INVALID_MQES		(-6102)
+#define NVME_ERR_INVALID_SQES		(-6103)
+#define NVME_ERR_INVALID_CQES		(-6104)
+#define NVME_ERR_INVALID_DDRREQALIGN	(-6150)
+#define NVME_ERR_INVALID_DDRREQSIZE	(-6151)
+// Error codes from 7000 to 7999 for command processing errors
+#define NVME_ERR_INVALID_CMPL_SQID	(-7001)
+#define NVME_ERR_INVALID_CMPL_SQHD	(-7002)
+#define NVME_ERR_IO_CMD_TIMEOUT		(-7003)
+#define NVME_ERR_ADMIN_CMD_TIMEOUT	(-7004)
+#define NVME_ERR_CMPL_CID_MISMATCH	(-7005)
+// Error codes from 8000 to 8999 are generic driver errors
+#define NVME_ERR_NOT_ENABLED		(-8000)
+
+typedef struct nvme_namespace_params_t {
+	bool		formatted;
+	uint64_t	num_blocks;
+	uint32_t	block_size;
+} nvme_namespace_params_t;
+
+int nvme_init(int nvme_id, pci_device_t bridge, uint32_t dart_id);
+void nvme_quiesce(int nvme_id);
+void nvme_quiesce_all(void);
+int nvme_read_blocks(int nvme_id, uint32_t nsid, void *ptr, uint32_t block, uint32_t count);
+int nvme_write_blocks(int nvme_id, uint32_t nsid, const void *ptr, uint32_t block, uint32_t count);
+int nvme_identify_namespace(int nvme_id, uint32_t nsid, nvme_namespace_params_t *params_out);
+uint32_t nvme_get_max_transfer_blocks(int nvme_id);
+int nvme_init_mass_storage(int nvme_id);
+int nvme_init_mass_storage_panic(int nvme_id);
+
+#if WITH_DEVICETREE
+void nvme_update_devicetree (int nvme_id, dt_node_t *node);
+#endif
+
+#endif // DRIVERS_NVME_H

include/drivers/pci.h

@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2008-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_PCI_PCI_H
+#define __DRIVERS_PCI_PCI_H
+
+#include <sys.h>
+#include <sys/types.h>
+
+typedef void (*pci_config_read_cb_t)(void *priv, void *dst, uint32_t bdfo, int size);
+typedef void (*pci_config_write_cb_t)(void *priv, const void *src, uint32_t bdfo, int size);
+
+typedef struct pci_device * pci_device_t;
+
+void pci_init(void);
+void pci_free(pci_device_t dev);
+
+// Config space accessors
+uint8_t pci_config_read8(pci_device_t dev, uint16_t offset);
+uint16_t pci_config_read16(pci_device_t dev, uint16_t offset);
+uint32_t pci_config_read32(pci_device_t dev, uint16_t offset);
+void pci_config_write8(pci_device_t dev, uint16_t offset, uint8_t value);
+void pci_config_write16(pci_device_t dev, uint16_t offset, uint16_t value);
+void pci_config_write32(pci_device_t dev, uint16_t offset, uint32_t value);
+
+uint64_t pci_get_bar_size(pci_device_t dev, unsigned bar_idx);
+pci_device_t pci_get_bridge(pci_device_t dev);
+uint32_t pci_get_class_code(pci_device_t dev);
+uint16_t pci_get_device_id(pci_device_t dev);
+uint8_t pci_get_header_type(pci_device_t dev);
+uint8_t pci_get_revision_id(pci_device_t dev);
+uint16_t pci_get_vendor_id(pci_device_t dev);
+
+uintptr_t pci_map_bar(pci_device_t dev, unsigned bar_idx);
+void pci_bus_master_enable(pci_device_t dev, bool enable);
+void pci_memory_space_enable(pci_device_t dev, bool enable);
+
+// Capabilities
+uint16_t pci_find_capability(pci_device_t dev, uint16_t capability_id);
+uint16_t pci_find_extended_capability(pci_device_t dev, uint16_t capability_id, uint8_t min_version);
+
+// Power management
+void pci_set_powerstate(pci_device_t dev, uint8_t powerstate);
+void pci_enable_pcie_aspm(pci_device_t dev);
+void pci_enable_pcie_l1ss(pci_device_t dev);
+bool pci_enable_pcie_ltr(pci_device_t dev);
+
+// Random info
+void pci_set_name(pci_device_t dev, const char *name);
+const char *pci_get_name(pci_device_t dev);
+
+// Bridges
+bool pci_is_bridge(pci_device_t dev);
+pci_device_t pci_create_host_bridge(const char *name, uint8_t bus_num, uint32_t memory_base, uint32_t memory_size, void *priv, pci_config_read_cb_t read_cb, pci_config_write_cb_t write_cb);
+pci_device_t pci_bridge_probe(pci_device_t bridge, uint8_t device_num, utime_t timeout);
+void pci_bridge_assign_secondary_bus(pci_device_t bridge);
+void pci_bridge_serr_enable(pci_device_t dev, bool enable);
+
+#define PCI_BUS_SHIFT 20
+#define PCI_DEVICE_SHIFT 15
+#define PCI_FUNCTION_SHIFT 12
+#define PCI_BDFO(bus, device, function, offset) ((((uint32_t)bus) << PCI_BUS_SHIFT) | (((uint32_t)device) << PCI_DEVICE_SHIFT) | (((uint32_t)function) << PCI_FUNCTION_SHIFT) | (offset))
+#define PCI_BDF(bus, device, function) (PCI_BDFO((bus), (device), (function), 0))
+#define PCI_DFO(device, function, offset) (PCI_BDFO(0, (device), (function), (offset)))
+#define PCI_DFO_MASK ((1 << PCI_BUS_SHIFT)-1)
+#define PCI_DEVICE_MASK (0x1F << PCI_DEVICE_SHIFT)
+#define PCI_FUNCTION_MASK (0x7 << PCI_FUNCTION_SHIFT)
+#define PCI_BUS(bdfo) (bdfo >> PCI_BUS_SHIFT)
+#define PCI_DEVICE(bdfo) (((bdfo) & PCI_DEVICE_MASK) >> PCI_DEVICE_SHIFT)
+#define PCI_FUNCTION(bdfo) (((bdfo) & PCI_FUNCTION_MASK) >> PCI_FUNCTION_SHIFT)
+
+#define PCI_CONFIG_VENDOR_ID			0x00
+#define PCI_CONFIG_DEVICE_ID			0x02
+#define PCI_CONFIG_COMMAND			0x04
+#define PCI_CONFIG_STATUS			0x06
+#define PCI_CONFIG_REVISION_ID			0x08
+#define PCI_CONFIG_CLASS_CODE			0x09
+#define PCI_CONFIG_CACHE_LINE_SIZE		0x0C
+#define PCI_CONFIG_LATENCY_TIMER		0x0D
+#define PCI_CONFIG_HEADER_TYPE			0x0E
+#define PCI_CONFIG_BIST				0x0F
+#define PCI_CONFIG_BASE_ADDRESS0		0x10
+#define PCI_CONFIG_BASE_ADDRESS1		0x14
+#define PCI_CONFIG_BASE_ADDRESS2		0x18
+#define PCI_CONFIG_BASE_ADDRESS3		0x1C
+#define PCI_CONFIG_BASE_ADDRESS4		0x20
+#define PCI_CONFIG_BASE_ADDRESS5		0x24
+#define PCI_CONFIG_CARDBUS_CIS_PTR		0x28
+#define PCI_CONFIG_SUBSYSTEM_VENDOR_ID		0x2C
+#define PCI_CONFIG_SUBSYSTEM_ID			0x2E
+#define PCI_CONFIG_EXPANSION_ROM_BASE		0x30
+#define PCI_CONFIG_CAPABILITIES_PTR		0x34
+#define PCI_CONFIG_INTERRUPT_LINE		0x3C
+#define PCI_CONFIG_INTERRUPT_PIN		0x3D
+#define PCI_CONFIG_MINIMUM_GRANT		0x3E
+#define PCI_CONFIG_MAXIMUM_LATENCY		0x3F
+
+#define PCI_CONFIG_PRIMARY_BUS_NUMBER		0x18
+#define PCI_CONFIG_SECONDARY_BUS_NUMBER		0x19
+#define PCI_CONFIG_SUBORDINATE_BUS_NUMBER	0x1A
+#define PCI_CONFIG_SECONDARY_LATENCY_TIMER	0x1B
+#define PCI_CONFIG_IO_BASE			0x1C
+#define PCI_CONFIG_IO_LIMIT			0x1D
+#define PCI_CONFIG_SECONDARY_STATUS		0x1E
+#define PCI_CONFIG_MEMORY_BASE			0x20
+#define PCI_CONFIG_MEMORY_LIMIT			0x22
+#define PCI_CONFIG_PREFETCHABLE_BASE		0x24
+#define PCI_CONFIG_PREFETCHABLE_LIMIT		0x26
+#define PCI_CONFIG_PREFETCHABLE_BASE_UPPER32	0x28
+#define PCI_CONFIG_PREFETCHABLE_LIMIT_UPPER32	0x2C
+#define PCI_CONFIG_IO_BASE_UPPER16		0x30
+#define PCI_CONFIG_IO_LIMIT_UPPER16		0x32
+#define PCI_CONFIG_BRIDGE_CONTROL		0x3E
+
+#define PCI_CMD_IO_SPACE_ENABLE			(1 << 0)
+#define PCI_CMD_MEMORY_SPACE_ENABLE		(1 << 1)
+#define PCI_CMD_BUS_MASTER_ENABLE		(1 << 2) 
+#define PCI_CMD_SERR_ENABLE			(1 << 8) 
+
+#define PCI_BRIDGE_CTRL_SERR_ENABLE		(1 << 1)
+
+#define PCI_STATUS_CAPABILITIES_LIST		(1 << 4)
+
+#define PCI_CAP_ID_PM				(0x01)
+
+#define PCI_PM_CAP_PMC				(0x02)
+#define PCI_PM_CAP_PMCSR			(0x04)
+#define PCI_PM_CAP_PMCSR_BSE			(0x06)
+#define PCI_PM_CAP_DATA				(0x07)
+
+#define PCI_PM_POWERSTATE_D0			(0x0)
+#define PCI_PM_POWERSTATE_D3			(0x3)
+
+// PCIe r3.0 section 7.8
+#define PCI_CAP_ID_PCIE				(0x10)
+
+#define PCI_PCIE_CAP_PCIE_CAPABILITIES		(0x02)
+#define PCI_PCIE_CAP_LINK_CAPABILITIES		(0x0C)
+#define PCI_PCIE_CAP_LINK_CONTROL		(0x10)
+#define PCI_PCIE_CAP_DEVICE_CAPABILITIES2	(0x24)
+#define PCI_PCIE_CAP_DEVICE_CONTROL2		(0x28)
+#define PCI_PCIE_CAP_LINK_CAPABILITIES2		(0x2C)
+#define PCI_PCIE_CAP_LINK_CONTROL2		(0x30)
+
+// PCIe r3.0 section 7.8.2
+#define PCI_PCIE_TYPE_ENDPOINT			(0)
+#define PCI_PCIE_TYPE_ROOT_PORT			(4)
+#define PCI_PCIE_TYPE_UPSTREAM			(5)
+#define PCI_PCIE_TYPE_DOWNSTREAM		(6)
+#define PCI_PCIE_TYPE_UNKNOWN			(UINT8_MAX) // for endpoints without a PCIe capability
+
+// PCIe r3.0 section 7.8.6/7.8.18
+#define PCI_PCIE_SPEED_GEN1			(0)
+#define PCI_PCIE_SPEED_GEN2			(1)
+#define PCI_PCIE_SPEED_GEN3			(2)
+
+// PCIe r3.0 section 7.25
+#define PCI_EXT_CAP_ID_LTR			(0x18)
+
+#define PCI_LTR_CAP_MAX_SNOOP_LATENCY		(0x04)
+#define PCI_LTR_CAP_MAX_NO_SNOOP_LATENCY	(0x06)
+
+#define PCI_EXT_CAP_ID_L1SS			(0x1E)
+
+#define PCI_L1SS_CAP_CAPABILITIES		(0x04)
+#define PCI_L1SS_CAP_CONTROL1			(0x08)
+#define PCI_L1SS_CAP_CONTROL2			(0x0c)
+
+#endif

include/drivers/phy.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+/*
+ * Ethernet PHY support.
+ */
+#ifndef __DRIVERS_PHY_H
+#define __DRIVERS_PHY_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+enum phy_speed {
+	PHY_SPEED_UNKNOWN,
+	PHY_SPEED_AUTO,
+	PHY_SPEED_10,
+	PHY_SPEED_100,
+	PHY_SPEED_1000
+};
+
+int	phy_init(int port);
+int	phy_set_speed(int port, enum phy_speed speed);
+bool	phy_get_link(int port);
+extern int	phy_read_reg(int port, uint32_t reg, uint16_t *data);
+extern int	phy_write_reg(int port, uint32_t reg, uint16_t data);
+
+__END_DECLS
+
+#endif /* __DRIVERS_PHY_H */

include/drivers/pke.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2008 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __DRIVERS_PKE_H
+#define __DRIVERS_PKE_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+bool pke_do_exp(uint8_t *dst, size_t *len,
+        size_t  uKeyLen, 
+        uint8_t * const base, size_t base_length,
+        uint8_t * const expn, size_t expn_length,
+        uint8_t * const mods, size_t mods_length);
+
+__END_DECLS
+
+#endif /* __DRIVERS_PKE_H */

include/drivers/power.h

@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2007-2010 Apple Inc. All rights reserved.
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_POWER_H
+#define __DRIVERS_POWER_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+#define kPowerBootFlagCold       (0)
+#define kPowerBootFlagColdButton (1)
+#define kPowerBootFlagWarm       (2)
+#define kPowerBootFlagResumeLost (3)
+
+int power_init(void);
+int power_late_init(void);
+int power_backlight_enable(u_int32_t backlight_level);
+int power_get_boot_flag(void);
+
+void power_suspend(void);
+void power_shutdown(void); // tell the pmu to pull the plug
+int power_set_soc_voltage(unsigned mv, int override);
+int power_set_cpu_voltage(unsigned mv, int override);
+int power_set_ram_voltage(unsigned mv, int override);
+
+#define POWER_RAIL_CPU       0
+#define POWER_RAIL_VDD_FIXED 1
+#define POWER_RAIL_SOC		 2
+#define POWER_RAIL_CPU_RAM   3
+#define POWER_RAIL_GPU       4
+#define POWER_RAIL_GPU_RAM   5	
+// not a rail, might move this to target
+#define POWER_RAIL_COUNT     6
+
+// @rail one of POWER_RAIL_* (replace power_get_buck_value(), backward compatible)
+int power_get_rail_value(int rail, unsigned mv, u_int32_t *buffer);
+// @rail one of POWER_RAIL_* (backward compatible with power_convert_dwi_to_mv())
+int power_convert_dwi_to_mv(int rail, u_int32_t dwival);
+// deprecated, use power_get_rail_value() ( buck is not the buck# )
+int power_get_buck_value(int buck, unsigned mv, u_int32_t *buffer);
+
+int power_set_display_voltage_offset(u_int32_t voltage_offset, bool fixed_boost);
+
+void power_set_usb_state(bool configured, bool suspended);
+void power_set_usb_enabled(bool enabed);
+int power_set_gpio(u_int32_t gpio, u_int32_t direction, u_int32_t value);
+int power_set_ldo(u_int32_t ldo, u_int32_t voltage);
+int power_enable_ldo(u_int32_t ldo, bool enable);
+bool power_get_gpio(u_int32_t gpio);
+void power_gpio_configure(u_int32_t gpio, u_int32_t config);
+
+bool power_needs_precharge(void);
+bool power_needs_thermal_trap(void);
+bool power_do_chargetrap(void);
+void power_cancel_buttonwait(void);
+bool power_is_suspended(void);
+void power_will_resume(void);
+bool power_has_usb(void);
+int power_read_dock_id(unsigned *id);
+bool power_get_diags_dock(void);
+u_int32_t power_get_boot_battery_level(void);
+u_int32_t power_get_battery_level(void);
+void power_get_usb_brick_id(uint32_t *id, size_t count);
+bool power_has_batterypack(void);
+bool power_enable_charging(bool inflow, bool charging);
+uint32_t power_get_available_charge_current(void);
+
+int power_get_nvram(u_int8_t key, u_int8_t *data);
+int power_set_nvram(u_int8_t key, u_int8_t data);
+void power_clr_events(int wake);
+
+
+#define kPowerNVRAMiBootStateName			"iBootState"
+#define kPowerNVRAMiBootStateKey			(0)
+
+#define kPowerNVRAMiBootStatePrecharge			(1 << 5)    // can be or'd with modes below
+#define kPowerNVRAMiBootStateThermalTrap		(1 << 0)
+#define kPowerNVRAMiBootStateModeMask			(0xd0)	    // bits 4, 6 and 7 (keep backwards compatible)
+#define kPowerNVRAMiBootStateModeNormalBoot		(0x00)
+#define kPowerNVRAMiBootStateModeResumed		(0x40)
+#define kPowerNVRAMiBootStateModeSuspended		(0x80)
+#define kPowerNVRAMiBootStateModeButtonwaitWithGraphics	(0x10)
+#define kPowerNVRAMiBootStateModeButtonwaitNoGraphics	(0x90)
+
+#define kPowerNVRAMiBootDebugName			"iBootDebug"
+#define kPowerNVRAMiBootDebugKey			(1)
+#define kPowerNVRAMiBootDebugIAPSerial			(1 << 0)
+#define kPowerNVRAMiBootDebugAltSerial			(1 << 1)
+#define kPowerNVRAMiBootDebugJtag			(1 << 2)
+#define kPowerNVRAMiBootDebugEarlyTracing		(1 << 3)
+#define kPowerNVRAMiBootDebugBatteryTrap		(1 << 4)
+#define kPowerNVRAMiBootDebugWDTWake			(1 << 7)
+
+#define kPowerNVRAMiBootStageName			"iBootStage"
+#define kPowerNVRAMiBootStageKey			(2)
+#define kPowerNVRAMiBootStageOff			(0x00)
+#define kPowerNVRAMiBootStageLLBStart			(0x10)
+#define kPowerNVRAMiBootStageLLBEnd			(0x1F)
+#define kPowerNVRAMiBootStageiBootStart			(0x20)
+#define kPowerNVRAMiBootStageiBootEnd			(0x2F)
+#define kPowerNVRAMDiagsStageDiagsBootComplete		(0xD0)
+#define kPowerNVRAMiBootStagePanicSave			(0xE0)
+#define kPowerNVRAMiBootStagePanicReboot		(0xE1)
+#define kPowerNVRAMiBootStagePrechargeReboot		(0xE2)
+#define kPowerNVRAMiBootStageBooted			(0xFF)
+
+#if PRODUCT_LLB
+#define kPowerNVRAMiBootStageProductStart		kPowerNVRAMiBootStageLLBStart
+#define kPowerNVRAMiBootStageProductEnd			kPowerNVRAMiBootStageLLBEnd
+#endif
+
+#if PRODUCT_IBOOT || PRODUCT_IBEC
+#define kPowerNVRAMiBootStageProductStart		kPowerNVRAMiBootStageiBootStart
+#define kPowerNVRAMiBootStageProductEnd			kPowerNVRAMiBootStageiBootEnd
+#endif
+
+#if PRODUCT_IBSS
+#define kPowerNVRAMiBootStageProductStart		kPowerNVRAMiBootStageLLBStart
+#define kPowerNVRAMiBootStageProductEnd			kPowerNVRAMiBootStageiBootEnd
+#endif
+
+#define kPowerNVRAMiBootErrorCountName			"iBootErrorCount"
+#define kPowerNVRAMiBootErrorCountKey			(3)
+#define kPowerNVRAMiBootErrorCountMask			(0x0F)
+#define kPowerNVRAMiBootErrorPanicShift 		(4)
+#define kPowerNVRAMiBootErrorBootShift  		(0)
+
+#define kPowerNVRAMiBootErrorStageName			"iBootErrorStage"
+#define kPowerNVRAMiBootErrorStageKey			(4)
+
+#define kPowerNVRAMiBootMemCalCAOffset0Key		(5)	// CA offset need 2 bytes
+#define kPowerNVRAMiBootMemCalCAOffset1Key		(6)
+#define kPowerNVRAMiBootMemCalCAOffset2Key		(7)
+#define kPowerNVRAMiBootMemCalCAOffset3Key		(8)
+
+#define kPowerNVRAMiBootMemCalCAOffset0Name		"iBootMemCalCAOffset0"
+#define kPowerNVRAMiBootMemCalCAOffset1Name		"iBootMemCalCAOffset1"
+#define kPowerNVRAMiBootMemCalCAOffset2Name		"iBootMemCalCAOffset2"
+#define kPowerNVRAMiBootMemCalCAOffset3Name		"iBootMemCalCAOffset3"
+
+#define kPowerNVRAMiBootBootFlags0Key			(9)
+#define kPowerNVRAMiBootBootFlags1Key			(10)
+
+#define kPowerNVRAMiBootBootFlags0Name			"iBootBootFlags0"
+#define kPowerNVRAMiBootBootFlags1Name			"iBootBootFlags1"
+
+#define kPowerNVRAMiBootEnterDFUName			"iBootEnterDFU"
+#define kPowerNVRAMiBootEnterDFUKey			(11)
+#define kPowerNVRAMiBootEnterDFURequest			(0xA0)
+#define kPowerNVRAMiBootEnterDFUOff			(0x00)
+
+#define kPowerNVRAMPropertyCount			(12)
+
+struct power_charge_limits
+{
+    uint16_t	upperVoltageLimit;	/* mV */
+    int16_t	lowerTempLimit;	/* cC */
+    int16_t	upperTempLimit;	/* cC */
+    uint16_t	currentSetting;	/* charger-dependent */
+};
+
+bool power_load_memory_calibration(void *settings, uint32_t settingsSize);
+bool power_store_memory_calibration(void *settings, uint32_t settingsSize);
+
+void pmu_early_init(void);
+void pmu_setup(void);
+void pmu_late_init(void);
+void pmu_will_resume(void);
+void pmu_shutdown(void);
+void pmu_suspend(void);
+void pmu_set_backlight_enable(uint32_t backlight_level);
+u_int32_t pmu_read_brick_id_level(void);
+int pmu_read_system_temperature(int idx, int *centiCelsiusTemperature);
+void pmu_check_events(bool *powersupply_change_event,
+		     bool *button_event,
+		     bool *other_wake_event);
+int pmu_uvwarn_config(int dev, uint32_t thresholdMV);
+
+bool power_load_voltage_knobs(void *settings, uint32_t settingsSize);
+bool power_store_voltage_knobs(void *settings, uint32_t settingsSize);
+
+utime_t power_get_calendar_time(void);
+
+
+// Dark boot API's
+
+void power_clear_dark_boot_flag (void); // Clears the dark boot flag from NVRAM. Call on every startup AFTER nvram is writable
+void power_disable_dark_boot (void);  // Disables dark boot by lighting up display to previous backlight command
+void power_dark_boot_checkpoint (void); // Checks for button presses and disables dark boot if needed.
+bool power_is_dark_boot (void); // Returns true if we are doing a dark boot.
+
+// smartport API
+//
+
+#define SMARTPORT_EXT_PWR_IN_SEL 1
+#define SMARTPORT_ACC_PWR_IN_SEL 0
+
+int smartport_get_data(int dev, uint16_t reg, uint8_t *byte); // low level, you don't need this
+int smartport_get_pwr_in_sel(int dev, uint8_t *sel); // power switch state
+
+
+__END_DECLS
+
+#endif /* __DRIVERS_POWER_H */

include/drivers/prc.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_PRC_H
+#define __DRIVERS_PRC_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+void prc_init(uint32_t display_width, uint32_t display_height);
+void prc_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl);
+
+__END_DECLS
+
+#endif /* __DRIVERS_PRC_H */

include/drivers/process_edid.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2010 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if WITH_HW_MCU
+
+#ifndef PROCESS_EDID_H
+#define PROCESS_EDID_H	1
+
+#if WITH_HW_DISPLAY_DISPLAYPORT
+#include <drivers/displayport.h>
+#endif
+
+#if WITH_HW_DISPLAY_HDMI
+#include <drivers/hdmi.h>
+#endif
+
+// Collect EDID data and decide on the best scoring display mode.
+int obtain_edid(void);
+
+// Break out of the EDID polling loop.
+void abort_edid(void);
+
+// Reject timings not matching these dimensions.
+void restrict_edid(uint32_t h_active, uint32_t v_active);
+
+// Get previously collected best display mode.
+int get_edid_timings(struct video_timing_data *data);
+
+// Get the detected downstream port type, e.g kDPDownstreamTypeHDMI
+int get_edid_downstream_type(void);
+
+#endif // PROCESS_EDID_H
+
+#endif // WITH_HW_MCU

include/drivers/radio.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2007-2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_RADIO_H
+#define __DRIVERS_RADIO_H
+
+#include <sys/types.h>
+
+#if WITH_DEVICETREE
+#include <lib/devicetree.h>
+#endif
+
+#include <target.h>
+
+__BEGIN_DECLS
+
+bool radio_get_property(enum target_property prop, void *data, int maxdata, int *retlen);
+void radio_init(void);
+void radio_early_init(void);
+void radio_late_init(void);
+void radio_quiesce(void);
+void radio_power_off(void);
+
+void radio_init_pins( void );
+
+void radio_pmu_power_on(void);
+void radio_pmu_power_off(void);
+
+bool radio_board_present(void);
+
+#if WITH_DEVICETREE
+int radio_update_device_tree(DTNode *radio_node);
+#endif
+
+__END_DECLS
+
+#endif /* ! __DRIVERS_RADIO_H */

include/drivers/reconfig.h

@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2013-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __RECONFIG_H
+#define __RECONFIG_H
+
+#include <sys/types.h>
+#include <sys/boot.h>
+
+typedef enum {
+	AWAKE_AOP_DDR_PRE = 0,
+	AWAKE_AOP_DDR_POST,
+	AOP_DDR_S2R_AOP_PRE,
+	AOP_DDR_S2R_AOP_POST,
+	S2R_AOP_AOP_DDR_PRE,
+	S2R_AOP_AOP_DDR_POST,
+	AOP_DDR_AWAKE_PRE,
+	AOP_DDR_AWAKE_POST,
+	MAX_STAGE
+} reconfig_stage_t;
+
+enum {
+	END_COMMAND = 0x0,
+	WRITE_COMMAND = 0x1,
+	READ_COMMAND = 0x2,
+	DELAY_COMMAND = 0x4,
+	NOP_COMMAND = 0x4,
+};
+
+typedef struct write_command_t {
+	uint32_t in_progress;
+	uint64_t address;
+	uint32_t is_reg64;
+	uint32_t offsets[4];
+	uint32_t value_count;
+	uint64_t values[16];
+
+} write_command_t;
+
+typedef enum {
+	REGION_ONLY,
+	COMMAND_ONLY,
+	REGION_AND_COMMAND,
+} reconfig_dump_t;
+
+void reconfig_init(enum boot_target target);
+
+void reconfig_command_write(reconfig_stage_t stage, uint64_t addr, uint64_t value, uint32_t is_reg64);
+
+void reconfig_command_read(reconfig_stage_t stage, uint64_t addr, uint64_t value, uint64_t mask, uint32_t retry_cnt, uint32_t is_reg64);
+
+void reconfig_command_delay(reconfig_stage_t stage, uint32_t delay);
+
+void reconfig_command_nop(reconfig_stage_t stage);
+
+void reconfig_command_raw(reconfig_stage_t stage, const uint32_t *cmd, uint32_t cmdItems);
+
+void reconfig_commit(reconfig_stage_t stage);
+
+void reconfig_lock(enum boot_target target);
+
+void dump_reconfig(reconfig_dump_t option);
+
+static void validate_stage(reconfig_stage_t stage);
+static void commit_write_command(reconfig_stage_t stage, write_command_t *wc);
+static void bounds_check_stage(reconfig_stage_t stage);
+static void reconfig_write_pending(reconfig_stage_t stage);
+
+// For 64 bit registers the data/mask etc.. need to be aligned to 64 bits
+// count * 4 is the register offset from the 64 bit aligned base. So the following should 
+// tell if we are aligned or not
+#define ALIGNED_64(count)		((count) % 2 == 0)
+#define ALIGNMENT_MARKER		0xDEADBEEF
+#define SEQUENCE_END			0xDEADDEAD
+
+#endif /* __RECONFIG_H */

include/drivers/rsecc.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_RSECC_H
+#define __DRIVERS_RSECC_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+enum rsecc_mode {
+	ECC_4BIT = 0,
+	ECC_6BIT,
+	ECC_8BIT,
+};
+
+int rsecc_encode(enum rsecc_mode mode, int sector_count, const void *datapointer, void *eccbuf);
+int rsecc_decode(enum rsecc_mode mode, int sector_count, void *datapointer, const void *eccbuf);
+
+__END_DECLS
+
+#endif /* __DRIVERS_RSECC_H */
+
+

include/drivers/sha1.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2007-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_SHA1_H
+#define __DRIVERS_SHA1_H
+
+#include <sys/types.h>
+#include <sys/hash.h>
+
+#if WITH_CORECRYPTO
+#include <corecrypto/ccsha1.h>
+#else
+#define CCSHA1_OUTPUT_SIZE	(20)			// bytes
+#endif
+
+__BEGIN_DECLS
+
+void sha1_calculate(const void *buffer, size_t length, void *result);
+#if WITH_CORECRYPTO
+const struct ccdigest_info *sha1_get_ccsha1_ccdigest_info();
+#endif
+
+__END_DECLS
+
+#endif /* __DRIVERS_SHA1_H */

include/drivers/shmcon.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_SHMCON_H
+#define __DRIVERS_SHMCON_H
+
+#include <sys/types.h>
+
+/*
+ * High-level shared memory console interface.
+ * Port argument exists for compatibility with UART functions
+ */
+int shmcon_init(void);
+
+int shmcon_getc(int port, bool wait);
+int shmcon_putc(int port, char c);
+int shmcon_puts(int port, const char *s);
+
+int shmcon_set_child(uint64_t phys_address, uint32_t num);
+
+#endif /* __DRIVERS_SHMCON_H */

include/drivers/spi.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2007 Apple Inc. All rights reserved.
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_SPI_H
+#define __DRIVERS_SPI_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+void spi_setup(int port, int baud, int width, bool master, int clkpol, int clkpha);
+int  spi_write_etc(int port, const void *buf, size_t len, bool wait, bool with_rx);
+int  spi_read_etc(int port, void *buf, size_t len, bool wait, bool with_tx);
+void spi_select(int port, bool select_state);
+
+void spi_init(void);
+
+u_int32_t spi_gpio_read(int port);
+void spi_gpio_write(int port, u_int32_t val);
+void spi_gpio_configure(int port, u_int32_t config);
+
+__END_DECLS
+
+#endif /* __DRIVERS_SPI_H */

include/drivers/sw_h2fmi.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_SW_H2FMI_H
+#define __DRIVERS_SW_H2FMI_H
+
+#include <sys/types.h>
+#include <lib/blockdev.h>
+
+__BEGIN_DECLS
+
+int sw_h2fmi_init(void);
+
+__END_DECLS
+
+#endif /* __DRIVERS_SW_H2FMI_H */

include/drivers/thermal.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2009 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_THERMAL_H
+#define __DRIVERS_THERMAL_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+/*
+ * Thermal management.
+ *
+ * Thermal status is reported via the following nodes in the MIB:
+ *
+ * Thermal.Temperature		unit current temperature in degrees Celsius.
+ * Thermal.Fanspeed		current fan speed
+ */
+
+/*
+ * thermal_init
+ *
+ * Initialise the thermal management system.
+ *
+ * If the default target is passed as 0, it is assumed the system already
+ * knows the default.
+ */
+int		thermal_init(u_int32_t default_target);
+
+/*
+ * thermal_set_target_temperature
+ *
+ * Set the target temperature to be maintained by the thermal system in degrees Celsius.
+ */
+int		thermal_set_target_temperature(u_int32_t temperature);
+
+/*
+ * thermal_soft_regulation_fail
+ *
+ * Called when the system is no longer able to provide services that may be required
+ * to perform soft thermal regulation, e.g. during a panic.  This allows a soft
+ * regulation algorithm to e.g. set the cooling system to maximum, as long as care is
+ * taken.
+ */
+void		thermal_soft_regulation_fail(void);
+
+__END_DECLS
+
+#endif /* __DRIVERS_THERMAL_H */

include/drivers/thunderbolt/nhi.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef THUNDERBOLT_NHI_H
+#define THUNDERBOLT_NHI_H
+
+#include <drivers/pci.h>
+#include <stdint.h>
+
+#define NHI_STATUS_OK				(0)
+#define NHI_STATUS_UNKNOWN_ERROR		(-1)
+#define NHI_STATUS_CRC_ERROR			(-2)
+#define NHI_STATUS_INVALID_DESCRIPTOR		(-3)
+#define NHI_STATUS_TIMEOUT			(-4)
+
+typedef struct nhi_sgl {
+	void *buffer;
+	uint32_t bytes;
+	struct nhi_sgl *next;
+} nhi_sgl_t;
+
+typedef struct nhi nhi_t;
+
+nhi_t *nhi_init(pci_device_t bridge, uint32_t dart_id);
+void nhi_quiesce_and_free(nhi_t *nhi);
+void nhi_init_tx_ring(nhi_t *nhi, uint32_t ring_idx, uint32_t num_buffers, uint32_t buffer_size);
+void nhi_init_rx_ring(nhi_t *nhi, uint32_t ring_idx, uint32_t num_buffers, uint32_t buffer_size);
+void nhi_disable_tx_ring(nhi_t *nhi, uint32_t ring_idx);
+void nhi_disable_rx_ring(nhi_t *nhi, uint32_t ring_idx);
+int32_t nhi_send_sgl(nhi_t *nhi, uint32_t ring_idx, const nhi_sgl_t *sgl, uint8_t sof_pdf, uint8_t eof_pdf);
+int32_t nhi_send_buffer(nhi_t *nhi, uint32_t ring_idx, void *buffer, uint32_t bytes, uint8_t sof_pdf, uint8_t eof_pdf);
+bool nhi_rx_buffer_available(nhi_t *nhi, uint32_t ring_idx);
+int32_t nhi_rx_buffer(nhi_t *nhi, uint32_t ring_idx, void *buffer, uint32_t bytes, uint8_t *sof_pdf, uint8_t *eof_pdf);
+
+#endif

include/drivers/thunderbolt/thunderboot.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef THUNDERBOOT_H
+#define THUNDERBOOT_H
+
+#include <drivers/pci.h>
+
+typedef struct thunderboot thunderboot_t;
+
+thunderboot_t * thunderboot_init(pci_device_t bridge, uint32_t dart_id);
+void thunderboot_quiesce_and_free(thunderboot_t *tb);
+
+int thunderboot_get_dfu_image(void *load_address, int load_length);
+
+void thunderboot_putchar(int c);
+
+int thunderboot_serial_send_cmd_string(u_int8_t *buffer, u_int32_t len);
+void thunderboot_transfer_prepare(void *load_address, uint32_t length);
+int thunderboot_transfer_wait(void);
+
+#endif

include/drivers/tristar.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2011 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_TRISTAR_H
+#define __DRIVERS_TRISTAR_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+bool tristar_set_usb_brick_detect(int select);
+bool tristar_read_id(uint8_t digital_id[6]);
+bool tristar_enable_acc_pwr(bool enabled);
+
+__END_DECLS
+
+#endif /* __DRIVERS_CHARGER_H */
+

include/drivers/uart.h

@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+#ifndef __DRIVERS_UART_H
+#define __DRIVERS_UART_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+/*
+ * High-level UART interface.
+ */
+int uart_init(void);
+
+int uart_getc(int port, bool wait);
+int uart_puts(int port, const char *s);
+int uart_putc(int port, char c);
+
+int uart_send_break(int port, bool enable);
+
+/*
+ * Low-level UART primitives required by the drivers/uart module.
+ */
+enum uart_parity {
+	PARITY_NONE,
+	PARITY_ODD,
+	PARITY_EVEN
+};
+int uart_hw_init(u_int32_t port, u_int32_t baudrate);
+int uart_hw_getc(u_int32_t port);
+int uart_hw_putc(u_int32_t port, char c);
+
+/* optional, backdoor for tweaking UART config */
+int uart_hw_init_extended(u_int32_t port, u_int32_t baudrate, u_int32_t databits,
+			  enum uart_parity parity, u_int32_t stopbits);
+/* set interrupt mode on/off, explicit buffer size */
+int uart_hw_set_rx_buf(u_int32_t port, bool interrupt, size_t buffer_len);
+
+__END_DECLS
+
+#endif /* __DRIVERS_UART_H */

include/drivers/usb/synopsys_otg_public.h

@@ -0,0 +1,95 @@
+#ifndef _SYNOPSYS_OTG_PUBLIC_H_
+#define _SYNOPSYS_OTG_PUBLIC_H_
+
+#include <sys/types.h>
+#include <drivers/usb/usb_chap9.h>
+
+__BEGIN_DECLS
+
+//===================================================================================
+//		Enums, structs and Typedefs
+//===================================================================================
+enum
+{
+	USB_IO_ERROR = -1,
+	USB_IO_SUCCESS = 0,
+	USB_IO_ABORTED
+};
+
+enum
+{
+	CABLE_CONNECTED = 0,
+	CABLE_DISCONNECTED,
+	USB_RESET,
+	USB_ENUM_DONE
+};
+
+enum {
+    CONNECTION_SPEED_FULL = 0,
+    CONNECTION_SPEED_HIGH
+};
+
+struct usb_device_io_request
+{
+	u_int32_t endpoint;
+	volatile u_int8_t *io_buffer;
+	int status;
+	int io_length;
+	int return_count;
+	void (*callback) (struct usb_device_io_request *io_request);
+	struct usb_device_io_request *next;
+};
+
+struct usb_endpoint_instance
+{
+	int		endpoint_address;
+	int 		max_packet_size;
+	int 		attributes;
+	int 		bInterval;
+	
+	int 		transfer_size;
+	int 		packet_count;
+    
+	struct usb_endpoint_instance *next_ep;
+    
+	struct usb_device_io_request *io_head;
+	struct usb_device_io_request *io_tail;
+    
+	int		tx_fifo_number;
+};
+
+struct usb_controller_ops
+{
+	void (*start) (void);
+	void (*stop) (void);
+	void (*set_address) (int new_address);
+	void (*stall_endpoint) (u_int32_t endpoint, bool stall);
+	void (*reset_endpoint_data_toggle) (u_int32_t endpoint);
+	bool (*is_endpoint_stalled) (u_int32_t endpoint);
+	void (*do_endpoint_io) (struct usb_device_io_request *req);
+	void (*activate_endpoint) (u_int32_t endpoint, int type, int max_packet_size, int interval);
+	void (*deactivate_endpoint) (u_int32_t endpoint);
+	void (*abort_endpoint) (u_int32_t endpoint);
+	void (*do_test_mode)(int test_selector);
+	int (*get_connection_speed) (void);
+};
+
+struct usb_interface_instance
+{
+	int (*interface_request_handler) (struct usb_device_request *request, u_int8_t ** out_data);
+	void (*non_setup_data_phase_finished_callback) (int data_rcvd);
+	void (*activate_interface) (void);
+	void (*bus_reset_handler) (void);
+	int (*get_interface_handler) (void);
+	int (*set_interface_handler) (int alt_setting);
+};
+
+//===================================================================================
+//		Global APIs
+//===================================================================================
+
+void usb_init (void);
+
+__END_DECLS
+
+#endif

include/drivers/usb/usb_chap9.h

@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2007-2008 Apple Inc. All rights reserved.
+ * Copyright (C) 2006 Apple Computer, Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+
+#ifndef _USB_CHAP9_H_
+#define _USB_CHAP9_H_
+
+#include <sys/types.h>
+
+//====================================================================
+// USB Descriptor Types
+//====================================================================
+#define USB_DT_DEVICE				1
+#define USB_DT_CONFIGURATION                    2
+#define USB_DT_STRING                           3
+#define USB_DT_INTERFACE                        4
+#define USB_DT_ENDPOINT                         5
+#define USB_DT_DEVICE_QUALIFIER                 6
+#define USB_DT_OTHER_SPEED_CONFIGURATION	7
+
+//====================================================================
+// USB Endpoints Types
+//====================================================================
+#define USB_ENDPOINT_CONTROL            0x00
+#define USB_ENDPOINT_ISOCHRONOUS        0x01
+#define USB_ENDPOINT_BULK               0x02
+#define USB_ENDPOINT_INTERRUPT          0x03
+
+//====================================================================
+// USB Standard Request Types
+//====================================================================
+#define USB_REQ_GET_STATUS              0x00
+#define USB_REQ_CLEAR_FEATURE           0x01
+#define USB_REQ_SET_FEATURE             0x03
+#define USB_REQ_SET_ADDRESS             0x05
+#define USB_REQ_GET_DESCRIPTOR          0x06
+#define USB_REQ_SET_DESCRIPTOR          0x07
+#define USB_REQ_GET_CONFIGURATION       0x08
+#define USB_REQ_SET_CONFIGURATION       0x09
+#define USB_REQ_GET_INTERFACE           0x0A
+#define USB_REQ_SET_INTERFACE           0x0B
+
+//====================================================================
+// USB Feature Types
+//====================================================================
+#define USB_FEATURE_ENDPOINT_HALT		0x00
+#define USB_FEATURE_REMOTE_WAKEUP		0x01
+#define USB_FEATURE_TEST_MODE			0x02
+
+//====================================================================
+// USB Device Request Types
+//====================================================================
+#define USB_REQ_TYPE_STANDARD           0x00
+#define USB_REQ_TYPE_CLASS              0x20
+#define USB_REQ_TYPE_VENDOR             0x40
+
+//====================================================================
+// USB Class Codes
+//====================================================================
+#define USB_CLASS_INTERFACE_SPECIFIC         0
+#define USB_CLASS_VENDOR_SPECIFIC            0xff
+
+//====================================================================
+// 		USB Chap9 specific consts
+//====================================================================
+#define USB_DT_DEVICE_SIZE		18
+#define USB_DT_CONFIGURATION_SIZE      	9
+#define USB_DT_INTERFACE_SIZE   	9
+#define USB_DT_ENDPOINT_SIZE    	7
+#define USB_DT_DEVICE_QUALIFIER_SIZE    10
+#define USB_DT_STRING_SIZE		6
+
+#define USB_DIR_OUT                     0
+#define USB_DIR_IN                      0x80
+
+#define USB_ENDPOINT_MASK               0x03
+#define USB_ENDPOINT_NUMBER_MASK        0x0f
+#define USB_ENDPOINT_DIR_MASK           0x80
+
+#define USB_BCD_VERSION			0x0200
+
+#define USB_REQ_DIRECTION_MASK          0x80
+#define USB_REQ_TYPE_MASK               0x60
+#define USB_REQ_RECIPIENT_MASK          0x1f
+
+#define USB_REQ_DEVICE2HOST             0x80
+#define USB_REQ_HOST2DEVICE             0x00
+
+#define USB_REQ_RECIPIENT_DEVICE        0x00
+#define USB_REQ_RECIPIENT_INTERFACE     0x01
+#define USB_REQ_RECIPIENT_ENDPOINT      0x02
+#define USB_REQ_RECIPIENT_OTHER         0x03
+
+#define SETUP_PACKET_LEN	0x8
+
+#define EP0_IN		0x80
+#define EP0_OUT		0x0
+//====================================================================
+// 		Enums, structs and typedefs
+//====================================================================
+struct usb_device_request
+{
+    u_int8_t bmRequestType;
+    u_int8_t bRequest;
+    u_int16_t wValue;
+    u_int16_t wIndex;
+    u_int16_t wLength;
+} __attribute__((packed));
+
+struct usb_device_descriptor
+{
+    u_int8_t bLength;
+    u_int8_t bDescriptorType;
+    u_int16_t bcdUSB;
+    u_int8_t bDeviceClass;
+    u_int8_t bDeviceSubClass;
+    u_int8_t bDeviceProtocol;
+    u_int8_t bMaxPacketSize0;
+    u_int16_t idVendor;
+    u_int16_t idProduct;
+    u_int16_t bcdDevice;
+    u_int8_t iManufacturer;
+    u_int8_t iProduct;
+    u_int8_t iSerialNumber;
+    u_int8_t bNumConfigurations;
+} __attribute__((packed));
+
+struct usb_configuration_descriptor
+{
+    u_int8_t bLength;
+    u_int8_t bDescriptorType;
+    u_int16_t wTotalLength;
+    u_int8_t bNumInterfaces;
+    u_int8_t bConfigurationValue;
+    u_int8_t iConfiguration;
+    u_int8_t bmAttributes;
+    u_int8_t bMaxPower;
+} __attribute__((packed));
+
+struct usb_interface_descriptor
+{
+    u_int8_t bLength;
+    u_int8_t bDescriptorType;
+    u_int8_t bInterfaceNumber;
+    u_int8_t bAlternateSetting;
+    u_int8_t bNumEndpoints;
+    u_int8_t bInterfaceClass;
+    u_int8_t bInterfaceSubClass;
+    u_int8_t bInterfaceProtocol;
+    u_int8_t iInterface;
+} __attribute__((packed));
+
+struct usb_endpoint_descriptor
+{
+    u_int8_t bLength;
+    u_int8_t bDescriptorType;
+    u_int8_t bEndpointAddress;
+    u_int8_t bmAttributes;
+    u_int16_t wMaxPacketSize;
+    u_int8_t bInterval;
+} __attribute__((packed));
+
+struct usb_string_descriptor
+{
+    u_int8_t bLength;
+    u_int8_t bDescriptorType;
+    u_int8_t wData[2];
+} __attribute__((packed));
+
+struct usb_device_qualifier_descriptor
+{
+    u_int8_t bLength;
+    u_int8_t bDescriptorType;
+    u_int16_t bcdUSB;
+    u_int8_t bDeviceClass;
+    u_int8_t bDeviceSubClass;
+    u_int8_t bDeviceProtocol;
+    u_int8_t bMaxPacketSize0;
+    u_int8_t bNumConfigurations;
+    u_int8_t bReserved;
+} __attribute__((packed));
+
+enum
+{
+	DEVICE_ST_UNKNOWN = -1,
+	DEVICE_ST_INIT = 0,
+    DEVICE_ST_ATTACHED,
+    DEVICE_ST_POWERED,
+    DEVICE_ST_DEFAULT,
+    DEVICE_ST_ADDRESSED,
+    DEVICE_ST_CONFIGURED,
+    DEVICE_ST_SUSPENDED
+};
+
+//====================================================================
+// 		USB driver specific consts
+//====================================================================
+#define EP0_MAX_PACKET_SIZE	0x40
+#define HS_BULK_EP_MAX_PACKET_SIZE	0x200
+#define HS_INT_EP_MAX_PACKET_SIZE	0x40
+#define FS_EP_MAX_PACKET_SIZE		0x40
+
+#endif // _USB_CHAP9_H_
+
+

include/drivers/usb/usb_controller.h

@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2010-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+
+#ifndef _USB_CONTROLLER_H_
+#define _USB_CONTROLLER_H_
+
+#include <sys/types.h>
+#include <drivers/usb/usb_core.h>
+
+__BEGIN_DECLS
+
+#define MAX_SUPPORTED_USB_CONTROLLER	(2)
+
+typedef enum {
+	USB_CONTROLLER_synopsys_otg,
+	USB_CONTROLLER_dbgfifo,
+} USB_CONTROLLER_T;
+
+struct usb_controller_functions {
+	int (*init)(void);
+	void (*free_func)(void);
+	int (*start)(void);
+	void (*stop)(void);
+	void (*set_address)(uint32_t new_address);
+	int (*get_connection_speed)(void);
+	void (*activate_endpoint)(uint32_t endpoint, int type, int max_packet_size, int interval);
+	void (*do_endpoint_io)(struct usb_device_io_request *req);
+	void (*stall_endpoint)(uint32_t endpoint, bool stall);
+	void (*reset_endpoint_data_toggle)(uint32_t endpoint);
+	bool (*is_endpoint_stalled)(uint32_t endpoint);
+	void (*do_test_mode)(uint32_t selector);
+	void (*abort_endpoint)(uint32_t endpoint);
+	void (*deactivate_endpoint)(uint32_t endpoint);
+};
+
+int usb_controller_register(const struct usb_controller_functions *controller_functions);
+int usb_controller_init(void);
+void usb_controller_free(void);
+int usb_controller_start(void);
+void usb_controller_stop(void);
+void usb_controller_set_address(u_int32_t new_address);
+int usb_controller_get_connection_speed(void);
+void usb_controller_activate_endpoint(u_int32_t endpoint, int type, int max_packet_size, int interval);
+void usb_controller_do_endpoint_io(struct usb_device_io_request *req);
+void usb_controller_stall_endpoint(u_int32_t endpoint, bool stall);
+void usb_controller_reset_endpoint_data_toggle(u_int32_t endpoint);
+bool usb_controller_is_endpoint_stalled(u_int32_t endpoint);
+void usb_controller_do_test_mode(u_int32_t selector);
+void usb_controller_abort_endpoint(u_int32_t endpoint);
+void usb_controller_deactivate_endpoint(u_int32_t endpoint);
+
+__END_DECLS
+
+#endif // _USB_CONTROLLER_H_

include/drivers/usb/usb_core.h

@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2007-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+
+#ifndef _USB_CORE_H_
+#define _USB_CORE_H_
+
+#include <sys/types.h>
+#include <drivers/usb/usb_chap9.h>
+
+__BEGIN_DECLS
+
+//===================================================================================
+//		consts and macros
+//===================================================================================
+
+#define APPLE_USB_DFU_INTF		0
+#define APPLE_USB_TRNSFR_INTF	        APPLE_USB_DFU_INTF
+#define APPLE_USB_SERIAL_INTF		0x1
+
+#define APPLE_USB_SERIAL_CONFIG_STRING_IDX      4
+#define APPLE_USB_SERIAL_INTF_STRING_INDEX      5
+
+#define APPLE_USB_SERIAL_EP_BULK_IN     0x81
+#define APPLE_USB_SERIAL_EP_BULK_OUT    0x2
+#define APPLE_USB_TRNSFR_EP_BULK_OUT	0x4
+#define APPLE_USB_TRNSFR_EP_BULK_IN	0x85
+
+#define APPLE_USB_DFU_TOTAL_INTFS	1
+#define APPLE_USB_DFU_CLASS		0xfe
+#define APPLE_USB_DFU_SUBCLASS		0x1
+#define APPLE_USB_DFU_PROTOCOL		0x0
+
+#define APPLE_USB_SERIAL_TOTAL_EPS	2
+#define APPLE_USB_SERIAL_TOTAL_INTFS    2
+#define APPLE_USB_SERIAL_CLASS		0xff
+#define APPLE_USB_SERIAL_SUBCLASS	0xff
+#define APPLE_USB_SERIAL_PROTOCOL	0x51
+
+#if WITH_BULK_UPLOAD
+#define APPLE_USB_TRNSFR_TOTAL_EPS      2
+#else
+#define APPLE_USB_TRNSFR_TOTAL_EPS      1
+#endif
+
+#define APPLE_USB_TRNSFR_TOTAL_INTFS    1
+#define APPLE_USB_DFU_TRNSFR_CLASS      0xfe
+#define APPLE_USB_DFU_TRNSFR_SUBCLASS   0x1
+#define APPLE_USB_DFU_TRNSFR_PROTOCOL   0x2
+#define APPLE_USB_TRNSFR_CLASS		APPLE_USB_DFU_TRNSFR_CLASS
+#define APPLE_USB_TRNSFR_SUBCLASS	APPLE_USB_DFU_TRNSFR_SUBCLASS
+#define APPLE_USB_TRNSFR_PROTOCOL       APPLE_USB_DFU_TRNSFR_PROTOCOL
+
+//===================================================================================
+//		Enums, structs and Typedefs
+//===================================================================================
+
+enum
+{
+	USB_IO_ERROR = -1,
+	USB_IO_SUCCESS = 0,
+	USB_IO_ABORTED
+};
+
+enum
+{
+	CABLE_CONNECTED = 0,
+	CABLE_DISCONNECTED,
+	USB_RESET,
+	USB_ENUM_DONE
+};
+
+enum {
+    CONNECTION_SPEED_FULL = 0,
+    CONNECTION_SPEED_HIGH
+};
+
+#if WITH_RECOVERY_MODE
+enum {
+	PR_RESET_REQUEST = 0,	// put device into reset state before starting restore with bulk blaster protocol
+	PR_VENDOR_REQUEST = 0,
+	PR_VENDOR_BLIND_REQUEST // return success on usb before executing the command, primarily for fsboot or reboot
+};
+#endif
+
+struct usb_device_io_request
+{
+	u_int32_t                       endpoint;
+	volatile u_int8_t               *io_buffer;
+	int                             status;
+	u_int32_t                       io_length;
+	u_int32_t                       return_count;
+	void (*callback) (struct usb_device_io_request *io_request);
+	struct usb_device_io_request    *next;
+};
+
+struct usb_interface_instance
+{
+    int                                     total_interfaces;
+    struct usb_interface_descriptor   *interface_descs;
+    int                                     total_other_descs;
+    void                              *other_descs;
+    int                                     total_endpoints;
+    struct usb_endpoint_descriptor    *endpoint_descs;
+    int                                     total_string_descs;
+    char                              **string_descs;
+    
+	int (*handle_request) (struct usb_device_request *request, u_int8_t ** out_data);
+	void (*non_setup_data_phase_finished_callback) (u_int32_t data_rcvd);
+	void (*activate_interface) (void);
+	void (*deactivate_interface) (void);
+	void (*activate_endpoints) (void);
+	void (*deactivate_endpoints) (void);
+	void (*handle_bus_reset) (void);
+	int (*handle_get_interface) (void);
+	int (*handle_set_interface) (int alt_setting);
+	int (*handle_vendor_request) (struct usb_device_request *request);
+};
+
+//===================================================================================
+//			Global APIs
+//===================================================================================
+
+int usb_core_init (const char *config_desc_string);
+void usb_core_free (void);
+int usb_core_start();
+void usb_core_stop();
+void usb_core_handle_usb_control_receive (u_int8_t *ep0_rx_buffer, bool is_setup, int receive_length, bool *data_phase);
+void usb_core_register_interface (struct usb_interface_instance *if_ops);
+void usb_core_event_handler (int event);
+void usb_core_do_transfer (int endpoint, u_int8_t *buffer, int length, void (*callback)(struct usb_device_io_request *));
+void usb_core_send_zlp (void);
+void usb_core_complete_endpoint_io (struct usb_device_io_request *req);
+void usb_core_activate_endpoint (u_int32_t endpoint, int type, int max_packet_size, int interval);
+void usb_core_deactivate_endpoint (u_int32_t endpoint);
+void usb_core_abort_endpoint (int endpoint);
+bool usb_core_get_connection_speed (void);
+bool usb_core_get_cable_state (void);
+
+__END_DECLS
+
+#endif

include/drivers/usb/usb_debug.h

@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2010-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+int usb_send_data_to_file(const char *filename, size_t amount, uintptr_t address, int printCompletionStatus);
+

include/drivers/usb/usb_public.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2007-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+
+#ifndef _USB_PUBLIC_H_
+#define _USB_PUBLIC_H_
+
+#include <drivers/usb/usb_controller.h>
+
+__BEGIN_DECLS
+
+enum {
+    USB_TRANSFER_TYPE_DFU_GET,
+    USB_TRANSFER_TYPE_DFU_PUT,
+    USB_TRANSFER_TYPE_BULK_GET,
+    USB_TRANSFER_TYPE_BULK_PUT
+};
+
+//===================================================================================
+//		Global APIs
+//===================================================================================
+
+int usb_early_init();
+int usb_init_with_controller(struct usb_controller_functions *controller_funcs);
+int usb_init();
+void usb_quiesce(void);
+
+int getDFUImage(void* buffer, int len);
+int usb_dfu_init(void);
+void usb_dfu_exit(void);
+
+int usb_transfer_init(void);
+void usb_transfer_exit(void);
+void usb_transfer_prepare(int type, void *address, u_int32_t maxlen);
+u_int32_t usb_transfer_start();
+
+int usb_serial_early_init(void);
+int usb_serial_init(void);
+void usb_serial_exit(void);
+void usb_serial_putchar(int);
+int usb_serial_send_cmd_string(u_int8_t *buffer, u_int32_t len);
+bool usb_serial_is_active();
+
+__END_DECLS
+
+#endif

include/drivers/usbphy.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2007 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Computer, Inc.
+ */
+
+#ifndef __DRIVERS_USBPHY_H
+#define __DRIVERS_USBPHY_H
+
+#include <sys/types.h>
+
+#if WITH_DEVICETREE
+#include <lib/devicetree.h>
+#endif
+
+__BEGIN_DECLS
+
+void usbphy_power_up(void);
+void usbphy_enable_pullup(void);
+void usbphy_power_down(void);
+bool usbphy_is_cable_connected(void);
+bool usbphy_set_dpdm_monitor(int select);
+#if WITH_CONJOINED_USB_PHYS
+void usbphy_select_phy(int index);
+#endif
+
+#if WITH_DEVICETREE
+extern void usbphy_update_device_tree(DTNode *pmgr_node);
+#endif
+
+__END_DECLS
+
+
+#endif
+

include/drivers/wpc.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __DRIVERS_WPC_H
+#define __DRIVERS_WPC_H
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+void wpc_init(uint32_t display_width, uint32_t display_height);
+void wpc_install_gamma_table(u_int32_t *red_lut, u_int32_t *green_lut, u_int32_t *blue_lut, struct syscfg_wpcl *wpcl);
+
+__END_DECLS
+
+#endif /* __DRIVERS_WPC_H */