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@@ -0,0 +1,294 @@
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/*
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* Copyright (C) 2015 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <platform.h>
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#include <platform/pmgr.h>
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#include <debug.h>
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static uint64_t pmgr_binning_read_register(uint64_t address, uint32_t low, uint32_t high, bool reg64)
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{
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uint64_t result = 0;
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do {
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uint64_t current_low;
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uint64_t offset;
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uint64_t register_value;
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if (reg64) {
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offset = high/64;
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current_low = offset * 64;
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register_value = ((uint64_t *)(address))[offset];
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} else {
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offset = high/32;
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current_low = offset * 32;
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register_value = ((uint32_t *)(address))[offset];
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}
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// Mask useful bit : [current_low:high]
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register_value &= (1ULL << (high - current_low + 1)) - 1;
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if (current_low <= low) {
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result |= register_value >> (low - current_low);
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break;
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}
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result |= register_value << (current_low - low);
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high = current_low - 1;
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} while (1);
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return result;
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}
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static uint64_t pmgr_binning_read(const struct pmgr_binning_fuse_to_register *fuse_to_register, uint32_t binning_low, uint32_t binning_high)
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{
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uint32_t result = 0;
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while (1) {
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uint32_t i = 0;
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while (fuse_to_register[i].register_address != 0) {
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if ((fuse_to_register[i].binning_high >= binning_high) && (fuse_to_register[i].binning_low <= binning_high)) {
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break;
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}
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i++;
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}
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if (fuse_to_register[i].register_address == 0) {
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return PMGR_BINNING_NOTFOUND;
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}
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if ((fuse_to_register[i].binning_high >= binning_high) && (fuse_to_register[i].binning_low <= binning_low)) {
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result |= pmgr_binning_read_register(fuse_to_register[i].register_address,
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binning_low - fuse_to_register[i].binning_low + fuse_to_register[i].register_low,
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binning_high - fuse_to_register[i].binning_low + fuse_to_register[i].register_low,
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fuse_to_register[i].register_64bit);
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break;
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}
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result |= pmgr_binning_read_register(fuse_to_register[i].register_address,
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fuse_to_register[i].register_low,
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binning_high - fuse_to_register[i].binning_low + fuse_to_register[i].register_low,
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fuse_to_register[i].register_64bit) << (fuse_to_register[i].binning_low - binning_low);
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binning_high = fuse_to_register[i].binning_low - 1;
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}
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return result;
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}
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static uint32_t pmgr_binning_from_const_data(enum pmgr_binning_type_t type, uint32_t mode, bool use_binning)
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{
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uint32_t i;
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for (i = 0; i < pmgr_binning_mode_to_const_data_size; i++) {
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if (pmgr_binning_mode_to_const_data[i].type != type) {
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continue;
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}
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if (pmgr_binning_mode_to_const_data[i].mode != mode) {
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continue;
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}
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if ((use_binning) && pmgr_binning_mode_to_const_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_mode_to_const_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
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continue;
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}
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if ((use_binning) && (pmgr_binning_get_revision() < pmgr_binning_mode_to_const_data[i].fuse_revision_minimum)) {
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continue;
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}
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if ((!use_binning) && (pmgr_binning_mode_to_const_data[i].fuse_revision_minimum != 0)) {
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continue;
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}
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return pmgr_binning_mode_to_const_data[i].mv;
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}
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return PMGR_BINNING_NOTFOUND;
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}
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uint32_t pmgr_binning_from_config_data(uint32_t voltage_index, const struct pmgr_binning_voltage_index_to_config **config_data)
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{
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uint32_t i;
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for (i = 0; i < pmgr_binning_voltage_index_to_config_data_size; i++) {
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if (pmgr_binning_voltage_index_to_config_data[i].voltage_index != voltage_index) {
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continue;
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}
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if (pmgr_binning_voltage_index_to_config_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_voltage_index_to_config_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
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continue;
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}
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if (pmgr_binning_get_revision() < pmgr_binning_voltage_index_to_config_data[i].fuse_revision_minimum) {
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continue;
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}
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*config_data = &pmgr_binning_voltage_index_to_config_data[i];
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return pmgr_binning_voltage_index_to_config_data[i].safe_voltage;
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}
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return PMGR_BINNING_NOTFOUND;
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}
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int32_t pmgr_binning_get_voltage_offset(uint32_t voltage_index, enum pmgr_binning_type_t type)
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{
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uint32_t i;
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uint32_t size = 0;
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const struct pmgr_binning_voltage_index_to_offset *voltage_index_to_offset;
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uint32_t board_id = platform_get_board_id();
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for (i = 0; i < pmgr_binning_board_id_to_offsets_data_size; i++) {
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if (pmgr_binning_board_id_to_offsets_data[i].board_id != board_id) {
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continue;
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}
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if (pmgr_binning_board_id_to_offsets_data[i].type != type) {
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continue;
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}
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if (platform_get_chip_revision() < pmgr_binning_board_id_to_offsets_data[i].chip_rev_min) {
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continue;
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}
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if (pmgr_binning_board_id_to_offsets_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_board_id_to_offsets_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
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continue;
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}
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voltage_index_to_offset = pmgr_binning_board_id_to_offsets_data[i].voltage_offsets;
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size = pmgr_binning_board_id_to_offsets_data[i].size;
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break;
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}
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for (i = 0; i < size; i++) {
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if (voltage_index_to_offset[i].voltage_index != voltage_index) {
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continue;
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}
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if (pmgr_binning_get_revision() < voltage_index_to_offset[i].fuse_revision_minimum) {
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continue;
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}
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return voltage_index_to_offset[i].offset;
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}
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return 0;
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}
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uint32_t pmgr_binning_mode_get_value(enum pmgr_binning_type_t type, uint32_t mode)
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{
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uint32_t i = 0;
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do {
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if (pmgr_binning_mode_to_fuse_data[i].type == PMGR_BINNING_END_OF_LIST) {
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return PMGR_BINNING_NOTFOUND;
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}
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if (pmgr_binning_mode_to_fuse_data[i].type != type) {
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i++;
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continue;
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}
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if (pmgr_binning_mode_to_fuse_data[i].mode != mode) {
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i++;
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continue;
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}
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if (type != PMGR_BINNING_GROUP && pmgr_binning_mode_to_fuse_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_mode_to_fuse_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
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i++;
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continue;
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}
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break;
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} while (1);
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if (pmgr_binning_mode_to_fuse_data[i].low > pmgr_binning_mode_to_fuse_data[i].high) {
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panic("Invalid low (%u) and high (%u) mode_to_fuse_data for type %u mode %u\n", pmgr_binning_mode_to_fuse_data[i].low, pmgr_binning_mode_to_fuse_data[i].high, type, mode);
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}
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uint32_t result = pmgr_binning_read(pmgr_binning_mode_to_fuse_data[i].fuse_to_register, pmgr_binning_mode_to_fuse_data[i].low, pmgr_binning_mode_to_fuse_data[i].high);
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return result;
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}
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uint32_t pmgr_binning_get_base(void)
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{
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static uint32_t base = 0;
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if (base == 0) {
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base = pmgr_binning_mode_get_value(PMGR_BINNING_BASE, 0);
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}
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return base;
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}
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uint32_t pmgr_binning_get_group(void)
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{
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static uint32_t group = 0;
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if (group == 0) {
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group =pmgr_binning_mode_get_value(PMGR_BINNING_GROUP, 0);
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}
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return group;
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}
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uint32_t pmgr_binning_get_revision(void)
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{
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static uint32_t revision = 0;
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if (revision == 0) {
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revision = pmgr_binning_mode_get_value(PMGR_BINNING_REV, 0);
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}
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return revision;
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}
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uint32_t pmgr_binning_mode_get_mv(enum pmgr_binning_type_t type, uint32_t mode)
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{
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uint32_t value = pmgr_binning_mode_get_value(type, mode);
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if ((value == PMGR_BINNING_NOTFOUND) || (value == 0)) {
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return PMGR_BINNING_NOTFOUND;
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}
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return 25 * (pmgr_binning_get_base() + 1) + value * 5;
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}
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uint32_t pmgr_binning_get_mv(uint32_t voltage_index, bool sram, bool use_binning)
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{
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uint32_t voltage;
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int32_t voltage_offset;
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uint32_t mode;
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enum pmgr_binning_type_t type;
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if (sram) {
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if (voltage_index >= pmgr_binning_voltage_config_sram_data_size) {
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return PMGR_BINNING_NOTFOUND;
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}
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const struct pmgr_binning_voltage_config *binning_voltage_config;
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binning_voltage_config = &pmgr_binning_voltage_config_sram_data[voltage_index];
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voltage = binning_voltage_config->safe_voltage;
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type = binning_voltage_config->type;
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mode = binning_voltage_config->mode;
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if ((voltage == 0) && (type != PMGR_BINNING_NONE)){
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return pmgr_binning_from_const_data(type, mode, use_binning);
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}
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} else {
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const struct pmgr_binning_voltage_index_to_config *config_data;
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if (pmgr_binning_from_config_data(voltage_index, &config_data) == PMGR_BINNING_NOTFOUND) {
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return PMGR_BINNING_NOTFOUND;
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}
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voltage = config_data->safe_voltage;
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type = config_data->type;
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mode = config_data->mode;
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if (use_binning) {
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uint32_t voltage_binning = pmgr_binning_mode_get_mv(type, mode);
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if (voltage_binning != PMGR_BINNING_NOTFOUND) {
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voltage = voltage_binning;
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}
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}
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}
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voltage_offset = pmgr_binning_get_voltage_offset(voltage_index, type);
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if ((int32_t)voltage + voltage_offset < 0) {
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panic("Invalid voltage offset");
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}
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return voltage + voltage_offset;
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}
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const struct pmgr_binning_vol_adj *pmgr_binning_get_vol_adj(uint32_t chipdid, uint32_t chip_rev, uint32_t voltage_index)
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{
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uint32_t fuse_rev = pmgr_binning_get_revision();
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for (size_t i = 0; i < pmgr_binning_voltadj_entry_data_size; i++) {
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if (voltage_index != pmgr_binning_voltadj_entry_data[i].voltage_index) {
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continue;
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}
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if ((chip_rev < pmgr_binning_voltadj_entry_data[i].chip_rev_min)) {
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continue;
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}
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if ((fuse_rev < pmgr_binning_voltadj_entry_data[i].fuse_rev_min)) {
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continue;
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}
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return &pmgr_binning_voltadj_entry_data[i].voltages;
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}
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return NULL;
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}
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@@ -0,0 +1,344 @@
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/*
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* Copyright (c) 2015 Apple Inc. All rights reserved.
|
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*
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||||
* This document is the property of Apple Inc.
|
||||
* It is considered confidential and proprietary.
|
||||
*
|
||||
* This document may not be reproduced or transmitted in any form,
|
||||
* in whole or in part, without the express written permission of
|
||||
* Apple Inc.
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||||
*/
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#if !RELEASE_BUILD && WITH_MENU
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#include <sys/menu.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <platform.h>
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#include <stdio.h>
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#include <sys.h>
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#include <lib/env.h>
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#include <platform/pmgr.h>
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static bool pmgr_binning_menu_override_get_voltage_indexes(bool gpu, uint32_t *voltage_indexes, uint32_t voltage_index_size, uint32_t *voltage_index_found)
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{
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uint32_t freq = 0;
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uint32_t i = 0;
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const char *name = env_get(gpu?"pmgr_gpu_override":"pmgr_cpu_override");
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const struct pmgr_binning_voltage_index_to_config *config_data;
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*voltage_index_found = 0;
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if (name == NULL) {
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return false;
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}
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while (i < voltage_index_size) {
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if (i > 0) {
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name = strchr(name, ',');
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if (name == NULL) {
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break;
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}
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name++;
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}
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voltage_indexes[i] = atoi(name);
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if (pmgr_binning_from_config_data(voltage_indexes[i], &config_data) == PMGR_BINNING_NOTFOUND) {
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return false;
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}
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if ((gpu) && (config_data->type != PMGR_BINNING_GPU)) {
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return false;
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}
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if ((!gpu) && (config_data->type != PMGR_BINNING_CPU)) {
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return false;
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}
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freq = pmgr_platform_get_freq(gpu, voltage_indexes[i]);
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if (freq == 0) {
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return false;
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}
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i++;
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}
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*voltage_index_found = i;
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return true;
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}
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static bool pmgr_binning_menu_find_safe_voltage(enum pmgr_binning_type_t type, uint32_t mode,
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uint32_t *safe_voltage, uint32_t *freq)
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{
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uint32_t i;
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*freq = 0;
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for (i = 0; i < pmgr_binning_voltage_config_sram_data_size; i++) {
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if (pmgr_binning_voltage_config_sram_data[i].mode != mode) {
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continue;
|
||||
}
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if (pmgr_binning_voltage_config_sram_data[i].type != type) {
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continue;
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||||
}
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*safe_voltage = pmgr_binning_voltage_config_sram_data[i].safe_voltage;
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return true;
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}
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for (i = 0; i < pmgr_binning_voltage_index_to_config_data_size; i++) {
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if (pmgr_binning_voltage_index_to_config_data[i].mode != mode) {
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continue;
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||||
}
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||||
if (pmgr_binning_voltage_index_to_config_data[i].type != type) {
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continue;
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}
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if (type == PMGR_BINNING_CPU) {
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*freq = pmgr_platform_get_freq(false, pmgr_binning_voltage_index_to_config_data[i].voltage_index);
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} else if (type == PMGR_BINNING_GPU) {
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*freq = pmgr_platform_get_freq(true, pmgr_binning_voltage_index_to_config_data[i].voltage_index);
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}
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*safe_voltage = pmgr_binning_voltage_index_to_config_data[i].safe_voltage;
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return true;
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}
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return false;
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}
|
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static void pmgr_binning_menu_print_type(enum pmgr_binning_type_t type)
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{
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uint32_t mode;
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for (mode = 1; mode < 63; mode++) {
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uint32_t result = pmgr_binning_mode_get_value(type, mode);
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uint32_t safe_voltage;
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uint32_t freq;
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if ((result == PMGR_BINNING_NOTFOUND) || (result == 0)) {
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continue;
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}
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printf(" mode %u %u mV (0x%x)", mode, pmgr_binning_mode_get_mv(type, mode), pmgr_binning_mode_get_value(type, mode));
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||||
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if (!pmgr_binning_menu_find_safe_voltage(type, mode, &safe_voltage, &freq)) {
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printf(" no safe voltage");
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} else {
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printf(" safe voltage %u mV", safe_voltage);
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}
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||||
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if (freq > 0) {
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printf(" %u MHz", freq);
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}
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printf("\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void pmgr_binning_menu_voltage_config_print(const struct pmgr_binning_voltage_config *voltage_config, uint32_t voltage_index)
|
||||
{
|
||||
const char *name = "";
|
||||
uint32_t freq = 0, safe_voltage = 0, mode = 0, type = 0;
|
||||
bool sram = false;
|
||||
|
||||
if (voltage_config != NULL) {
|
||||
safe_voltage = voltage_config->safe_voltage;
|
||||
mode = voltage_config->mode;
|
||||
type = voltage_config->type;
|
||||
}
|
||||
else {
|
||||
const struct pmgr_binning_voltage_index_to_config *config_data;
|
||||
if (pmgr_binning_from_config_data(voltage_index, &config_data) == PMGR_BINNING_NOTFOUND) {
|
||||
return;
|
||||
}
|
||||
safe_voltage = config_data->safe_voltage;
|
||||
mode = config_data->mode;
|
||||
type = config_data->type;
|
||||
}
|
||||
if (type == PMGR_BINNING_NONE) {
|
||||
return;
|
||||
}
|
||||
switch (type) {
|
||||
case PMGR_BINNING_CPU:
|
||||
name = "CPU";
|
||||
freq = pmgr_platform_get_freq(false, voltage_index);
|
||||
break;
|
||||
case PMGR_BINNING_GPU:
|
||||
name = "GPU";
|
||||
freq = pmgr_platform_get_freq(true, voltage_index);
|
||||
break;
|
||||
case PMGR_BINNING_SOC:
|
||||
name = "SOC";
|
||||
break;
|
||||
case PMGR_BINNING_CPU_SRAM:
|
||||
name = "CPU SRAM";
|
||||
sram = true;
|
||||
break;
|
||||
case PMGR_BINNING_GPU_SRAM:
|
||||
name = "GPU SRAM";
|
||||
sram = true;
|
||||
break;
|
||||
case PMGR_BINNING_SRAM:
|
||||
name = "SRAM";
|
||||
sram = true;
|
||||
break;
|
||||
default:
|
||||
name = "Unknown";
|
||||
break;
|
||||
}
|
||||
|
||||
printf(" %s index %u safe voltage %u mV",
|
||||
name,
|
||||
voltage_index,
|
||||
pmgr_binning_get_mv(voltage_index, sram, false));
|
||||
|
||||
if (pmgr_binning_mode_get_mv(type, mode) != PMGR_BINNING_NOTFOUND) {
|
||||
printf(" binning %u mV", pmgr_binning_get_mv(voltage_index, sram, true));
|
||||
} else {
|
||||
printf(" no binning %u mV", pmgr_binning_get_mv(voltage_index, sram, true));
|
||||
}
|
||||
|
||||
printf(" offset %d mV", pmgr_binning_get_voltage_offset(voltage_index, type));
|
||||
|
||||
if (mode != PMGR_BINNING_MODE_NONE && mode > 0) {
|
||||
printf(" mode %u", mode);
|
||||
}
|
||||
|
||||
if (freq > 0) {
|
||||
printf(" %u MHz", freq);
|
||||
}
|
||||
|
||||
if (sram && safe_voltage == 0) {
|
||||
uint32_t i;
|
||||
for (i = 0; i < pmgr_binning_mode_to_const_data_size; i++) {
|
||||
if (pmgr_binning_mode_to_const_data[i].type != type) {
|
||||
continue;
|
||||
}
|
||||
if (pmgr_binning_mode_to_const_data[i].mode != mode) {
|
||||
continue;
|
||||
}
|
||||
if (pmgr_binning_mode_to_const_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_mode_to_const_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
|
||||
continue;
|
||||
}
|
||||
printf(" fuse >= %d %d mV", pmgr_binning_mode_to_const_data[i].fuse_revision_minimum, pmgr_binning_mode_to_const_data[i].mv + pmgr_binning_get_voltage_offset(voltage_index, type));
|
||||
}
|
||||
}
|
||||
else if (!sram && mode != PMGR_BINNING_MODE_NONE) {
|
||||
uint32_t i;
|
||||
for (i = 0; i < pmgr_binning_voltage_index_to_config_data_size; i++) {
|
||||
if (pmgr_binning_voltage_index_to_config_data[i].voltage_index != voltage_index) {
|
||||
continue;
|
||||
}
|
||||
if (pmgr_binning_voltage_index_to_config_data[i].type != type) {
|
||||
continue;
|
||||
}
|
||||
if (pmgr_binning_voltage_index_to_config_data[i].bingroup != pmgr_binning_get_group() && pmgr_binning_voltage_index_to_config_data[i].bingroup != PMGR_BINNING_GROUP_ALL) {
|
||||
continue;
|
||||
}
|
||||
printf(" fuse >= %d %d mV", pmgr_binning_voltage_index_to_config_data[i].fuse_revision_minimum, pmgr_binning_voltage_index_to_config_data[i].safe_voltage + pmgr_binning_get_voltage_offset(voltage_index, type));
|
||||
}
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
static void pmgr_binning_menu_current_values_type(enum pmgr_binning_type_t type)
|
||||
{
|
||||
uint32_t i = 0;
|
||||
uint32_t freq;
|
||||
uint32_t voltage;
|
||||
while (pmgr_platform_get_perf_state(type, i, &voltage, &freq)) {
|
||||
if (freq == 0) {
|
||||
printf(" state %u: %u mV", i, voltage);
|
||||
} else {
|
||||
printf(" state %u: %u Mhz %u mV", i, freq / 1000000, voltage);
|
||||
}
|
||||
if ((type == PMGR_BINNING_CPU) && (pmgr_platform_get_perf_state(PMGR_BINNING_CPU_SRAM, i, &voltage, &freq))) {
|
||||
printf(" SRAM %u mV", voltage);
|
||||
}
|
||||
if ((type == PMGR_BINNING_GPU) && (pmgr_platform_get_perf_state(PMGR_BINNING_GPU_SRAM, i, &voltage, &freq))) {
|
||||
printf(" SRAM %u mV", voltage);
|
||||
}
|
||||
printf("\n");
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
static int do_pmgr(int argc, struct cmd_arg *args)
|
||||
{
|
||||
uint32_t voltage_indexes[32];
|
||||
uint32_t max_voltage_index = 0;
|
||||
uint32_t voltage_index_found;
|
||||
if ((argc < 2) || ((strcmp(args[1].str, "binning") != 0) && (strcmp(args[1].str, "values") != 0))) {
|
||||
printf("Usage\n");
|
||||
printf(" pmgr [values | [binning [internal|values]]]\n");
|
||||
printf(" pmgr binning: fused value\n");
|
||||
printf(" pmgr binning internal: fused value and all known operating points\n");
|
||||
printf(" pmgr values: values currently set in PMGR/ACC registers\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if ((argc > 1) && (strcmp(args[1].str, "values") == 0)) {
|
||||
printf("CPU:\n");
|
||||
pmgr_binning_menu_current_values_type(PMGR_BINNING_CPU);
|
||||
printf("GPU:\n");
|
||||
pmgr_binning_menu_current_values_type(PMGR_BINNING_GPU);
|
||||
printf("SOC:\n");
|
||||
pmgr_binning_menu_current_values_type(PMGR_BINNING_SOC);
|
||||
return 0;
|
||||
}
|
||||
|
||||
printf("Fuse revision %u base %u bin group %u\n", pmgr_binning_get_revision(), pmgr_binning_get_base(), pmgr_binning_get_group());
|
||||
printf(" CPU\n");
|
||||
pmgr_binning_menu_print_type(PMGR_BINNING_CPU);
|
||||
printf(" CPU SRAM\n");
|
||||
pmgr_binning_menu_print_type(PMGR_BINNING_CPU_SRAM);
|
||||
printf(" GPU\n");
|
||||
pmgr_binning_menu_print_type(PMGR_BINNING_GPU);
|
||||
printf(" GPU SRAM\n");
|
||||
pmgr_binning_menu_print_type(PMGR_BINNING_GPU_SRAM);
|
||||
printf(" SRAM\n");
|
||||
pmgr_binning_menu_print_type(PMGR_BINNING_SRAM);
|
||||
printf(" SOC\n");
|
||||
pmgr_binning_menu_print_type(PMGR_BINNING_SOC);
|
||||
|
||||
if ((argc > 2) && (strcmp(args[2].str, "internal") == 0)) {
|
||||
uint32_t i;
|
||||
printf("\n");
|
||||
for (i = 0; i < pmgr_binning_voltage_index_to_config_data_size; i++) {
|
||||
if (pmgr_binning_voltage_index_to_config_data[i].voltage_index > max_voltage_index) {
|
||||
max_voltage_index = pmgr_binning_voltage_index_to_config_data[i].voltage_index;
|
||||
}
|
||||
}
|
||||
for (i = 0; i <= max_voltage_index; i++) {
|
||||
pmgr_binning_menu_voltage_config_print(NULL, i);
|
||||
}
|
||||
for (i = 0; i < pmgr_binning_voltage_config_sram_data_size; i++) {
|
||||
pmgr_binning_menu_voltage_config_print(&pmgr_binning_voltage_config_sram_data[i], i);
|
||||
}
|
||||
}
|
||||
|
||||
if (pmgr_binning_menu_override_get_voltage_indexes(false, voltage_indexes, sizeof(voltage_indexes)/sizeof(voltage_indexes[0]), &voltage_index_found)) {
|
||||
uint32_t i;
|
||||
for (i = 0; i < voltage_index_found; i++) {
|
||||
if (i == 0) {
|
||||
printf("\n\nOverridden CPU states:\n");
|
||||
}
|
||||
printf(" state %u ", i + 3); // state 0 (bypass), 1 (securerom) and 2 (current state) are not overridden
|
||||
pmgr_binning_menu_voltage_config_print(NULL, voltage_indexes[i]);
|
||||
}
|
||||
}
|
||||
if (pmgr_binning_menu_override_get_voltage_indexes(true, voltage_indexes, sizeof(voltage_indexes)/sizeof(voltage_indexes[0]), &voltage_index_found)) {
|
||||
uint32_t i;
|
||||
for (i = 0; i < voltage_index_found; i++) {
|
||||
if (i == 0) {
|
||||
printf("\n\nOverridden GPU states:\n");
|
||||
}
|
||||
printf(" state %u ", i + 1); // state 0 (off) are not overridden
|
||||
pmgr_binning_menu_voltage_config_print(NULL, voltage_indexes[i]);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pmgr_binning_menu_update_states(void)
|
||||
{
|
||||
uint32_t voltage_indexes[32];
|
||||
uint32_t voltage_index_found;
|
||||
|
||||
if (pmgr_binning_menu_override_get_voltage_indexes(false, voltage_indexes, sizeof(voltage_indexes)/sizeof(voltage_indexes[0]), &voltage_index_found)) {
|
||||
pmgr_platform_set_perf_state(false, 3, voltage_indexes, voltage_index_found);
|
||||
}
|
||||
if (pmgr_binning_menu_override_get_voltage_indexes(true, voltage_indexes, sizeof(voltage_indexes)/sizeof(voltage_indexes[0]), &voltage_index_found)) {
|
||||
pmgr_platform_set_perf_state(true, 1, voltage_indexes, voltage_index_found);
|
||||
}
|
||||
}
|
||||
|
||||
// _command, _function, _help, _meta
|
||||
MENU_COMMAND_DEVELOPMENT(pmgr, do_pmgr, "Print pmgr data", NULL);
|
||||
|
||||
#endif // !RELEASE_BUILD && WITH_MENU
|
||||
@@ -0,0 +1,42 @@
|
||||
# Copyright (C) 2015 Apple Inc. All rights reserved.
|
||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
|
||||
#
|
||||
LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
|
||||
# All H8+ chip must use pmgr_binning
|
||||
PMGR_BINNING=0
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8000)
|
||||
PMGR_BINNING=1
|
||||
endif
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8001)
|
||||
PMGR_BINNING=1
|
||||
endif
|
||||
|
||||
ifeq ($(SUB_PLATFORM),s8003)
|
||||
PMGR_BINNING=1
|
||||
endif
|
||||
|
||||
ifeq ($(PMGR_BINNING),1)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/pmgr_binning.o
|
||||
|
||||
ifneq ($(BUILD),RELEASE)
|
||||
ifeq ($(PRODUCT),iBoot)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/pmgr_binning_menu.o
|
||||
endif
|
||||
ifeq ($(PRODUCT),iBEC)
|
||||
ALL_OBJS += \
|
||||
$(LOCAL_DIR)/pmgr_binning_menu.o
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
Reference in new issue
Block a user