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/*
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* Copyright (C) 2007-2013 Apple Inc. All rights reserved.
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*
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* This document is the property of Apple Inc.
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* It is considered confidential and proprietary.
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*
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* This document may not be reproduced or transmitted in any form,
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* in whole or in part, without the express written permission of
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* Apple Inc.
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*/
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#include <debug.h>
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#include <drivers/miu.h>
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#include <platform.h>
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#include <platform/memmap.h>
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#include <platform/miu.h>
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#include <platform/soc/miu.h>
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#include <platform/soc/pmgr.h>
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#include <platform/clocks.h>
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#include <platform/soc/hwclocks.h>
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static void miu_configure_bridge(const u_int32_t *bridge_settings);
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#define BRIDGE_SHIFT (16)
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#define BRIDGE_MASK (0xFFFF)
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#define NRT_DART_WIDGETS (0 << BRIDGE_SHIFT)
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#define NRT_DART_BRIDGE (1 << BRIDGE_SHIFT)
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#define NRT_TOP_WIDGETS (2 << BRIDGE_SHIFT)
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#define NRT_TOP_BRIDGE (3 << BRIDGE_SHIFT)
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#define RT_TOP_WIDGETS (4 << BRIDGE_SHIFT)
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#define RT_TOP_BRIDGE (5 << BRIDGE_SHIFT)
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#define UPERF_WIDGETS (6 << BRIDGE_SHIFT)
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#define UPERF_BRIDGE (7 << BRIDGE_SHIFT)
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#define CDIO_WIDGETS (8 << BRIDGE_SHIFT)
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#define CDIO_BRIDGE (9 << BRIDGE_SHIFT)
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static const u_int32_t bridge_registers[] = {
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NRT_DART_WIDGETS_BASE_ADDR, NRT_DART_PL301_BASE_ADDR,
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NRT_TOP_WIDGETS_BASE_ADDR, NRT_TOP_PL301_BASE_ADDR,
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RT_TOP_WIDGETS_BASE_ADDR, RT_TOP_PL301_BASE_ADDR,
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UPERF_WIDGETS_BASE_ADDR, UPERF_PL301_BASE_ADDR,
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CDIO_WIDGETS_BASE_ADDR, CDIO_PL301_BASE_ADDR,
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};
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#if APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
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// The following settings are based on H4P Tunables Revision 0.12
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static const u_int32_t bridge_settings_static[] = {
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// Configure recommended transaction limits in CDIO
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CDIO_WIDGETS | CDIO_IOP_RTLIMIT, 0x00000808,
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CDIO_WIDGETS | CDIO_IOP_WTLIMIT, 0x00000808,
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CDIO_WIDGETS | CDIO_CDMA_RTLIMIT, 0x00000808,
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CDIO_WIDGETS | CDIO_CDMA_WTLIMIT, 0x00000808,
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CDIO_WIDGETS | CDIO_UPERF_RTLIMIT, 0x00000404,
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CDIO_WIDGETS | CDIO_UPERF_WTLIMIT, 0x00000404,
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CDIO_WIDGETS | CDIO_AUDIO_RTLIMIT, 0x00000808,
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CDIO_WIDGETS | CDIO_AUDIO_WTLIMIT, 0x00000808,
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CDIO_WIDGETS | CDIO_PIO_RTLIMIT, 0x00000808,
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CDIO_WIDGETS | CDIO_PIO_WTLIMIT, 0x00000404,
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// Configure recommended bridge settings in CDIO
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CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0, 0x00000000,
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CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0, 0x01000001,
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CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0, 0x02000002,
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CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0, 0x03000003,
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CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI0, 0x04000004,
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CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0, 0x00000000,
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CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0, 0x01000001,
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CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0, 0x02000002,
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CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0, 0x03000003,
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CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI0, 0x04000004,
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CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1, 0x00000000,
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CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1, 0x01000001,
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CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1, 0x02000002,
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CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1, 0x03000003,
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CDIO_BRIDGE | CDIO_AR_CHAN_ARB_MI1, 0x04000004,
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CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1, 0x00000000,
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CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1, 0x01000001,
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CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1, 0x02000002,
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CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1, 0x03000003,
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CDIO_BRIDGE | CDIO_AW_CHAN_ARB_MI1, 0x04000004,
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// Configure recommended features in CDIO
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CDIO_WIDGETS | CDIO_IOP_WREQSP, 0x00000003,
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CDIO_WIDGETS | CDIO_CDMA_WGATHER, 0x00000100,
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CDIO_WIDGETS | CDIO_UPERF_WGATHER, 0x00000100,
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CDIO_WIDGETS | CDIO_AUDIO_WGATHER, 0x00000100,
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// Configure recommended traffic attributes in UPERF
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// AxCACHE = Cacheable
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// AxUSER = enable Shared bit
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UPERF_WIDGETS | UPERF_OTG_QOS, 0x01010101,
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UPERF_WIDGETS | UPERF_OTG_CACHE, 0x01020102,
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UPERF_WIDGETS | UPERF_EHCI_QOS, 0x01010101,
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UPERF_WIDGETS | UPERF_EHCI_CACHE, 0x01020102,
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UPERF_WIDGETS | UPERF_OHCI0_QOS, 0x01010101,
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UPERF_WIDGETS | UPERF_OHCI0_CACHE, 0x01020102,
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UPERF_WIDGETS | UPERF_OHCI1_QOS, 0x01010101,
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UPERF_WIDGETS | UPERF_OHCI1_CACHE, 0x01020102,
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0, 0,
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0, 0
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};
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#endif // APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
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#if WITH_DEVICETREE || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
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static const u_int32_t bridge_settings_dynamic[] = {
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// Configure recommended transaction limits in HPerf-NRT DART
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NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER0_RTLIMIT, 0x00000707,
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NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER0_WTLIMIT, 0x00000404,
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NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER1_RTLIMIT, 0x00000707,
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NRT_DART_WIDGETS | HPERF_NRT_DART_SCALER1_WTLIMIT, 0x00000404,
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NRT_DART_WIDGETS | HPERF_NRT_DART_DART_RTLIMIT, 0x00000808,
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NRT_DART_WIDGETS | HPERF_NRT_DART_DART_WTLIMIT, 0x00000808,
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// Configure recommended bridge settings in HPerf-NRT DART
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NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI, 0x00000000, // JPEG0 High Priority
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NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI, 0x01000001, // JPEG1 High Priority
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NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI, 0x02000102, // Scaler0 Reduced Priority
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NRT_DART_BRIDGE | HPERF_NRT_DART_AR_CHAN_ARB_MI, 0x03000103, // Sclaer1 Reduced Priority
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NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI, 0x00000000, // JPEG0 High Priority
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NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI, 0x01000001, // JPEG1 High Priority
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NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI, 0x02000102, // Scaler0 Reduced Priority
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NRT_DART_BRIDGE | HPERF_NRT_DART_AW_CHAN_ARB_MI, 0x03000103, // Sclaer1 Reduced Priority
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// Configure recommended bridge settings in HPerf-NRT DART
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NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG0_QOS, 0x01010101, // JPEG0 LLT Traffic for R&W
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NRT_DART_WIDGETS | HPERF_NRT_DART_JPEG1_QOS, 0x01010101, // JPEG0 LLT Traffic for R&W
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0, 0,
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// Configure recommended transaction limits in HPerf-NRT Top
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NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_RTLIMIT, 0x00001010,
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NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_WTLIMIT, 0x00000808,
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NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_RTLIMIT, 0x00001010,
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NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_WTLIMIT, 0x00000808,
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NRT_TOP_WIDGETS | HPERF_NRT_TOP_TOP_RTLIMIT, 0x00003F3F,
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NRT_TOP_WIDGETS | HPERF_NRT_TOP_TOP_WTLIMIT, 0x00000F0F,
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// Configure recommended bridge settings in HPerf-NRT Top
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NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI, 0x00000000,
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NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI, 0x01000001,
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NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI, 0x02000002,
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NRT_TOP_BRIDGE | HPERF_NRT_TOP_AR_CHAN_ARB_MI, 0x03000003,
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NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI, 0x00000000,
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NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI, 0x01000001,
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NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI, 0x02000002,
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NRT_TOP_BRIDGE | HPERF_NRT_TOP_AW_CHAN_ARB_MI, 0x03000003,
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// Configure recommended features in HPerf-NRT Top
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NRT_TOP_WIDGETS | HPERF_NRT_TOP_DART_WGATHER, 0x00000000,
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NRT_TOP_WIDGETS | HPERF_NRT_TOP_VENC_WREQSP, 0x00000003,
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NRT_TOP_WIDGETS | HPERF_NRT_TOP_VDEC_WREQSP, 0x00000003,
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0, 0,
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// Configure recommended transaction limits in HPerf-RT Top
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RT_TOP_WIDGETS | HPERF_RT_TOP_TOP_RTLIMIT, 0x00003F3F,
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RT_TOP_WIDGETS | HPERF_RT_TOP_TOP_WTLIMIT, 0x00000F0F,
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RT_TOP_WIDGETS | HPERF_RT_TOP_DISP0_RTLIMIT, 0x00000C0C,
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RT_TOP_WIDGETS | HPERF_RT_TOP_DISP1_RTLIMIT, 0x00001010,
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RT_TOP_WIDGETS | HPERF_RT_TOP_ISP_RTLIMIT, 0x00000C0C,
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RT_TOP_WIDGETS | HPERF_RT_TOP_ISP_WTLIMIT, 0x00001010,
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// Configure recommended bridge settings in HPerf-RT Top
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RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI, 0x00000000,
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RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI, 0x01000001,
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RT_TOP_BRIDGE | HPERF_RT_TOP_AR_CHAN_ARB_MI, 0x02000002,
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0, 0,
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0, 0
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};
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#endif // WITH_DEVICETREE || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
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int miu_initialize_internal_ram(void)
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{
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#if APPLICATION_SECUREROM
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// Ensure that rPMGR_SCRATCH0-3 get cleared
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rPMGR_SCRATCH0 = 0;
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rPMGR_SCRATCH1 = 0;
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rPMGR_SCRATCH2 = 0;
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rPMGR_SCRATCH3 = 0;
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#endif /* APPLICATION_SECUREROM */
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// Save the Security Epoch in the top byte of PMGR_SCRATCH0
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rPMGR_SCRATCH0 &= ~0xFF000000;
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rPMGR_SCRATCH0 |= (platform_get_security_epoch()) << 24;
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return 0;
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}
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int miu_init(void)
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{
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#if APPLICATION_IBOOT && !PRODUCT_IBEC
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// Verify that the Security Epoch in PMGR_SCRATCH0 matches
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if ((rPMGR_SCRATCH0 >> 24) != platform_get_security_epoch()) {
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panic("miu_init: Epoch Mismatch\n");
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}
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#endif
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#if APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC
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// Configure recommended transaction limits in CIF
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rCIF_RTLIMIT = 0x00000808;
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rCIF_WTLIMIT = 0x00000808;
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// Tunables recommendation, for SCU clock-gating
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// (will change to 0x80 for <rdar://problem/8267114>)
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rCIF_IDLETMR = 0x00000010;
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#endif
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#if APPLICATION_SECUREROM || (APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC)
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// Configure bridges that are statically powered
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clock_gate(CLK_UPERF, true);
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miu_configure_bridge(bridge_settings_static);
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clock_gate(CLK_UPERF, false);
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#endif
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#if APPLICATION_IBOOT && !PRODUCT_IBOOT && !PRODUCT_IBEC
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// Configure bridges that are dynamically powered
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clock_gate(CLK_HPERFNRT, true);
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clock_gate(CLK_HPERFRT, true);
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miu_configure_bridge(bridge_settings_dynamic);
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clock_gate(CLK_HPERFNRT, false);
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clock_gate(CLK_HPERFRT, false);
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/* Enable the SCU. Note that we explicitly do NOT touch the
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* "power status" register, since the default is supposed to
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* be correct, and the real control is in the CPU's "SMP"
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* bit. */
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rSCU_TAG_INVAL = 0xff; /* invalidate SCU tags for all CPUs */
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/* Enable SCU, standby, speculative linefills, and parity */
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rSCU_CONTROL = (1 << 5) | (1 << 3) | (1 << 2) | (1 << 0);
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#endif
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/* remap whatever bank of ram we're in to zero */
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if (TEXT_BASE == SRAM_BASE)
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miu_select_remap(REMAP_SRAM);
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else if ((TEXT_BASE >= SDRAM_BASE) && (TEXT_BASE < SDRAM_END))
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miu_select_remap(REMAP_SDRAM);
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return 0;
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}
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static void miu_configure_bridge(const u_int32_t *bridge_settings)
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{
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volatile u_int32_t *reg;
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u_int32_t cnt = 0, bridge, offset, data;
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while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
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while ((bridge_settings[cnt] != 0) || (bridge_settings[cnt + 1] != 0)) {
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bridge = bridge_settings[cnt] >> BRIDGE_SHIFT;
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offset = bridge_settings[cnt] & BRIDGE_MASK;
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data = bridge_settings[cnt + 1];
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reg = (volatile u_int32_t *)(bridge_registers[bridge] + offset);
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*reg = data;
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cnt += 2;
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}
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cnt += 2;
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}
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}
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void miu_suspend(void)
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{
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/* XXX ? */
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}
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int miu_initialize_dram(bool resume)
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{
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#if APPLICATION_IBOOT
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mcu_initialize_dram(resume);
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#endif
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return 0;
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}
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void miu_select_remap(enum remap_select sel)
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{
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switch (sel) {
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case REMAP_SRAM:
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rREMAP_CTL = (rREMAP_CTL & ~3) | (1 << 0); // remap_sel = 1
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rPL310_FILTER_START = 0x1;
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break;
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case REMAP_SDRAM:
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rREMAP_CTL = (rREMAP_CTL & ~3) | (2 << 0); // remap_sel = 2
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// Leave low megabyte heading to DRAM for wake-from-sleep,
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// Otherwise send everything below DRAM to the PIO block.
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// Currently this is for testing only; it is not POR.
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rPL310_FILTER_END = 0x80000000;
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rPL310_FILTER_START = 0x00100001;
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break;
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}
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/* read remap register to ensure it has been updated */
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rREMAP_CTL;
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}
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void miu_bypass_prep(void)
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{
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#if APPLICATION_IBOOT
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extern void mcu_bypass_prep(void);
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mcu_bypass_prep();
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#endif
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}
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#if WITH_DEVICETREE
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void miu_update_device_tree(DTNode *pmgr_node)
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{
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u_int32_t propSize;
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char *propName;
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void *propData;
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// Fill in the bridge-settings property
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propName = "bridge-settings";
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if (FindProperty(pmgr_node, &propName, &propData, &propSize)) {
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if (propSize >= sizeof(bridge_settings_dynamic)) {
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memcpy(propData, bridge_settings_dynamic, sizeof(bridge_settings_dynamic));
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}
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}
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}
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#endif
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@@ -0,0 +1,15 @@
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# Copyright (C) 2007 Apple Inc. All rights reserved.
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||||
#
|
||||
# This document is the property of Apple Inc.
|
||||
# It is considered confidential and proprietary.
|
||||
#
|
||||
# This document may not be reproduced or transmitted in any form,
|
||||
# in whole or in part, without the express written permission of
|
||||
# Apple Inc.
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#
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LOCAL_DIR := $(GET_LOCAL_DIR)
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OPTIONS += \
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WITH_HW_MIU=1
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ALL_OBJS += $(LOCAL_DIR)/miu.o
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Reference in new issue
Block a user