first and last commit

2023-07-08 13:03:17 -07:00
commit 1bf4efd552
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#if WITH_TARGET_AMC_PARAMS
+#include <target/amcconfig.h>
+#else
+static const struct amc_param amc_params = {
+	.flags     	 	= (FLAG_AMC_PARAM_BUSTAT23 | FLAG_AMC_PARAM_SLOW_BOOT | FLAG_AMC_PARAM_ZQCL),
+
+	.tREFi      		= 0x5d,
+	.longsrcnt  		= 0x2008,
+	.srextrarefcnt		= 0x00020000,
+	.rdlat      		= 6,
+	.wrlat      		= 3,
+	.phyrdlat   		= 10,
+	.phywrlat   		= 2,
+	.pdn        		= 0x22000403,
+	.read       		= 0x00000203,
+	.bustat     		= 0x00222209,
+	.bustat2    		= 0x00222209,
+	.derate     		= 0x2483135b,
+	.mcphyupdate		= 0x05030000,
+	.autoref_params		= 0x00000021,
+	.pwrmngtparam_small	= 0x00011000,
+	.pwrmngtparam_guided	= 0x01801000,
+	.chnldec		= 0x00050000,
+	.aref_freq0		= 0x00000110,
+	.schen_default		= 0x00000110,
+	.mr1			= 0x44,
+	.mr2			= 0x1a,
+	.mr3			= 0x02,
+	.pwrmngten_default	= 0x00100100,
+	.mcphyupdate1		= 0x00000001,
+	.odts			= 0x190,
+	.readleveling		= 0x00000300,
+	.offset_shift_hynix	= -2,
+	.offset_shift_elpida	= -1,
+	
+	.freq     		= {
+		{	// 800MHz
+			.cas         = 0x00000308,
+			.pch         = 0x00030612,
+			.act         = 0x12040908,
+			.autoref     = 0x19350000,
+			.selfref     = 0x00039060,
+			.modereg     = 0x20250782,
+			.mifcassch   = 0x00000110,
+			.arefparam   = 0x0c022131,
+		},
+		{	// 400MHz
+			.cas         = 0x00000005,
+			.pch         = 0x00000009,
+			.act         = 0x09020505,
+			.autoref     = 0x0d1b0000,
+			.selfref     = 0x0001d000,
+			.modereg     = 0x00130000,
+			.mifcassch   = 0x00000000,
+			.arefparam   = 0x00000101,
+		},
+		{	// 200MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000005,
+			.act         = 0x08020303,
+			.autoref     = 0x070e0000,
+			.selfref     = 0x0000f000,
+			.modereg     = 0x000a0000,
+			.mifcassch   = 0x00000000,
+			.arefparam   = 0x00000101,
+		},
+		{	// 50MHz
+			.cas         = 0x00000003,
+			.pch         = 0x00000003,
+			.act         = 0x08020303,
+			.autoref     = 0x02040000,
+			.selfref     = 0x00004000,
+			.modereg     = 0x00030000,
+			.mifcassch   = 0x00000000,
+			.arefparam   = 0x00000101,
+		}
+	}
+};
+
+static const struct amc_tunable amc_tunables[] = {
+	{ &rAMC_MCSARBCFG,		0x00000001 },
+	{ &rAMC_OPIDLETMR,		0x00200000 },
+	{ &rAMC_OPTMRADJPARAM,		0x20400064 },
+	{ &rAMC_MIFACTSCH,		0x00000001 },
+	{ &rAMC_MIFCASSCH_FREQ(0),	0x10000010 },
+	{ &rAMC_PSQRQCTL0,		0xff010110 },
+	{ &rAMC_PSQRQCTL1,		0x00001728 },
+	{ &rAMC_PSQRQTIMER0,		0x00000040 },
+	{ &rAMC_PSQRQTIMER1,		0x00000014 },
+	{ &rAMC_PSQRQTIMER2,		0x00000040 },
+	{ &rAMC_PSQRQBRST,		0x04100410 },
+	{ &rAMC_PSQRQSCHCRD,		0x00101400 },
+	{ &rAMC_PSQWQCTL0,		0x00010100 },
+	{ &rAMC_PSQWQBRST,		0x04100410 },
+	{ &rAMC_PSQWQSCHCRD,		0x00101400 },
+	{ &rAMC_MCUQOS,			0x00001919 },
+	{ &rAMC_MCUQOSLLT,		0x0000011f },
+};
+#endif
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+/*
+ * The amc_param struct is defined in drivers/apple/amp/amp.h, and this
+ * file should only by included from that amp.c.
+ */
+
+#if WITH_TARGET_AMP_PARAMS
+#include <target/ampconfig.h>
+#else
+static struct amp_params amc_phy_params = {
+	.freq = {
+		{
+			.caoutdllscl = 0x00000008,
+			.dqsindllscl = 0x00000008,
+			.rdcapcfg = 0x0102050f,
+		},
+		{
+			.caoutdllscl = 0x00000010,
+			.dqsindllscl = 0x00000010,
+			.rdcapcfg = 0x21020509,
+		},
+		{
+			.caoutdllscl = 0x00000020,
+			.dqsindllscl = 0x00000020,
+			.rdcapcfg = 0x41020506,
+		},
+		{
+			.caoutdllscl = 0x0000003f,
+			.dqsindllscl = 0x0000003f,
+			.rdcapcfg = 0x61020504,
+		},
+	},
+	.drive_strength = 0x14141414,
+	.cacalib_hw_loops = 8,
+	.cacalib_sw_loops = 8,
+};
+#endif
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_ERROR_HANDLER_H
+#define __PLATFORM_ERROR_HANDLER_H
+
+
+void platform_enable_error_handler();
+
+
+#endif // __PLATFORM_ERROR_HANDLER_H
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_GPIODEF_H
+#define __PLATFORM_GPIODEF_H
+
+/* S5L8960X specific gpio -> pin mappings */
+
+#include <platform/gpio.h>
+#include <platform/soc/hwregbase.h>
+
+#if WITH_TARGET_CONFIG
+# include <target/gpiodef.h>
+#endif
+
+/* define platform-specific gpios in a generic fashion here. */
+#define GPIO_BOARD_ID0		GPIO( 9, 0)
+#define GPIO_BOARD_ID1		GPIO( 9, 1)
+#define GPIO_BOARD_ID2		GPIO( 9, 2)
+#define GPIO_BOARD_ID3		GPIO( 2, 2)
+
+#define GPIO_BOOT_CONFIG0	GPIO( 2, 4)
+#define GPIO_BOOT_CONFIG1	GPIO(13, 1)
+#define GPIO_BOOT_CONFIG2	GPIO(13, 4)
+#define GPIO_BOOT_CONFIG3	GPIO(13, 5)
+
+#define GPIO_REQUEST_DFU1	GPIO( 0, 3)	// formerly known as HOLD_KEY
+#define GPIO_REQUEST_DFU2	GPIO( 0, 2)	// formerly known as MENU_KEY
+#define GPIO_FORCE_DFU		GPIO(13, 2)
+#define GPIO_DFU_STATUS		GPIO(13, 3)
+
+#define SPI_NOR0		(0)
+
+#if SUPPORT_FPGA
+#define GPIO_SPI0_CS		GPIO(GPIO_PAD_SPI, 0)
+#else
+#define GPIO_SPI0_CS		GPIO( 9, 3)
+#endif
+
+#define GPIO_IIC0_SCL		GPIO(10, 1)
+#define GPIO_IIC0_SDA		GPIO(10, 0)
+#define GPIO_IIC1_SCL		GPIO(10, 3)
+#define GPIO_IIC1_SDA		GPIO(10, 2)
+#define GPIO_IIC2_SCL		GPIO(12, 5)
+#define GPIO_IIC2_SDA		GPIO(12, 4)
+#define GPIO_IIC3_SCL		GPIO(21, 4)
+#define GPIO_IIC3_SDA		GPIO(21, 3)
+
+#endif /* ! __PLATFORM_GPIODEF_H */
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_IMAGE_DEVICES_H
+#define __PLATFORM_IMAGE_DEVICES_H
+
+static const struct image_device platform_image_devices[] = {
+#if defined(WITH_HW_ASP)
+    { "asp_fw", 0x00000 }
+#elif defined(WITH_ANC_FIRMWARE)
+    { "anc_firmware", 0x00000 }
+#elif defined(WITH_NAND_BOOT)
+    { "nand_firmware", 0x00000 }
+#elif defined(WITH_SW_H2FMI)
+    { "sw-h2fmi", 0x0000 }
+#else
+    { "nor0", 0x00000 }
+#endif
+};
+
+#if WITH_SYSCFG
+static const struct image_device platform_syscfg_devices[] = {
+#if defined(WITH_NAND_BOOT)
+       { "nand_syscfg", 0x00000 }
+#else
+       { "nor0", 0x00000 }
+#endif
+};
+#endif /* WITH_SYSCFG */
+
+#endif /* ! __PLATFORM_IMAGE_DEVICES_H */
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_MEMCONFIG_H
+#define __PLATFORM_MEMCONFIG_H
+
+/* S5L8960X SoC Mem Pin Configuration */
+
+static const gpio_t memory_interface_gpios[] = {
+	/* Not needed */
+};
+#endif /* ! __PLATFORM_MEMCONFIG_H */
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2011-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_MEMMAP_H
+#define __PLATFORM_MEMMAP_H
+
+#include <platform/memmap_defaults.h>
+
+/* S5L8960X specific memory map */
+
+///////////////////////////////////////////////////////////////////////////////////
+//           0x800000000 + dram_size     -------------------------------
+//                                       |        ASP (8MiB)           |
+//                                       |-----------------------------|
+//                                       |         TZ1 (1MiB)          |
+//                                       -------------------------------
+//                                       |   Consistent Debug (4KiB)   |
+//                                       |-----------------------------|
+//                                       |  Sleep Token Buffer (4KiB)  |
+//                                       |-----------------------------|
+//                                       |        Panic (512KiB)       |
+//                                       |-----------------------------|
+//                                       |        Display              |
+//                                       |   (Framebuffer + scratch)   |
+//                                       |                             |
+//                                       |                             |
+//                                       |-----------------------------|
+//                                       |                             |
+//                                       |     iBoot (Heap)            |
+//                                       |  (Variable size depending   |
+//                                       |    on DISPLAY_SIZE)         |
+//                       0x830180000 --> |-----------------------------|
+//                                       |     iBoot (Stacks)          |
+//                                       |     (STACKS_SIZE)           |
+//                       0x83017C000 --> |-----------------------------|
+//                                       |     iBoot (Page Tables)     |
+//                                       |     (PAGE_TABLES_SIZE)      |
+//                       0x830100000 --> |-----------------------------|
+//                                       |     iBoot (Text + Data)     |
+//                                       |     (TEXT_FOOTPRINT)        |
+//                       0x830000000 --> |-----------------------------| <-- 0x800000000 + dram_size - 256MB
+//                                       |                             |
+//                                       |          Unused             |
+//                                       |                             |
+//                                       |-----------------------------|
+//                                       |                             |
+//                                       |         (Ramdisk)           |
+//                                       |    (Kernel + DeviceTree)    |
+//                                       |       Secure memory         |
+//                                       |                             |
+//                                       |-----------------------------|
+//                                       |                             |
+//                                       |        Load region /        |
+//                                       |     Insecure Memory         |
+//                                       |    (overlaps with TZ0)      |    |-----------------------------|
+//                                       |                             |    |          TZ0 (varies)       |
+//                       0x800000000 --> -------------------------------    -------------------------------
+
+///////////////////////////////////////////////////////////////////////////////////
+
+#define SDRAM_BASE		(0x800000000ULL)
+#define SDRAM_BANK_LEN		(SDRAM_LEN)
+#define SDRAM_BANK_COUNT	(1)
+#define SDRAM_END		(SDRAM_BASE + SDRAM_LEN)
+
+// We'll map the DRAM uncached at the end of the cached mapping
+#define SDRAM_BASE_UNCACHED	(SDRAM_END)
+
+#define VROM_BASE		(0x100000000ULL)
+#define VROM_BANK_LEN		(0x00100000ULL)
+#define VROM_LEN		(0x00080000ULL)
+#define VROM_RSVD		(0x00100000ULL)		// 512 KiB reserved for SecureROM testing, remaining 512 KiB for Data and book-keeping
+#define SRAM_BASE		(0x180000000ULL)
+#define SRAM_LEN		(0x000400000ULL)	// 4 MiB
+#define SRAM_BANK_LEN		(SRAM_LEN)
+#define SRAM_BANK_COUNT		(1)
+#define SRAM_END		(SRAM_BASE + SRAM_LEN)
+
+#define IO_BASE			(0x200000000ULL)
+#define IO_SIZE			(0x10000000ULL)
+
+#define SECUREROM_LOAD_ADDRESS	(VROM_BASE)
+
+/* reserved for ASP */
+// NOTE ASP_SIZE is now defined by the platform or target makefile.
+#define ASP_BASE		(SDRAM_END - (ASP_SIZE))
+
+// Reserved for TZ1/AP Monitor
+#define TZ1_SIZE		(0x00100000ULL)
+#define TZ1_BASE		(ASP_BASE - TZ1_SIZE)
+
+#define CONSISTENT_DEBUG_SIZE	(0x00004000ULL)
+#define CONSISTENT_DEBUG_BASE	(TZ1_BASE - CONSISTENT_DEBUG_SIZE)
+
+/* reserved area for sleep token info */
+#define SLEEP_TOKEN_BUFFER_SIZE	(0x00001000ULL)
+#define SLEEP_TOKEN_BUFFER_BASE	(CONSISTENT_DEBUG_BASE - SLEEP_TOKEN_BUFFER_SIZE)
+
+/* reserved area for panic info */
+#define PANIC_SIZE		(0x00080000ULL)
+#define PANIC_BASE		(SLEEP_TOKEN_BUFFER_BASE - PANIC_SIZE)
+
+/* reserved area for display */
+// DISPLAY_SIZE comes from platform's rules.mk
+#define DISPLAY_BASE		(PANIC_BASE - DISPLAY_SIZE)
+
+// Reserved for TZ0/SEP
+// TZ0_SIZE is defined by the platform or target makefile
+#define TZ0_BASE		(SDRAM_BASE)
+
+/* where to stick heap and insecure memory */
+#if APPLICATION_SECUREROM
+
+#define DATA_SIZE		(0x00040000ULL)
+
+#define BOOK_KEEPING_BASE	(DATA_BASE + DATA_SIZE)
+#define BOOK_KEEPING_SIZE	(0x00020000ULL)
+
+#define BOOT_TRAMPOLINE_BASE	(BOOK_KEEPING_BASE + BOOK_KEEPING_SIZE)
+#define BOOT_TRAMPOLINE_SIZE	(0x1000ULL)
+
+#define HEAP_BASE		(SRAM_BASE + VROM_RSVD)
+#if !SUPPORT_FPGA
+#define HEAP_SIZE               (0x00100000ULL)
+#else
+#define HEAP_SIZE		(0x00080000ULL)
+#endif
+#define HEAP_END		(HEAP_BASE + HEAP_SIZE)
+
+#define INSECURE_MEMORY_SIZE	(0x00080000ULL)
+#define INSECURE_MEMORY_BASE	(SRAM_BASE + SRAM_LEN - INSECURE_MEMORY_SIZE)
+
+#endif /* APPLICATION_SECUREROM */
+
+#if APPLICATION_IBOOT
+
+#if WITH_DFU_MODE
+/* LLB, iBSS DFU */
+
+/* reserved area for iBoot */
+#define IBOOT_SIZE		(0x01400000ULL)
+#define IBOOT_BASE		(DISPLAY_BASE - IBOOT_SIZE)
+
+#define INSECURE_MEMORY_SIZE	(IBOOT_SIZE)
+#define INSECURE_MEMORY_BASE	(IBOOT_BASE)
+
+// SRAM memory map will usually look like the following:
+//
+// ROM Testing		0x000000 - 0x100000	(1024 KiB)
+// Heap			0x100000 - 0x1FEFFF	(1020 KiB)
+// Guard		0x1FF000 - 0x1FFFFF	(   4 KiB)
+// Unused		0x200000 - 0x37FFFF	(1536 KiB)
+// Code/Data		0x380000 - 0x3DFFFF	( 384 KiB)
+// Page Tables		0x3E0000 - 0x3FBFFF	( 112 KiB)
+// Stacks		0x3FC000 - 0x3FFFFF	(  16 KiB)
+
+#define HEAP_BASE		(SRAM_BASE + VROM_RSVD)
+#if !SUPPORT_FPGA
+#define HEAP_SIZE               (0x00100000ULL - PAGE_SIZE)
+#else
+#define HEAP_SIZE		(0x00080000ULL - PAGE_SIZE)
+#endif
+#define HEAP_END		(HEAP_BASE + HEAP_SIZE)
+#define HEAP_GUARD		(HEAP_END)
+
+#define PAGE_TABLES_BASE	(TEXT_BASE + TEXT_FOOTPRINT)
+#define PAGE_TABLES_SIZE	(STACKS_BASE - PAGE_TABLES_BASE)
+#define STACKS_BASE		(SRAM_BASE + SRAM_LEN - STACKS_SIZE)
+#define STACKS_SIZE		(EXCEPTION_STACK_SIZE + BOOTSTRAP_STACK_SIZE + INTERRUPT_STACK_SIZE)
+
+#else /* !WITH_DFU_MODE */
+
+/* iBoot, iBEC */
+
+// SDRAM memory map will usually look like the following:
+//
+// iBoot Text		0x830000000 - 0x8300FFFFF	(  1 MiB)
+// Page Tables		0x830100000 - 0x83017AFFF	(492 KiB)
+// Stacks		0x83017B000 - 0x83017EFFF	( 16 KiB)
+// Boot trampoline	0x83017F000 - 0x83017FFFF	(  4 KiB)
+// Heap			0x830180000 - (DISPLAY_BASE - 1 page)
+// Guard		(DISPLAY_BASE - 1 page) - DISPLAY_BASE
+
+/* reserved area for iBoot */
+#define IBOOT_BASE		(TEXT_BASE)
+#define IBOOT_SIZE		(HEAP_END - IBOOT_BASE)
+
+#define PAGE_TABLES_BASE	(IBOOT_BASE + TEXT_FOOTPRINT)
+#define PAGE_TABLES_SIZE	(0x0007B000ULL)
+#define STACKS_BASE		(PAGE_TABLES_BASE + PAGE_TABLES_SIZE)
+#define STACKS_SIZE		(EXCEPTION_STACK_SIZE + BOOTSTRAP_STACK_SIZE + INTERRUPT_STACK_SIZE)
+#define BOOT_TRAMPOLINE_BASE	(STACKS_BASE + STACKS_SIZE)
+#define BOOT_TRAMPOLINE_SIZE	(PAGE_SIZE)
+
+#define HEAP_BASE		(BOOT_TRAMPOLINE_BASE + BOOT_TRAMPOLINE_SIZE)
+#define HEAP_SIZE		(DISPLAY_BASE - HEAP_BASE - PAGE_SIZE)
+#define HEAP_END		(HEAP_BASE + HEAP_SIZE)
+#define HEAP_GUARD		(HEAP_END)
+#if (HEAP_GUARD != (DISPLAY_BASE - PAGE_SIZE))
+#error "Memory map configuration error"
+#endif
+
+#define INSECURE_MEMORY_BASE	(SDRAM_BASE)
+#define INSECURE_MEMORY_SIZE	(DEFAULT_LOAD_SIZE)
+
+#define SECURE_MEMORY_BASE	(INSECURE_MEMORY_BASE + INSECURE_MEMORY_SIZE)
+#define SECURE_MEMORY_SIZE	(DEFAULT_FREE_ADDRESS - SECURE_MEMORY_BASE)
+
+/* unused area */
+#define UNUSED_MEMORY_BASE	(SECURE_MEMORY_BASE + SECURE_MEMORY_SIZE)
+#define UNUSED_MEMORY_SIZE	(IBOOT_BASE - UNUSED_MEMORY_BASE)
+
+#endif /* !WITH_DFU_MODE */
+
+#endif /* APPLICATION_IBOOT */
+
+#endif /* ! __PLATFORM_MEMMAP_H */
@@ -0,0 +1,268 @@
+/*
+ * Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_PINCONFIG_H
+#define __PLATFORM_PINCONFIG_H
+
+/* Default S5L8960X SoC Pin Configuration */
+
+static const uint32_t gpio_default_cfg[GPIO_GROUP_COUNT * GPIOPADPINS] = {
+/* Port  0 */
+	CFG_DISABLED,							// TST_CLKOUT		->
+	CFG_FUNC0,							// WDOG			->
+	CFG_IN,								// GPIO0		-> MENU_KEY (REQUEST_DFU2)
+	CFG_IN,								// GPIO1		-> HOLD_KEY (REQUEST_DFU1)
+	CFG_DISABLED,							// GPIO2		->
+	CFG_DISABLED,							// GPIO3		->
+	CFG_DISABLED,							// GPIO4		->
+	CFG_DISABLED,							// GPIO5		->
+
+/* Port  1 */
+	CFG_DISABLED,							// GPIO6		->
+	CFG_DISABLED,							// GPIO7		->
+	CFG_DISABLED,							// GPIO8		->
+	CFG_DISABLED,							// GPIO9		->
+	CFG_DISABLED,							// GPIO10		->
+	CFG_DISABLED,							// GPIO11		->
+	CFG_DISABLED,							// GPIO12		->
+	CFG_DISABLED,							// GPIO13		->
+
+/* Port  2 */
+	CFG_DISABLED,							// GPIO14		->
+	CFG_DISABLED,							// GPIO15		->
+	CFG_DISABLED,							// GPIO16		-> BOARD_ID[3]
+	CFG_DISABLED,							// GPIO17		->
+	CFG_DISABLED,							// GPIO18		-> BOOT_CONFIG[0]
+	CFG_DISABLED,							// GPIO19		->
+	CFG_DISABLED,							// GPIO20		->
+	CFG_DISABLED,							// GPIO21		->
+
+/* Port  3 */
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+
+/* Port  4 */
+	CFG_DISABLED,							// UART1_TXD		->
+	CFG_DISABLED,							// UART1_RXD		->
+	CFG_DISABLED,							// UART1_RTSN		->
+	CFG_DISABLED,							// UART1_CTSN		->
+	CFG_DISABLED,							// UART2_TXD		->
+	CFG_DISABLED,							// UART2_RXD		->
+	CFG_DISABLED,							// UART2_RTSN		->
+	CFG_DISABLED,							// UART2_CTSN		->
+
+/* Port 5 */
+	CFG_DISABLED,							// UART3_TXD		->
+	CFG_DISABLED,							// UART3_RXD		->
+	CFG_DISABLED,							// UART3_RTSN		->
+	CFG_DISABLED,							// UART3_CTSN		->
+	CFG_DISABLED,							// UART5_RXD		->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+
+/* Port  6 */
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+
+/* Port  7 */
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+
+/* Port  8 */
+	CFG_DISABLED,							// UART4_TXD		->
+	CFG_DISABLED,							// UART4_RXD		->
+	CFG_DISABLED,							// UART4_RTSN		->
+	CFG_DISABLED,							// UART4_CTSN		->
+	CFG_DISABLED,							// SPI1_SCLK		->
+	CFG_DISABLED,							// SPI1_MOSI		->
+	CFG_DISABLED,							// SPI1_MISO		->
+	CFG_DISABLED,							// SPI1_SSIN		->
+
+/* Port  9 */
+	CFG_DISABLED,							// SPI0_SCLK		-> SPI0_SCLK/BOARD_ID[0]
+	CFG_DISABLED,							// SPI0_MOSI		-> SPI0_MOSI/BOARD_ID[1]
+	CFG_DISABLED,							// SPI0_MISO		-> SPI0_MISO/BOARD_ID[2]
+	CFG_DISABLED,							// SPI0_SSIN		->
+	CFG_DISABLED,							// SPI2_SCLK		->
+	CFG_DISABLED,							// SPI2_MOSI		->
+	CFG_DISABLED,							// SPI2_MISO		->
+	CFG_DISABLED,							// SPI2_SSIN		->
+
+/* Port  10 */
+	CFG_DISABLED,							// I2C0_SDA		->
+	CFG_DISABLED,							// I2C0_SCL		->
+	CFG_DISABLED,							// I2C1_SDA		->
+	CFG_DISABLED,							// I2C1_SCL		->
+	CFG_DISABLED,							// ISP0_SDA		->
+	CFG_DISABLED,							// ISP0_SCL		->
+	CFG_DISABLED,							// ISP1_SDA		->
+	CFG_DISABLED,							// ISP1_SCL		->
+
+/* Port  11 */
+	CFG_DISABLED,							// SENSOR0_RST		->
+	CFG_DISABLED,							// SENSOR0_CLK		->
+	CFG_DISABLED,							// SENSOR0_XSHUTDOWN	->
+	CFG_DISABLED,							// SENSOR0_ISTRB	->
+	CFG_DISABLED,							// SENSOR1_RST		->
+	CFG_DISABLED,							// SENSOR1_CLK		->
+	CFG_DISABLED,							// SENSOR1_XSHUTDOWN	->
+	CFG_DISABLED,							// SENSOR1_ISTRB	->
+
+/* Port  12 */
+	CFG_DISABLED,							// SPI3_MOSI		->
+	CFG_DISABLED,							// SPI3_MISO		->
+	CFG_DISABLED,							// SPI3_SCLK		->
+	CFG_DISABLED,							// SPI3_SSIN		->
+	CFG_DISABLED,							// I2C2_SDA		->
+	CFG_DISABLED,							// I2C2_SCL		->
+	CFG_DISABLED,							// GPIO22		->
+	CFG_DISABLED,							// GPIO23		->
+
+/* Port  13 */
+	CFG_DISABLED,							// GPIO24		->
+	CFG_DISABLED,							// GPIO25		-> BOOT_CONFIG[1]
+	CFG_IN | PULL_DOWN,						// GPIO26		-> FORCE_DFU
+	CFG_DISABLED | PULL_DOWN,					// GPIO27		-> DFU_STATUS
+	CFG_DISABLED,							// GPIO28		-> BOOT_CONFIG[2]
+	CFG_DISABLED,							// GPIO29		-> BOOT_CONFIG[3]
+	CFG_DISABLED,							// GPIO30		->
+	CFG_DISABLED,							// GPIO31		->
+
+/* Port  14 */
+	CFG_DISABLED,							// GPIO32		->
+	CFG_DISABLED,							// GPIO33		->
+	CFG_DISABLED,							// GPIO34		->
+	CFG_DISABLED,							// GPIO35		->
+	CFG_DISABLED,							// GPIO36		->
+	CFG_DISABLED,							// GPIO37		->
+	CFG_DISABLED,							// GPIO38		->
+	CFG_DISABLED,							// DISPLAY_SYNC		->
+
+/* Port  15 */
+	CFG_DISABLED,							// SOCHOT0		->
+	CFG_DISABLED,							// SOCHOT1		->
+	CFG_DISABLED,							// UART0_TXD		->
+	CFG_DISABLED,							// UART0_RXD		->
+	CFG_DISABLED,							// DWI_DI		->
+	CFG_DISABLED,							// DWI_D0		->
+	CFG_DISABLED,							// DWI_CLK		->
+	CFG_DISABLED,							// NULL			->
+
+/* Port  16 */
+	CFG_DISABLED,							// I2S0_LRCK		->
+	CFG_DISABLED,							// I2S0_BCLK		->
+	CFG_DISABLED,							// I2S0_DOUT		->
+	CFG_DISABLED,							// I2S0_DIN		->
+	CFG_DISABLED,							// I2S1_MCK		->
+	CFG_DISABLED,							// I2S1_LRCK		->
+	CFG_DISABLED,							// I2S1_BCLK		->
+	CFG_DISABLED,							// I2S1_DOUT		->
+	
+/* Port  17 */	
+	CFG_DISABLED,							// I2S1_DIN		->
+	CFG_DISABLED,							// I2S2_LRCK		->
+	CFG_DISABLED,							// I2S2_BCLK		->
+	CFG_DISABLED,							// I2S2_DOUT		->
+	CFG_DISABLED,							// I2S2_DIN		->
+	CFG_DISABLED,							// I2S3_MCK		->
+	CFG_DISABLED,							// I2S3_LRCK		->
+	CFG_DISABLED,							// I2S3_BCLK		->
+
+/* Port  18 */	
+	CFG_DISABLED,							// I2S3_DOUT		->
+	CFG_DISABLED,							// I2S3_DIN		->
+	CFG_DISABLED,							// I2S4_LRCK		->
+	CFG_DISABLED,							// I2S4_BCLK		->
+	CFG_DISABLED,							// I2S4_DOUT		->
+	CFG_DISABLED,							// I2S4_DIN		->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+
+/* Port 19 */
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+
+/* Port 20 */
+	CFG_DISABLED,							// TMR32_PWM0		->
+	CFG_DISABLED,							// TMR32_PWM1		->
+	CFG_DISABLED,							// TMR32_PWM2		->
+	CFG_DISABLED,							// SIO_7816UART0_SDA	->
+	CFG_DISABLED,							// SIO_7816UART0_SCL	->
+	CFG_DISABLED,							// SIO_7816UART0_RST	->
+	CFG_DISABLED,							// SIO_7816UART1_SDA	->
+	CFG_DISABLED,							// SIO_7816UART1_SCL	->
+
+/* Port 21 */
+	CFG_DISABLED,							// SIO_7816UART0_RST	->
+	CFG_DISABLED,							// UART6_TXD		->
+	CFG_DISABLED,							// UART6_RXD		->
+	CFG_DISABLED,							// I2C3_SDA		->
+	CFG_DISABLED,							// I2C3_SCL		->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+
+/* Port 22 */
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+
+/* Port 23 */
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+
+/* Port 24 */
+	CFG_DISABLED,							// EPD_HPD		->
+	CFG_DISABLED,							// I2S0_MCK		->
+	CFG_DISABLED,							// I2S2_MCK		->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+	CFG_DISABLED,							// NULL			->
+};
+
+#endif /* ! __PLATFORM_PINCONFIG_H */
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+
+#ifndef __PLATFORM_SOC_CCC_H
+#define __PLATFORM_SOC_CCC_H
+
+#define rCCC_CPU0_IMPL_IORVBAR			(*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x000))
+#define rCCC_CPU0_IMPL_CPU_IOACC_CTL_EL3	(*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x008))
+#define rCCC_CPU0_IMPL_FED_ERR_STS		(*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x010))
+#define rCCC_CPU0_IMPL_LSU_ERR_STS		(*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x018))
+#define rCCC_CPU0_IMPL_MMU_ERR_STS		(*(volatile u_int64_t *)(CCC_CPU0_SYS_BASE_ADDR + 0x020))
+
+#define CCC0_IMPL_BASE_ADDR			(CCC0_SYS_BASE_ADDR + 0x40000)
+#define rCCC_CCC_IMPL_CPM_IOACC_CTL_EL3		(*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x000))
+#define rCCC_CCC_IMPL_L2C_ERR_STS		(*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x008))
+#define rCCC_CCC_IMPL_L2C_ERR_ADR		(*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x010))
+#define rCCC_CCC_IMPL_L2C_ERR_INF		(*(volatile u_int64_t *)(CCC0_IMPL_BASE_ADDR + 0x018))
+
+#define rCCC_CPU1_IMPL_IORVBAR			(*(volatile u_int64_t *)(CCC_CPU1_SYS_BASE_ADDR + 0x000))
+#define rCCC_CPU2_IMPL_IORVBAR			(*(volatile u_int64_t *)(CCC_CPU2_SYS_BASE_ADDR + 0x000))
+
+#endif /* __PLATFORM_SOC_CCC_H */
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_CHIPID_H
+#define __PLATFORM_SOC_CHIPID_H
+
+#include <platform/chipid.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rCFG_FUSE0			(*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x00))
+#define	rCFG_FUSE1			(*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x04))
+#define	rCFG_FUSE2			(*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x08))
+#define	rCFG_FUSE3			(*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x0C))
+#define	rCFG_FUSE4			(*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x10))
+#define	rCFG_FUSE5			(*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x14))
+
+#define	rECIDLO				(*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x20))
+#define	rECIDHI				(*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x24))
+
+#define rAP_SECURITY			(*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x40))
+#define rSEP_SECURITY			(*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x44))
+
+#define rCFG_FUSE0_RAW			(*(volatile uint32_t *)(CHIPID_BASE_ADDR + 0x100))
+
+uint32_t chipid_get_soc_voltage(uint32_t index);
+uint32_t chipid_get_gpu_voltage(uint32_t index);
+
+#define CHIPID_CPU_VOLTAGE_BYPASS		(0)
+#define CHIPID_CPU_VOLTAGE_SECUREROM	(1)
+#define CHIPID_CPU_VOLTAGE_V0			(2)
+#define CHIPID_CPU_VOLTAGE_V1			(3)
+#define CHIPID_CPU_VOLTAGE_V2			(4)
+#define CHIPID_CPU_VOLTAGE_V3			(5)
+#define CHIPID_CPU_VOLTAGE_V4			(6)
+
+// CPU Boot Voltage - Should be cleaned up since not used for H6
+#if SUB_TARGET_N51 || SUB_TARGET_N53 || SUB_TARGET_J85 || SUB_TARGET_J86 || SUB_TARGET_J87 || SUB_TARGET_J85M || SUB_TARGET_J86M || SUB_TARGET_J87M
+#define CHIPID_CPU_VOLTAGE_MED		(CHIPID_CPU_VOLTAGE_V2)
+#else
+#define CHIPID_CPU_VOLTAGE_MED		(CHIPID_CPU_VOLTAGE_V1)
+#endif
+
+uint32_t chipid_get_cpu_voltage(uint32_t index);
+
+uint32_t chipid_get_ram_voltage(uint32_t index);
+
+int32_t chipid_get_cpu_temp_offset(uint32_t cpu_number);
+
+uint32_t chipid_get_fused_pmgr_thermal_sensor_cal_70C(uint32_t sensorID);
+uint32_t chipid_get_fused_pmgr_thermal_sensor_cal_25C(uint32_t sensorID);
+uint32_t chipid_get_fused_ccc_thermal_sensor_cal_70C(uint32_t sensorID);
+uint32_t chipid_get_fused_ccc_thermal_sensor_cal_25C(uint32_t sensorID);
+uint32_t chipid_get_fuse_revision(void);
+
+uint32_t chipid_get_total_rails_leakage();
+
+bool chipid_valid_thermal_sensor_cal_data_expected(void);	// <rdar://problem/13127987>
+
+#endif /* __PLATFORM_SOC_CHIPID_H */
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2012-2014 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __APPLE_DISPLAY_H
+#define __APPLE_DISPLAY_H
+
+// Platform-specific displaypipe tunables
+static struct adfe_v1_tuneable adfe_tuneables[] = 
+{
+#if DISPLAY_IPHONE_TUNABLES
+	{
+		.name = "default",
+		.disp_dpcclkcntl[0] = 			(DPCCLKCNTL_FLOOR(0x20)	|
+							 DPCCLKCNTL_PIPE_ENABLE |
+							 DPCCLKCNTL_LB_ENABLE	|
+							 DPCCLKCNTL_GATEENAB),
+		.disp_dpbclklvl_clock_off_level[0] =	DPBCLKLVL_OFFLVL(0x7f8),
+		.disp_dpbclklvl_clock_on_level[0] =	DPBCLKLVL_ONLVL(0x1e1),
+		.disp_dpcqoscnfg[0] =			(DPCQOSCNFG_QOS_TIMER(0xFA0)	|
+							 DPCQOSCNFG_PIPE_ENABLE		|
+							 DPCQOSCNFG_VIDFIFO_ENABLE	|
+							 DPCQOSCNFG_UIFIFO_ENABLE	|
+							 DPCQOSCNFG_QOS_ENABLE),
+		.disp_dpbqoslvl_med_watermark[0] =	DPBQOSLVL_MED_WATERMARK(0x1d7),
+		.disp_dpbqoslvl_high_watermark[0] =	DPBQOSLVL_HIGH_WATERMARK(0x13a),
+		.disp_dpureqcfg[0] =			DPUREQCFG_REQ_CNT(0x18),
+		.disp_dpusrcstrd[0] =			DPUSRCSTRD_SRCBURST_4BLOCKS,
+		.disp_dpvreqcfg[0] =			DPVREQCFG_REQ_CNT(0x6),
+		.disp_dpvsrcstrd[0] =			DPVSRCSTRD_SRCBURST_2BLOCKS,
+		.disp_dpcwbstrd[0] =			DPCWBSTRD_DSTBURST_4BLOCKS,
+	
+		.disp_dpcclkcntl[1] = 			(DPCCLKCNTL_FLOOR(0x20)	|
+							 DPCCLKCNTL_LB_ENABLE	|
+							 DPCCLKCNTL_GATEENAB),
+		.disp_dpbclklvl_clock_off_level[1] =	DPBCLKLVL_OFFLVL(0x7f8),
+		.disp_dpbclklvl_clock_on_level[1] =	DPBCLKLVL_ONLVL(0x1e1),
+		.disp_dpcqoscnfg[1] =			(DPCQOSCNFG_QOS_TIMER(0xFA0)	|
+							 DPCQOSCNFG_PIPE_ENABLE		|
+							 DPCQOSCNFG_VIDFIFO_ENABLE	|
+							 DPCQOSCNFG_UIFIFO_ENABLE	|
+							 DPCQOSCNFG_QOS_ENABLE),
+		.disp_dpbqoslvl_med_watermark[1] =	DPBQOSLVL_MED_WATERMARK(0x1d7),
+		.disp_dpbqoslvl_high_watermark[1] =	DPBQOSLVL_HIGH_WATERMARK(0x13a),
+		.disp_dpureqcfg[1] =			DPUREQCFG_REQ_CNT(0x18),
+		.disp_dpusrcstrd[1] =			DPUSRCSTRD_SRCBURST_4BLOCKS,
+		.disp_dpvreqcfg[1] =			DPVREQCFG_REQ_CNT(0x6),
+		.disp_dpvsrcstrd[1] =			DPVSRCSTRD_SRCBURST_2BLOCKS,
+		.disp_dpcwbstrd[1] =			DPCWBSTRD_DSTBURST_4BLOCKS,
+	},
+#endif	//DISPLAY_IPHONE_TUNABLES
+
+//Tunables for targets using the the timing based on landscape ipads
+#if DISPLAY_LANDSCAPE_IPAD_TUNABLES || DISPLAY_APPLE_TV_TUNABLES || DISPLAY_FPGA_TUNABLES
+	{
+		.name = "default",
+		.disp_dpcclkcntl[0] = 			(DPCCLKCNTL_FLOOR(0x20)	|
+							 DPCCLKCNTL_LB_ENABLE	|
+							 DPCCLKCNTL_GATEENAB),
+		.disp_dpbclklvl_clock_off_level[0] =	DPBCLKLVL_OFFLVL(0x7f8),
+		.disp_dpbclklvl_clock_on_level[0] =	DPBCLKLVL_ONLVL(0x708),
+		
+		.disp_dpcqoscnfg[0] =			(DPCQOSCNFG_QOS_TIMER(0x5780)	|
+							 DPCQOSCNFG_VIDFIFO_ENABLE	|
+							 DPCQOSCNFG_UIFIFO_ENABLE	|
+							 DPCQOSCNFG_QOS_ENABLE),
+		.disp_dpbqoslvl_med_watermark[0] =	DPBQOSLVL_MED_WATERMARK(0x5dc),
+		.disp_dpbqoslvl_high_watermark[0] =	DPBQOSLVL_HIGH_WATERMARK(0x3e8),
+		.disp_dpureqcfg[0] =			DPUREQCFG_REQ_CNT(0x73),
+		.disp_dpusrcstrd[0] =			DPUSRCSTRD_SRCBURST_4BLOCKS,
+		.disp_dpvreqcfg[0] =			DPVREQCFG_REQ_CNT(0x39),
+		.disp_dpvsrcstrd[0] =			DPVSRCSTRD_SRCBURST_2BLOCKS,
+		.disp_dpcwbstrd[0] =			DPCWBSTRD_DSTBURST_4BLOCKS,	
+
+		.disp_dpcclkcntl[1] = 			(DPCCLKCNTL_FLOOR(0x20)	|
+							 DPCCLKCNTL_LB_ENABLE	|
+							 DPCCLKCNTL_GATEENAB),
+		.disp_dpbclklvl_clock_off_level[1] =	DPBCLKLVL_OFFLVL(0x7f8),
+		.disp_dpbclklvl_clock_on_level[1] =	DPBCLKLVL_ONLVL(0x708),
+		
+		.disp_dpcqoscnfg[1] =			(DPCQOSCNFG_QOS_TIMER(0x5780)	|
+							 DPCQOSCNFG_VIDFIFO_ENABLE	|
+							 DPCQOSCNFG_UIFIFO_ENABLE	|
+							 DPCQOSCNFG_QOS_ENABLE),
+		.disp_dpbqoslvl_med_watermark[1] =	DPBQOSLVL_MED_WATERMARK(0x5dc),
+		.disp_dpbqoslvl_high_watermark[1] =	DPBQOSLVL_HIGH_WATERMARK(0x3e8),
+		.disp_dpureqcfg[1] =			DPUREQCFG_REQ_CNT(0x73),
+		.disp_dpusrcstrd[1] =			DPUSRCSTRD_SRCBURST_4BLOCKS,
+		.disp_dpvreqcfg[1] =			DPVREQCFG_REQ_CNT(0x39),
+		.disp_dpvsrcstrd[1] =			DPVSRCSTRD_SRCBURST_2BLOCKS,
+		.disp_dpcwbstrd[1] =			DPCWBSTRD_DSTBURST_4BLOCKS,
+	},
+	
+#if DISPLAY_IPHONE_TUNABLES
+#error DISPLAY_IPHONE_TUNABLES set for IPAD
+#endif
+	
+#endif //DISPLAY_LANDSCAPE_IPAD_TUNABLES || DISPLAY_APPLE_TV_TUNABLES
+};
+
+#endif	/* ! __APPLE_DISPLAY_H */
@@ -0,0 +1,350 @@
+/*
+ * Copyright (C) 2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Computer, Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_DISPLAY_COLOR_MANAGER_TABLES_H
+#define __PLATFORM_DISPLAY_COLOR_MANAGER_TABLES_H
+
+//identity matrix
+const uint32_t linear_identity_matrix_tables[] = {
+	0x00001000, 0x00000000,  0x00000000, 0x00000000,
+	0x00000000, 0x00000000,  0x00001000, 0x00000000,
+	0x00000000, 0x00000000,  0x00000000, 0x00000000,
+	0x00001000, 0x00000000,  0x00000000,
+};
+
+const uint32_t linear_rgb_engamma_tables[] = {
+	0x001a0000,
+	0x00470033,
+	0x00650057,
+	0x007c0071,
+	0x00900087,
+	0x00a20099,
+	0x00b100aa,
+	0x00c000b9,
+	0x00cd00c6,
+	0x00d900d3,
+	0x00e500df,
+	0x00f000eb,
+	0x00fa00f5,
+	0x01040100,
+	0x010e0109,
+	0x01170113,
+	0x0120011c,
+	0x01290124,
+	0x0131012d,
+	0x01390135,
+	0x0141013d,
+	0x01480144,
+	0x0150014c,
+	0x01570153,
+	0x015e015a,
+	0x01640161,
+	0x016b0168,
+	0x0172016e,
+	0x01780175,
+	0x017e017b,
+	0x01840181,
+	0x018a0187,
+	0x0190018e,
+	0x01960193,
+	0x019c0199,
+	0x01a2019f,
+	0x01a701a4,
+	0x01ac01aa,
+	0x01b201af,
+	0x01b701b4,
+	0x01bc01ba,
+	0x01c101bf,
+	0x01c601c4,
+	0x01cb01c9,
+	0x01d001ce,
+	0x01d501d3,
+	0x01da01d8,
+	0x01df01dc,
+	0x01e301e1,
+	0x01e801e6,
+	0x01ec01ea,
+	0x01f101ef,
+	0x01f501f3,
+	0x01fa01f8,
+	0x01fe01fc,
+	0x02030200,
+	0x02070205,
+	0x020b0209,
+	0x020f020d,
+	0x02130211,
+	0x02170215,
+	0x021b0219,
+	0x021f021d,
+	0x02230221,
+	0x02270225,
+	0x022b0229,
+	0x022f022d,
+	0x02330231,
+	0x02370235,
+	0x023b0239,
+	0x023e023c,
+	0x02420240,
+	0x02460244,
+	0x02490248,
+	0x024d024b,
+	0x0251024f,
+	0x02540252,
+	0x02580256,
+	0x025b0259,
+	0x025f025d,
+	0x02620260,
+	0x02660264,
+	0x02690267,
+	0x026c026b,
+	0x0270026e,
+	0x02730271,
+	0x02760275,
+	0x027a0278,
+	0x027d027b,
+	0x0280027f,
+	0x02830282,
+	0x02870285,
+	0x028a0288,
+	0x028d028b,
+	0x0290028f,
+	0x02930292,
+	0x02960295,
+	0x029a0298,
+	0x029d029b,
+	0x02a0029e,
+	0x02a302a1,
+	0x02a602a4,
+	0x02a902a7,
+	0x02ac02aa,
+	0x02af02ad,
+	0x02b202b0,
+	0x02b502b3,
+	0x02b802b6,
+	0x02ba02b9,
+	0x02bd02bc,
+	0x02c002bf,
+	0x02c302c2,
+	0x02c602c5,
+	0x02c902c7,
+	0x02cc02ca,
+	0x02ce02cd,
+	0x02d102d0,
+	0x02d402d3,
+	0x02d702d5,
+	0x02d902d8,
+	0x02dc02db,
+	0x02df02de,
+	0x02e202e0,
+	0x02e402e3,
+	0x02e702e6,
+	0x02ea02e8,
+	0x02ec02eb,
+	0x02ef02ee,
+	0x02f202f0,
+	0x02f402f3,
+	0x02f702f5,
+	0x02f902f8,
+	0x02fc02fb,
+	0x02ff02fd,
+	0x03010300,
+	0x03040302,
+	0x03060305,
+	0x03090307,
+	0x030b030a,
+	0x030e030c,
+	0x0310030f,
+	0x03130311,
+	0x03150314,
+	0x03180316,
+	0x031a0319,
+	0x031d031b,
+	0x031f031e,
+	0x03210320,
+	0x03240323,
+	0x03260325,
+	0x03290327,
+	0x032b032a,
+	0x032d032c,
+	0x0330032f,
+	0x03320331,
+	0x03340333,
+	0x03370336,
+	0x03390338,
+	0x033c033a,
+	0x033e033d,
+	0x0340033f,
+	0x03420341,
+	0x03450344,
+	0x03470346,
+	0x03490348,
+	0x034c034a,
+	0x034e034d,
+	0x0350034f,
+	0x03520351,
+	0x03550353,
+	0x03570356,
+	0x03590358,
+	0x035b035a,
+	0x035d035c,
+	0x0360035f,
+	0x03620361,
+	0x03640363,
+	0x03660365,
+	0x03680367,
+	0x036b0369,
+	0x036d036c,
+	0x036f036e,
+	0x03710370,
+	0x03730372,
+	0x03750374,
+	0x03770376,
+	0x037a0378,
+	0x037c037b,
+	0x037e037d,
+	0x0380037f,
+	0x03820381,
+	0x03840383,
+	0x03860385,
+	0x03880387,
+	0x038a0389,
+	0x038c038b,
+	0x038e038d,
+	0x0390038f,
+	0x03920391,
+	0x03940393,
+	0x03970396,
+	0x03990398,
+	0x039b039a,
+	0x039d039c,
+	0x039f039e,
+	0x03a103a0,
+	0x03a303a2,
+	0x03a503a4,
+	0x03a703a6,
+	0x03a803a8,
+	0x03aa03a9,
+	0x03ac03ab,
+	0x03ae03ad,
+	0x03b003af,
+	0x03b203b1,
+	0x03b403b3,
+	0x03b603b5,
+	0x03b803b7,
+	0x03ba03b9,
+	0x03bc03bb,
+	0x03be03bd,
+	0x03c003bf,
+	0x03c203c1,
+	0x03c403c3,
+	0x03c603c5,
+	0x03c703c6,
+	0x03c903c8,
+	0x03cb03ca,
+	0x03cd03cc,
+	0x03cf03ce,
+	0x03d103d0,
+	0x03d303d2,
+	0x03d503d4,
+	0x03d603d5,
+	0x03d803d7,
+	0x03da03d9,
+	0x03dc03db,
+	0x03de03dd,
+	0x03e003df,
+	0x03e103e1,
+	0x03e303e2,
+	0x03e503e4,
+	0x03e703e6,
+	0x03e903e8,
+	0x03ea03ea,
+	0x03ec03eb,
+	0x03ee03ed,
+	0x03f003ef,
+	0x03f203f1,
+	0x03f303f3,
+	0x03f503f4,
+	0x03f703f6,
+	0x03f903f8,
+	0x03fb03fa,
+	0x03fc03fb,
+	0x03fe03fd,
+	0x03ff03ff,
+};
+
+const uint32_t linear_rgb_degamma_tables[] = {
+	0x00280000,
+	0x0077004f,
+	0x00c7009e,
+	0x012100f0,
+	0x018d0152,
+	0x020d01c8,
+	0x02a40253,
+	0x035002f4,
+	0x041403ac,
+	0x04f1047c,
+	0x05e60565,
+	0x06f50667,
+	0x081e0783,
+	0x096308ba,
+	0x0ac40a0c,
+	0x0c400b7b,
+	0x0ddb0d06,
+	0x0f920eaf,
+	0x11681076,
+	0x135d125b,
+	0x1571145f,
+	0x17a61683,
+	0x19fa18c8,
+	0x1c701b2d,
+	0x1f071db3,
+	0x21c0205b,
+	0x249c2325,
+	0x279a2612,
+	0x2abc2922,
+	0x2e022c56,
+	0x316c2fae,
+	0x34fb332a,
+	0x38ae36cb,
+	0x3c883a92,
+	0x40873e7e,
+	0x44ad4290,
+	0x48fa46ca,
+	0x4d6d4b2a,
+	0x52094fb1,
+	0x56cc5460,
+	0x5bb75938,
+	0x60cc5e37,
+	0x66096360,
+	0x6b7068b2,
+	0x70fb6e2e,
+	0x76b673d3,
+	0x7c9b79a3,
+	0x82ab7f9e,
+	0x88e685c3,
+	0x8f4d8c14,
+	0x95e09291,
+	0x9c9e9939,
+	0xa38aa00e,
+	0xaaa2a710,
+	0xb1e7ae3f,
+	0xb95ab59b,
+	0xc0fabd24,
+	0xc8c9c4db,
+	0xd0c5ccc1,
+	0xd8f1d4d5,
+	0xe14cdd18,
+	0xe9d5e58b,
+	0xf28fee2c,
+	0xfb78f6fe,
+	0xffffffff,
+};
+
+#endif
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2013-2015 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __APPLE_DISPLAY_TIMINGS_H
+#define __APPLE_DISPLAY_TIMINGS_H
+
+//Supported timings by this platform
+static struct display_timing timing_list[] =
+{
+#if DEBUG_BUILD || SUB_TARGET_N51 || SUB_TARGET_N53 || SUB_TARGET_CYCLONIC
+	{ 
+	.display_name =   	"n51",	
+	.host_clock_id =  	CLK_VCLK0, 
+	.pixel_clock = 	  	61540000, 
+	.dot_pitch = 	  	326, 
+	.h_active =	  	640,
+	.h_pulse_width =  	6,  
+	.h_back_porch =   	32,  
+	.h_front_porch =  	4,  
+	.v_active = 	  	1136, 
+	.v_pulse_width =  	3,  
+	.v_back_porch =   	13, 
+	.v_front_porch =  	352, 
+	.neg_vclk = 	  	0, 
+	.neg_hsync = 	  	0, 
+	.neg_vsync = 	  	0, 
+	.neg_vden = 	  	0, 
+	.display_depth =  	24, 
+	.display_type =   	DISPLAY_TYPE_PINOT, 
+	.display_config =	NULL,
+	},
+#endif
+#if DEBUG_BUILD || WITH_HW_DISPLAY_DISPLAYPORT
+	{ 
+	.display_name =   	"720p",	
+	.host_clock_id =  	CLK_VCLK1, 
+	.pixel_clock = 	  	00000000, 
+	.dot_pitch = 	  	243, 
+	.h_active =	  	1280,
+	.h_pulse_width =  	40,  
+	.h_back_porch =   	110, 
+	.h_front_porch =  	220, 
+	.v_active = 	  	720,
+	.v_pulse_width =  	5,  
+	.v_back_porch =   	5, 
+	.v_front_porch =  	20, 
+	.neg_vclk = 	  	0, 
+	.neg_hsync = 	  	0, 
+	.neg_vsync = 	  	0, 
+	.neg_vden = 	  	0, 
+	.display_depth =  	24, 
+	.display_type =   	DISPLAY_TYPE_DP,     
+	.display_config =	NULL,
+	},
+	
+	{ 
+	.display_name =   	"720p-j34",	
+	.host_clock_id =  	CLK_VCLK0, 
+	.pixel_clock = 	  	74250000, 
+	.dot_pitch = 	  	243, 
+	.h_active =	  	1280,
+	.h_pulse_width =  	40, 
+	.h_back_porch =   	110, 
+	.h_front_porch =  	220, 
+	.v_active = 	  	720, 
+	.v_pulse_width =  	5, 
+	.v_back_porch =   	5, 
+	.v_front_porch =  	20, 
+	.neg_vclk = 	  	0, 
+	.neg_hsync = 	  	0, 
+	.neg_vsync = 	  	0, 
+	.neg_vden = 	  	0, 
+	.display_depth =  	24, 
+	.display_type =   	DISPLAY_TYPE_DP,     
+	.display_config =	NULL,
+	},
+#endif
+#if DEBUG_BUILD || SUB_TARGET_J71 || SUB_TARGET_J72 || SUB_TARGET_J73
+	{ 
+	.display_name =   	"ipad4",	
+	.host_clock_id =  	CLK_VCLK0, 
+	.pixel_clock = 	  	200000000, 
+	.dot_pitch = 	  	264, 
+	.h_active =	  	1536,
+	.h_pulse_width =  	15, 
+	.h_back_porch =   	52, 
+	.h_front_porch =  	16, 
+	.v_active = 	  	2048,
+	.v_pulse_width =  	1,  
+	.v_back_porch =   	3, 
+	.v_front_porch =  	7, 
+	.neg_vclk = 	  	0, 
+	.neg_hsync = 	  	0, 
+	.neg_vsync = 	  	0, 
+	.neg_vden = 	  	0, 
+	.display_depth =  	24, 
+	.display_type =   	DISPLAY_TYPE_EDP, 
+	.display_config =	NULL,
+	},
+#endif
+#if DEBUG_BUILD || SUB_TARGET_J85 || SUB_TARGET_J86 || SUB_TARGET_J87 || SUB_TARGET_J85M || SUB_TARGET_J86M || SUB_TARGET_J87M
+	{ 
+	.display_name =   	"ipad4b",	
+	.host_clock_id =  	CLK_VCLK0, 
+	.pixel_clock = 	  	200000000, 
+	.dot_pitch = 	  	326, 
+	.h_active =	  	1536,
+	.h_pulse_width =  	16,  
+	.h_back_porch =   	48, 
+	.h_front_porch =  	12, 
+	.v_active = 	  	2048,
+	.v_pulse_width =  	4,  
+	.v_back_porch =   	8, 
+	.v_front_porch =  	8, 
+	.neg_vclk = 	  	0, 
+	.neg_hsync = 	  	0, 
+	.neg_vsync = 	  	0, 
+	.neg_vden = 	  	0, 
+	.display_depth =  	24, 
+	.display_type =   	DISPLAY_TYPE_EDP, 
+	.display_config =	NULL,
+	},
+#endif
+};
+#endif	/* ! __APPLE_DISPLAY_TIMINGS_H */
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWCLOCKS_H
+#define __PLATFORM_SOC_HWCLOCKS_H
+
+#include <platform/clocks.h>
+
+#if SUPPORT_FPGA
+#define OSC_FREQ	(5000000UL)
+#else
+#define OSC_FREQ	(24000000UL)
+#endif
+
+// Start from an offset of 128. So that we are safely outside the PS indexes.
+#define CLK_FCLK	(HWCLOCK_BASE+128)
+#define CLK_ACLK	(HWCLOCK_BASE+129)
+#define CLK_HCLK	(HWCLOCK_BASE+130)
+#define CLK_PCLK	(HWCLOCK_BASE+131)
+#define CLK_VCLK0	(HWCLOCK_BASE+132)
+#define CLK_VCLK1	(HWCLOCK_BASE+133)
+#define CLK_MCLK	(HWCLOCK_BASE+134)
+#define CLK_NCLK	(HWCLOCK_BASE+135)
+#define CLK_USBPHYCLK	(HWCLOCK_BASE+136)
+#define CLK_NCOREF	(HWCLOCK_BASE+137)
+#define CLK_ANS_LINK	(HWCLOCK_BASE+138)
+
+/* 
+ * S5L8960X clock gate devices. 
+ * Refers to the ps register offsets.
+ */
+enum {
+	CLK_CPU0,
+	CLK_CPU1,
+	CLK_CPM,
+	CLK_LIO,
+	CLK_IOMUX,
+	CLK_AIC,
+	CLK_DEBUG,
+	CLK_DWI,
+	CLK_GPIO,
+	CLK_MCA0,
+	CLK_MCA1,
+	CLK_MCA2,
+	CLK_MCA3,
+	CLK_MCA4,
+	CLK_PWM0,
+	CLK_I2C0,
+	CLK_I2C1,
+	CLK_I2C2,
+	CLK_I2C3,
+	CLK_SPI0,
+	CLK_SPI1,
+	CLK_SPI2,
+	CLK_SPI3,
+	CLK_UART0,
+	CLK_UART1,
+	CLK_UART2,
+	CLK_UART3,
+	CLK_UART4,
+	CLK_UART5,
+	CLK_UART6,
+	CLK_SECUART0,
+	CLK_SECUART1,
+	CLK_AES0,
+	CLK_SIO,
+	CLK_SIO_P,
+	CLK_HSIC0_PHY,
+	CLK_HSIC1_PHY,
+	CLK_HSIC2_PHY,
+	CLK_ISPSENS0,
+	CLK_ISPSENS1,
+	CLK_MCC,
+	CLK_MCU,
+	CLK_AMP,
+	CLK_USB,
+	CLK_USBCTLREG,
+	CLK_USB2HOST0_OHCI,
+	CLK_USB2HOST0,
+	CLK_USB2HOST1_OHCI,
+	CLK_USB2HOST1,
+	CLK_USB_OTG,
+	CLK_SMX,
+	CLK_SF,
+	CLK_CP,
+	CLK_DISP_BUSMUX,
+	CLK_DISP0,
+	CLK_MIPI_DSI,
+	CLK_MIPI = CLK_MIPI_DSI,
+	CLK_EDPLINK,
+	CLK_DPLINK = CLK_EDPLINK,
+	CLK_DISP1,
+	CLK_ISP,
+	CLK_MEDIA,
+	CLK_MSR,
+	CLK_JPG,
+	CLK_VDEC,
+	CLK_VENC,
+	CLK_ANS,
+	CLK_ANS_DLL,
+	CLK_ADSP,
+	CLK_GFX,
+	PMGR_LAST_DEVICE,
+	CLK_SEP = CLK_GFX + 10,
+};
+
+#endif /* ! __PLATFORM_SOC_HWCLOCKS_H */
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWISR_H
+#define __PLATFORM_SOC_HWISR_H
+
+#define INT_SW0				0	// Software 0 Interrupt
+#define INT_SW1				1	// Software 1 Interrupt
+#define INT_SW2				2	// Software 2 Interrupt
+#define INT_SW3				3	// Software 3 Interrupt
+#define INT_WDT				4	// Watchdog Timer Interrupt
+#define INT_DWI				5	// DWI Interrupt
+#define INT_PMGR_PERF_CNTRS		6	// PMGR Performace Counters Interrupt
+#define INT_THERM_TEMP0			7	// Thermal Temp 0 Interrupt
+#define INT_THERM_ALARM0		8	// Thermal Alarm 0 Interrupt
+#define INT_THERM_TEMP1			9	// Thermal Temp 1 Interrupt
+#define INT_THERM_ALARM1		10	// Thermal Alarm 1 Interrupt
+
+// Reserved 11 - 19
+
+#define INT_THERM_FS_ACT0		20	// Thermal Failsafe Active 0 Interrupt
+#define INT_THERM_FS_ACT1		21	// Thermal Failsafe Active 1 Interrupt
+#define INT_THERM_FS_EXT0		22	// Thermal Failsafe Exit 0 Interrupt
+#define INT_THERM_FS_EXT1		23	// Thermal Failsafe Exit 1 Interrupt
+#define INT_SOC_THERM_FS_ACT0		24	// SoC Thermal Failsafe Active 0 Interrupt
+#define INT_SOC_THERM_FS_ACT1		25	// SoC Thermal Failsafe Active 1 Interrupt
+
+// Reserved 26 - 31
+
+#define INT_ISP_KF_INBOX_EMPTY		32	// ISP KF Inbox Empty Interrupt
+#define INT_ISP_KF_INBOX_NOTEMPTY	33	// ISP KF Inbox Not Empty Interrupt
+#define INT_ISP_KF_OUTBOX_EMPTY		34	// ISP KF Outbox Empty Interrupt
+#define INT_ISP_KF_OUTBOX_NOTEMPTY	35	// ISP KF Outbox Not Empty Interrupt
+#define INT_ISP0			36	// ISP 0 Interrupt
+#define INT_ISP1       			37	// ISP 1 Interrupt
+#define INT_ISP2			38	// ISP 2 Interrupt
+#define INT_ISP3       			39	// ISP 3 Interrupt
+#define INT_ISP_DART			40	// ISP DART Interrupt
+
+// Reserved 41 - 43
+
+#define INT_SEP_KF_INBOX_EMPTY		44	// SEP KF Inbox Empty Interrupt
+#define INT_SEP_KF_INBOX_NOTEMPTY	45	// SEP KF Inbox Not Empty Interrupt
+#define INT_SEP_KF_OUTBOX_EMPTY		46	// SEP KF Outbox Empty Interrupt
+#define INT_SEP_KF_OUTBOX_NOTEMPTY	47	// SEP KF Outbox Not Empty Interrupt
+
+// Reserved 48 - 51
+
+#define INT_ANS_KF_INBOX_EMPTY		52	// ANS KF Inbox Empty Interrupt
+#define INT_ANS_KF_INBOX_NOTEMPTY	53	// ANS KF Inbox Not Empty Interrupt
+#define INT_ANS_KF_OUTBOX_EMPTY		54	// ANS KF Outbox Empty Interrupt
+#define INT_ANS_KF_OUTBOX_NOTEMPTY	55	// ANS KF Outbox Not Empty Interrupt
+#define INT_ANS_CHNL0			56	// ANS Channel 0 Interrupt
+#define INT_ANS_CHNL1			57	// ANS Channel 1 Interrupt
+
+// Reserved 58 - 63
+
+#define INT_DISP0			64	// Display 0 Interrupt
+#define INT_DISP0_PERF_CNTRS		65	// Display 0 Performace Counters Interrupt 
+#define INT_DISP0_BACK_END_VBI		66	// Display 0 Back End VBI Interrupt
+#define INT_DISP0_BACK_END_MISC		67	// Display 0 Back End Misc Interrupt
+#define INT_MIPIDSI			68	// MIPI DSI Interrupt
+#define INT_EDP0			69	// Display Port
+#define INT_DPORT0			INT_EDP0
+
+// Reserved 70 - 73
+
+#define INT_DISP1			74	// Display 1 Interrupt
+#define INT_DISP1_PERF_CNTRS		75	// Display 1 Performace Counters Interrupt 
+#define INT_DISP1_BACK_END		76	// Display 1 Back End Interrupt
+
+// Reserved 77 - 79
+
+#define INT_VDEC			80	// Video Decoder Interrupt
+
+// Reserved 81
+
+#define INT_VENC			82	// Video Encoder Interrupt
+
+// Reserved 83
+
+#define INT_GFX				84	// GFX Interrupt
+#define INT_GFX_SLEEP			85	// GFX Sleep Interrupt
+#define INT_GFX_WAKE			86	// GFX Wake Interrupt
+#define INT_GFX_CHG			87	// GFX Change Interrupt
+
+// Reserved 88 - 89
+
+#define INT_ADSP_F0			90	// ADSP F0 Interrupt
+#define INT_ADSP_F1			91	// ADSP F1 Interrupt
+#define INT_ADSP_T0			92	// ADSP T0 Interrupt
+#define INT_ADSP_T1			93	// ADSP T1 Interrupt
+
+// Reserved 94
+
+#define INT_JPEG			95	// JPEG Interrupt
+#define INT_JPEG_ERR			96	// JPEG Error Interrupt
+#define INT_JPEG_DART			97	// JPEG DART Interrupt
+#define INT_JPEG_DART_PERF		98	// JPEG DART Performance Interrupt
+
+// Reserved 99
+
+#define INT_MSR				100	// MSR Interrupt
+#define INT_MSR_SMMU			101	// MSR SMMU Interrupt
+#define INT_MSR_DART			102	// MSR DART Interrupt
+#define INT_MSR_DAR_PERF		103	// MSR DART Performance Interrupt
+
+// Reserved 104-107
+
+#define INT_GPIO_CLASS0			108	// GPIO Class 0 Interrupt
+#define INT_GPIO_CLASS1			109	// GPIO Class 1 Interrupt
+#define INT_GPIO_CLASS2			110	// GPIO Class 2 Interrupt
+#define INT_GPIO_CLASS3			111 	// GPIO Class 3 Interrupt
+#define INT_GPIO_CLASS4			112	// GPIO Class 4 Interrupt
+#define INT_GPIO_CLASS5			113	// GPIO Class 5 Interrupt
+#define INT_GPIO_CLASS6			114	// GPIO Class 6 Interrupt
+
+// Reserved 115-127
+
+#define INT_MEM_CONTROLLER		128	// Memory Controller Interrupt
+#define INT_MCU_CHNL0_PHY		129	// MCU Channel 0 PHY
+#define INT_MCU_CHNL1_PHY		130	// MCU Channel 0 PHY
+
+// Reserved 131
+
+#define INT_SIO_KF_INBOX_EMPTY		132	// SIO KF Inbox Empty Interrupt
+#define INT_SIO_KF_INBOX_NOTEMPTY	133	// SIO KF Inbox Not Empty Interrupt
+#define INT_SIO_KF_OUTBOX_EMPTY		134	// SIO KF Outbox Empty Interrupt
+#define INT_SIO_KF_OUTBOX_NOTEMPTY	135	// SIO KF Outbox Not Empty Interrupt
+#define INT_SPI0			136	// SPI 0 Interrupt
+#define INT_SPI1			137	// SPI 1 Interrupt
+#define INT_SPI2			138	// SPI 2 Interrupt
+#define INT_SPI3			139	// SPI 3 Interrupt
+#define INT_UART0			140	// UART 0 Interrupt
+#define INT_UART1			141	// UART 1 Interrupt
+#define INT_UART2			142	// UART 2 Interrupt
+#define INT_UART3			143	// UART 3 Interrupt
+#define INT_UART4			144	// UART 4 Interrupt
+#define INT_UART5			145	// UART 5 Interrupt
+#define INT_UART6			146	// UART 6 Interrupt
+#define INT_UART7			147	// UART 7 Interrupt
+#define INT_MCA0			148	// Multi-Channel Audio 0 Interrupt
+#define INT_MCA1			149	// Multi-Channel Audio 1 Interrupt
+#define INT_MCA2			150	// Multi-Channel Audio 2 Interrupt
+#define INT_MCA3			151	// Multi-Channel Audio 3 Interrupt
+#define INT_MCA4			152	// Multi-Channel Audio 4 Interrupt
+#define INT_SEC_UART0			153	// Secure UART 0 Interrupt
+#define INT_SEC_UART1			154	// Secure UART 1 Interrupt
+#define INT_IIC0			155	// I2C 0 Interrupt
+#define INT_IIC1			156	// I2C 1 Interrupt
+#define INT_IIC2			157	// I2C 2 Interrupt
+#define INT_IIC3			158	// I2C 3 Interrupt
+#define INT_PWM				159	// PWM Interrupt
+#define INT_AES0			160	// AES 0 Interrupt
+
+// Reserved 161
+
+#define INT_USB_OTG			162	// USB OTG Interrupt
+#define INT_USB2HOST0_EHCI		163	// USB EHCI 0 Interrupt
+#define INT_USB2HOST0_OHCI		164	// USB OHCI 0 Interrupt
+#define INT_USB2HOST1_EHCI		165	// USB EHCI 1 Interrupt
+
+// Reserved 166 - 167
+
+#define INT_USBOTG_RESUME		168	// USB OTG Resume Interrupt
+#define INT_USB_20_BATT_CHRG_DET	169	// USB 2.0 Battery Charge Detect Interrupt
+#define INT_USB2HOST0_PHY_RESUME	170	// USB Host 0 Resume Interrupt
+#define INT_USB2HOST1_PHY_RESUME	171	// USB Host 1 Resume Interrupt
+
+// Reserved 172
+
+#define INT_COHERENCE_PNT_ERR		173	// Coherence Point Error Interrupt
+#define INT_COHERENCE_PNT_PERF_CNTRS	174	// Coherence Point Performance Counters Interrupt
+
+// Reserved 175
+
+#define INT_CPU0_COMM_TX		176	// CPU 0 COMM TX Interrupt
+#define INT_CPU0_COMM_RX		177	// CPU 0 COMM RX Interrupt
+#define INT_CPU0_PMU_IRQ		178	// CPU 0 PMU IRQ Interrupt
+#define INT_CPU1_COMM_TX		179	// CPU 1 COMM TX Interrupt
+#define INT_CPU1_COMM_RX		180	// CPU 1 COMM RX Interrupt
+#define INT_CPU1_PMU_IRQ		181	// CPU 1 PMU IRQ Interrupt
+
+// Reserved 182 - 184
+
+#define INT_CTM_TRIGGER0		185	// CTM Trigger 0 Interrupt
+#define INT_CTM_TRIGGER1		186	// CTM Trigger 1 Interrupt
+#define INT_CTM_TRIGGER2		187	// CTM Trigger 2 Interrupt
+#define INT_CTM_TRIGGER3		188	// CTM Trigger 3 Interrupt
+
+// Reserved 189 - 191
+
+#endif /* ! __PLATFORM_SOC_HWISR_H */
@@ -0,0 +1,270 @@
+/*
+ * Copyright (C) 2011-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_HWREGBASE_H
+#define __PLATFORM_SOC_HWREGBASE_H
+
+#include <platform/memmap.h>
+
+/* S5L8960X Reg Base Defs */
+
+#define AMC_BASE_ADDR			(IO_BASE + 0x000000000)		// AMC Config
+
+#define SWTCH_FAB_BASE_ADDR		(IO_BASE + 0x000800000)		// Switch Fabric Config
+
+#define CP_COM_BASE_ADDR		(IO_BASE + 0x000D00000)		// CP Common Registers
+#define CP_COM_INT_BASE_ADDR    (CP_COM_BASE_ADDR + 0x10000) // CP Common Interrupt Config Registers
+
+// XXX clarify these
+#define CP_0_DT_BASE_ADDR		(IO_BASE + 0x000D20000)		// Dup Tag Config and Debug
+#define CP_0_DT_DBG_CA0_ADDR		(IO_BASE + 0x000D30000)		// Dup Tag Debug backdoor Ram Access For CP0/CA0
+#define CP_0_CCU_CSR_BASE_ADDR		(IO_BASE + 0x000D90000)		// CTT and MIU Config and Debug
+#define CP_1_DT_BASE_ADDR		(IO_BASE + 0x000E20000)		// Dup Tag Config and Debug
+#define CP_1_DT_DBG_CA0_ADDR		(IO_BASE + 0x000E30000)		// Dup Tag Debug backdoor Ram Access For CP1/CA0
+#define CP_1_CCU_CSR_BASE_ADDR		(IO_BASE + 0x000E90000)		// CTT and MIU Config and Debug
+
+#define RGX_CR_BASE_ADDR		(IO_BASE + 0x001000000)		// G3 Rogue Space
+#define GPC_BASE_ADDR			(IO_BASE + 0x001e00000)		// G3 Power Controller Space
+
+#define IMGV42AF_AFC_AIU_BASE_ADDR	(IO_BASE + 0x001f00000)		// IMGv42AF: Local PIO Config Space of AF AIU Block
+#define IMGV42AF_AFUSR_BASE_ADDR	(IO_BASE + 0x001f02000)		// IMGv42AF: Bridge PIO Space
+
+#define CCC_ROM_TABLE_BASE_ADDR		(IO_BASE + 0x002000000)		// Cyclone ROM Table
+#define CCC_CPU0_DBG_BASE_ADDR		(IO_BASE + 0x002010000)		// Cyclone CPU0 Debug Registers
+#define CCC_CPU0_CTI_BASE_ADDR		(IO_BASE + 0x002020000)		// Cyclone CPU0 CTI Registers
+#define CCC_CPU0_PMU_BASE_ADDR		(IO_BASE + 0x002030000)		// Cyclone CPU0 PMU Registgers
+#define CCC_CPU0_TRC_BASE_ADDR		(IO_BASE + 0x002040000)		// Cyclone CPU0 TRACE Registers
+#define CCC_CPU0_SYS_BASE_ADDR		(IO_BASE + 0x002050000)		// Cyclone CPU0 Implementation Specific Registers
+#define CCC_CPU1_DBG_BASE_ADDR		(IO_BASE + 0x002110000)		// Cyclone CPU1 Debug Registers
+#define CCC_CPU1_CTI_BASE_ADDR		(IO_BASE + 0x002120000)		// Cyclone CPU1 CTI Registers
+#define CCC_CPU1_PMU_BASE_ADDR		(IO_BASE + 0x002130000)		// Cyclone CPU1 PMU Registgers
+#define CCC_CPU1_TRC_BASE_ADDR		(IO_BASE + 0x002140000)		// Cyclone CPU1 TRACE Registers
+#define CCC_CPU1_SYS_BASE_ADDR		(IO_BASE + 0x002150000)		// Cyclone CPU1 Implementation Specific Registers
+#define CCC0_SYS_BASE_ADDR		(IO_BASE + 0x002200000)		// Cyclone Core Complex Registers
+#define CCC_SOC_BUSMUX_BASE_ADDR	(IO_BASE + 0x004000000)		// AF SoC BusMux Config
+#define SOC_BUSMUX_BASE_ADDR		(IO_BASE + 0x004000000)		// AF SoC BusMux Config
+#define CCC_CAM_BUSMUX_BASE_ADDR	(IO_BASE + 0x005000000)		// AF Camera BusMux Config
+
+#define ISP_AFC_AIU_0_BASE_ADDR		(IO_BASE + 0x005B00000)		// ISP AXI to AF Bridge
+#define ISP_AFC_AIU_1_BASE_ADDR		(IO_BASE + 0x005B10000)		// ISP AXI to AF Bridge
+#define ISP_INTR2AXI_BASE_ADDR		(IO_BASE + 0x005B20000)		// ISP Interrupt to AXI Widget
+#define ISP_DART_BASE_ADDR		(IO_BASE + 0x005B22000)		// ISP DART
+#define ISP_SMMU_BASE_ADDR		(IO_BASE + 0x005B24000)		// ISP SMMU
+#define ISP_ISPCTRL_R0_BASE_ADDR	(IO_BASE + 0x005B40000)		// SISP Region 0 Control
+#define ISP_MIPI_CSI_0_BASE_ADDR	(IO_BASE + 0x005B80000)		// MIPI CSI Controller
+#define ISP_MIPI_CSI_1_BASE_ADDR	(IO_BASE + 0x005B81000)		// MIPI CSI Controller
+#define ISP_SMB_0_BASE_ADDR		(IO_BASE + 0x005B82000)		// SMB Controller
+#define ISP_SMB_1_BASE_ADDR		(IO_BASE + 0x005B83000)		// SMB Controller
+#define ISP_FD_BASE_ADDR		(IO_BASE + 0x005B84000)		// Face Detect
+#define ISP_AISP_BASE_ADDR		(IO_BASE + 0x005BA0000)		// AISP
+#define ISP_ISPCTRL_R1_BASE_ADDR	(IO_BASE + 0x005BC0000)		// SISP Region 1 Control
+#define ISP_AKF_BASE_ADDR		(IO_BASE + 0x005C00000)		// SISP KF Widgets and Config
+#define ISP_DISP_BUSMUX_BASE_ADDR	(IO_BASE + 0x006000000)		// AF Display BusMux Config
+
+#define DISP0_FAB_BASE_ADDR		(IO_BASE + 0x006100000)		// DisplayPipe0 AF and AXI Config
+#define DISP0_BASE_ADDR			(IO_BASE + 0x006200000) 	// DisplayPipe0 Frontend Config
+#define DISP0_ADBE_BASE_ADDR		(IO_BASE + 0x006300000)		// DisplayPipe0 Backend Config
+#define DISP0_AAP_BASE_ADDR		(IO_BASE + 0x006340000)		// DisplayPipe0 Ambient-Adaptive Pixel Config
+#define DISP0_DPB_BASE_ADDR		(IO_BASE + 0x006380000)		// DisplayPipe0 Pixel Backlight Config
+#define DISP0_DITHER_BASE_ADDR		(IO_BASE + 0x0063C0000)		// DisplayPipe0 Dither Config
+#define DITHER_BASE_ADDR		DISP0_DITHER_BASE_ADDR
+#define DITHER_VERSION			(3)
+#define DISP0_CM_BASE_ADDR		(IO_BASE + 0x006300000)		// DisplayPipe0 Color Manager
+#define DISP_CM_BASE_ADDR		DISP0_CM_BASE_ADDR
+
+#define DISP0_MIPI_DSI_BASE_ADDR	(IO_BASE + 0x006400000)		// DisplayPipe0 MIPI DSI Config
+#define DISP0_DPTX_BASE_ADDR		(IO_BASE + 0x006500000)		// DisplayPipe0 DisplayPort TX Config
+
+#define DISP1_FAB_BASE_ADDR		(IO_BASE + 0x006900000)		// DisplayPipe1 AF and AXI Config
+#define DISP1_BASE_ADDR			(IO_BASE + 0x006A00000) 	// DisplayPipe1 Frontend Config
+#define DISP1_ADBE_BASE_ADDR		(IO_BASE + 0x006B00000)		// DisplayPipe1 Backend Config
+#define DISP1_MEDIA_BUSMUX_BASE_ADDR	(IO_BASE + 0x007000000)		// DisplayPipe1 AF Media BusMux Config
+
+#define MSR_AFC_AIU_BASE_ADDR		(IO_BASE + 0x007800000)		// MSR AXI2AF AFC_AIU
+#define MSR_BASE_ADDR			(IO_BASE + 0x007900000)		// Memory Scalar Rotator
+#define MSR_SMMU_BASE_ADDR		(IO_BASE + 0x007904000)		// MSR SMMU
+#define MSR_DART_BASE_ADDR		(IO_BASE + 0x007908000)		// DART for MSR SMMU
+#define MSR_INTR2AXI_BASE_ADDR		(IO_BASE + 0x00790C000)		// MSR Interrupt to AXI Widget
+
+#define AJPEG_AFC_AIU_BASE_ADDR		(IO_BASE + 0x007A00000)		// AJPEG AXI2AF AFC_AIU
+#define AJPEG_INTR2AXI_BASE_ADDR	(IO_BASE + 0x007B00000)		// AJPEG Interrupt to AXI Widget
+#define AJPEG_BASE_ADDR			(IO_BASE + 0x007B01000)		// AJPEG Wrap
+#define AJPEG_DART_BASE_ADDR		(IO_BASE + 0x007B03000)		// AJPEG DART
+
+#define VXE_AFC_AIU_BASE_ADDR		(IO_BASE + 0x007C00000)		// VXE AXI2AF AFC_AIU
+#define VXE_INTR2AXI_BASE_ADDR		(IO_BASE + 0x007C01000)		// VXE Interrupt to AXI Widget
+#define VXE_PL301_BASE_ADDR		(IO_BASE + 0x007C02000)		// VXE PL301 Config
+#define VXE_CFG_BASE_ADDR		(IO_BASE + 0x007D00000)		// VXE Config Registers
+
+#define VXD_AFC_AIU_BASE_ADDR		(IO_BASE + 0x007E00000)		// VXD AXI2AF AFC_AIU
+#define VXD_INTR2AXI_BASE_ADDR		(IO_BASE + 0x007E01000)		// VXD Interrupt to AXI Widget
+#define VXD_PL301_BASE_ADDR		(IO_BASE + 0x007E02000)		// VXD PL301 Config
+#define VXD_CFG_BASE_ADDR		(IO_BASE + 0x007F00000)		// VXD Config Registers
+
+#define ANS_AFC_AIU_BASE_ADDR		(IO_BASE + 0x008000000)		// ANS AXI2AF AFC_AIU
+#define ANS_PL301_BASE_ADDR		(IO_BASE + 0x008010000)		// ANS PL301 Config
+#define ANS_AKF_PL301_TLMT_BASE_ADDR	(IO_BASE + 0x008020000)		// ANS KF Transaction Limit Widget
+#define ANS_AKF_INTR2AXI_BASE_ADDR	(IO_BASE + 0x008021000)		// ANS KF Interrupt to AXI Widget
+#define ANS_ANC_PL301_TLMT_0_BASE_ADDR	(IO_BASE + 0x008030000)		// ANS NAND Controller Transaction Limit Widget
+#define ANS_ANC_PL301_TLMT_1_BASE_ADDR	(IO_BASE + 0x008031000)		// ANS NAND Controller Transaction Limit Widget
+#define ANS_ANC_INTR2AXI_0_BASE_ADDR	(IO_BASE + 0x008038000)		// ANS NAND Controller Interrupt to AXI Widget
+#define ANS_ANC_INTR2AXI_1_BASE_ADDR	(IO_BASE + 0x008039000)		// ANS NAND Controller Interrupt to AXI Widget
+#define ANS_AKF_BASE_ADDR		(IO_BASE + 0x008040000)		// ANS KF Wrapper
+// XXX AKF DBG (IO_BASE + 0x008060000) - (IO_BASE + 0x008070000)
+#define ANS_CFG_BASE_BADDR		(IO_BASE + 0x008080000)		// ANS Config
+#define ANS_PPN_N_PL_BASE_ADDR		(IO_BASE + 0x008081000)		// ANS PPN-N-PL Config
+#define ANS_ANC_BASE_ADDR		(IO_BASE + 0x008700000)		// ANC Broadcast writes to all ANCs
+#define ANS_ANC_0_BASE_ADDR		(IO_BASE + 0x008800000)		// ANS NAND Controller 0
+#define ANS_ANC_1_BASE_ADDR		(IO_BASE + 0x008900000)		// ANS NAND Controller 1
+#define ANS_IO_BUSMUX_BASE_ADDR		(IO_BASE + 0x009000000) 	// ANS AF IO BusMux Config
+
+#define IOBUSMUX_BASE_ADDR		(IO_BASE + 0x009000000)		// IO BusMux Config
+
+#define SB_BASE_ADDR			(IO_BASE + 0x00A000000)		// South Bridge
+
+#define ASIO_MISC_0_BASE_ADDR		(IO_BASE + 0x00A000000)		// ASIO Shim0 Misc Registers
+#define ASIO_AUD_MUX_BASE_ADDR		(IO_BASE + 0x00A005000)		// ASIO Audio I2S Switch Config 
+#define ASIO_SPI_BASE_ADDR		(IO_BASE + 0x00A080000)		// ASIO SPI Device
+#define ASIO_SPI_TX_CFG_BASE_ADDR	(IO_BASE + 0x00A081000)		// ASIO SPI TX DMA Channel
+#define ASIO_SPI_RX_CFG_BASE_ADDR	(IO_BASE + 0x00A081800)		// ASIO SPI RX DMA Channel
+#define ASIO_SPI_TX_FIFO_BASE_ADDR	(IO_BASE + 0x00A082000)		// ASIO SPI TX DMA Shim FIFO
+#define ASIO_SPI_RX_FIFO_BASE_ADDR	(IO_BASE + 0x00A083000)		// ASIO SPI RX DMA Shim FIFO
+#define ASIO_UART_BASE_ADDR		(IO_BASE + 0x00A0A0000)		// ASIO UART Device
+#define ASIO_UART_TX_CFG_BASE_ADDR	(IO_BASE + 0x00A0A1000)		// ASIO UART TX DMA Channel
+#define ASIO_UART_RX_CFG_BASE_ADDR	(IO_BASE + 0x00A0A1800)		// ASIO UART RX DMA Channel
+#define ASIO_UART_TX_FIFO_BASE_ADDR	(IO_BASE + 0x00A0A2000)		// ASIO UART TX DMA Shim FIFO
+#define ASIO_UART_RX_FIFO_BASE_ADDR	(IO_BASE + 0x00A0A3000)		// ASIO UART RX DMA Shim FIFO
+#define ASIO_MCA_BASE_ADDR		(IO_BASE + 0x00A0C0000)		// ASIO MCA Device
+#define ASIO_MCA_TX_CFG_BASE_ADDR	(IO_BASE + 0x00A0C1000)		// ASIO MCA TX DMA Channel
+#define ASIO_MCA_RX_CFG_BASE_ADDR	(IO_BASE + 0x00A0C1800)		// ASIO MCA RX DMA Channel
+#define ASIO_MCA_TX_FIFO_BASE_ADDR	(IO_BASE + 0x00A0C2000)		// ASIO MCA TX DMA Shim FIFO
+#define ASIO_MCA_RX_FIFO_BASE_ADDR	(IO_BASE + 0x00A0C3000)		// ASIO MCA RX DMA Shim FIFO
+#define ASIO_MISC_1_BASE_ADDR		(IO_BASE + 0x00A100000)		// ASIO Shim1 Misc Registers
+#define ASIO_AES_BASE_ADDR		(IO_BASE + 0x00A108000)		// ASIO AES Config and DMA Registers
+#define ASIO_SMB_0_BASE_ADDR		(IO_BASE + 0x00A110000)		// ASIO I2C 0 Device
+#define ASIO_SMB_1_BASE_ADDR		(IO_BASE + 0x00A111000)		// ASIO I2C 1 Device
+#define ASIO_SMB_2_BASE_ADDR		(IO_BASE + 0x00A112000)		// ASIO I2C 2 Device
+#define ASIO_SMB_3_BASE_ADDR		(IO_BASE + 0x00A113000)		// ASIO I2C 3 Device
+#define ASIO_PWM_BASE_ADDR		(IO_BASE + 0x00A118000)		// ASIO PWM
+#define ASIO_SEP_UART_0_BASE_ADDR	(IO_BASE + 0x00A11C000)		// ASIO SCR Device 0
+#define ASIO_SEP_UART_1_BASE_ADDR	(IO_BASE + 0x00A11D000)		// ASIO SCR Device 1
+#define ASIO_AKF_BASE_ADDR		(IO_BASE + 0x00AE00000)		// ASIO KF Wrapper
+// XXX ASIO AKF DBG
+
+#define ADSP_BASE_ADDR			(IO_BASE + 0x00B000000)		// Audience Core
+
+#define AUSB_CTL_REG_BASE_ADDR		(IO_BASE + 0x00C000000)		// USBCTL Config
+#define AUSB_CTL_USB20PHY_REG_OFFSET	(0x20)				// USB20PHY Register offset within AUSBCTL registers
+#define AUSB_OTG_BASE_ADDR		(IO_BASE + 0x00C100000)		// USB OTG
+#define AUSB_USB2HOST0_EHCI_BASE_ADDR	(IO_BASE + 0x00C200000)		// EHCI0
+#define AUSB_USB2HOST0_OHCI_BASE_ADDR	(IO_BASE + 0x00C300000)		// OHCI0
+#define AUSB_USB2HOST1_EHCI_BASE_ADDR	(IO_BASE + 0x00C400000)		// EHCI1
+#define AUSB_USB2HOST1_OHCI_BASE_ADDR	(IO_BASE + 0x00C500000)		// OHCI1
+#define AUSB_PL301_BASE_ADDR		(IO_BASE + 0x00C800000)		// AUSB PL301 4-AHB Master to 1-AXI Slave
+#define AUSB_PL301_WIDGET_BASE_ADDR	(IO_BASE + 0x00C900000)		// AUSB PL301 Widget
+#define AUSB_INTR2AXI_BASE_ADDR		(IO_BASE + 0x00CA00000)		// AUSB Interrupt to AXI Widget
+#define AUSB_AFIFO_WIDGET_BASE_ADDR	(IO_BASE + 0x00CB00000)		// AUSB Async FIFO
+
+#define ASEP_AKF_BASE_ADDR		(IO_BASE + 0x00D000000)		// ASEP AKF control Registers
+
+#define PMGR_BASE_ADDR			(IO_BASE + 0x00E000000)		// PMGR
+
+#define AIC_BASE_ADDR			(IO_BASE + 0x00E100000)		// AIC
+#define AIC_WIRE_VIRT_BASE_ADDR		(IO_BASE + 0x00E110000)		// AIC Wrapper
+
+#define DWI_BASE_ADDR			(IO_BASE + 0x00E200000)		// DWI
+
+#define GPIO_BASE_ADDR			(IO_BASE + 0x00E300000)		// GPIO
+
+#define AMPS_0_DQ_BASE_ADDR		(IO_BASE + 0x00E400000)		// AMP 0 DQ DRAM PHY
+#define AMPS_0_CA_BASE_ADDR		(IO_BASE + 0x00E410000)		// AMP 0 CA DRAM PHY
+#define AMPS_1_DQ_BASE_ADDR		(IO_BASE + 0x00E420000)		// AMP 1 DQ DRAM PHY
+#define AMPS_1_CA_BASE_ADDR		(IO_BASE + 0x00E430000)		// AMP 1 CA DRAM PHY
+
+#define LIO_MEM_PL301_BASE_ADDR		(IO_BASE + 0x00E900000)		// PL310 for pd_lio memory
+#define LIO_PIO_PL310_BASE_ADDR		(IO_BASE + 0x00E940000)		// PL310 for pd_lio PIO
+#define LIO_SIO_AFIFO_WIDGETS_BASE_ADDR	(IO_BASE + 0x00E9C0000)		// SIO Async FIFO for pd_lio
+#define LIO_DAP_AFIFO_WIDGETS_BASE_ADDR	(IO_BASE + 0x00E9C8000)		// SIO Async FIFO for pd_lio
+#define LIO_AFC_AIU_BASE_ADDR		(IO_BASE + 0x00F010000)		// LIO AXI to AF Bridge
+
+#define DBG_WRP_BASE_ADDR		(IO_BASE + 0x00F000000)		// Debug Sub-system Config
+
+/* iBoot Specific Defs */
+
+#define AKF_VERSION			(1)
+
+#define UART0_BASE_ADDR			(ASIO_UART_BASE_ADDR)
+#define UART1_BASE_ADDR			(ASIO_UART_BASE_ADDR + 0x04000)
+#define UART2_BASE_ADDR			(ASIO_UART_BASE_ADDR + 0x08000)
+#define UART3_BASE_ADDR			(ASIO_UART_BASE_ADDR + 0x0C000)
+#define UART4_BASE_ADDR			(ASIO_UART_BASE_ADDR + 0x10000)
+#define UART5_BASE_ADDR			(ASIO_UART_BASE_ADDR + 0x14000)
+#define UART6_BASE_ADDR			(ASIO_UART_BASE_ADDR + 0x18000)
+#define UARTS_COUNT			(7)
+#define UART_VERSION			(1)
+
+#define SPI0_BASE_ADDR			(ASIO_SPI_BASE_ADDR)
+#define SPI1_BASE_ADDR			(ASIO_SPI_BASE_ADDR + 0x04000)
+#define SPI2_BASE_ADDR			(ASIO_SPI_BASE_ADDR + 0x08000)
+#define SPI3_BASE_ADDR			(ASIO_SPI_BASE_ADDR + 0x0C000)
+#define SPI_VERSION			(1)
+#define SPIS_COUNT			(4)
+
+#define IIC_BASE_ADDR			(ASIO_SMB_0_BASE_ADDR)
+#define IIC_SPACING			(0x00001000)
+#define IICS_COUNT			(4)
+
+#define USBPHY_VERSION			(4)
+
+#define DSIM_BASE_ADDR			(DISP0_MIPI_DSI_BASE_ADDR)
+#define DSIM_LANE_COUNT			(4)
+#define DSIM_VERSION			(2)
+
+#define EDP_BASE_ADDR			(DISP0_DPTX_BASE_ADDR)
+#define DP_BASE_ADDR			(EDP_BASE_ADDR)
+#define DISPLAYPORT_VERSION		(3)
+
+#define ADBE_DISPLAYPIPE_BASE_ADDR	(DISP0_BASE_ADDR)
+#define DISP_VERSION			(5)
+
+#define AMP_BASE_ADDR			(AMPS_0_DQ_BASE_ADDR)
+#define AMP_SPACING			(0x00020000)
+#define AMP_CA_SPACING			(0x00010000)
+
+#define CHIPID_BASE_ADDR		(PMGR_BASE_ADDR + 0x2A000)
+
+#define GPIO_VERSION			(3)
+#define GPIO_GROUP_COUNT		(25)
+#define GPIO_PAD_SPI                    (GPIO_GROUP_COUNT)
+
+#define AIC_VERSION			(1)
+#define AIC_INT_COUNT			(192)
+
+#define PMGR_WDG_VERSION		(1)
+
+#define USBOTG_BASE_ADDR		(AUSB_OTG_BASE_ADDR)
+
+#define AES_AP_BASE_ADDR		(ASIO_AES_BASE_ADDR)
+#define AES_AP_VERSION			(0)
+
+#if SUB_PLATFORM_S5L8970X
+#define DART0_BASE_ADDR			(PCI_BASE + 0x1002000)
+#define DART1_BASE_ADDR			(PCI_BASE + 0x2002000)
+#define DART2_BASE_ADDR			(PCI_BASE + 0x3002000)
+#define DART3_BASE_ADDR			(PCI_BASE + 0x4002000)
+
+#define PCIE_PORT0_DART_ID		(0)
+#define PCIE_PORT1_DART_ID		(1)
+#define PCIE_PORT2_DART_ID		(2)
+#define PCIE_PORT3_DART_ID		(3)
+#define NUM_DARTS			(4)
+#endif
+
+#endif /* ! __PLATFORM_SOC_HWREGBASE_H */
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_MIU_H
+#define __PLATFORM_SOC_MIU_H
+
+#include <lib/devicetree.h>
+#include <platform/soc/hwregbase.h>
+
+#define	rTZSROMCTRL_ROMADDRREMAP		(*(volatile u_int32_t *)(AMC_BASE_ADDR + 0x0904))
+#define	rTZSROMCTRL_TZ0REGIONADDR		(*(volatile u_int32_t *)(AMC_BASE_ADDR + 0x0908))
+#define	rTZSROMCTRL_TZ1REGIONADDR		(*(volatile u_int32_t *)(AMC_BASE_ADDR + 0x090C))
+#define	rTZSROMCTRL_TZ0LOCK			(*(volatile u_int32_t *)(AMC_BASE_ADDR + 0x0910))
+#define	rTZSROMCTRL_TZ1LOCK			(*(volatile u_int32_t *)(AMC_BASE_ADDR + 0x0914))
+
+
+#define ASIO_CLK_CTRL				(0x100004)
+#define rASIO_CLK_CTRL				(*(volatile u_int32_t *)(SB_BASE_ADDR + ASIO_CLK_CTRL))
+#define ASIO_AKF_IDLE_CTRL			(0xe00024)
+#define rASIO_AKF_IDLE_CTRL			(*(volatile u_int32_t *)(SB_BASE_ADDR + ASIO_AKF_IDLE_CTRL))
+#define DYN_CLK_GATING				(0x49a0000)
+#define rDYN_CLK_GATING				(*(volatile u_int32_t *)(SB_BASE_ADDR + DYN_CLK_GATING))
+#define SIO_ASYNC_FIFO_SB_RD_RATE_LIMIT		(0x49c0000)
+#define rSIO_ASYNC_FIFO_SB_RD_RATE_LIMIT	(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_RD_RATE_LIMIT))
+#define SIO_ASYNC_FIFO_SB_WR_RATE_LIMIT		(0x49c0004)
+#define rSIO_ASYNC_FIFO_SB_WR_RATE_LIMIT	(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_WR_RATE_LIMIT))
+#define SIO_ASYNC_FIFO_SB_WGATHER		(0x49c0010)
+#define rSIO_ASYNC_FIFO_SB_WGATHER		(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_ASYNC_FIFO_SB_WGATHER))
+#define SIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT	(0x49e0000)
+#define rSIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT	(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_RD_RATE_LIMIT))
+#define SIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT	(0x49e0004)
+#define rSIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT	(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_WR_RATE_LIMIT))
+#define SIO_DAPASYNC_FIFO_SB_WGATHER		(0x49e0010)
+#define rSIO_DAPASYNC_FIFO_SB_WGATHER		(*(volatile u_int32_t *)(SB_BASE_ADDR + SIO_DAPASYNC_FIFO_SB_WGATHER))
+#define AIU_SB_ARBCFG				(0x5010000)
+#define rAIU_SB_ARBCFG				(*(volatile u_int32_t *)(SB_BASE_ADDR + AIU_SB_ARBCFG))
+#define AIU_SB_CPG_CNTL				(0x5010014)
+#define rAIU_SB_CPG_CNTL			(*(volatile u_int32_t *)(SB_BASE_ADDR + AIU_SB_CPG_CNTL))
+
+
+#define SOCBUSMUX_ARBCFG			(0x0000)
+#define rSOCBUSMUX_ARBCFG			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + SOCBUSMUX_ARBCFG))
+#define DWRRCFG_DISPMUX_BULK			(0x0008)
+#define rDWRRCFG_DISPMUX_BULK			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + DWRRCFG_DISPMUX_BULK))
+#define TLIMIT_LVL0_CAMERAMUX			(0x0034)
+#define rTLIMIT_LVL0_CAMERAMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL0_CAMERAMUX))
+#define TLIMIT_LVL1_CAMERAMUX			(0x0038)
+#define rTLIMIT_LVL1_CAMERAMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_CAMERAMUX))
+#define TLIMIT_LVL1_MEDIAMUX			(0x0048)
+#define rTLIMIT_LVL1_MEDIAMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_MEDIAMUX))
+#define TLIMIT_LVL2_MEDIAMUX			(0x004c)
+#define rTLIMIT_LVL2_MEDIAMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL2_MEDIAMUX))
+#define TLIMIT_LVL0_IOMUX			(0x0054)
+#define rTLIMIT_LVL0_IOMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL0_IOMUX))
+#define TLIMIT_LVL1_IOMUX			(0x0058)
+#define rTLIMIT_LVL1_IOMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL1_IOMUX))
+#define TLIMIT_LVL2_IOMUX			(0x005c)
+#define rTLIMIT_LVL2_IOMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL2_IOMUX))
+#define TLIMIT_LVL3_IOMUX			(0x0060)
+#define rTLIMIT_LVL3_IOMUX			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + TLIMIT_LVL3_IOMUX))
+#define SOCBUSMUX_CPG_CNTL			(0x0088)
+#define rSOCBUSMUX_CPG_CNTL			(*(volatile u_int32_t *)(SOC_BUSMUX_BASE_ADDR + SOCBUSMUX_CPG_CNTL))
+
+
+#define IOBUSMUX_ARBCFG				(0x0000)
+#define rIOBUSMUX_ARBCFG			(*(volatile u_int32_t *)(IOBUSMUX_BASE_ADDR + IOBUSMUX_ARBCFG))
+#define IOBUSMUX_CPG_CNTL			(0x001c)
+#define rIOBUSMUX_CPG_CNTL			(*(volatile u_int32_t *)(IOBUSMUX_BASE_ADDR + IOBUSMUX_CPG_CNTL))
+
+
+#define SWITCH_FAB_ARBCFG			(0x0004)
+#define	rSWITCH_FAB_ARBCFG			(*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_ARBCFG))
+#define	SWITCH_FAB_PIOLIMIT			(0x0028)
+#define	rSWITCH_FAB_PIOLIMIT			(*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_PIOLIMIT))
+#define	SWITCH_FAB_CPG_CNTL			(0x0074)
+#define rSWITCH_FAB_CPG_CNTL			(*(volatile u_int32_t *)(SWTCH_FAB_BASE_ADDR + SWITCH_FAB_CPG_CNTL))
+
+
+#define CP_DYN_CLK_GATING_CTRL			(0x000c)
+#define rCP_DYN_CLK_GATING_CTRL			(*(volatile u_int32_t *)(CP_COM_BASE_ADDR + CP_DYN_CLK_GATING_CTRL))
+
+
+#define CPCOM_INT_NORM_REQUEST			(0x0000)
+#define rCP_COM_INT_NORM_REQUEST         (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_REQUEST))
+#define CPCOM_INT_NORM_MASK_SET			(0x0004)
+#define rCP_COM_INT_NORM_MASK_SET         (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_SET))
+#define CPCOM_INT_NORM_MASK_CLR			(0x0008)
+#define rCP_COM_INT_NORM_MASK_CLR         (*(volatile u_int32_t *)(CP_COM_INT_BASE_ADDR + CPCOM_INT_NORM_MASK_CLR))
+
+#define LIO_MEMCACHE_DATASETID_OVERRIDE		(0x1000)
+
+
+#define MEDIABUSMUX_REGS_ARBCFG			(0x000000)
+#define MEDIABUSMUX_REGS_DWRRCFG_JPEG_BULK	(0x000004)
+#define MEDIABUSMUX_REGS_DWRRCFG_MSR_BULK	(0x000008)
+#define MEDIABUSMUX_REGS_DWRRCFG_VXE_LLT	(0x00000c)
+#define MEDIABUSMUX_REGS_DWRRCFG_VXE_BULK	(0x000010)
+#define MEDIABUSMUX_REGS_DWRRCFG_VXD_LLT	(0x000014)
+#define MEDIABUSMUX_REGS_DWRRCFG_VXD_BULK	(0x000018)
+#define MEDIABUSMUX_REGS_CPG_CNTL		(0x00003c)
+#define MEDIABUSMUX_REGS_CPG_CNTL		(0x00003c)
+
+#define MSR_REGS_ARBCFG				(0x000000)
+#define MSR_REGS_CPG_CNTL			(0x000014)
+#define MSR_REGS_AW_TLIMIT			(0x00001c)
+#define MSR_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)
+
+#define AJPEG_REGS_ARBCFG			(0x000000)
+#define AJPEG_REGS_CPG_CNTL			(0x000014)
+#define AJPEG_REGS_MEMCACHE_DATASETID_OVERRIDE  (0x001000)
+
+#define VXE_REGS_ARBCFG				(0x000000)
+#define VXE_REGS_CPG_CNTL			(0x000014)
+#define VXE_REGS_AR_TLIMIT			(0x000020)
+#define VXE_REGS_MEMCACHE_HINT_OVERRIDE		(0x001004)
+#define VXE_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)
+
+#define VENC_INT_IDLE_CTRL			(0x030004)
+#define VENC_INT_AxCACHE_REMAPPING_REG(_x,_n)	(0x030018 + ((_x) * 8) + ((_n) * 4))
+
+#define VXD_REGS_ARBCFG				(0x000000)
+#define VXD_REGS_CPG_CNTL			(0x000014)
+#define VXD_REGS_MEMCACHE_HINT_OVERRIDE		(0x001004)
+#define VXD_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)
+
+#define VDEC_INT_IDLE_CTRL			(0x030004)
+#define VDEC_INT_AxCACHE_REMAPPING_REG(_x,_n)	(0x030018 + ((_x) * 8) + ((_n) * 4))
+
+#define CAMERABUSMUX_REGS_ARBCFG		(0x000000)
+#define CAMERABUSMUX_REGS_ISPKF_RT		(0x000004)
+#define CAMERABUSMUX_REGS_CPG_CNTL		(0x00002c)
+
+#define ISP_DMA_REGS_ARBCFG			(0x000000)
+#define ISP_DMA_REGS_CPG_CNTL			(0x000014)
+#define ISP_DMA_REGS_BW_THRESHOLD		(0x000018)
+#define ISP_DMA_REGS_AW_LIMIT			(0x00001c)
+#define ISP_DMA_REGS_AR_LIMIT			(0x000020)
+#define ISP_DMA_REGS_MEMCACHE_DATASETID_OVERRIDE (0x01000)
+
+#define ISP_KF_REGS_ARBCFG			(0x010000)
+#define ISP_KF_REGS_CPG_CNTL			(0x010014)
+#define ISP_KF_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x011000)
+
+#define DISPBUSMUX_REGS_ARBCFG			(0x000000)
+#define DISPBUSMUX_REGS_DWRRCFG_DP1_BULK	(0x000008)
+#define DISPBUSMUX_REGS_CPG_CNTL		(0x00001c)
+
+#define DISPLAYPIPE0_REGS_ARBCFG		(0x000000)
+#define DISPLAYPIPE0_REGS_CPG_CNTL		(0x000014)
+#define DISPLAYPIPE0_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)
+
+#define DISPLAYPIPE1_REGS_ARBCFG		(0x000000)
+#define DISPLAYPIPE1_REGS_CPG_CNTL		(0x000014)
+#define DISPLAYPIPE1_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)
+
+#define ANS_REGS_ARBCFG				(0x000000)
+#define ANS_REGS_CPG_CNTL			(0x000014)
+#define ANS_REGS_MEMCACHE_DATASETID_OVERRIDE	(0x001000)
+#define ANS_KF_TLIMIT_RD			(0x020008)
+#define ANS_KF_TLIMIT_WR			(0x02000c)
+#define ANS_ANC0_TLIMIT_RD			(0x030008)
+#define ANS_ANC0_TLIMIT_WR			(0x03000c)
+#define ANS_ANC1_TLIMIT_RD			(0x031008)
+#define ANS_ANC1_TLIMIT_WR			(0x03100c)
+
+#define GFX_REGS_ARBCFG				(0x000000)
+#define GFX_REGS_CPG_CNTL			(0x000014)
+
+#define GFX_IMG4_AFUSER_REGS_MCCFG_0	(0x000000)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_1	(0x000004)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_2	(0x000008)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_3	(0x00000C)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_4	(0x000010)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_5	(0x000014)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_6	(0x000018)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_7	(0x00001C)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_8	(0x000020)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_9	(0x000024)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_10	(0x000028)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_11	(0x00002C)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_12	(0x000030)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_13	(0x000034)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_14	(0x000038)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_15	(0x00003C)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_16	(0x000040)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_17	(0x000044)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_18	(0x000048)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_19	(0x00004C)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_20	(0x000050)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_21	(0x000054)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_22	(0x000058)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_23	(0x00005C)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_24	(0x000060)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_25	(0x000064)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_26	(0x000068)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_27	(0x00006C)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_28	(0x000070)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_29	(0x000074)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_30	(0x000078)
+#define GFX_IMG4_AFUSER_REGS_MCCFG_31	(0x00007C)
+
+#define AUSB_REGS_RD_RATE_LIMIT			(0x001000)
+#define AUSB_REGS_WRALIMIT			(0x001004)
+#define AUSB_REGS_WGATHER			(0x001010)
+
+
+enum remap_select {
+  REMAP_SRAM = 0,
+  REMAP_SDRAM
+};
+
+extern void miu_select_remap(enum remap_select sel);
+extern void miu_bypass_prep(void);
+extern void miu_update_device_tree(DTNode *pmgr_node);
+
+#endif /* ! __PLATFORM_SOC_MIU_H */
@@ -0,0 +1,562 @@
+/*
+ * Copyright (C) 2011 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_SOC_PMGR_H
+#define __PLATFORM_SOC_PMGR_H
+
+#include <lib/devicetree.h>
+#include <platform/soc/hwregbase.h>
+
+////////////////////////////////////////////////////////////
+//
+//  PMGR specific
+//
+////////////////////////////////////////////////////////////
+
+#define PMGR_PLL_COUNT		    (6)
+
+#define rPMGR_PLL_CTL(_n)	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + ((_n) * 0x1000)))
+#define	 PMGR_PLL_ENABLE	    (1 << 31)
+#define	 PMGR_PLL_LOCKED	    (1 << 30)
+#define	 PMGR_PLL_LOAD		    (1 << 29)
+#define	 PMGR_PLL_EXT_BYPASS	(1 << 27)
+#define	 PMGR_PLL_ENABLED	    (1 << 26)
+#define	 PMGR_PLL_BYP_ENABLED	(1 << 25)
+#define	 PMGR_PLL_M_SHIFT	    (12)
+#define	 PMGR_PLL_M_MASK	    (0x1FF)
+#define	 PMGR_PLL_P_SHIFT	    (4)
+#define	 PMGR_PLL_P_MASK	    (0x1F)
+#define	 PMGR_PLL_S_SHIFT	    (0)
+#define	 PMGR_PLL_S_MASK	    (0xF)
+#define	 PMGR_PLL_M(_m)		    (((_m) & PMGR_PLL_M_MASK) << PMGR_PLL_M_SHIFT)
+#define	 PMGR_PLL_P(_p)		    (((_p) & PMGR_PLL_P_MASK) << PMGR_PLL_P_SHIFT)
+#define	 PMGR_PLL_S(_s)		    (((_s) & PMGR_PLL_S_MASK) << PMGR_PLL_S_SHIFT)
+#define	 PMGR_PLL_FREQ(_m, _p, _s) ((((_m) * OSC_FREQ) / (_p))/((_s) + 1))
+
+#define rPMGR_PLL_CFG(_n)	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0004 + ((_n) * 0x1000)))
+#define	 PMGR_PLL_OFF_MODE_SHIFT    (30)
+#define	 PMGR_PLL_OFF_MODE_MASK	    (0x3)
+#define	 PMGR_PLL_VCO_OUT_SEL	    (1 << 27)
+#define	 PMGR_PLL_LOCK_TIME_MASK    (0xFFFF)
+#define	 PMGR_PLL_LOCK_TIME(_n)	    (((_n) & PMGR_PLL_LOCK_TIME_MASK) << 0)
+
+#define rPMGR_PLL_ANA_PARAMS(_n, _p)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0008 + ((_n) * 0x0004) + ((_p) * 0x1000)))
+#define rPMGR_PLL_FD_CTL(_n)			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0010 + ((_n) * 0x1000)))
+#define rPMGR_PLL_DEBUG(_n)		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0014 + ((_n) * 0x1000)))
+#define rPMGR_PLL_DELAY_CTL(_n, _p)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x0018 + ((_n) * 0x0004) + ((_p) * 0x1000)))
+
+#define rPMGR_MCU_FIXED_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10000))
+#define rPMGR_MCU_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10004))
+#define rPMGR_MIPI_DSI_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10008))
+#define rPMGR_NCO_REF0_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1000C))
+#define rPMGR_NCO_REF1_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10010))
+#define rPMGR_NCO_ALG0_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10014))
+#define rPMGR_NCO_ALG1_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10018))
+#define rPMGR_HSICPHY_REF_12M_CLK_CFG	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1001C))
+#define rPMGR_USB480_0_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10020))
+#define rPMGR_USB480_1_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10024))
+#define rPMGR_USB_OHCI_48M_CLK_CFG	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10028))
+#define rPMGR_USB_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1002C))
+#define rPMGR_USB_FREE_60M_CLK_CFG	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10030))
+#define rPMGR_ADSP_T_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10034))
+#define rPMGR_ADSP_P_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10038))
+#define rPMGR_ADSP_TS_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1003C))
+#define rPMGR_SIO_C_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10040))
+#define rPMGR_SIO_P_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10044))
+#define rPMGR_ISP_C_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10048))
+#define rPMGR_ISP_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1004C))
+#define rPMGR_ISP_SENSOR0_REF_CLK_CFG	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10050))
+#define rPMGR_ISP_SENSOR1_REF_CLK_CFG	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10054))
+#define rPMGR_VDEC_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10058))
+#define rPMGR_VENC_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1005C))
+#define rPMGR_VID0_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10060))
+#define rPMGR_DISP0_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10064))
+#define rPMGR_DISP1_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10068))
+#define rPMGR_AJPEG_IP_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1006C))
+#define rPMGR_AJPEG_WRAP_CLK_CFG	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10070))
+#define rPMGR_MSR_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10074))
+#define rPMGR_AF_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10078))
+#define rPMGR_ANS_DLL_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1007C))
+#define rPMGR_ANS_C_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10080))
+#define rPMGR_ANC_LINK_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10084))
+#define rPMGR_LIO_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10088))
+#define rPMGR_MCA0_M_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1008C))
+#define rPMGR_MCA1_M_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10090))
+#define rPMGR_MCA2_M_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10094))
+#define rPMGR_MCA3_M_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10098))
+#define rPMGR_MCA4_M_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1009C))
+#define rPMGR_SEP_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x100A0))
+#define rPMGR_GPIO_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x100A4))
+#define rPMGR_SPI0_N_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x100A8))
+#define rPMGR_SPI1_N_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x100AC))
+#define rPMGR_SPI2_N_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x100B0))
+#define rPMGR_SPI3_N_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x100B4))
+#define rPMGR_DEBUG_CLK_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x100B8))
+
+#define PMGR_FIRST_CLK_CFG		(&rPMGR_MCU_FIXED_CLK_CFG)
+#define PMGR_LAST_CLK_CFG		(&rPMGR_DEBUG_CLK_CFG)
+#define PMGR_CLK_CFG_COUNT	    (((((void *)(PMGR_LAST_CLK_CFG)) - ((void *)(PMGR_FIRST_CLK_CFG))) / 4) + 1)
+#define PMGR_CLK_NUM(_r)	    (((void *)&(rPMGR_ ## _r ## _CLK_CFG) - ((void *)(PMGR_FIRST_CLK_CFG))) / 4)
+
+#define rPMGR_S0_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10200))
+#define rPMGR_S1_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10204))
+#define rPMGR_S2_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10208))
+#define rPMGR_S3_CLK_CFG		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1020C))
+#define rPMGR_ISP_REF0_CLK_CFG	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10210))
+#define rPMGR_ISP_REF1_CLK_CFG	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10214))
+
+#define PMGR_FIRST_SPARE_CLK_CFG	(&rPMGR_S0_CLK_CFG)
+#define PMGR_LAST_SPARE_CLK_CFG		(&rPMGR_ISP_REF1_CLK_CFG)
+#define PMGR_SPARE_CLK_CFG_COUNT	(((((void *)(PMGR_LAST_SPARE_CLK_CFG)) - ((void *)(PMGR_FIRST_SPARE_CLK_CFG))) / 4) + 1)
+
+#define rPMGR_CLK_DIVIDER_ACG_CFG	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10300))
+#define rPMGR_CLK_DIVIDER_ACG_CFG1	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10304))
+#define rPMGR_PLL_ACG_CFG			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x10308))
+   #define PMGR_ACG_CFG_PLLX_AUTO_DISABLE(_n)	(1 << (_n))
+
+#define PMGR_CLK_CFG_ENABLE			(1 << 31)
+#define PMGR_CLK_CFG_PENDING		(1 << 30)
+#define PMGR_CLK_CFG_PENDING_SHIFT	(30)
+#define PMGR_CLK_CFG_SRC_SEL_MASK	(0x3F)
+#define PMGR_CLK_CFG_CFG_SEL_SHIFT	(16)
+#define PMGR_CLK_CFG_SRC_SEL_SHIFT	(24)
+#define PMGR_CLK_CFG_SRC_SEL(_n)	((_n) << PMGR_CLK_CFG_SRC_SEL_SHIFT)
+#define PMGR_CLK_CFG_DIVISOR_MASK	(0x3F)
+#define PMGR_CLK_CFG_DIVISOR(_n)	((_n) << 0)
+
+#define rPMGR_NCO_CLK_CFG(_n)	(*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * 0x1000 + 0x11000 + 0x0))
+#define rPMGR_NCO_DIV_INT(_n)	(*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * 0x1000 + 0x11000 + 0x4))
+#define rPMGR_NCO_DIV_FRAC_N1(_n)   (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * 0x1000 + 0x11000 + 0x8))
+#define rPMGR_NCO_DIV_FRAC_N2(_n)   (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * 0x1000 + 0x11000 + 0xc))
+#define rPMGR_NCO_DIV_FRAC_PRIME(_n) (*(volatile uint32_t *) (PMGR_BASE_ADDR + (_n) * 0x1000 + 0x11000 + 0x10))
+
+#define PMGR_NUM_NCO	5
+
+#define rPMGR_AGILE_CLK_CTL		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1b000))
+
+#define kPMGR_GFX_STATE_MAX		(16)
+#define rPMGR_GFX_PERF_STATE_ENTRY(_n)	(*(volatile uint32_t *)(PMGR_BASE_ADDR + (_n) * 0x10 + 0x1c000))
+#define rPMGR_GFX_PERF_STATE_CTL	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1c200))
+#define rPMGR_GFX_PERF_STATE_SOCHOT	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x1c300))
+
+#define rPMGR_CPU0_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20000))
+#define rPMGR_CPU1_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20008))
+#define rPMGR_CPM_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20010))
+#define rPMGR_LIO_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20018))
+#define rPMGR_IOMUX_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20020))
+#define rPMGR_AIC_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20028))
+#define rPMGR_DEBUG_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20030))
+#define rPMGR_DWI_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20038))
+#define rPMGR_GPIO_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20040))
+#define rPMGR_MCA0_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20048))
+#define rPMGR_MCA1_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20050))
+#define rPMGR_MCA2_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20058))
+#define rPMGR_MCA3_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20060))
+#define rPMGR_MCA4_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20068))
+#define rPMGR_PWM0_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20070))
+#define rPMGR_I2C0_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20078))
+#define rPMGR_I2C1_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20080))
+#define rPMGR_I2C2_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20088))
+#define rPMGR_I2C3_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20090))
+#define rPMGR_SPI0_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20098))
+#define rPMGR_SPI1_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200A0))
+#define rPMGR_SPI2_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200A8))
+#define rPMGR_SPI3_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200B0))
+#define rPMGR_UART0_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200B8))
+#define rPMGR_UART1_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200C0))
+#define rPMGR_UART2_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200C8))
+#define rPMGR_UART3_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200D0))
+#define rPMGR_UART4_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200D8))
+#define rPMGR_UART5_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200E0))
+#define rPMGR_UART6_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200E8))
+#define rPMGR_SECUART0_PS	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200F0))
+#define rPMGR_SECUART1_PS	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x200F8))
+#define rPMGR_AES0_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20100))
+#define rPMGR_SIO_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20108))
+#define rPMGR_SIO_P_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20110))
+#define rPMGR_HSIC0_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20118))
+#define rPMGR_HSIC1_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20120))
+#define rPMGR_HSIC2_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20128))
+#define rPMGR_ISPSENS0_PS	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20130))
+#define rPMGR_ISPSENS1_PS	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20138))
+#define rPMGR_MCC_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20140))
+#define rPMGR_MCU_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20148))
+#define rPMGR_AMP_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20150))
+#define rPMGR_USB_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20158))
+#define rPMGR_USBCTLREG_PS	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20160))
+#define rPMGR_USB2HOST0_OHCI_PS	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20168))
+#define rPMGR_USB2HOST0_PS	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20170))
+#define rPMGR_USB2HOST1_OHCI_PS	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20178))
+#define rPMGR_USB2HOST1_PS	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20180))
+#define rPMGR_USB_OTG_PS	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20188))
+#define rPMGR_SMX_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20190))
+#define rPMGR_SF_PS				(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20198))
+#define rPMGR_CP_PS		    	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201A0))
+#define rPMGR_DISP_BUSMUX_PS	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201A8))
+#define rPMGR_DISP0_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201B0))
+#define rPMGR_MIPI_DSI_PS	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201B8))
+#define rPMGR_DP_PS		    	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201C0))
+#define rPMGR_DISP1_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201C8))
+#define rPMGR_ISP_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201D0))
+#define rPMGR_MEDIA_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201D8))
+#define rPMGR_MSR_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201E0))
+#define rPMGR_JPG_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201E8))
+#define rPMGR_VDEC_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201F0))
+#define rPMGR_VENC_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x201F8))
+#define rPMGR_ANS_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20200))
+#define rPMGR_ANS_DLL_PS	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20208))
+#define rPMGR_ADSP_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20210))
+#define rPMGR_GFX_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20218))
+#define rPMGR_SEP_PS		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20268))
+
+#define	 PMGR_PS_RESET			(1 << 31)
+#define	 PMGR_PS_ACTUAL_PS_SHIFT	(4)
+#define	 PMGR_PS_ACTUAL_PS_MASK		(0xF)
+#define	 PMGR_PS_MANUAL_PS_MASK		(0xF)
+#define	 PMGR_PS_RUN_MAX		(0xF)
+#define	 PMGR_PS_CLOCK_OFF		(0x4)
+#define	 PMGR_PS_POWER_OFF		(0x0)
+
+#define PMGR_FIRST_PS			(&rPMGR_CPU0_PS)
+#define PMGR_LAST_PS			(&rPMGR_GFX_PS)
+#define PMGR_PS_COUNT			(((((void *)(PMGR_LAST_PS)) - ((void *)(PMGR_FIRST_PS))) / 8) + 1)
+#define PMGR_PS_NUM(_r)			(((void *)&(rPMGR_ ## _r ## _PS) - ((void *)(PMGR_FIRST_PS))) / 8)
+
+#define rPMGR_PWRGATE_CPU0_CFG0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20800))
+
+#define rPMGR_PWRGATE_AMC_CFG0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20830))
+#define rPMGR_PWRGATE_AMC_CFG1		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20834))
+
+#define rPMGR_PWRGATE_USB_CFG0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20840))
+#define rPMGR_PWRGATE_USB_CFG1		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20844))
+
+#define rPMGR_PWRGATE_ACS_CFG0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20850))
+#define rPMGR_PWRGATE_ACS_CFG1		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20854))
+
+#define rPMGR_PWRGATE_DISP0_CFG0	(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20860))
+#define rPMGR_PWRGATE_DISP0_CFG1	(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20864))
+
+#define rPMGR_PWRGATE_DISP1_CFG0	(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20870))
+#define rPMGR_PWRGATE_DISP1_CFG1	(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20874))
+
+#define rPMGR_PWRGATE_ISP_CFG0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20880))
+#define rPMGR_PWRGATE_ISP_CFG1		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20884))
+
+#define rPMGR_PWRGATE_MEDIA_CFG0	(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20890))
+#define rPMGR_PWRGATE_MEDIA_CFG1	(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20894))
+
+#define rPMGR_PWRGATE_DEC_CFG0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208a0))
+#define rPMGR_PWRGATE_DEC_CFG1		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208a4))
+
+#define rPMGR_PWRGATE_ENC_CFG0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208b0))
+#define rPMGR_PWRGATE_ENC_CFG1		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208b4))
+
+#define rPMGR_PWRGATE_ANS_CFG0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208c0))
+#define rPMGR_PWRGATE_ANS_CFG1		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208c4))
+
+#define rPMGR_PWRGATE_ADSP_CFG0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208d0))
+#define rPMGR_PWRGATE_ADSP_CFG1		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208d4))
+
+#define rPMGR_PWRGATE_GFX_CFG0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208e0))
+#define rPMGR_PWRGATE_GFX_CFG1		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208e4))
+
+#define rPMGR_PWRGATE_SEP_CFG0		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208f0))
+#define rPMGR_PWRGATE_SEP_CFG1		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x208f4))
+
+#define rPMGR_MCU_ASYNC_RESET		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x20a00))
+
+#define rPMGR_VOLMAN_CTL		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20c00))
+#define rPMGR_VOLMAN_SOC_VOLTAGE	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20c10))
+#define rPMGR_VOLMAN_SRAM_VOLTAGE	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20c14))
+#define rPMGR_VOLMAN_GFX_VOLTAGE	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20c18))
+#define rPMGR_VOLMAN_CPU_VOLTAGE	(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20c1C))
+#define rPMGR_VOLMAN_SOC_DELAY		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20c30))
+#define rPMGR_VOLMAN_SRAM_DELAY		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20c34))
+#define rPMGR_VOLMAN_GFX_DELAY		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20c38))
+#define rPMGR_VOLMAN_CPU_DELAY		(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x20c3C))
+
+#define	 PMGR_VOLMAN_DISABLE_VOL_CHANGE (1 << 10)
+
+#define rPMGR_EMA_GFX0			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x26010))
+#define rPMGR_EMA_GFX1			(*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x26014))
+
+#define rPMGR_CHIP_WDOG_TMR		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27000))
+#define rPMGR_CHIP_WDOG_RST_CNT		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27004))
+#define rPMGR_CHIP_WDOG_INTR_CNT	(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27008))
+#define rPMGR_CHIP_WDOG_CTL		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2700c))
+#define rPMGR_SYS_WDOG_TMR		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27010))
+#define rPMGR_SYS_WDOG_RST_CNT		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x27014))
+#define rPMGR_SYS_WDOG_CTL		(*(volatile uint32_t *) (PMGR_BASE_ADDR + 0x2701c))
+
+#define rPMGR_SCRATCH(_n)	    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x29000 + ((_n)*4)))
+#define rPMGR_SCRATCH0		    rPMGR_SCRATCH(0)			/* Flags */
+#define rPMGR_SCRATCH1		    rPMGR_SCRATCH(1)
+#define rPMGR_SCRATCH2		    rPMGR_SCRATCH(2)
+#define rPMGR_SCRATCH3		    rPMGR_SCRATCH(3)
+#define rPMGR_SCRATCH4		    rPMGR_SCRATCH(4)
+#define rPMGR_SCRATCH5		    rPMGR_SCRATCH(5)
+#define rPMGR_SCRATCH6		    rPMGR_SCRATCH(6)
+#define rPMGR_SCRATCH7		    rPMGR_SCRATCH(7)			/* Consistent debug root pointer */
+#define rPMGR_SCRATCH8		    rPMGR_SCRATCH(8)
+#define rPMGR_SCRATCH9		    rPMGR_SCRATCH(9)
+#define rPMGR_SCRATCH10		    rPMGR_SCRATCH(10)
+#define rPMGR_SCRATCH11		    rPMGR_SCRATCH(11)
+#define rPMGR_SCRATCH12		    rPMGR_SCRATCH(12)
+#define rPMGR_SCRATCH13		    rPMGR_SCRATCH(13)			/* Memory info */
+#define rPMGR_SCRATCH14		    rPMGR_SCRATCH(14)			/* Boot Nonce 0 */
+#define rPMGR_SCRATCH15		    rPMGR_SCRATCH(15)			/* Boot Nonce 1 */
+#define rPMGR_SCRATCH16		    rPMGR_SCRATCH(16)			/* Boot Manifest Hash 0 */
+#define rPMGR_SCRATCH17		    rPMGR_SCRATCH(17)			/* Boot Manifest Hash 1 */
+#define rPMGR_SCRATCH18		    rPMGR_SCRATCH(18)			/* Boot Manifest Hash 2 */
+#define rPMGR_SCRATCH19		    rPMGR_SCRATCH(19)			/* Boot Manifest Hash 3 */
+#define rPMGR_SCRATCH20		    rPMGR_SCRATCH(20)			/* Boot Manifest Hash 4 */
+#define rPMGR_SCRATCH21		    rPMGR_SCRATCH(21)
+#define rPMGR_SCRATCH22		    rPMGR_SCRATCH(22)
+#define rPMGR_SCRATCH23		    rPMGR_SCRATCH(23)
+
+#define rPMGR_THERMAL0_CTL0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B000))
+#define rPMGR_THERMAL0_CTL1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B004))
+#define rPMGR_THERMAL0_CTL2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B008))
+#define rPMGR_THERMAL0_CTL3			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B00C))
+#define rPMGR_THERMAL0_RDBK0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B010))
+#define rPMGR_THERMAL0_RDBK1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B014))
+#define rPMGR_THERMAL0_SUM			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B018))
+#define rPMGR_THERMAL0_SUM_CNT			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B01C))
+#define rPMGR_THERMAL1_CTL0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B040))
+#define rPMGR_THERMAL1_CTL1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B044))
+#define rPMGR_THERMAL1_CTL2			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B048))
+#define rPMGR_THERMAL1_CTL3			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B04C))
+#define rPMGR_THERMAL1_RDBK0			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B050))
+#define rPMGR_THERMAL1_RDBK1			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B054))
+#define rPMGR_THERMAL1_SUM			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B058))
+#define rPMGR_THERMAL1_SUM_CNT			(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2B05C))	
+
+#define rPMGR_SOCHOT_FAILSAFE_CTL		(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2C000))
+#define rPMGR_SOCHOT_FAILSAFE_TRIP_TEMP_0	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2C010))
+#define rPMGR_SOCHOT_FAILSAFE_TRIP_TEMP_1	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2C014))
+#define rPMGR_SOCHOT_FAILSAFE_ASSERT_COUNT_0	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2C018))
+#define rPMGR_SOCHOT_FAILSAFE_ASSERT_COUNT_1	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2C01C))
+#define rPMGR_SOCHOT_FAILSAFE_DEASSERT_COUNT_0	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2C020))
+#define rPMGR_SOCHOT_FAILSAFE_DEASSERT_COUNT_1	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2C024))
+#define rPMGR_SOCHOT_FAILSAFE_SOCHOT0_COUNT_LO	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2C080))
+#define rPMGR_SOCHOT_FAILSAFE_SOCHOT0_COUNT_HI	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2C084))
+#define rPMGR_SOCHOT_FAILSAFE_SOCHOT1_COUNT_LO	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2C088))
+#define rPMGR_SOCHOT_FAILSAFE_SOCHOT1_COUNT_HI	(*(volatile u_int32_t *)(PMGR_BASE_ADDR + 0x2C08C))
+
+
+#define rPMGR_MISC_ACG		    (*(volatile uint32_t *)(PMGR_BASE_ADDR + 0x32000))
+
+enum {
+    PMGR_CLK_OSC = 0,
+    PMGR_CLK_PLL0,
+    PMGR_CLK_PLL1,
+    PMGR_CLK_PLL2,
+    PMGR_CLK_PLL3,
+    PMGR_CLK_PLL4,
+    PMGR_CLK_PLL5,
+    PMGR_CLK_CPU,
+    PMGR_CLK_MCU_FIXED,
+    PMGR_CLK_MCU,
+    PMGR_CLK_MIPI_DSI,
+    PMGR_CLK_NCO_REF0,
+    PMGR_CLK_NCO_REF1,
+    PMGR_CLK_NCO_ALG0,
+    PMGR_CLK_NCO_ALG1,
+    PMGR_CLK_HSICPHY_REF_12M,
+    PMGR_CLK_USB480_0,
+    PMGR_CLK_USB480_1,
+    PMGR_CLK_USB_OHCI_48M,
+    PMGR_CLK_USB,
+    PMGR_CLK_USB_FREE_60M,
+    PMGR_CLK_ADSP_T,
+    PMGR_CLK_ADSP_P,
+    PMGR_CLK_ADSP_TS,
+    PMGR_CLK_SIO_C,
+    PMGR_CLK_SIO_P,
+    PMGR_CLK_ISP_C,
+    PMGR_CLK_ISP,
+    PMGR_CLK_ISP_SENSOR0_REF,
+    PMGR_CLK_ISP_SENSOR1_REF,
+    PMGR_CLK_VDEC,
+    PMGR_CLK_VENC,
+    PMGR_CLK_VID0,
+    PMGR_CLK_DISP0,
+    PMGR_CLK_DISP1,
+    PMGR_CLK_AJPEG_IP,
+    PMGR_CLK_AJPEG_WRAP,
+    PMGR_CLK_MSR,
+    PMGR_CLK_AF,
+    PMGR_CLK_ANS_DLL,
+    PMGR_CLK_ANS_C,
+    PMGR_CLK_ANC_LINK,
+    PMGR_CLK_LIO,
+    PMGR_CLK_MCA0_M,
+    PMGR_CLK_MCA1_M,
+    PMGR_CLK_MCA2_M,
+    PMGR_CLK_MCA3_M,
+    PMGR_CLK_MCA4_M,
+    PMGR_CLK_SEP,
+    PMGR_CLK_GPIO,
+    PMGR_CLK_SPI0_N,
+    PMGR_CLK_SPI1_N,
+    PMGR_CLK_SPI2_N,
+    PMGR_CLK_SPI3_N,
+    PMGR_CLK_DEBUG,
+    PMGR_CLK_S0,
+    PMGR_CLK_S1,
+    PMGR_CLK_S2,
+    PMGR_CLK_S3,
+    PMGR_CLK_ISP_REF0,
+    PMGR_CLK_ISP_REF1,
+    PMGR_CLK_COUNT,
+    PMGR_CLK_NOT_SUPPORTED
+};
+
+#define PMGR_CLK_CFG_INDEX(_clk) ((_clk) - PMGR_CLK_MCU_FIXED)
+////////////////////////////////////////////////////////////
+//
+//  CCC specific
+//
+////////////////////////////////////////////////////////////
+
+#define CCC_PWRCTL_BASE		    (CCC_ROM_TABLE_BASE_ADDR + 0x220000)
+#define CCC_CPM_THERMAL_BASE        (CCC_ROM_TABLE_BASE_ADDR + 0x230000)
+
+#define rCCC_PRE_TD_TMR		    (*(volatile uint32_t *)(CCC_PWRCTL_BASE + 0x008))
+#define rCCC_PRE_FLUSH_TMR	    (*(volatile uint32_t *)(CCC_PWRCTL_BASE + 0x010))
+
+#define rCCC_APSC_SCR		    (*(volatile uint64_t *)(CCC_PWRCTL_BASE + 0x020))
+#define CCC_APSC_PENDING	    (1 << 31)
+#define CCC_APSC_MANUAL_CHANGE(_d)  ((1 << 25) | (((_d) & 0x7) << 22))
+
+
+#define rCCC_DVFM_CFG	            (*(volatile uint32_t *)(CCC_PWRCTL_BASE + 0x040))
+#define rCCC_DVFM_SCR		    (*(volatile uint64_t *)(CCC_PWRCTL_BASE + 0x048))
+#define rCCC_DVFM_CFG_SEL	    (*(volatile uint32_t *)(CCC_PWRCTL_BASE + 0x050))
+#define rCCC_DVFM_DLY		    (*(volatile uint32_t *)(CCC_PWRCTL_BASE + 0x058))
+
+#define rCCC_PLL_CFG2		    (*(volatile uint32_t *)(CCC_PWRCTL_BASE + 0x0F8))
+#define CCC_PLL_CFG2_RELOCKBYS2_S4_MASK	(0x6)
+#define CCC_PLL_CFG2_RELOCKBYS2_S4_DIV2	(0x6)
+
+#define kDVFM_STATE_BYPASS		(0)
+#define kDVFM_STATE_SECUREROM		(kDVFM_STATE_BYPASS + 1)
+#define kDVFM_STATE_IBOOT		(kDVFM_STATE_BYPASS + 2)
+#define kDVFM_STATE_V0			(kDVFM_STATE_IBOOT + 0)
+#define kDVFM_STATE_V1			(kDVFM_STATE_IBOOT + 1)
+#define kDVFM_STATE_V2			(kDVFM_STATE_IBOOT + 2)
+#define kDVFM_STATE_V3			(kDVFM_STATE_IBOOT + 3)
+#define kDVFM_STATE_V4			(kDVFM_STATE_IBOOT + 4)
+
+#if SUB_TARGET_N51 || SUB_TARGET_N53 || SUB_TARGET_J85 || SUB_TARGET_J86 || SUB_TARGET_J87 || SUB_TARGET_J85M || SUB_TARGET_J86M || SUB_TARGET_J87M
+#define kDVFM_STATE_VMAX		(kDVFM_STATE_V4)
+#define kDVFM_STATE_VNOM		(kDVFM_STATE_V3)
+#elif SUB_TARGET_J34 || SUB_TARGET_J34M || SUB_TARGET_J71 || SUB_TARGET_J72 || SUB_TARGET_J73
+#define kDVFM_STATE_VMAX		(kDVFM_STATE_V4)
+#define kDVFM_STATE_VNOM		(kDVFM_STATE_V2)
+#else
+#define kDVFM_STATE_VMAX		(kDVFM_STATE_V3)
+#define kDVFM_STATE_VNOM		(kDVFM_STATE_V2)
+#endif
+
+#define kDVFM_STATE_VBOOST		(kDVFM_STATE_VMAX)
+
+#define kDVFM_STATE_IBOOT_CNT		(kDVFM_STATE_VMAX + 1)
+
+#define kVOLTAGE_STATES1_COUNT      	(kDVFM_STATE_VMAX - kDVFM_STATE_V0 + 1)
+#define kVOLTAGE_STATES1_SIZE       	(kVOLTAGE_STATES1_COUNT*2)  // Minimum size of voltage-state1 property in devicetree
+
+#define CCC_DVFM_STATE_COUNT	(8)
+#define rCCC_DVFM_ST(_n)	    (*(volatile uint64_t *)(CCC_PWRCTL_BASE + 0x068 + ((_n) * 8)))
+
+#define	 CCC_DVFM_ST_PLL_P(_p)	    (((_p) & 0x1F) << 13)
+#define	 CCC_DVFM_ST_PLL_M(_m)	    (((_m) & 0x1FF) << 4)
+#define	 CCC_DVFM_ST_PLL_S(_s)	    (((_s) & 0xF) << 0)
+#define	 CCC_DVFM_ST_SAFE_VOL_SHIFT (56)
+#define	 CCC_DVFM_ST_VOLADJ0(_adj0) ((((uint64_t)_adj0) & 0x3F) << 30)
+#define	 CCC_DVFM_ST_VOLADJ1(_adj1) ((((uint64_t)_adj1) & 0x3F) << 36)
+#define	 CCC_DVFM_ST_VOLADJ2(_adj2) ((((uint64_t)_adj2) & 0x3F) << 42)
+#define	 CCC_DVFM_ST_SAFEVOL(_svol) ((((uint64_t)_svol) & 0xFF) << CCC_DVFM_ST_SAFE_VOL_SHIFT)
+
+#define  rCCC_EFUSE_DVFM(_n)	(*(volatile uint32_t *)(CCC_PWRCTL_BASE + 0x0a8 + ((_n) * 8)))
+
+#define	 CCC_DVFM_CFG_TEMPTHRES0(_tt0)	(((_tt0) & 0x7F) << 0)
+#define	 CCC_DVFM_CFG_TEMPTHRES1(_tt1)	(((_tt1) & 0x7F) << 7)
+#define	 CCC_DVFM_CFG_TEMPOFFST0(_to0)	(((_to0) & 0x7F) << 14)
+#define	 CCC_DVFM_CFG_TEMPOFFST1(_to1)	(((_to1) & 0x7F) << 21)
+
+#define rCCC_PWRCTRL_MSTR_PLLCTL    (*(volatile uint32_t *)(CCC_PWRCTL_BASE + 0x0B8))
+
+#define rCCC_PWRCTRL_PLL_SCR0	    (*(volatile uint32_t *)(CCC_PWRCTL_BASE + 0x0C0))
+
+#define rCCC_PWRCTRL_PLL_SCR1	    (*(volatile uint32_t *)(CCC_PWRCTL_BASE + 0x0C8))
+
+
+#define rCCC_THRM0_CTL0             (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x00))
+#define rCCC_THRM0_CTL1             (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x08))
+#define rCCC_THRM0_CTL2             (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x10))
+#define rCCC_THRM0_CTL3             (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x18))
+#define rCCC_THRM0_RD_BK0           (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x20))
+#define rCCC_THRM0_RD_BK1           (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x28))
+#define rCCC_THRM0_SUM              (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x30))
+#define rCCC_THRM0_SUM_CNT          (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x38))
+#define rCCC_THRM1_CTL0             (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x40))
+#define rCCC_THRM1_CTL1             (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x48))
+#define rCCC_THRM1_CTL2             (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x50))
+#define rCCC_THRM1_CTL3             (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x58))
+#define rCCC_THRM1_RD_BK0           (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x60))
+#define rCCC_THRM1_RD_BK1           (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x68))
+#define rCCC_THRM1_SUM              (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x70))
+#define rCCC_THRM1_SUM_CNT          (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x78))
+#define rCCC_THRM_FSCTL             (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x80))
+#define rCCC_THRM_FSTRIP_T0         (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x90))
+#define rCCC_THRM_FSTRIP_T1         (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0x98))
+#define rCCC_THRM_FSASRT_CNT0       (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0xA0))
+#define rCCC_THRM_FSASRT_CNT1       (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0xA8))
+#define rCCC_THRM_FSDE_ASRT_CNT0    (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0xB0))
+#define rCCC_THRM_FSDE_ASRT_CNT1    (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0xB8))
+#define rCCC_THRM_FSHOT0_TSTAMP     (*(volatile uint64_t*)(CCC_CPM_THERMAL_BASE + 0xC0))
+#define rCCC_THRM_FSHOT1_TSTAMP     (*(volatile uint64_t*)(CCC_CPM_THERMAL_BASE + 0xC8))
+#define rCCC_DVFM_EFUSE_TADC0       (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0xD0))
+#define rCCC_DVFM_EFUSE_TADC1       (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0xD8))
+#define rCCC_THEM_EFUSE_TADC0       (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0xE0))
+#define rCCC_THEM_EFUSE_TADC1       (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0xE8))
+#define rCCC_DVFM_FSHOT_IDX         (*(volatile uint32_t*)(CCC_CPM_THERMAL_BASE + 0xF0))
+
+
+#define	 CCC_PLL_P_SHIFT	    (9)
+#define	 CCC_PLL_P_MASK		    (0x1F)
+#define	 CCC_PLL_M_SHIFT	    (18)
+#define	 CCC_PLL_M_MASK		    (0x1FF)
+#define	 CCC_PLL_S_SHIFT	    (0)
+#define	 CCC_PLL_S_MASK		    (0xF)
+#define	 CCC_PLL_M(_m)		    (((_m) & CCC_PLL_M_MASK) << CCC_PLL_M_SHIFT)
+#define	 CCC_PLL_P(_p)		    (((_p) & CCC_PLL_P_MASK) << CCC_PLL_P_SHIFT)
+#define	 CCC_PLL_S(_s)		    (((_s) & CCC_PLL_S_MASK) << CCC_PLL_S_SHIFT)
+#define	 CCC_PLL_ENABLE		    (1 << 31)
+#define	 CCC_PLL_LOCKED		    (1 << 29)
+#define	 CCC_PLL_LOAD		    (1 << 27)
+
+
+////////////////////////////////////////////////////////////
+//
+//  Externs
+//
+////////////////////////////////////////////////////////////
+
+extern void pmgr_update_device_tree(DTNode *pmgr_node);
+extern void pmgr_gfx_update_device_tree(DTNode *gfx_node);
+void sochot_pmgr_update_device_tree(DTNode *node);
+void sochot_ccc_update_device_tree(DTNode *node);
+void temp_sensor_pmgr_update_device_tree(DTNode *node);
+void temp_sensor_ccc_update_device_tree(DTNode *node);
+void thermal_init(void);
+
+#endif /* ! __PLATFORM_SOC_PMGR_H */
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2011-2012 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_TRAMPOLINE_H
+#define __PLATFORM_TRAMPOLINE_H
+
+#include <platform/soc/hwregbase.h>
+
+/* ROM related registers in AMC space */
+
+#define SECURITY_REG		(AMC_BASE_ADDR + 0x900)
+#define ROM_READ_DISABLE	(1 << 0)
+
+#define REMAP_REG		(AMC_BASE_ADDR + 0x904)
+
+#endif /* ! __PLATFORM_TRAMPOLINE_H */
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2012-2013 Apple Inc. All rights reserved.
+ *
+ * This document is the property of Apple Inc.
+ * It is considered confidential and proprietary.
+ *
+ * This document may not be reproduced or transmitted in any form,
+ * in whole or in part, without the express written permission of
+ * Apple Inc.
+ */
+#ifndef __PLATFORM_USBCONFIG_H
+#define __PLATFORM_USBCONFIG_H
+
+/*
+ * per Alcatraz Tunables 0.23:
+ */
+#define USBPHY_OTGTUNE0		(0x374493F3)
+
+#define USBOTG_AHB_DMA_BURST	(DWCUSB_GAHBCFG_HBST_INCR16)
+
+/* 
+ * Do we need to extend EHCI DMA Address register with additional bits
+ * as per AUSBPL301_Widgets Register Specification
+ */
+#define USBEHCI_ADDR_EXT_WIDGET_EN	1
+
+#ifdef WITH_TARGET_USB_CONFIG
+#include <target/usbconfig.h>
+#endif /* WITH_TARGET_USB_CONFIG */
+
+#endif /* ! __PLATFORM_USBCONFIG_H */